Wafer level sub-assembly bonding method

Abstract

The present application relates to a wafer level interconnection bonding packaging method, which aligns a device wafer with a wafer level substrate provided with a corresponding array of shallow cavities, each shallow cavity being provided with a second pad and each chip being provided with a first pad. The relative translation and rotation deviation is calculated by collecting the coordinates of the alignment marks, and the motion stage is driven to compensate for the post-pressing, so that the shallow cavities cover the chips and the chip pads are lower than the inclined surface pads. The shallow cavity array is divided into several bonding blocks according to the period, each bonding head is allocated an independent block without interference, and the wire bonding sequence and motion trajectory are planned, the staggered start timing is set, the pre-specified bonding process parameters are uniformly applied, and the multi-bonding head parallel wire bonding is executed, thereby ensuring the interconnection accuracy, improving the packaging efficiency and reducing the unit packaging cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor wafer-level packaging technology, and in particular to a wafer-level inter-level bonding packaging method. Background Technology

[0002] In the semiconductor packaging field, advanced packaging technologies, such as flip-chip bonding, achieve interconnection between the chip and the substrate through micro-bumps. However, its process is complex, involving multiple photolithography, electroplating, and reflow processes, resulting in high unit packaging costs. Wire bonding, as another mainstream interconnection method, is mature and cost-effective. However, in traditional planar substrate structures, the chip pads and substrate pads are located at the same horizontal plane or close to the same height. The interconnect leads need to fan outward from the chip periphery to the substrate pads, resulting in long lead paths. The parasitic inductance and signal crosstalk generated by this lead path restrict signal integrity performance in high-frequency applications. To achieve both short interconnect paths and low manufacturing costs within the wire bonding process framework, the industry continues to explore technical paths to optimize the interconnect architecture through substrate structure design improvements. However, when attempting to upgrade packaging structures involving vertical alignment of chips and substrates from single-chip manufacturing to 8- to 12-inch wafer-level parallel manufacturing, two mutually restrictive challenges are commonly encountered. First, the high-precision alignment and bonding between the entire substrate and the device wafer requires overcoming global pose deviations caused by wafer warpage and thermal expansion. Second, the batch bonding path planning and cycle optimization for hundreds of chips at the wafer scale necessitates maximizing parallel operation efficiency while ensuring the accuracy of each bonding point. This contradiction between precision and efficiency prevents existing single-chip packaging equipment and processes from being directly transferred to wafer-level manufacturing scenarios, hindering the development of such packaging structures towards low-cost, high-efficiency wafer-level packaging. Summary of the Invention

[0003] The main objective of this invention is to provide a wafer-level inter-chip bonding and packaging method. By extending the shallow cavity inter-chip structure from single-chip packaging to parallel manufacturing at the whole wafer level, it enables sub-micron level alignment and bonding of hundreds of chips and multi-bonding head collaborative parallel wire bonding at the wafer scale. This achieves the goal of significantly improving packaging efficiency and reducing unit packaging cost while ensuring interconnection accuracy.

[0004] To achieve the above objectives, the present invention provides a wafer-level inter-layer bonding and packaging method, comprising the following steps:

[0005] A device wafer with multiple chips distributed in an array is aligned with a wafer-level substrate having a shallow cavity array. The shallow cavity array corresponds one-to-one with the chip positions. Each chip has a first pad, and the cavity wall of each shallow cavity has at least one bevel, with a second pad on the bevel.

[0006] The coordinate data of the first alignment mark on the wafer-level substrate and the second alignment mark on the device wafer are collected, and the relative translational and rotational deviations between the wafer-level substrate and the device wafer are calculated.

[0007] Based on the relative translational and rotational deviations, the motion stage carrying the wafer-level substrate is driven to perform translational and rotational compensation relative to the motion stage carrying the device wafer. The motion stage is driven to press the wafer-level substrate onto the surface of the device wafer. Each shallow cavity of the wafer-level substrate covers the corresponding device wafer chip, and the chip pad is lower than the inclined pad.

[0008] The shallow cavity array on the device wafer and wafer-level substrate assembly after periodic arrangement is divided into several bonding blocks; based on the bonding block division results, independent bonding blocks are allocated to each bonding head that do not overlap spatially and do not interfere with each other during operation, and the wire bonding sequence of each bonding head in its respective block is planned to generate the motion trajectory of each bonding head.

[0009] Based on the bonding block division results, the staggered start-up sequence of each bonding head is set, and each bonding head is controlled to start operation synchronously according to the staggered start-up sequence. The pre-calibrated bonding pressure, ultrasonic power and bonding temperature are uniformly applied to perform parallel wire bonding of multiple bonding heads.

[0010] Furthermore, the step of having at least one-step inclined plane on the wall of each shallow cavity of the wafer-level substrate, wherein a second pad is provided on the inclined plane, includes:

[0011] On the wafer-level substrate, cutouts are processed at predetermined positions corresponding to each chip on the device wafer;

[0012] Along the edge of the hollowed-out opening, a lower gentle slope is etched at a first angle to form a lower gentle slope, and an upper steep slope is etched at a second angle above the lower gentle slope to form an upper steep slope, thus forming a double-step inclined cavity wall.

[0013] A second pad is formed in a predetermined area of ​​at least one of the inclined planes, forming a vertical layer with the first pad on the chip.

[0014] Further, the step of acquiring the coordinate data of the first alignment mark on the wafer-level substrate and the second alignment mark on the device wafer includes:

[0015] Multiple first alignment marks are provided in the shallow cavity array peripheral reserved area of ​​the wafer-level substrate, and multiple second alignment marks corresponding to the positions of the first alignment marks are provided in the chip array peripheral reserved area of ​​the device wafer.

[0016] The plurality of first alignment marks and the plurality of second alignment marks are symmetrically distributed on the periphery of the wafer-level substrate and the device wafer, respectively.

[0017] The spatial coordinates of the first alignment mark and the second alignment mark are acquired synchronously, and the relative translational and rotational deviations between the wafer-level substrate and the device wafer are calculated.

[0018] Further, based on the relative translational and rotational deviations, the step of driving the motion stage carrying the wafer-level substrate to perform translational and rotational compensation relative to the motion stage carrying the device wafer includes:

[0019] The relative translational deviation is decomposed into translational components in the X-axis direction and translational components in the Y-axis direction, and the rotational deviation is decomposed into rotational angular components around the Z-axis.

[0020] The motion stage carrying the wafer-level substrate is driven to perform compensated displacement of the translation component along the X and Y axes, and compensated rotation of the rotational angular component around the Z axis;

[0021] During the compensation process, the actual position of the motion stage is continuously acquired at a preset sampling frequency through the built-in grating ruler feedback system of the motion stage, compared with the target compensation position, and the motion stage is driven to make corrections with the position deviation signal until the relative translation deviation and rotation deviation both converge to within a predetermined threshold.

[0022] Further, the step of driving the motion stage to press the wafer-level substrate onto the surface of the device wafer includes:

[0023] The motion stage carrying the wafer-level substrate is controlled to descend along the Z-axis, so that the wafer-level substrate approaches the surface of the device wafer at a preset contact speed.

[0024] When the current feedback value of the Z-axis drive motor of the motion stage reaches the preset contact determination threshold, it is determined that the wafer-level substrate and the surface of the device wafer have made initial contact.

[0025] After initial contact is determined, the system switches to pressure control mode and gradually increases the pressing force applied to the wafer-level substrate according to a preset loading curve.

[0026] The gap changes at multiple points between the wafer-level substrate and the device wafer are monitored in real time during the lamination process until the uniformity of the fitting gap between each shallow cavity and the corresponding chip meets the preset conditions.

[0027] Further, the step of periodically arranging the shallow cavity array on the bonded device wafer and wafer-level substrate assembly into several bonding blocks includes:

[0028] Obtain the arrangement spacing of the shallow cavity array in the X and Y axis directions, and identify the row and column periodicity of the array;

[0029] According to the row and column periodicity, the shallow cavity array on the device wafer and wafer-level substrate assembly that has been bonded is divided into multiple strip regions along the X-axis direction, or into multiple rectangular blocks along the X-axis and Y-axis directions.

[0030] The divided strip regions or rectangular blocks are matched and verified with the motion range of each bonding head to determine the correspondence between each bonding block and the bonding head.

[0031] Furthermore, the step of allocating independent bonding blocks for each bonding head that do not spatially overlap and do not interfere with each other's operations, based on the bonding block partitioning results, includes:

[0032] Obtain the range of motion of each bonding head in the X and Y axes, and determine the three-dimensional working space envelope of each bonding head;

[0033] Based on the division result of the bonding blocks, spatially adjacent bonding blocks are respectively assigned to bonding heads whose three-dimensional working space envelopes are isolated from each other, and the three-dimensional working space envelopes of any two bonding heads do not overlap.

[0034] Set the start and end points of the operation within the bonding blocks assigned to each bonding head, and constrain the wire bonding path of each bonding head to the interior of the assigned bonding blocks.

[0035] Furthermore, the steps of planning the wire bonding sequence of each bonding head within its respective block and generating the motion trajectory of each bonding head include:

[0036] Each bonding head is controlled to move to the starting point of the assigned bonding block, and the starting point of each operation is consistent with the spatial orientation of the first shallow cavity in its respective block.

[0037] Based on the consistent spatial orientation, a unified bonding point access order is planned for all bonding heads, the position coordinates of each shallow cavity within the bonding block are obtained, and a bonding point position matrix is ​​constructed.

[0038] The unified key point access order is determined with the goal of minimizing the total path length from the starting point of the job, through all key points in the block, back to the ending point of the job.

[0039] Based on the unified bonding point access order and the slope direction of each shallow cavity, the bonding head is inserted to perform a lead motion segment from the slope pad to the chip pad at each bonding point, generating a continuous motion trajectory of all bonding heads within their respective blocks.

[0040] Furthermore, the steps for setting the staggered startup timing of each bonding head based on the bonding block partitioning results include:

[0041] Obtain the total length of the motion trajectory of each bonding head within its assigned bonding block, and estimate the single-block operation time of each bonding head;

[0042] The single-block operation time of each bonding head is compared, and the longest single-block operation time is used as the benchmark period.

[0043] Based on the difference between the single-block operation time of each bonding head and the reference cycle, the delayed start time of the bonding head with the shorter single-block operation time is determined, and the bonding completion time of each bonding head tends to be consistent, forming a staggered start sequence.

[0044] Furthermore, before performing parallel wire bonding with multiple bonding heads, the bonding pressure, ultrasonic power, and bonding temperature are pre-calibrated.

[0045] Based on the test assembly prepared in the same batch as the device wafer and wafer-level substrate assembly that have been bonded, the test assembly is divided into a central region and at least one annular edge region, and test bonding points are selected in the central region and the annular edge region respectively.

[0046] Different combinations of bonding pressure, ultrasonic power and bonding temperature were applied at each test bonding point to test the bonding strength under each combination.

[0047] The same set of bonding pressure, ultrasonic power, and bonding temperature values, which keep the difference in bonding strength between the central region and the annular edge region within a predetermined threshold, are selected as the pre-calibrated uniform application parameters and applied to the parallel wire bonding of the device wafers and wafer-level substrate assemblies in the same batch.

[0048] The wafer-level inter-layer bonding and packaging method provided by this invention has the following beneficial effects:

[0049] This invention achieves submicron-level alignment and bonding with the chip array on the device wafer by creating a shallow cavity array with beveled surfaces on a wafer-level substrate. This allows the chip pads and beveled pads to form a layered arrangement in the vertical direction, providing the physical basis for ultra-short interconnect paths in subsequent wire bonding. By acquiring the coordinates of alignment marks and compensating for deviations, translational and rotational deviations between the wafer-level substrate and the device wafer are actively corrected before bonding, effectively overcoming the interference of wafer warpage and thermal expansion on the overall alignment accuracy. The bonded shallow cavity array is divided into bonding blocks according to a periodic arrangement, and multiple spatially non-interfering bonding heads are assigned to perform wire bonding in parallel. By coordinating the completion time of each bonding head through staggered start-up timing, the total cycle time of batch bonding is shortened. By pre-calibrating a unified combination of bonding process parameters suitable for the central and edge regions of the wafer, the spatial consistency of the bonding strength distribution across the entire wafer is ensured. The entire approach elevates shallow cavity inter-chip bonding from single-chip packaging to wafer-level parallel manufacturing, significantly shortening the interconnect path of a single chip while increasing packaging output efficiency by orders of magnitude and reducing unit packaging costs. Attached Figure Description

[0050] Figure 1 This is a schematic flowchart of a wafer-level inter-level bonding and packaging method in one embodiment of the present invention;

[0051] Figure 2 This is a schematic diagram of the structure of a wafer-level inter-level bonding and packaging method in one embodiment of the present invention;

[0052] Figure 3 This is a schematic cross-sectional view of the single or double-step inclined plane of the shallow cavity wall of the substrate in one embodiment of the present invention.

[0053] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0055] Reference Figure 1 This is a schematic flowchart of a wafer-level inter-layer bonding and packaging method proposed in this invention, including the following steps:

[0056] S1, align the device wafer with multiple chips distributed in the array with the wafer-level substrate with a shallow cavity array; the shallow cavity array corresponds one-to-one with the chip position, the chip is provided with a first pad, each shallow cavity has at least one inclined surface in its cavity wall, and a second pad is provided on the inclined surface.

[0057] S2, Collect the coordinate data of the first alignment mark on the wafer-level substrate and the second alignment mark on the device wafer, and calculate the relative translational deviation and rotational deviation between the wafer-level substrate and the device wafer;

[0058] S3, based on the relative translational deviation and rotational deviation, drive the motion stage carrying the wafer-level substrate to perform translational and rotational compensation relative to the motion stage carrying the device wafer. After the compensation is completed, drive the motion stage to press the wafer-level substrate onto the surface of the device wafer. Each shallow cavity of the wafer-level substrate covers the corresponding device wafer chip, and the chip pad is lower than the inclined pad.

[0059] S4. The shallow cavity array on the device wafer and wafer-level substrate assembly that has been bonded is arranged in a periodic manner and divided into several bonding blocks. Based on the bonding block division results, independent bonding blocks are allocated to each bonding head that do not overlap spatially and do not interfere with each other during operation. The wire bonding sequence of each bonding head in its respective block is planned, and the motion trajectory of each bonding head is generated.

[0060] S5, based on the bonding block division results, set the staggered start-up sequence of each bonding head, control each bonding head to start operation synchronously according to the staggered start-up sequence, uniformly apply the pre-calibrated bonding pressure, ultrasonic power and bonding temperature, and perform multi-bonding head parallel wire bonding.

[0061] As described in step S1 above, this step establishes the structural foundation for wafer-level inter-chip bonding packaging. A device wafer with multiple chips arranged in an array, and a wafer-level substrate with an array of shallow cavities. The shallow cavity array corresponds one-to-one with the chip positions; that is, the position of each perforation on the wafer-level substrate matches the arrangement of the chips on the device wafer. Each chip has a first pad, forming the electrical lead-out terminal on the device side; the cavity wall of each shallow cavity has at least one bevel, on which a second pad is provided, forming the electrical lead-out terminal on the substrate side. Through this structural configuration, after subsequent bonding, the first pads on the chips and the second pads on the bevels of the shallow cavities will be at different height planes, forming a layered arrangement of pads in the vertical direction, providing the physical basis for ultra-short interconnect paths in subsequent wire bonding.

[0062] As described in step S2 above, this step performs precise position measurement between the wafer-level substrate and the device wafer. A first alignment mark is set on the wafer-level substrate, and a second alignment mark is set on the device wafer, with the two corresponding to each other in position. By acquiring the spatial coordinate data of the first and second alignment marks, the relative positional relationship between the two carriers in the plane is obtained. Based on the acquired coordinate data, the relative translational and rotational deviations between the wafer-level substrate and the device wafer are calculated. This deviation data reflects the actual spatial pose difference between the wafer-level substrate and the device wafer before bonding, and is the direct basis for subsequent high-precision compensation bonding. The measurement link established in this step establishes the alignment accuracy at the whole wafer scale on quantified deviation data, providing a data foundation for achieving sub-micron level alignment.

[0063] As described in step S3 above, this step drives the motion stage system to complete the compensation and bonding actions based on the obtained deviation data. The motion stage carrying the wafer-level substrate and the motion stage carrying the device wafer constitute a relative motion system. According to the relative translational and rotational deviations, the motion stage carrying the wafer-level substrate is driven to perform translational compensation and rotational compensation movements relative to the motion stage carrying the device wafer, so that the wafer-level substrate and the device wafer achieve high-precision alignment in the plane. After compensation, the motion stage is driven to press the wafer-level substrate onto the surface of the device wafer in the vertical direction. After pressing, each shallow cavity of the wafer-level substrate covers the chip on the corresponding position of the device wafer, and the first pad on the chip is spatially lower than the second pad on the inclined surface, establishing the vertical layering relationship between the pads.

[0064] As described in step S4 above, spatial planning is performed on the assembled device wafer and wafer-level substrate to perform batch bonding operations. The shallow cavity array on the assembly is divided into several bonding blocks according to its periodic arrangement in the X and Y axes. Based on the division of the bonding blocks, independent bonding blocks that do not overlap spatially and do not interfere with each other during operation are assigned to multiple bonding heads. On this basis, the wire bonding sequence of each bonding head in its respective block is planned, and the motion trajectory of each bonding head is generated. This step, through spatial block division and task allocation, decomposes the large-scale wire bonding task on the entire wafer into multiple independent work units that can be executed in parallel by multiple bonding heads and do not conflict spatially, providing an executable spatial scheduling scheme for high-efficiency parallel bonding.

[0065] As described in step S5 above, multi-bonding head collaborative scheduling and parallel bonding operations are performed in the time dimension. Based on the aforementioned bonding block division results, a staggered startup sequence for each bonding head is set. Each bonding head starts sequentially or staggered according to this staggered startup sequence, synchronously performing wire bonding operations within its assigned bonding block. During parallel wire bonding, pre-calibrated bonding pressure, ultrasonic power, and bonding temperature are uniformly applied to each bonding head to maintain consistent bonding quality across the entire wafer's central and edge regions. This step, through staggered scheduling in the time dimension and spatial uniformity of process parameters, ensures both efficiency and quality in wafer-level parallel bonding.

[0066] In one embodiment, step S1, where each shallow cavity wall of the wafer-level substrate has at least one-step slope, and the slope has a second pad, includes:

[0067] On the wafer-level substrate, cutouts are processed at predetermined positions corresponding to each chip on the device wafer;

[0068] Along the edge of the hollowed-out opening, a lower gentle slope is etched at a first angle to form a lower gentle slope, and an upper steep slope is etched at a second angle above the lower gentle slope to form an upper steep slope, thus forming a double-step inclined cavity wall.

[0069] A second pad is formed in a predetermined area of ​​at least one of the inclined planes, forming a vertical layer with the first pad on the chip.

[0070] Reference Figure 2 This is a schematic diagram of a wafer-level inter-chip bonding and packaging method according to an embodiment of the present invention. In specific implementation, cutouts are processed on the wafer-level substrate material at predetermined positions corresponding to each chip on the device wafer. Here, the wafer-level substrate material refers to a whole sheet of unpatterned substrate material, the size of which matches the device wafer, and is an 8-inch to 12-inch circular wafer-level substrate. The processing position of the cutouts is determined according to the arrangement coordinates of the chip array on the device wafer, so that each cutout coincides with the position of the corresponding chip in the planar projection. The cutouts can be processed using deep reactive ion etching or laser cutting processes, penetrating from the upper surface to the lower surface of the substrate material to form a through-hole structure. The planar dimension of the cutout is larger than the planar dimension of the corresponding chip to ensure that the chip can be encapsulated within the cavity space defined by the opening during subsequent bonding.

[0071] Along the edge of the cutout opening, a lower gently sloping surface is etched at a first angle to form a lower gently sloping surface, and an upper steeply sloping surface is etched at a second angle above the lower gently sloping surface to form an upper steeply sloping surface, thus forming a double-tiered sloping cavity wall. Specifically, in the first etching process, sloping etching is performed at the first angle along the edge of the cutout opening towards the interior of the substrate. The first angle is a small inclination relative to the horizontal plane of the substrate, and the etching depth accounts for a portion of the total depth of the shallow cavity, forming a lower gently sloping surface with a relatively gentle slope. This lower gently sloping surface provides a smooth lead transition area for subsequent wire bonding, which helps to reduce the bending stress of the lead when crossing the height difference of the pads. In the second etching process, etching continues at a second angle in the upper region of the lower gently sloping surface. The second angle is greater than the first angle, etching to the upper surface of the substrate to form an upper steeply sloping surface with a steeper slope. Through the above-described double-tiered sloping structure, the cavity wall presents a composite sloping shape with a gentle slope at the bottom and a steep slope at the top in the height direction. The lower gentle slope serves to release stress and facilitate smooth transition of lead paths, while the upper steep slope provides the location for the second pad, making the second pad significantly higher than the first pad on the chip, thus enhancing the vertical layering effect of the pads.

[0072] A second pad is fabricated in a predetermined area on at least one level of ramp, forming a vertical layer with the first pad on the chip. After etching the cavity walls of the double-level ramp, a predetermined area is selected on the at least one level of ramp to fabricate the second pad. This predetermined area is preferably located in the middle or upper part of the upper steep ramp to maximize the height difference between the second pad and the first pad on the chip, thereby forming a clear vertical layer relationship. The fabrication process of the second pad includes depositing a metal layer in the predetermined area of ​​the ramp and forming the pad pattern through photolithography and etching. The position and number of the second pads correspond one-to-one with the first pads on the chip, and each second pad provides an electrical connection point on the substrate side for subsequent wire bonding. Since the second pad is located on the ramp, while the first pad is located on the horizontal surface of the chip, a natural height difference is formed between the two, constituting the basis of the vertical interconnect structure where the chip pad is lower than the ramp pad.

[0073] Reference Figure 3This is a schematic cross-sectional view of a single or double-step inclined plane on the shallow cavity wall of a substrate according to an embodiment of the present invention. When the shallow cavity wall of the wafer-level substrate adopts a double-step inclined plane structure, that is, the lower gentle slope and the upper steep slope together constitute the double-step inclined cavity wall, the fabrication of the second pad further includes setting two sets of pads on the double-step inclined plane respectively. Among them, the inner step pad is fabricated in a predetermined area closer to the chip on the lower gentle slope, and the outer step pad is fabricated in a predetermined area further away from the chip on the upper steep slope. The inner step pad and the outer step pad are staggered in both the vertical and horizontal directions: in the vertical direction, the inner step pad and the outer step pad are located at different heights on the inclined plane, with the inner step pad closer to the chip plane and the outer step pad closer to the upper surface of the substrate; in the horizontal direction, the inner step pad and the outer step pad are staggered along the inclined plane direction, and the two do not overlap in the planar projection. The aforementioned inner and outer pads are collectively referred to as the second pads, both forming a vertical layered relationship with the first pads on the chip, but with different height differences between the layers. This configuration of double-layered ramps and two sets of pads provides the structural basis for function-driven pad grouping. The inner pads, being closer to the chip, have shorter lead paths and are used to connect high-speed signal groups, achieving extremely short-distance transmission. The outer pads, being higher and farther from the chip, have relatively longer lead paths and are used to connect power, ground, and low-speed signal groups. This method of spatially grouping pads according to signal transmission requirements layers the leads of different functions vertically and branches them horizontally, avoiding the high-density congestion problem caused by concentrated wiring on both long sides.

[0074] In one embodiment, step S2, which involves acquiring coordinate data of the first alignment mark on the wafer-level substrate and the second alignment mark on the device wafer, includes:

[0075] Multiple first alignment marks are provided in the shallow cavity array peripheral reserved area of ​​the wafer-level substrate, and multiple second alignment marks corresponding to the positions of the first alignment marks are provided in the chip array peripheral reserved area of ​​the device wafer.

[0076] The plurality of first alignment marks and the plurality of second alignment marks are symmetrically distributed on the periphery of the wafer-level substrate and the device wafer, respectively.

[0077] The spatial coordinates of the first alignment mark and the second alignment mark are acquired synchronously, and the relative translational and rotational deviations between the wafer-level substrate and the device wafer are calculated.

[0078] In specific implementation, multiple first alignment marks are set in the peripheral reserved area of ​​the shallow cavity array on the wafer-level substrate. The surface of the wafer-level substrate is divided into two parts: a shallow cavity array area and a peripheral reserved area. The shallow cavity array area is used to arrange the hollowed-out shallow cavities corresponding to the chips, while the peripheral reserved area is located in the annular area at the edge of the entire wafer-level substrate. No shallow cavity structures are fabricated in this area; it is specifically used for setting the alignment marks. The specific form of the first alignment marks can be a cross mark, an annular mark, or a grating mark, and they are fabricated on the surface of the wafer-level substrate using photolithography or laser direct writing processes. Multiple second alignment marks corresponding to the positions of the first alignment marks are set in the peripheral reserved area of ​​the chip array on the device wafer. The surface of the device wafer is also divided into a chip array area and a peripheral reserved area. The chip array area arranges multiple chips, while the peripheral reserved area is located in the annular area at the edge of the device wafer. No chips are placed in this area; it is specifically used for setting the second alignment marks. The form of the second alignment marks matches that of the first alignment marks, ensuring that the vision system can simultaneously identify and align the two sets of marks. The planar position of each second alignment mark corresponds one-to-one with the design position of the first alignment mark before bonding. That is, when the wafer-level substrate and the device wafer are in an ideal alignment state, the center of each pair of first alignment marks and second alignment marks coincides.

[0079] Multiple first alignment marks and multiple second alignment marks are symmetrically distributed around the periphery of the wafer-level substrate and the device wafer, respectively. Specifically, the first alignment marks are arranged at preset angular intervals around the periphery of the wafer-level substrate, and can be selected from a four-mark, six-mark, or eight-mark distribution with equal angles. The purpose of the symmetrical distribution is to enable the alignment marks to reflect the pose deviation between the wafer-level substrate and the device wafer from multiple directions, thereby improving the measurement sensitivity of rotational deviation. The second alignment marks are distributed in the same way as the first alignment marks on the device wafer, and form a one-to-one correspondence with the first alignment marks in their designed positions.

[0080] After the alignment marks are set, the spatial coordinates of the first and second alignment marks are simultaneously acquired. Simultaneous acquisition refers to obtaining the coordinate values ​​of each pair of first and second alignment marks at the same or multiple time points using a unified spatial reference. During acquisition, the vision system's detection field of view covers the outer marking areas of the wafer-level substrate and the device wafer, identifying the center position or feature point position of each mark and extracting the coordinate data of each mark in the device coordinate system. After acquisition, the coordinate data of all first and second alignment marks are transmitted to the alignment calculation unit. The alignment calculation unit calculates the relative translational and rotational deviations between the wafer-level substrate and the device wafer based on the coordinate deviations between each pair of marks. The relative translational deviation is calculated by averaging or weighting the translational deviations of all pair of marks to reflect the overall offset of the two carriers in the X and Y axes; the rotational deviation is calculated by the angular change in the direction of the line connecting each pair of marks to reflect the rotation angle of the two carriers around the vertical axis. The calculated relative translational and rotational deviations constitute the direct input quantities for subsequent motion stage compensation.

[0081] In one embodiment, step S3, which involves driving the motion stage carrying the wafer-level substrate to perform translational and rotational compensation relative to the motion stage carrying the device wafer based on the relative translational and rotational deviations, includes:

[0082] The relative translational deviation is decomposed into translational components in the X-axis direction and translational components in the Y-axis direction, and the rotational deviation is decomposed into rotational angular components around the Z-axis.

[0083] The motion stage carrying the wafer-level substrate is driven to perform compensated displacement of the translation component along the X and Y axes, and compensated rotation of the rotational angular component around the Z axis;

[0084] During the compensation process, the actual position of the motion stage is continuously acquired at a preset sampling frequency through the built-in grating ruler feedback system of the motion stage, compared with the target compensation position, and the motion stage is driven to make corrections with the position deviation signal until the relative translation deviation and rotation deviation both converge to within a predetermined threshold.

[0085] In specific implementation, the relative translational and rotational deviations calculated in step S2 are decomposed into components. The relative translational deviation refers to the positional offset of the wafer-level substrate and the device wafer along the X-axis and Y-axis directions in the plane, which is decomposed into translational components along the X-axis and Y-axis directions. The rotational deviation refers to the rotation angle of the wafer-level substrate relative to the device wafer about the Z-axis perpendicular to the wafer plane, which is decomposed into a rotational angular component about the Z-axis. This decomposition separates the coupled planar pose deviations into three independent compensated degrees of freedom, enabling the motion stage to perform corrective movements in each direction sequentially.

[0086] The motion stage carrying the wafer-level substrate performs compensation movements for each component. This embodiment employs a dual-motion stage architecture, where the motion stage carrying the wafer-level substrate and the motion stage carrying the device wafer can move independently, or one can serve as a reference while the other performs compensation movements. Taking the motion stage carrying the device wafer remaining stationary and the motion stage carrying the wafer-level substrate performing compensation movements as an example, the motion stage carrying the wafer-level substrate is driven to move along the X-axis by a compensation displacement equal to the X-axis translation component, and then along the Y-axis by a compensation displacement equal to the Y-axis translation component, thus correcting in-plane translational deviations. Simultaneously, the motion stage is driven to rotate around the Z-axis by an angle equal to the rotational angular component, thus correcting rotational deviations. The execution order of translational and rotational compensation can be parallel or sequential depending on the control strategy, and each compensation movement is driven by a linear motor or piezoelectric actuator built into the motion stage.

[0087] During the compensation process, the compensation accuracy is controlled in real-time using a closed-loop control system built into the motion stage, employing a built-in grating ruler feedback system. The motion stage is equipped with grating ruler displacement sensors on each of its X, Y, and Z axes. These sensors continuously acquire the actual position value of the motion stage on that axis at a preset sampling frequency. The preset sampling frequency is determined based on the control bandwidth of the motion stage and is typically set at the kilohertz level to ensure real-time tracking of position changes. The acquired actual position values ​​are transmitted to the motion controller using the grating ruler feedback system. The motion controller compares the actual position with the target compensation position and calculates the position deviation signal between them. The target compensation position is the desired pose of the motion stage determined by the aforementioned translational and rotational angular components. When a deviation exists between the actual position and the target compensation position, the position deviation signal drives the motion stage's drive unit to output a correction torque, propelling the motion stage in the direction that reduces the deviation. This acquisition-comparison-correction process is continuously iterated until both the relative translational and rotational deviations converge to within a predetermined threshold. The predetermined threshold is determined based on the alignment accuracy required by the process. When the deviation converges to within this threshold, it is determined that the wafer-level substrate and the device wafer have reached a submicron-level alignment state, and the compensation process is completed. Only after this compensation does the stage system proceed to the subsequent lamination step.

[0088] In one embodiment, the step of driving a motion stage to press the wafer-level substrate onto the surface of the device wafer includes:

[0089] The motion stage carrying the wafer-level substrate is controlled to descend along the Z-axis, so that the wafer-level substrate approaches the surface of the device wafer at a preset contact speed.

[0090] When the current feedback value of the Z-axis drive motor of the motion stage reaches the preset contact determination threshold, it is determined that the wafer-level substrate and the surface of the device wafer have made initial contact.

[0091] After initial contact is determined, the system switches to pressure control mode and gradually increases the pressing force applied to the wafer-level substrate according to a preset loading curve.

[0092] The gap changes at multiple points between the wafer-level substrate and the device wafer are monitored in real time during the lamination process until the uniformity of the fitting gap between each shallow cavity and the corresponding chip meets the preset conditions.

[0093] In practice, the motion stage carrying the wafer-level substrate descends along the Z-axis, bringing the substrate close to the device wafer surface at a preset contact speed. The Z-axis is perpendicular to the wafer plane, and the descent is driven by the Z-axis motor of the motion stage. The preset contact speed is the downward speed of the motion stage set at the initial stage of bonding. This speed selection must balance process efficiency and contact safety. If the contact speed is too high, an impact load may be generated at the moment of contact between the wafer-level substrate and the device wafer surface, leading to chip damage or substrate breakage; if the contact speed is too low, it increases the wasted process time. The preset contact speed is usually set in the lower speed range of micrometers per second to millimeters per second, and the specific value is determined comprehensively based on the thickness of the wafer-level substrate, the elastic modulus of the material, and the pressure resistance of the chip.

[0094] During the descent, the current feedback value of the Z-axis drive motor of the motion stage is continuously monitored. The operating current of the Z-axis drive motor is directly related to the load it bears when driving the motion stage downwards. When the wafer-level substrate has not yet contacted the device wafer surface, the motor load is mainly the gravitational component of the motion stage and the wafer-level substrate, and the current feedback value remains at a low baseline level. At the instant the lower surface of the wafer-level substrate makes initial contact with the upper surface of the device wafer, the contact force between the two surfaces creates an additional load on the motor, and the motor current feedback value immediately increases. When this current feedback value reaches the preset contact determination threshold, the control system determines that the wafer-level substrate and the device wafer surface have made initial contact. The preset contact determination threshold is determined jointly based on the current baseline value during the no-load operation of the motion stage and the current increment corresponding to the contact force, reliably distinguishing between the non-contact and contact states and avoiding misjudgments caused by noise or minor vibrations.

[0095] After initial contact is determined, the motion stage control system switches from position control mode to pressure control mode. Position control mode is used for precise positioning and feeding before contact, with the control target being the Z-axis spatial position of the motion stage. Pressure control mode is used for adjusting the clamping force after contact, with the control target being the clamping force applied by the wafer-level substrate to the device wafer surface. After the mode switch, the clamping force applied to the wafer-level substrate is gradually increased according to a preset loading curve. The preset loading curve refers to the set trajectory of the clamping force changing over time, and its form can be a ramp loading curve, a stepped loading curve, or a composite loading curve with a holding section. The design principle of the loading curve is to establish initial contact and adaptive position adjustment between the wafer-level substrate and the device wafer with a smaller clamping force in the early stages of clamping, and then gradually increase the clamping force to completely fit each shallow cavity onto the corresponding chip. This gradual loading method can prevent chip breakage or increased wafer warping due to excessive instantaneous clamping force, and also facilitates the discharge of residual gas inside the shallow cavities.

[0096] During the lamination process, the gap changes at multiple points between the wafer-level substrate and the device wafer are monitored in real time. This multi-point gap monitoring can be achieved using multiple gap sensors distributed at different radial and angular positions on the wafer. Each sensor synchronously collects distance data between the lower surface of the wafer-level substrate and the upper surface of the device wafer. By analyzing the gap change trends at these multiple points, the uniformity of the lamination process can be determined: if the gaps at each point decrease synchronously with the increase of the lamination force and eventually become uniform, it indicates that uniform bonding has been achieved between the wafer-level substrate and the device wafer; if the gaps at some points are significantly larger than those at others, it indicates the existence of localized unbonded areas, requiring further increase in lamination force or adjustment of the loading strategy. Monitoring continues until the uniformity of the mounting gaps between each shallow cavity and the corresponding chip meets preset conditions. These preset conditions refer to the difference in gap values ​​at each monitoring point falling within the allowable tolerance range, which is determined based on the requirements for pad height consistency in wire bonding. Once the gap uniformity meets the preset conditions, the lamination step is completed, and the device wafer and wafer-level substrate assembly proceed to the subsequent bonding block division and parallel wire bonding processes.

[0097] In one embodiment, step S4, which involves periodically arranging the shallow cavity array on the bonded device wafer and wafer-level substrate assembly into several bonding blocks, includes:

[0098] Obtain the arrangement spacing of the shallow cavity array in the X and Y axis directions, and identify the row and column periodicity of the array;

[0099] According to the row and column periodicity, the shallow cavity array on the device wafer and wafer-level substrate assembly that has been bonded is divided into multiple strip regions along the X-axis direction, or into multiple rectangular blocks along the X-axis and Y-axis directions.

[0100] The divided strip regions or rectangular blocks are matched and verified with the motion range of each bonding head to determine the correspondence between each bonding block and the bonding head.

[0101] In practice, the arrangement spacing of the shallow cavity array in the X and Y axes is obtained to identify the row and column periodicity of the array. The arrangement of the shallow cavity array is determined by the arrangement of the chip array on the device wafer. Since the chips are repeatedly arranged on the device wafer according to photolithography at a fixed step distance, the corresponding shallow cavity array also exhibits a regular two-dimensional periodic arrangement feature. Methods for obtaining the arrangement spacing include reading the design layout data of the device wafer and extracting the column spacing in the X-axis direction and the row spacing in the Y-axis direction; alternatively, a vision system can be used to scan and image the surface of the assembled component to identify the geometric center coordinates of each shallow cavity, and the average arrangement spacing is calculated by the difference in coordinates between adjacent shallow cavity centers in the X and Y axes. After obtaining the arrangement spacing data, the row and column periodicity of the array is identified: if the spacing of each column of shallow cavities in the X-axis direction remains constant, and the spacing of each row of shallow cavities in the Y-axis direction remains constant, then the array has regular periodicity in both the X and Y axes. The identification result of the row and column periodicity directly determines the geometric basis for subsequent block division.

[0102] Based on the identified row and column periodicity, the shallow cavity array on the assembly is divided into multiple bonding blocks. Two methods can be used for block division. The first method divides the shallow cavity array into multiple strip regions along the X-axis, i.e., dividing in only one direction, with each strip region spanning the entire shallow cavity row of the wafer along the Y-axis. This method is suitable when the bonding head's travel distance in the Y-axis direction can cover the entire wafer. The second method divides the shallow cavity array into multiple rectangular blocks along both the X and Y axes, forming an M×N block grid. This method is suitable when the bonding head's travel distance needs to be limited in both the X and Y axes. Regardless of the division method used, the principle is to make the number of shallow cavities in each bonding block as equal as possible to achieve a balanced distribution of the workload on each bonding head. The division operation is based on the row and column periodicity of the array: taking strip region division as an example, the number of columns in each strip region is determined by dividing the total number of columns in the shallow cavity array by the number of bonding heads; taking rectangular block division as an example, the size of each rectangular block is determined by dividing the total number of columns by the number of blocks in the X-axis direction and the total number of rows by the number of blocks in the Y-axis direction. Due to the strict periodicity of the array, the number of shallow cavities in each block is basically consistent with the spatial range.

[0103] The divided strip regions or rectangular blocks are matched and verified with the travel range of each bonding head to determine the correspondence between each bonding block and bonding head. Each bonding head is mounted on its own motion axis in the bonding device, and each bonding head has a limited travel range in both the X and Y axes. The matching verification ensures that the spatial span of each divided bonding block falls entirely within the reachable travel range of its assigned bonding head. If the spatial span of a block exceeds the travel range of the corresponding bonding head, the block division scheme needs to be adjusted, for example, by increasing the number of blocks to reduce the size of a single block. If all blocks meet the travel constraints, the matching verification is complete, each block is officially identified as a corresponding bonding block, and a one-to-one correspondence between each bonding head and bonding block is established. This correspondence serves as the basis for subsequent bonding sequence planning and parallel execution space allocation.

[0104] In one embodiment, the step of allocating independent bonding blocks for each bonding head that do not spatially overlap and do not interfere with each other's operations based on the bonding block partitioning result includes:

[0105] Obtain the range of motion of each bonding head in the X and Y axes, and determine the three-dimensional working space envelope of each bonding head;

[0106] Based on the division result of the bonding blocks, spatially adjacent bonding blocks are respectively assigned to bonding heads whose three-dimensional working space envelopes are isolated from each other, and the three-dimensional working space envelopes of any two bonding heads do not overlap.

[0107] Set the start and end points of the operation within the bonding blocks assigned to each bonding head, and constrain the wire bonding path of each bonding head to the interior of the assigned bonding blocks.

[0108] In practice, the travel range of each bonding head in the X and Y axes is obtained to determine the three-dimensional working space envelope of each bonding head. In a multi-bonding head parallel bonding device, each bonding head is mounted on an independent motion mechanism with its own X-axis and Y-axis motion guides. The travel range refers to the maximum movable distance of the bonding head in the X and Y axes, defined by the mechanical or soft control limits of the guides. The travel range of each bonding head is obtained by reading the travel parameters of each motion axis in the equipment control system. Based on obtaining the planar travel range, the three-dimensional working space envelope of each bonding head is further determined. The three-dimensional working space envelope refers to the maximum spatial range that a single bonding head and its carrying bonding tools can reach in three-dimensional space during the bonding operation. The boundaries of this envelope in the X and Y axes are determined by the planar travel range of the bonding head, and the boundary in the Z-axis direction is jointly determined by the lifting stroke of the bonding head and the axial length of the bonding tool. Furthermore, the geometric dimensions of the bonding head itself, including its body width, the outline of the bonding tool, and the swing space of the connecting cable, are all included in the calculation of the three-dimensional working space envelope. By superimposing these spatial dimensions, the boundary coordinates of the complete working envelope of each bonding head in three-dimensional space are obtained. This three-dimensional working space envelope serves as the quantitative basis for subsequent spatial interference judgment.

[0109] Based on the bonding block division, spatially adjacent bonding blocks are assigned to bonding heads with mutually isolated 3D working space envelopes. After the bonding block division is completed, the entire assembly is divided into multiple spatially adjacent or contiguous blocks. Adjacent bonding blocks are adjacent to each other at their boundaries, and their internal shallow cavities and chips are located near the boundaries of their respective blocks. If two spatially adjacent blocks are assigned to two bonding heads with overlapping 3D working space envelopes, during parallel operations, the two bonding heads may move to the vicinity of their respective block boundaries and simultaneously perform wire bonding on the shallow cavities in their boundary regions. At this time, because the 3D working space envelopes of the two bonding heads overlap, their bodies or bonding tools may mechanically collide at the boundaries, or their movement paths may obstruct each other, leading to operational interference. To avoid the above-mentioned interference risk, spatially adjacent bonding blocks are assigned to bonding heads with mutually isolated 3D working space envelopes. The mutual isolation of the three-dimensional workspace envelopes means that the three-dimensional workspace envelopes of any two bonding heads have no spatial overlap in the X, Y, and Z axes; that is, there is a safety distance greater than zero between the two envelopes. By ensuring that adjacent blocks are assigned to bonding heads with non-overlapping envelopes, even if each bonding head moves to the block boundary region simultaneously during parallel operation, its body and tool remain within their respective spatial envelopes and will not intrude into the workspace of other bonding heads, thus ensuring the independence and safety of parallel operation in the spatial dimension.

[0110] Within each bonding block assigned to a bonding head, a start point and an end point are set to constrain the wire bonding path of each bonding head to the interior of the assigned bonding block. The start point is the spatial position of the bonding head when it begins wire bonding, and the end point is the spatial position the bonding head returns to after completing wire bonding at all bonding points within the block. The start and end points are determined based on the positions of the first and last shallow cavities to be bonded within the block, respectively, or can be set at specific corners or edges of the block to facilitate the connection of movement paths. After setting the start and end points, the entire movement trajectory of each bonding head during wire bonding is restricted to the interior of the assigned bonding block. That is, the movement of the bonding head in the X and Y axes does not cross the block boundaries; it only completes a complete work cycle within the block, starting from the start point, traversing all bonding points, and returning to the end point. This constraint completely separates the wire bonding paths of each bonding head from the paths of other bonding heads in adjacent blocks, avoiding cross-block motion interference at the path level. Through spatial envelope isolation and intra-block path constraints, multiple bonding heads can operate in parallel without spatial interference across the entire wafer.

[0111] In one embodiment, the steps of planning the wire bonding sequence of each bonding head within its respective block and generating the motion trajectory of each bonding head include:

[0112] Each bonding head is controlled to move to the starting point of the assigned bonding block, and the starting point of each operation is consistent with the spatial orientation of the first shallow cavity in its respective block.

[0113] Based on the consistent spatial orientation, a unified bonding point access order is planned for all bonding heads, the position coordinates of each shallow cavity within the bonding block are obtained, and a bonding point position matrix is ​​constructed.

[0114] The unified key point access order is determined with the goal of minimizing the total path length from the starting point of the job, through all key points in the block, back to the ending point of the job.

[0115] Based on the unified bonding point access order and the slope direction of each shallow cavity, the bonding head is inserted to perform a lead motion segment from the slope pad to the chip pad at each bonding point, generating a continuous motion trajectory of all bonding heads within their respective blocks.

[0116] In practice, each bonding head is controlled to move to the starting point of its assigned bonding block. Driven by its respective motion mechanism, each bonding head moves independently from its initial standby position to the starting point of its assigned bonding block. For the completed device wafer and wafer-level substrate assembly, the shallow cavity array is determined by the chip array on the device wafer. The chip array is arranged in rows and columns on the entire circular wafer. Therefore, the bonding blocks divided in the central region of the wafer have a complete rectangular array of shallow cavities, with each block containing an equal number of rows and columns of shallow cavities. For the regularized blocks in the central region, the starting point of each block is set on the same side of the first row and first column of shallow cavities within the block, ensuring that the starting point of each block is completely consistent in spatial orientation relative to the first group of shallow cavities within its block. This consistency in spatial orientation provides a geometric basis for establishing a unified bonding point access sequence for each regularized block.

[0117] For a central, well-defined block with consistent spatial orientation, the coordinates of each shallow cavity within the block are obtained, and a bonding point location matrix is ​​constructed. Taking this block as a representative, the row and column positions of all shallow cavities within it are extracted in the local coordinate system, and a bonding point location matrix is ​​established with the row number as the first index and the column number as the second index. Each element in the matrix corresponds to the coordinate position of a shallow cavity, and the number of rows and columns of the matrix is ​​consistent with the number of rows and columns of shallow cavities contained in the well-defined block. Since the number and arrangement of shallow cavities in each central well-defined block are exactly the same, this bonding point location matrix is ​​applicable to all well-defined blocks, eliminating the need to reconstruct it for each block individually. For bonding blocks located at the wafer edge region and whose shape is incomplete due to circular wafer boundary cutting, the coordinates of the actual effective shallow cavities contained within each edge block are obtained separately, and an independent bonding point location matrix is ​​constructed for each edge block. Positions of shallow cavities missing due to wafer boundary cutting are marked as invalid points and automatically skipped during subsequent path planning.

[0118] Based on this, the bond point access order is determined with the goal of minimizing the total path length of the bonding head from the start point of the job, traversing all valid bond points within the block, and returning to the end point of the job. For regular blocks in the central region, since their bond point position matrix is ​​uniform, the planned bond point access order serves as the unified access order for all regular blocks. Path planning uses the start point of the job as the path origin and the end point of the job as the path destination, treating all bond points within the matrix as intermediate access nodes, with the shortest total transfer path as the optimization objective. When the bonding head moves at the same speed in the row and column directions, a serpentine scanning order, either row-wise or column-wise, is used as the optimal access order, ensuring that the transfer path between adjacent bond points is free of repetition and omission, minimizing the proportion of idle travel. For irregular blocks in the edge region, the optimal bond point access order for each block is solved based on the independent bond point position matrix of each edge block. During path planning, missing shallow cavity locations marked as invalid points are automatically skipped, ensuring that the bonding head only traverses the actually existing valid bonding points within the edge block, thus avoiding invalid travel in blank areas.

[0119] After determining the bonding point access order for each block, based on the bonding point access order and the slope direction of each shallow cavity, a lead-feeding segment is inserted at each bonding point, moving from the slope pad to the chip pad. At each bonding point, the bonding head first moves to a position above the second pad on the slope of the shallow cavity, performing lead bonding to the first pad on the chip. The feed direction of the lead matches the slope direction of the shallow cavity. This lead-feeding segment is used as a dwell segment at the bonding point and is sequentially inserted between the transfer movement segments between adjacent bonding points, generating a complete and continuous movement trajectory for each bonding head within its assigned block. For regular blocks in the central region, the movement trajectories of each block are completely consistent due to the uniform bonding point access order, and the movement rhythm of each bonding head is synchronized. For irregular blocks in the edge region, the movement trajectories of each block differ due to the varying number and distribution of effective bonding points, but the movement trajectories of each bonding head are constrained within their respective blocks, maintaining spatial isolation from the trajectories of adjacent blocks.

[0120] For shallow cavities with double-step ramps and two sets of pads, the wire bonding sequence needs to distinguish between the inner and outer pads. At each bonding point, the bonding head first performs a wire bonding action from the inner pad to the corresponding first pad on the chip, and then performs a wire bonding action from the outer pad to the corresponding first pad on the chip. Since the inner and outer pads are at different heights and horizontal positions on the ramps, the feed direction and wire length of each wire bonding sequence are determined independently: the inner pad, being closer to the chip, has a shorter wire path; the outer pad, being higher and farther from the chip, has a longer wire path. The wire bonding sequences of the two sets of pads are spatially connected, forming a complete wire bonding sequence at a bonding point.

[0121] Because the number of effective bonding points in irregular blocks at the edge is less than that in regular blocks at the center, if the bonding heads of the edge blocks and the center blocks start simultaneously and run at the same pace, the edge block bonding heads will complete all bonding tasks before the center block bonding heads, resulting in them being idle. To save overall process time, the completion time of the edge block bonding heads is coordinated with that of the center block bonding heads: the edge block bonding heads can perform wire bonding at a slightly reduced bonding speed within their respective blocks, making their completion time closer to that of the center block bonding heads. This allows all bonding heads to enter the next process stage synchronously in subsequent parallel workflows. Specific methods for reducing the bonding speed include appropriately increasing the pause time in the transfer motion segment between adjacent bonding points, or adjusting the execution speed of the wire action segment within the process allowable range, so that the single-point bonding cycle time of the edge blocks is slightly longer than that of the center blocks, without affecting bonding quality. Through the aforementioned speed adjustment, the bonding heads of each block tend to be consistent in the time it takes to complete all their bonding tasks. Combined with the staggered start-up sequence set in subsequent steps, the overall collaborative optimization of the operation cycle of all bonding heads on the entire wafer is achieved.

[0122] In one embodiment, step S5, which involves setting the staggered startup timing of each bonding head based on the bonding block partitioning results, includes:

[0123] Obtain the total length of the motion trajectory of each bonding head within its assigned bonding block, and estimate the single-block operation time of each bonding head;

[0124] The single-block operation time of each bonding head is compared, and the longest single-block operation time is used as the benchmark period.

[0125] Based on the difference between the single-block operation time of each bonding head and the reference cycle, the delayed start time of the bonding head with the shorter single-block operation time is determined, and the bonding completion time of each bonding head tends to be consistent, forming a staggered start sequence.

[0126] In practice, the total length of the motion trajectory of each bonding head within its assigned bonding block is obtained, and the single-block operation time of each bonding head is estimated. The total length of the motion trajectory of each bonding head is determined by the path planning result of step S4 above, and its value is equal to the cumulative length of the spatial path traversed by the bonding head from the operation start point, sequentially traversing all valid bonding points within the block according to the determined bonding point access order, completing the lead wire action segment at each bonding point, and returning to the operation termination point. For regular blocks in the central region, the total length of the motion trajectory of each block is the same; for irregular blocks in the edge region, the total length of the motion trajectory of each block varies depending on the number of valid bonding points. The single-block operation time refers to the estimated total time required for the bonding head to start from the operation start point, complete the lead wire bonding of all bonding points within the block, and return to the operation termination point. This time is estimated by decomposing the motion trajectory into two types of path segments: the transfer motion segment between bonding points and the lead wire action segment at the bonding point. The time consumed in the transfer motion segment is obtained by dividing the transfer path length by the transfer speed of the bonding head, and the time consumed in the lead wire action segment is determined by the single-point bonding time set in the lead wire bonding process. By summing up the times consumed in each path segment, the estimated single-block operation time of each bonding head is obtained.

[0127] The single-block operation time of each bonding head is compared, and the longest single-block operation time is used as the baseline cycle. Among all bonding heads, because the number of effective bonding points in irregular blocks at the edge region is less than that in regular blocks at the center region, the single-block operation time has approached that of the center block after speed adjustment, but residual differences may still exist. Simultaneously, although the movement trajectories of each bonding head have been optimized, there may still be slight deviations in operation time between different blocks due to differences in block position and shape. The single-block operation time of all bonding heads is compared one by one, and the one with the largest value is selected as the baseline cycle. The baseline cycle is the bonding time of the longest-running block among all bonding blocks on the entire wafer, determining the overall cycle length of the parallel bonding process.

[0128] Based on the difference between the single-block operation time and the reference cycle for each bonding head, the delayed start time for bonding heads with shorter single-block operation times is determined. For bonding heads with a single-block operation time equal to the reference cycle, the delayed start time is zero, meaning they start immediately at the beginning of the parallel bonding process. For bonding heads with a single-block operation time less than the reference cycle, the difference between the two is calculated; this difference represents the amount of time that bonding head can delay starting. At the beginning of the parallel bonding process, this bonding head does not start immediately but waits for the delayed start time to expire before starting. By assigning corresponding delayed start times to each bonding head with a shorter operation time, the bonding completion time of all bonding heads after their delayed start approaches the end time of the reference cycle. The bonding completion times of all bonding heads tend to be consistent, forming a staggered start sequence. The specific data of the staggered start sequence includes the start time sequence of each bonding head, which is transmitted to the main control system of the bonding equipment as the basis for scheduling the parallel bonding process.

[0129] After determining the staggered start-up sequence, each bonding head is controlled to start its operation synchronously according to this sequence. The main control system of the bonding equipment sends start commands to each bonding head at its predetermined start time, based on the staggered start-up sequence. Upon receiving the start command, each bonding head starts from its respective work starting point and executes wire bonding operations within its assigned bonding block according to its respective motion trajectory generated in step S4. During parallel wire bonding, pre-calibrated bonding pressure, ultrasonic power, and bonding temperature are uniformly applied to each bonding head. Bonding pressure refers to the vertical force applied by the bonding tool to the contact interface between the lead and the pad at the moment of wire bonding; ultrasonic power refers to the ultrasonic vibration energy applied by the bonding tool during the bonding process; and bonding temperature refers to the operating temperature maintained in the bonding area during the bonding process. These three parameters have been determined through a pre-calibration step before formal batch bonding, forming a unified combination of process parameters applicable to the central and edge regions of the entire wafer. During parallel bonding, regardless of whether each bonding head is located in a regular block in the central region or an irregular block in the edge region, the bonding equipment applies the same set of bonding pressure, ultrasonic power, and bonding temperature values ​​to each bonding head. By uniformly applying pre-calibrated process parameters, the bonding strength distribution of all bonding points on the entire wafer remains uniform, and the difference in bonding strength between the central and edge regions of the wafer is controlled within a predetermined threshold. After completing wire bonding of all bonding points within its respective block, each bonding head returns to its respective work termination point, and the parallel wire bonding process is completed.

[0130] In one embodiment, before performing multi-bonding head parallel wire bonding, the method further includes a step of pre-calibrating the bonding pressure, ultrasonic power, and bonding temperature.

[0131] Based on the test assembly prepared in the same batch as the device wafer and wafer-level substrate assembly that have been bonded, the test assembly is divided into a central region and at least one annular edge region, and test bonding points are selected in the central region and the annular edge region respectively.

[0132] Different combinations of bonding pressure, ultrasonic power and bonding temperature were applied at each test bonding point to test the bonding strength under each combination.

[0133] The same set of bonding pressure, ultrasonic power, and bonding temperature values, which keep the difference in bonding strength between the central region and the annular edge region within a predetermined threshold, are selected as the pre-calibrated uniform application parameters and applied to the parallel wire bonding of the device wafers and wafer-level substrate assemblies in the same batch.

[0134] In practice, test assemblies are provided from the same batch as the device wafers and wafer-level substrate assemblies that have been bonded. In the actual production process, device wafers and wafer-level substrates from the same batch undergo bonding using the same materials, process conditions, and equipment parameters. Therefore, the material characteristics, bonding state, and the nesting relationship between the shallow cavity and the chip are highly consistent among assemblies from the same batch. The test assemblies are one or more assemblies selected from this batch, specifically for pre-calibrating process parameters and do not enter the formal product packaging process. The test assemblies are divided into a central region and at least one annular edge region. The division method is based on the circular geometry of the assembly: the central region refers to the circular area centered on the assembly's center with a preset radius, where the shallow cavity and chip are in a relatively stable process environment; the annular edge region refers to the annular area extending from the central region to the edge of the assembly, further divided into one or more concentric annular regions according to radial distance. This incorporates the differences in process conditions caused by different positions of the wafer during manufacturing into the calibration range, ensuring that the calibration results cover the entire area from the wafer center to the edge.

[0135] Test bonding points were selected in both the central region and the annular edge region. The selection of test bonding points must be representative: within the central region, several shallow cavities were selected as test bonding points according to a uniform distribution principle; similarly, several shallow cavities were selected as test bonding points in each annular edge region according to a uniform distribution principle. The number of test bonding points selected in each region was determined proportionally based on the region area and the total number of shallow cavities, ensuring that the test results in each region reflect the overall bonding quality level within that region. After selection, the region number and coordinate location of each test bonding point were recorded.

[0136] Different combinations of bonding pressure, ultrasonic power, and bonding temperature were applied at each test bonding point to test the bonding strength under each combination. Bonding pressure, ultrasonic power, and bonding temperature are three main process parameters affecting wire bonding strength, and they interact during the wire bonding process. To calibrate a uniform parameter combination applicable to the entire wafer, a parameter combination traversal test was adopted: multiple levels of bonding pressure, ultrasonic power, and bonding temperature were taken within a preset range at certain steps, forming multiple parameter combinations. At each test bonding point, wire bonding operations were performed sequentially with each parameter combination. After bonding, the bonding strength of the bonding point was tested. The bonding strength test used a wire pull test method, applying gradually increasing tension to the bonding wire until the wire broke or the solder joint detached. The tension value at breakage was recorded as the bonding strength of that bonding point. The bonding strength data of each test bonding point under different parameter combinations are summarized to form a dataset of the correspondence between parameter combinations and bonding strength classified by region.

[0137] A set of bonding pressure, ultrasonic power, and bonding temperature values ​​that keep the bond strength difference between the central region and the annular edge region within a predetermined threshold are selected as pre-calibrated uniform application parameters. In the aggregated dataset, for each parameter combination, the average bond strength of all tested bonding points in the central region and the average bond strength of all tested bonding points in the annular edge region are calculated, and the difference between the two is calculated. This difference is compared with the predetermined threshold. The predetermined threshold is the upper limit of allowable bond strength difference set according to packaging reliability requirements. When the bond strength difference between the central region and the edge region exceeds this threshold, it indicates that the bonding quality consistency of this parameter combination is insufficient across different regions and is not suitable for wafer-level uniform application. All parameter combinations are iterated through, and several candidate parameter combinations that keep the strength difference within the predetermined threshold are selected. If multiple candidate parameter combinations exist, the optimal combination is further selected based on the highest average bond strength or the widest process window, and this is used as the pre-calibrated uniform application parameter. This uniform application parameter is written into the process formula of the bonding equipment and applied to the parallel wire bonding of all device wafers and wafer-level substrate assemblies in the same batch. It is uniformly applied to the entire wafer surface and is not adjusted due to different regional locations.

[0138] When the wafer-level substrate adopts a double-step bevel structure and the second pad includes an inner-step pad and an outer-step pad, the pre-calibrated uniform application parameters are applicable to the wire bonding of both the inner-step pad and the outer-step pad. During the parameter calibration stage, the selection of test bonding points must cover the inner-step pad positions and outer-step pad positions in both the central region and the annular edge region. Specifically, test bonding points containing inner-step pads and test bonding points containing outer-step pads are selected in both the central region and the annular edge region. At each test bonding point, different combinations of bonding pressure, ultrasonic power, and bonding temperature are applied to the inner-step pad and the outer-step pad, and the bonding strength of each combination is tested. When selecting uniform application parameters, two conditions must be met simultaneously: the difference in bonding strength between the inner-step pads in the central region and the annular edge region must be within a predetermined threshold, and the difference in bonding strength between the outer-step pads in the central region and the annular edge region must be within a predetermined threshold. A unified set of bonding pressure, ultrasonic power, and bonding temperature values ​​was ultimately determined, applicable to both inner and outer level pads. During parallel wire bonding, these unified parameters are applied to all bonding heads, regardless of whether the bonding head is currently performing wire bonding on inner or outer level pads. This ensures that the bonding strength distribution of inner and outer level pads remains uniform across the entire wafer.

[0139] In summary, this invention aligns a device wafer with multiple chips arranged in an array with a wafer-level substrate having a shallow cavity array. The shallow cavity array corresponds one-to-one with the chip positions. Each chip has a first pad, and each shallow cavity has at least one beveled surface on its wall, with a second pad on the beveled surface. Coordinate data of the first alignment mark on the wafer-level substrate and the second alignment mark on the device wafer are collected, and the relative translational and rotational deviations between the wafer-level substrate and the device wafer are calculated. Based on these relative translational and rotational deviations, a motion stage carrying the wafer-level substrate is driven to perform translational and rotational compensation relative to a motion stage carrying the device wafer. The motion stage then presses the wafer-level substrate onto the surface of the device wafer. Each shallow cavity covers the corresponding device wafer chip, with the chip pads lower than the beveled pads. The shallow cavity array on the assembled device wafer and wafer-level substrate is arranged periodically and divided into several bonding blocks. Based on the bonding block division results, independent bonding blocks are allocated to each bonding head, ensuring no spatial overlap and no operational interference. The wire bonding sequence of each bonding head within its respective block is planned, generating the motion trajectory of each bonding head. The staggered start-up sequence of each bonding head is set based on the bonding block division results, controlling each bonding head to start operation synchronously according to the staggered start-up sequence. Pre-calibrated bonding pressure, ultrasonic power, and bonding temperature are uniformly applied to perform parallel wire bonding of multiple bonding heads, thereby significantly improving packaging efficiency and reducing unit packaging cost while ensuring interconnection accuracy.

[0140] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A wafer-level inter-layer bonding and packaging method, characterized in that, Includes the following steps: A device wafer with multiple chips distributed in an array is aligned with a wafer-level substrate having a shallow cavity array. The shallow cavity array corresponds one-to-one with the chip positions. Each chip has a first pad, and the cavity wall of each shallow cavity has at least one bevel, with a second pad on the bevel. The coordinate data of the first alignment mark on the wafer-level substrate and the second alignment mark on the device wafer are collected, and the relative translational and rotational deviations between the wafer-level substrate and the device wafer are calculated. Based on the relative translational and rotational deviations, the motion stage carrying the wafer-level substrate is driven to perform translational and rotational compensation relative to the motion stage carrying the device wafer. The motion stage is driven to press the wafer-level substrate onto the surface of the device wafer. Each shallow cavity of the wafer-level substrate covers the corresponding device wafer chip, and the chip pad is lower than the inclined pad. The shallow cavity array on the device wafer and wafer-level substrate assembly after periodic arrangement is divided into several bonding blocks; based on the bonding block division results, independent bonding blocks are allocated to each bonding head that do not overlap spatially and do not interfere with each other during operation, and the wire bonding sequence of each bonding head in its respective block is planned to generate the motion trajectory of each bonding head. Based on the bonding block division results, the staggered start-up sequence of each bonding head is set, and each bonding head is controlled to start operation synchronously according to the staggered start-up sequence. The pre-calibrated bonding pressure, ultrasonic power and bonding temperature are uniformly applied to perform parallel wire bonding of multiple bonding heads.

2. The wafer-level inter-layer bonding and packaging method according to claim 1, characterized in that, The step of having at least one-step inclined plane on the wall of each shallow cavity of the wafer-level substrate, and having a second pad on the inclined plane, includes: On the wafer-level substrate, cutouts are processed at predetermined positions corresponding to each chip on the device wafer; Along the edge of the hollowed-out opening, a lower gentle slope is etched at a first angle to form a lower gentle slope, and an upper steep slope is etched at a second angle above the lower gentle slope to form an upper steep slope, thus forming a double-step inclined cavity wall. A second pad is formed in a predetermined area of ​​at least one of the inclined planes, forming a vertical layer with the first pad on the chip.

3. The wafer-level inter-layer bonding and packaging method according to claim 1, characterized in that, The step of acquiring the coordinate data of the first alignment mark on the wafer-level substrate and the second alignment mark on the device wafer includes: Multiple first alignment marks are provided in the shallow cavity array peripheral reserved area of ​​the wafer-level substrate, and multiple second alignment marks corresponding to the positions of the first alignment marks are provided in the chip array peripheral reserved area of ​​the device wafer. The plurality of first alignment marks and the plurality of second alignment marks are symmetrically distributed on the periphery of the wafer-level substrate and the device wafer, respectively. The spatial coordinates of the first alignment mark and the second alignment mark are acquired synchronously, and the relative translational and rotational deviations between the wafer-level substrate and the device wafer are calculated.

4. The wafer-level inter-layer bonding and packaging method according to claim 1, characterized in that, The step of driving the motion stage carrying the wafer-level substrate to perform translational and rotational compensation relative to the motion stage carrying the device wafer based on the relative translational and rotational deviations includes: The relative translational deviation is decomposed into translational components in the X-axis direction and translational components in the Y-axis direction, and the rotational deviation is decomposed into rotational angular components around the Z-axis. The motion stage carrying the wafer-level substrate is driven to perform compensated displacement of the translation component along the X and Y axes, and compensated rotation of the rotational angular component around the Z axis; During the compensation process, the actual position of the motion stage is continuously acquired at a preset sampling frequency through the built-in grating ruler feedback system of the motion stage, compared with the target compensation position, and the motion stage is driven to make corrections with the position deviation signal until the relative translation deviation and rotation deviation are both converged to within the predetermined threshold.

5. The wafer-level inter-layer bonding and packaging method according to claim 1, characterized in that, The step of pressing the wafer-level substrate onto the surface of the device wafer by the driving motion stage includes: The motion stage carrying the wafer-level substrate is controlled to descend along the Z-axis, so that the wafer-level substrate approaches the surface of the device wafer at a preset contact speed. When the current feedback value of the Z-axis drive motor of the motion stage reaches the preset contact determination threshold, it is determined that the wafer-level substrate and the surface of the device wafer have made initial contact. After initial contact is determined, the system switches to pressure control mode and gradually increases the pressing force applied to the wafer-level substrate according to a preset loading curve. The gap changes at multiple points between the wafer-level substrate and the device wafer are monitored in real time during the lamination process until the uniformity of the fitting gap between each shallow cavity and the corresponding chip meets the preset conditions.

6. The wafer-level inter-layer bonding and packaging method according to claim 1, characterized in that, The step of periodically arranging the shallow cavity array on the bonded device wafer and wafer-level substrate assembly into several bonding blocks includes: Obtain the arrangement spacing of the shallow cavity array in the X and Y axis directions, and identify the row and column periodicity of the array; According to the row and column periodicity, the shallow cavity array on the device wafer and wafer-level substrate assembly that has been bonded is divided into multiple strip regions along the X-axis direction, or into multiple rectangular blocks along the X-axis and Y-axis directions. The divided strip regions or rectangular blocks are matched and verified with the motion range of each bonding head to determine the correspondence between each bonding block and the bonding head.

7. The wafer-level inter-layer bonding and packaging method according to claim 1, characterized in that, The step of allocating independent bonding blocks for each bonding head that do not overlap spatially and do not interfere with each other's operations based on the bonding block partitioning results includes: Obtain the range of motion of each bonding head in the X and Y axes, and determine the three-dimensional working space envelope of each bonding head; Based on the division result of the bonding blocks, spatially adjacent bonding blocks are respectively assigned to bonding heads whose three-dimensional working space envelopes are isolated from each other, and the three-dimensional working space envelopes of any two bonding heads do not overlap. Set the start and end points of the operation within the bonding blocks assigned to each bonding head, and constrain the wire bonding path of each bonding head to the interior of the assigned bonding blocks.

8. The wafer-level inter-layer bonding and packaging method according to claim 1, characterized in that, The steps of planning the wire bonding sequence of each bonding head within its respective block and generating the motion trajectory of each bonding head include: Each bonding head is controlled to move to the starting point of the assigned bonding block, and the starting point of each operation is consistent with the spatial orientation of the first shallow cavity in its respective block. Based on the consistent spatial orientation, a unified bonding point access order is planned for all bonding heads, the position coordinates of each shallow cavity within the bonding block are obtained, and a bonding point position matrix is ​​constructed. The unified key point access order is determined with the goal of minimizing the total path length from the starting point of the job, through all key points in the block, back to the ending point of the job. Based on the unified bonding point access order and the slope direction of each shallow cavity, the bonding head is inserted to perform a lead motion segment from the slope pad to the chip pad at each bonding point, generating a continuous motion trajectory of all bonding heads within their respective blocks.

9. The wafer-level inter-layer bonding and packaging method according to claim 1, characterized in that, The step of setting the staggered startup timing of each bonding head based on the bonding block partitioning results includes: Obtain the total length of the motion trajectory of each bonding head within its assigned bonding block, and estimate the single-block operation time of each bonding head; The single-block operation time of each bonding head is compared, and the longest single-block operation time is used as the benchmark period. Based on the difference between the single-block operation time of each bonding head and the reference cycle, the delayed start time of the bonding head with the shorter single-block operation time is determined, and the bonding completion time of each bonding head tends to be consistent, forming a staggered start sequence.

10. The wafer-level inter-layer bonding and packaging method according to claim 1, characterized in that, Before performing multi-bonding head parallel wire bonding, the method further includes a step of pre-calibrating the bonding pressure, ultrasonic power, and bonding temperature. Based on the test assembly prepared in the same batch as the device wafer and wafer-level substrate assembly that have been bonded, the test assembly is divided into a central region and at least one annular edge region, and test bonding points are selected in the central region and the annular edge region respectively. Different combinations of bonding pressure, ultrasonic power and bonding temperature were applied at each test bonding point to test the bonding strength under each combination. The same set of bonding pressure, ultrasonic power, and bonding temperature values, which keep the difference in bonding strength between the central region and the annular edge region within a predetermined threshold, are selected as the pre-calibrated uniform application parameters and applied to the parallel wire bonding of the device wafers and wafer-level substrate assemblies in the same batch.

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