Chip packaging structure manufacturing method, chip packaging structure, and electronic device

Abstract

The application provides a chip packaging structure preparation method, a chip packaging structure and an electronic device. First, a packaging plate is provided. The soldering bumps of the packaging plate are connected with the conductive columns protruding relative to the surface of the packaging layer and the chip pins of the bridge chip. The buffer layer is located on the first side of the packaging layer. The orthographic projection of the soldering bumps on the packaging layer is outside the orthographic projection of the buffer layer on the packaging layer. Then, a glass substrate is provided. Next, the side of the packaging plate provided with the buffer layer is connected with the side of the glass substrate provided with the connecting points. Then, a wiring layer is arranged on the side of the packaging plate away from the glass substrate. Finally, at least one chip is arranged on the side of the wiring layer away from the glass substrate, and a plastic packaging layer surrounding the chip is prepared, so as to obtain a chip packaging structure. In this way, the packaging plate is separately prepared first, and then the packaging plate is bonded with the glass substrate, so that the risk of warping deformation of the glass substrate is reduced, and the product yield of the chip packaging structure is ensured.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and more specifically, to a method for preparing a chip packaging structure, a chip packaging structure, and an electronic device. Background Technology

[0002] Currently, in semiconductor manufacturing processes, through-hole (TMV) technology is commonly used to create vertical conductive vias to achieve electrical connections between the chip and the glass substrate. However, the current methods for fabricating TMVs in chip packaging structures are suboptimal, easily leading to glass substrate warping, which affects the reliability of the chip packaging structure and product yield. Summary of the Invention

[0003] To overcome the technical problems mentioned in the background, this application provides a method for fabricating a chip packaging structure, the method comprising: A pre-fabricated packaging board is provided, wherein the packaging board includes conductive pillars, solder bumps, bridging chips, a buffer layer, and a packaging layer. The bridging chips are located within an accommodating space formed by a plurality of conductive pillars. The packaging layer is disposed around the conductive pillars and the bridging chips. The packaging layer includes a first side and a second side opposite to each other. On the first side, the chip pins of the conductive pillars and the bridging chips protrude relative to the surface of the packaging layer. On the second side, the chip pins of the conductive pillars and the bridging chips are flush with the surface of the packaging layer. The solder bumps are respectively connected to the conductive pillars and the chip pins of the bridging chips that protrude relative to the surface of the packaging layer. The buffer layer is located on the first side of the packaging layer, and the orthographic projection of the solder bumps on the packaging layer is outside the orthographic projection of the buffer layer on the packaging layer. A glass substrate is provided, wherein one side of the glass substrate includes a connection point; The side of the encapsulation plate with the buffer layer is connected to the side of the glass substrate with the connection point, wherein the encapsulation plate is bonded to the glass substrate through the connection of the solder bumps and the connection point; A wiring layer is provided on the side of the encapsulation board away from the glass substrate, wherein the wiring layer is electrically connected to the conductive pillars in the encapsulation board; At least one chip is disposed on the side of the wiring layer away from the glass substrate, and a molding layer is formed around the chip to obtain the chip package structure, wherein the chip is electrically connected to the wiring in the wiring layer.

[0004] In one possible implementation, the step of providing a pre-fabricated package board includes: Provide a substrate; A plurality of conductive pillars are formed on one side of the carrier substrate, wherein the conductive pillars form at least one accommodating space on the carrier substrate; The bridging chip is placed within the accommodating space; An encapsulation layer is formed on the side of the carrier substrate where the conductive pillars and the bridging chip are disposed, surrounding the conductive pillars and the bridging chip, wherein, on the side away from the carrier substrate, the chip pins of the conductive pillars and the bridging chip protrude relative to the surface of the encapsulation layer; The solder bumps are formed on the conductive pillars protruding relative to the encapsulation layer and on the chip pins of the bridging chip; A buffer layer is formed on the side of the encapsulation layer away from the carrier substrate, wherein the projection of the solder bumps onto the carrier substrate is located outside the projection of the buffer layer onto the carrier substrate. Remove the carrier substrate to obtain the encapsulation board.

[0005] In one possible implementation, the step of providing a carrier substrate includes: Provide a temporary carrier board; A release layer is formed on one side of the temporary carrier plate; A bonding layer is formed on the side of the release layer away from the temporary carrier plate to obtain the carrier substrate.

[0006] In one possible implementation, the step of removing the carrier substrate to obtain the packaging board includes: The bonding layer of the carrier substrate is removed to obtain the packaging board.

[0007] In one possible implementation, the step of creating the solder bumps on the conductive pillars protruding relative to the package layer and the chip pins of the bridging chip includes: The solder bumps are formed by electroplating on the conductive pillars that protrude relative to the encapsulation layer and on the chip pins of the bridging chip.

[0008] In one possible implementation, the step of fabricating a buffer layer on the side of the encapsulation layer away from the carrier substrate includes: Provide a layer of cushioning material; The buffer material layer is disposed on the side of the encapsulation layer away from the carrier substrate, and the buffer material layer is positioned around the conductive pillars, the chip pins, and the solder bumps by vacuum lamination to form the buffer layer.

[0009] Another objective of this application is to provide a chip packaging structure, the chip packaging structure comprising: A glass substrate, wherein one side of the glass substrate includes a connection point; A packaging board includes conductive pillars, solder bumps, a bridging chip, a buffer layer, and a packaging layer. The bridging chip is located within an accommodating space formed by a plurality of conductive pillars. The packaging layer is disposed around the conductive pillars and the bridging chip. The packaging layer includes a first side and a second side. On the first side, the chip pins of the conductive pillars and the bridging chip protrude relative to the surface of the packaging layer. On the second side, the chip pins of the conductive pillars and the bridging chip are flush with the surface of the packaging layer. The solder bumps are respectively connected to the conductive pillars and the chip pins of the bridging chip that protrude relative to the surface of the packaging layer. The buffer layer is located on the first side of the packaging layer, and the orthographic projection of the solder bumps on the packaging layer is outside the orthographic projection of the buffer layer on the packaging layer. A wiring layer is located on the side of the packaging board away from the glass substrate, and the wiring layer is electrically connected to the conductive pillars and the bridging chip of the packaging board. A chip layer is located on the side of the wiring layer away from the glass substrate. The chip layer includes at least one chip and a molding compound surrounding the chip. The chip is electrically connected to the wiring in the wiring layer.

[0010] In one possible implementation, the solder bumps of the packaging board are correspondingly arranged with respect to the connection points, and the conductive pillars and the chip pins of the bridging chip are also correspondingly arranged with respect to the connection points.

[0011] In one possible implementation, the width of the accommodating space is greater than the distance between adjacent conductive pillars in the direction of the plane where the glass substrate is located; In the direction of the plane where the glass substrate is located, the conductive pillars are evenly distributed on both sides of the bridging chip; The buffer layer includes a non-conductive adhesive film.

[0012] Another object of this application is to provide an electronic device, which includes the aforementioned chip package structures provided in this application.

[0013] Based on any of the above aspects, the chip packaging structure, chip packaging structure, and electronic device provided in this application embodiment firstly, a pre-fabricated packaging board is provided. The solder bumps of the packaging board are respectively connected to conductive pillars protruding from the surface of the packaging layer and chip pins bridging the chip. A buffer layer is located on a first side of the packaging layer, and the orthogonal projection of the solder bumps on the packaging layer is outside the orthogonal projection of the buffer layer on the packaging layer. Next, a glass substrate is provided. Then, the side of the packaging board with the buffer layer is connected to the side of the glass substrate with connection points. Next, a wiring layer is provided on the side of the packaging board away from the glass substrate. Finally, at least one chip is provided on the side of the wiring layer away from the glass substrate, and a molding compound surrounding the chip is formed to obtain the chip packaging structure. Thus, the above solution first independently fabricates the packaging board and then bonds it to the glass substrate, avoiding stress accumulation caused by directly fabricating the packaging board on the glass substrate, effectively reducing the risk of warping and deformation of the glass substrate. Meanwhile, the buffer layer set around the welding bumps can effectively absorb the thermal mismatch stress caused by the difference in thermal expansion coefficients during bonding, further suppressing the warping deformation of the glass substrate, thereby ensuring the product yield of the chip packaging structure. Attached Figure Description To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic flowchart of a chip packaging structure fabrication method provided in this embodiment; Figure 2a and Figure 2b for Figure 1 Corresponding process flow chart; Figure 3 for Figure 1 A flowchart of the sub-steps corresponding to step S11; Figure 4a and Figure 4b for Figure 3 Corresponding process flow chart; Figure 5 This is a schematic diagram of the carrier substrate provided in this embodiment; Figure 6 This is a schematic diagram of a chip packaging structure provided in this embodiment.

[0015] Icons: Chip package structure-1; Package board-10; Conductive pillar-100; Bridge chip-101; Chip pin-1010; Package layer-102; First side-102a; Second side-102b; Solder bump-103; Buffer layer-104; Glass substrate-20; Connection point-200; Wiring layer-30; Chip layer-40; Chip-400; Molding layer-401; Carrier substrate-50; Temporary carrier board-500; Release layer-501; Bonding layer-502; Accommodation space-1001. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0017] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0018] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0019] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0020] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0021] The inventors discovered through research that, currently, in semiconductor manufacturing processes, through-hole (TMV) technology is commonly used to create vertical conductive vias to achieve electrical connections between the chip and the glass substrate. However, the current methods for fabricating TMVs in chip packaging structures are inadequate. Specifically, TMVs are typically fabricated directly on the glass substrate of the chip packaging structure, i.e., copper pillars are directly grown on the glass substrate through electroplating. Due to the significant difference in thermal expansion coefficients between copper and glass, thermal and mechanical stresses accumulate simultaneously between the copper pillars and the glass substrate during electroplating, molding, and subsequent heat treatment. This continuous accumulation of stress can easily lead to warping and deformation of the glass substrate, and may even cause substrate cracking or interface delamination, affecting the reliability of the chip packaging structure and product yield.

[0022] In order to solve the aforementioned technical problems, the inventors have innovatively designed the following technical solutions, and the specific implementation scheme of this application will be described in detail below with reference to the accompanying drawings.

[0023] Please see Figure 1 and Figure 2a and Figure 2b , Figure 1 This is a schematic flowchart of the fabrication method of a chip packaging structure 1 provided in this embodiment. Figure 2a and Figure 2b for Figure 1 The corresponding manufacturing process diagram is shown below. The fabrication method of chip package structure 1 is described in detail below.

[0024] Step S11: A pre-fabricated packaging board 10 is provided, wherein the packaging board 10 includes conductive pillars 100, solder bumps 103, bridging chips 101, a buffer layer 104, and a packaging layer 102. The bridging chip 101 is located within an accommodating space 1001 formed by multiple conductive pillars 100. The packaging layer 102 is disposed around the conductive pillars 100 and the bridging chip 101. The packaging layer 102 includes a first side 102a and a second side 102b opposite to each other. On the first side 102a, the chip leads of the conductive pillars 100 and the bridging chip 101 are... The pin 1010 protrudes relative to the surface of the encapsulation layer 102. On the second side 102b, the conductive post 100 and the chip pin 1010 of the bridging chip 101 are flush with the surface of the encapsulation layer 102. The solder bump 103 is connected to the conductive post 100 and the chip pin 1010 of the bridging chip 101 that protrude relative to the surface of the encapsulation layer 102, respectively. The buffer layer 104 is located on the first side 102a of the encapsulation layer 102. The orthographic projection of the solder bump 103 on the encapsulation layer 102 is outside the orthographic projection of the buffer layer 104 on the encapsulation layer 102.

[0025] In this step, the encapsulation board 10 can be a TMV unit, which completes all the fabrication processes of the encapsulation board 10 on the carrier substrate 50 alone.

[0026] Step S12: A glass substrate 20 is provided, wherein one side of the glass substrate 20 includes a connection point 200.

[0027] In this step, the wiring layer 30 is pre-prepared inside the glass substrate 20, and a connection point 200 leading out from the internal wiring layer 30 is reserved on one side of the glass substrate 20, that is, the top of the glass substrate 20. The connection point 200 can be a pad or a bump, which is used to electrically connect with the solder bump 103 of the package board 10, and its position corresponds to the position of the solder bump 103 on the package board 10.

[0028] Step S13: Connect the side of the encapsulation plate 10 with the buffer layer 104 to the side of the glass substrate 20 with the connection point 200. The encapsulation plate 10 is bonded to the glass substrate 20 through the connection of the solder bumps 103 and the connection point 200.

[0029] In this step, the side of the encapsulation board 10 with the buffer layer 104 is positioned opposite to the side of the glass substrate 20 with the connection point 200, so that the buffer layer 104 of the encapsulation board 10 is attached to the surface of the glass substrate 20, and the welding bumps 103 correspond one-to-one with the connection points 200. Then, the electrical connection between the encapsulation board 10 and the glass substrate 20 is achieved by means of thermo-press bonding (TCB).

[0030] Specifically, a high-precision alignment system can be used to ensure that the solder bumps 103 of the encapsulation board 10 are precisely aligned with the connection points 200 of the glass substrate 20, and that the buffer layer 104 corresponds to the glass substrate 20. Subsequently, through thermocompression bonding, under heating and pressurization conditions, an intermetallic compound is formed between the solder bumps 103 and the connection points 200, thereby achieving a reliable electrical connection. During the bonding process, due to the difference in thermal expansion coefficients between the encapsulation layer 102 and the glass substrate 20, thermal mismatch stress will be generated at the bonding temperature and during subsequent cooling. The low modulus characteristics of the buffer layer 104 can effectively absorb these stresses, preventing stress from being directly transmitted to the glass substrate 20, thereby effectively reducing the warping of the glass substrate 20.

[0031] Step S14: A wiring layer 30 is provided on the side of the encapsulation board 10 away from the glass substrate 20, wherein the wiring layer 30 is electrically connected to the conductive pillars 100 in the encapsulation board 10.

[0032] In this step, the routing layer 30 can be a redistribution layer (RDL).

[0033] In step S15, at least one chip 400 is disposed on the side of the wiring layer 30 away from the glass substrate 20, and a molding compound 401 is fabricated around the chip 400 to obtain the chip package structure 1, wherein the chip 400 is electrically connected to the wiring in the wiring layer 30.

[0034] In this step, the chip 400 can be mounted in a flip-chip manner, and the plastic encapsulation layer 401 that wraps the chip 400 serves to protect the chip 400 and isolate it from moisture.

[0035] In the above scheme, by first fabricating the packaging board 10 independently and then bonding it to the glass substrate 20, the stress accumulation caused by directly fabricating the packaging board 10 on the glass substrate 20 is avoided, effectively reducing the risk of warping deformation of the glass substrate 20. At the same time, the buffer layer 104 provided around the solder bumps 103 can effectively absorb the thermal mismatch stress caused by the difference in thermal expansion coefficients when bonding with the glass substrate 20, further suppressing the warping deformation of the glass substrate 20, thereby ensuring the product yield of the chip packaging structure 1. Further, please see Figure 3 and Figure 4a and Figure 4b , Figure 3 for Figure 1 A flowchart illustrating the sub-steps corresponding to step S11. Figure 4a and Figure 4b for Figure 3 The corresponding process flow diagram. Step S11 can be implemented in the following way.

[0036] Sub-step S110, providing a carrier substrate 50.

[0037] In this step, a bonding layer 502 can be provided on the surface of the carrier substrate 50, and the subsequent package board 10 is fabricated on the basis of the bonding layer 502.

[0038] In sub-step S111, a plurality of conductive pillars 100 are formed on one side of the carrier substrate 50, wherein the conductive pillars 100 form at least one accommodating space 1001 on the carrier substrate 50.

[0039] In this step, multiple conductive pillars 100 can be fabricated on one side of the substrate 50 by electroplating or physical vapor deposition (PVD). The material of the conductive pillars 100 includes conductive metals such as copper. In the direction perpendicular to the plane of the substrate 50, the cross-sectional shape of the conductive pillars 100 can be rectangular. The multiple conductive pillars 100 are distributed according to a preset arrangement, and the multiple conductive pillars 100 and the substrate 50 enclose at least one cavity, namely an accommodating space 1001, for accommodating the bridging chip 101. In the direction of the plane of the substrate 50, the width of the accommodating space 1001 is greater than the distance between adjacent conductive pillars 100.

[0040] Sub-step S112: The bridging chip 101 is placed in the accommodating space 1001.

[0041] In this step, the pre-prepared bridge die 101 is placed within the accommodating space 1001. One side of the bridge die 101 has its chip pin 1010 in contact with the carrier substrate 50; that is, the chip pin 1010 on one side of the bridge die 101 and the surface of the conductive post 100 on that side are at the same horizontal plane. The bridge die 101 can be various functional chips 400, such as a memory chip 400, a sensor chip 400, etc., and its specific type is not limited here.

[0042] In sub-step S113, an encapsulation layer 102 is formed on the side of the carrier substrate 50 where the conductive pillar 100 and the bridging chip 101 are disposed, and the encapsulation layer 102 is located around the conductive pillar 100 and the bridging chip 101. On the side away from the carrier substrate 50, the chip pins 1010 of the conductive pillar 100 and the bridging chip 101 protrude relative to the surface of the encapsulation layer 102.

[0043] In this step, an encapsulation material is applied to the surface of the carrier substrate 50 using a molding process. This encapsulation material fills the gap between the conductive pillar 100 and the bridging chip 101, and at least covers the sidewalls of the conductive pillar 100 and the bridging chip 101, forming an encapsulation layer 102. The material of the encapsulation layer 102 can be epoxy molding compound (EMC), polyimide (PI), benzocyclobutene (BCB), or an insulating encapsulation material.

[0044] After molding, the encapsulation layer 102 has a first side 102a and a second side 102b. On the first side 102a, which is the side away from the carrier substrate 50, the top end face of the conductive pillar 100 and the top end face of the chip pin 1010 of the bridging chip 101 protrude outward at a certain height relative to the upper surface of the encapsulation layer 102, so as to facilitate the subsequent fabrication of solder bumps 103 on these protruding end faces.

[0045] On the second side 102b, that is, the side closer to the carrier substrate 50, the bottom end face of the conductive pillar 100 and the chip pin 1010 of the bridging chip 101 are flush with the lower surface of the encapsulation layer 102, so as to form a flat connection surface after the carrier substrate 50 is removed.

[0046] In this embodiment, during the molding process, a mold with a protruding structure can be directly used, or the top encapsulation layer 102 can be removed by a grinding process after molding, so that the conductive pillar 100 and the chip pin 1010 of the bridging chip 101 protrude from the surface of the encapsulation layer 102.

[0047] Sub-step S114: Solder bumps 103 are formed on the conductive pillars 100 protruding relative to the encapsulation layer 102 and the chip pins 1010 of the bridging chip 101.

[0048] In this step, a secondary electroplating process is performed on the surfaces of the protruding conductive pillar 100 and the bridging chip 101 to grow solder bumps 103. The material of the solder bumps 103 includes soldering metals such as tin. In the direction perpendicular to the plane of the carrier substrate 50, the cross-sectional shape of the solder bumps 103 can be rectangular. Furthermore, the dimensions of the solder bumps 103 can be matched to those of the conductive pillar 100 and the chip pin 1010.

[0049] In sub-step S115, a buffer layer 104 is formed on the side of the encapsulation layer 102 away from the carrier substrate 50, wherein the orthographic projection of the solder bumps 103 on the carrier substrate 50 is located outside the orthographic projection of the buffer layer 104 on the carrier substrate 50.

[0050] In this step, the buffer layer 104 is made of a low-modulus polymer film, such as a non-conductive film (NCF). The buffer material layer is placed on the side of the encapsulation layer 102 away from the carrier substrate 50. The buffer material layer is heated and pressurized in a vacuum environment using a vacuum lamination method, so that the buffer material layer fills the space between the conductive pillars 100 and the solder bumps 103, and also fills the space between the chip pins 1010 and the solder bumps 103. This buffer layer 104 serves as a stress buffer layer during subsequent bonding, preventing warping and deformation caused by the mismatch of the thermal expansion coefficients of the materials when the encapsulation layer 102 is bonded to the glass substrate 20.

[0051] In sub-step S116, the carrier substrate 50 is removed to obtain the encapsulation board 10.

[0052] In this step, the encapsulation board 10 is peeled off from the carrier substrate 50 to obtain the complete encapsulation board 10.

[0053] Further, please see Figure 5 , Figure 5 This is a schematic diagram of the carrier substrate 50 provided in this embodiment. Sub-step S110 can be implemented in the following manner.

[0054] First, a temporary carrier board of 500 is provided.

[0055] In this embodiment, the temporary carrier board 500 can be made of materials such as silicon or glass that have sufficient rigidity and a smooth surface to ensure the reliability of fabricating the encapsulation board 10 on it.

[0056] Next, a release layer 501 is fabricated on one side of the temporary carrier plate 500.

[0057] In this step, the release layer 501 includes the RL (release layer), which mainly protects the temporary carrier board 500.

[0058] Finally, a bonding layer 502 is fabricated on the side of the release layer 501 away from the temporary carrier plate 500 to obtain the carrier substrate 50.

[0059] In this step, the bonding layer 502 includes an AL adhesive layer, which is composed of an organic polymer sensitive to a specific wavelength of laser light and is typically adhesive. During subsequent debonding operations, the bonding layer 502 can be decomposed or lose its adhesiveness through laser debonding, heating, or other debonding methods, allowing it to separate from the encapsulation board 10.

[0060] Furthermore, sub-step S116 can be implemented in the following way.

[0061] Remove the bonding layer 502 of the carrier substrate 50 to obtain the packaging board 10.

[0062] In this step, the bonding layer 502 can be decomposed or lose its adhesiveness by debonding methods such as laser debonding or heating, so that it can be separated from the encapsulation board 10 to obtain the encapsulation board 10.

[0063] Furthermore, sub-step S114 can be implemented in the following way.

[0064] Solder bumps 103 are formed on the conductive pillars 100 protruding relative to the encapsulation layer 102 and the chip pins 1010 of the bridging chip 101 by electroplating.

[0065] Furthermore, sub-step S115 can be implemented in the following way. First, a layer of cushioning material is provided.

[0066] Next, a buffer material layer is placed on the side of the encapsulation layer 102 away from the carrier substrate 50, and the buffer material layer is placed around the conductive pillar 100, chip pin 1010 and solder bump 103 by vacuum pressing to form a buffer layer 104.

[0067] In this embodiment, the buffer material layer includes a non-conductive adhesive film (NCF). This buffer material layer is disposed on the side of the encapsulation layer 102 away from the carrier substrate 50. Vacuum lamination is used to heat and pressurize the buffer material layer in a vacuum environment, causing it to fill the gaps around the conductive pillars 100 and solder bumps 103, as well as the gaps around the chip leads 1010 and solder bumps 103, ultimately forming the buffer layer 104. In the vacuum lamination process, the vacuum environment effectively eliminates air bubbles generated between the buffer layer 104 and the encapsulation layer 102, while the heating and pressurizing operation allows the fluid buffer material layer to flow fully into the gaps that need to be filled, tightly bonding with the conductive pillars 100, chip leads 1010, and solder bumps 103.

[0068] Based on the same inventive concept, please refer to Figure 6 , Figure 6This is a schematic diagram of a chip packaging structure 1 provided in this embodiment. This application embodiment also provides a chip packaging structure 1, which includes a glass substrate 20, a packaging board 10, a wiring layer 30 and a chip layer 40.

[0069] One side of the glass substrate 20 includes a connection point 200. The encapsulation board 10 includes conductive pillars 100, solder bumps 103, a bridging chip 101, a buffer layer 104, and an encapsulation layer 102. The bridging chip 101 is located within the accommodating space 1001 formed by the plurality of conductive pillars 100. The encapsulation layer 102 is disposed around the conductive pillars 100 and the bridging chip 101. The encapsulation layer 102 includes a first side 102a and a second side 102b opposite to each other. On the first side 102a, the chip pins 10 of the conductive pillars 100 and the bridging chip 101 are connected. 10 protrudes relative to the surface of the encapsulation layer 102. On the second side 102b, the conductive pillar 100 and the chip pin 1010 of the bridging chip 101 are flush with the surface of the encapsulation layer 102. The solder bump 103 is connected to the conductive pillar 100 and the chip pin 1010 of the bridging chip 101 that protrude relative to the surface of the encapsulation layer 102, respectively. The buffer layer 104 is located on the first side 102a of the encapsulation layer 102. The orthographic projection of the solder bump 103 on the encapsulation layer 102 is outside the orthographic projection of the buffer layer 104 on the encapsulation layer 102.

[0070] The wiring layer 30 is located on the side of the package board 10 away from the glass substrate 20, and the wiring layer 30 is electrically connected to the conductive pillars 100 and the bridging chip 101 of the package board 10.

[0071] The chip layer 40 is located on the side of the wiring layer 30 away from the glass substrate 20. The chip layer 40 includes at least one chip 400 and a molding layer 401 surrounding the chip 400. The chip 400 is electrically connected to the wiring in the wiring layer 30.

[0072] In the above scheme, during the fabrication of the chip packaging structure 1, the packaging plate 10 is fabricated separately, and the side of the packaging plate 10 with the buffer layer 104 is fixed to the side of the glass substrate 20 with the connection point 200. On the one hand, by fabricating the packaging plate 10 independently first and then bonding it to the glass substrate 20, stress accumulation caused by directly fabricating the packaging plate 10 on the glass substrate 20 is avoided, effectively reducing the risk of warping deformation of the glass substrate 20. On the other hand, due to the difference in the coefficient of thermal expansion between the glass substrate 20 and the packaging layer 102, the buffer layer 104 located between the glass substrate 20 and the packaging layer 102 can buffer both of them. For example, during bonding, it can effectively absorb the thermal mismatch stress caused by the difference in the coefficient of thermal expansion, preventing the glass substrate 20 from warping deformation, thereby ensuring the product yield of the chip packaging structure 1.

[0073] Furthermore, please see again Figure 6In this embodiment, the solder bumps 103 of the packaging board 10 are correspondingly arranged with the connection points 200, and the conductive pillars 100 and the chip pins 1010 of the bridging chip 101 are also correspondingly arranged with the connection points 200. In this way, a reliable connection between the packaging board 10 and the glass substrate is ensured.

[0074] Furthermore, please see again Figure 6 In the direction of the plane where the glass substrate 20 is located, the width d1 of the accommodating space 1001 is greater than the distance d2 between adjacent conductive pillars 100. In this embodiment, the width d1 of the accommodating space 1001 is greater than the distance d2 between adjacent conductive pillars 100, which ensures that there is enough space for the arrangement of the bridging chip 101, makes full use of the space utilization of the chip packaging structure 1, and helps to reduce the size of the chip packaging structure 1.

[0075] The conductive pillars 100 are evenly spaced on both sides of the bridging chip 101 in the direction of the plane of the glass substrate 20. In this embodiment, the evenly spaced conductive pillars 100 are beneficial for uniform stress distribution and synchronous signal transmission.

[0076] The buffer layer 104 includes a non-conductive adhesive film. In this embodiment, the buffer layer 104 serves as a stress buffer layer and can be made of a low-modulus polymer film material.

[0077] Based on the same inventive concept, this application also provides an electronic device, which includes the aforementioned chip packaging structures 1 provided in this application. In this embodiment, the chip packaging structure 1 is fabricated by first independently manufacturing a packaging plate 10 and then bonding it to a glass substrate 20. This avoids stress accumulation caused by directly fabricating the packaging plate 10 on the glass substrate 20, effectively reducing the risk of warping deformation of the glass substrate 20. Simultaneously, the buffer layer 104 disposed around the solder bumps 103 can effectively absorb thermal mismatch stress caused by differences in thermal expansion coefficients during bonding, further suppressing warping deformation of the glass substrate 20, ensuring the product yield of the chip packaging structure 1, and thereby improving the market competitiveness of the electronic device.

[0078] In summary, the chip packaging structure, chip packaging structure, and electronic device provided in this application firstly involve providing a pre-fabricated packaging board. The solder bumps on the packaging board are connected to conductive pillars protruding from the surface of the packaging layer and to the chip pins of the bridging chip. A buffer layer is located on the first side of the packaging layer, and the orthographic projection of the solder bumps on the packaging layer is outside the orthographic projection of the buffer layer on the packaging layer. Next, a glass substrate is provided. Then, the side of the packaging board with the buffer layer is connected to the side of the glass substrate with the connection points. Next, a wiring layer is formed on the side of the packaging board away from the glass substrate. Finally, at least one chip is formed on the side of the wiring layer away from the glass substrate, and a molding compound is formed around the chip to obtain the chip packaging structure. In this way, the above method first independently fabricates the packaging board and then bonds it to the glass substrate, avoiding stress accumulation caused by directly fabricating the packaging board on the glass substrate and effectively reducing the risk of warping and deformation of the glass substrate. Meanwhile, the buffer layer set around the welding bumps can effectively absorb the thermal mismatch stress caused by the difference in thermal expansion coefficients during bonding, further suppressing the warping deformation of the glass substrate, thereby ensuring the product yield of the chip packaging structure. The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a chip packaging structure, characterized in that, The method includes: A pre-fabricated packaging board is provided, wherein the packaging board includes conductive pillars, solder bumps, bridging chips, a buffer layer, and a packaging layer. The bridging chips are located within an accommodating space formed by a plurality of conductive pillars. The packaging layer is disposed around the conductive pillars and the bridging chips. The packaging layer includes a first side and a second side opposite to each other. On the first side, the chip pins of the conductive pillars and the bridging chips protrude relative to the surface of the packaging layer. On the second side, the chip pins of the conductive pillars and the bridging chips are flush with the surface of the packaging layer. The solder bumps are respectively connected to the conductive pillars and the chip pins of the bridging chips that protrude relative to the surface of the packaging layer. The buffer layer is located on the first side of the packaging layer, and the orthographic projection of the solder bumps on the packaging layer is outside the orthographic projection of the buffer layer on the packaging layer. A glass substrate is provided, wherein one side of the glass substrate includes a connection point; The side of the encapsulation plate with the buffer layer is connected to the side of the glass substrate with the connection point, wherein the encapsulation plate is bonded to the glass substrate through the connection of the solder bumps and the connection point; A wiring layer is provided on the side of the encapsulation board away from the glass substrate, wherein the wiring layer is electrically connected to the conductive pillars in the encapsulation board; At least one chip is disposed on the side of the wiring layer away from the glass substrate, and a molding layer is formed around the chip to obtain the chip package structure, wherein the chip is electrically connected to the wiring in the wiring layer.

2. The method for fabricating the chip packaging structure as described in claim 1, characterized in that, The step of providing a pre-fabricated packaged board includes: Provide a substrate; A plurality of conductive pillars are formed on one side of the carrier substrate, wherein the conductive pillars form at least one accommodating space on the carrier substrate; The bridging chip is placed within the accommodating space; An encapsulation layer is formed on one side of the carrier substrate where the conductive pillars and the bridging chip are disposed, surrounding the conductive pillars and the bridging chip, wherein, on the side away from the carrier substrate, the chip pins of the conductive pillars and the bridging chip protrude relative to the surface of the encapsulation layer; The solder bumps are formed on the conductive pillars protruding relative to the encapsulation layer and on the chip pins of the bridging chip; A buffer layer is formed on the side of the encapsulation layer away from the carrier substrate, wherein the projection of the solder bumps onto the carrier substrate is located outside the projection of the buffer layer onto the carrier substrate. Remove the carrier substrate to obtain the encapsulation board.

3. The method for fabricating the chip packaging structure as described in claim 2, characterized in that, The step of providing a carrier substrate includes: Provide a temporary carrier board; A release layer is formed on one side of the temporary carrier plate; A bonding layer is formed on the side of the release layer away from the temporary carrier plate to obtain the carrier substrate.

4. The method for fabricating the chip packaging structure as described in claim 3, characterized in that, The step of removing the carrier substrate to obtain the packaging board includes: The bonding layer of the carrier substrate is removed to obtain the packaging board.

5. The method for fabricating the chip packaging structure as described in claim 2, characterized in that, The step of fabricating the solder bumps on the conductive pillars protruding relative to the encapsulation layer and the chip pins of the bridging chip includes: The solder bumps are formed by electroplating on the conductive pillars that protrude relative to the encapsulation layer and on the chip pins of the bridging chip.

6. The method for fabricating the chip packaging structure as described in claim 2, characterized in that, The step of fabricating a buffer layer on the side of the encapsulation layer away from the carrier substrate includes: Provide a layer of cushioning material; The buffer material layer is disposed on the side of the encapsulation layer away from the carrier substrate, and the buffer material layer is positioned around the conductive pillars, the chip pins, and the solder bumps by vacuum lamination to form the buffer layer.

7. A chip packaging structure, characterized in that, The chip packaging structure includes: A glass substrate, wherein one side of the glass substrate includes a connection point; A packaging board includes conductive pillars, solder bumps, a bridging chip, a buffer layer, and a packaging layer. The bridging chip is located within an accommodating space formed by a plurality of conductive pillars. The packaging layer is disposed around the conductive pillars and the bridging chip. The packaging layer includes a first side and a second side. On the first side, the chip pins of the conductive pillars and the bridging chip protrude relative to the surface of the packaging layer. On the second side, the chip pins of the conductive pillars and the bridging chip are flush with the surface of the packaging layer. The solder bumps are respectively connected to the conductive pillars and the chip pins of the bridging chip that protrude relative to the surface of the packaging layer. The buffer layer is located on the first side of the packaging layer, and the orthographic projection of the solder bumps on the packaging layer is outside the orthographic projection of the buffer layer on the packaging layer. A wiring layer is located on the side of the packaging board away from the glass substrate, and the wiring layer is electrically connected to the conductive pillars and the bridging chip of the packaging board. A chip layer is located on the side of the wiring layer away from the glass substrate. The chip layer includes at least one chip and a molding compound surrounding the chip. The chip is electrically connected to the wiring in the wiring layer.

8. The chip packaging structure as described in claim 7, characterized in that, The solder bumps on the packaging board are correspondingly set to the connection points, and the conductive pillars and the chip pins of the bridging chip are also correspondingly set to the connection points.

9. The chip packaging structure as described in claim 7, characterized in that, In the direction of the plane where the glass substrate is located, the width of the accommodating space is greater than the distance between adjacent conductive pillars; In the direction of the plane where the glass substrate is located, the conductive pillars are evenly distributed on both sides of the bridging chip; The buffer layer includes a non-conductive adhesive film.

10. An electronic device, characterized in that, The electronic device includes the chip packaging structure described in any one of claims 7-9.

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