A semiconductor package structure and a manufacturing method thereof

Abstract

The application provides a semiconductor packaging structure and a preparation method, which increases the thickness of an interposer, and greatly improves the structural strength and reliability. The semiconductor packaging structure comprises a silicon bridge chip, an organic filling layer and a silicon bridge chip peripheral metal pillar group. The silicon bridge chip comprises a chip body, an upper surface metal pillar and a lower surface metal pillar. The silicon bridge chip peripheral metal pillar group comprises at least two groups of metal pillars from a radial inner periphery to a radial outer periphery. N groups of metal pillar groups are arranged from inside to outside on the periphery of the silicon bridge chip, N is a natural number greater than or equal to 2, the metal pillars in the metal pillar group close to the radial inner periphery are obtained by one-time electroplating of the Nth time, the metal pillars in the metal pillar group close to the radial inner periphery are obtained by two-time combination of the Nth time electroplating and the N-1th time electroplating, and the metal pillars in the metal pillar group farthest to the radial outer periphery are obtained by combination of all N times of electroplating. The organic filling layer fills the three-dimensional space formed by the combination of the silicon bridge chip and the silicon bridge chip peripheral metal pillar group.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor packaging, specifically to a semiconductor packaging structure, and also provides a method for preparing the packaging structure. Background Technology

[0002] In the prior art, the 2.5D encapsulation organic interposer structure is shown below. Figure 1 This structure uses organic material 60 to seal the copper pillar 10 and silicon bridge chip 20 together, and then thins the front and back sides to expose the metals (10, 30, 40) at different positions simultaneously to achieve signal conduction. However, due to the limitations of photolithography (coating, exposure, development) and electroplating technology, the height uniformity of the copper pillar 10 is often very poor. At the same time, the stacking thickness of the photoresist is limited, making it difficult to increase the height of the copper pillar 10. The final height is often less than 100um, and the structural strength is extremely fragile. In addition, due to the very thin thickness of the interposer, the fabrication process of the silicon bridge chip 20 for signal conduction is extremely difficult. For example, the thickness of the chip after thinning is usually less than 70um, and the yield of processes such as thinning, temporary bonding and debonding, and mounting is often difficult to guarantee. Summary of the Invention

[0003] To address the aforementioned problems, this invention provides a semiconductor packaging structure that increases the thickness of the interposer layer, thereby significantly improving structural strength and reliability.

[0004] A semiconductor packaging structure, characterized in that it comprises: A silicon bridge chip, comprising a chip body, upper surface metal pillars, and lower surface metal pillars; Organic filler layer; And the peripheral metal pillar group of the silicon bridge chip, which includes at least two groups of metal pillar groups from the radial inner perimeter to the radial outer perimeter; The silicon bridge chip has N groups of metal pillars arranged from the inside out, where N is a natural number greater than or equal to 2. The metal pillars in the radially inner metal pillar group are obtained in one electroplating process. The metal pillars in the metal pillar group closer to the radially inner metal pillar group are obtained by combining the Nth and N-1th electroplating processes, and so on. The metal pillars in the outermost radial metal pillar group are obtained by combining all N electroplating processes. The organic filling layer fills the three-dimensional space formed by the silicon bridge chip and the metal pillar groups around the silicon bridge chip. The outer end faces of the metal pillar groups around the silicon bridge chip, as well as the upper and lower surface metal pillars of the silicon bridge chip, are exposed on the upper or lower surface of the organic filling layer.

[0005] Its further features are: When N equals 3, the peripheral metal pillar group of the silicon bridge chip includes a first metal pillar group in the radial inner perimeter, a second metal pillar group in the radial middle perimeter, and a third metal pillar group in the radial outer perimeter. The first metal pillar group, the second metal pillar group, and the third metal pillar group are arranged from the inside to the outside of the silicon bridge chip. The metal pillars in the first metal pillar group are obtained in one go through a third electroplating. The metal pillars in the second metal pillar group are obtained by a combination of a second electroplating and a third electroplating. The metal pillars in the third metal pillar group are obtained by a combination of a first electroplating, a second electroplating, and a third electroplating. The organic filling layer fills the three-dimensional space formed by the silicon bridge chip and the peripheral metal pillar group of the silicon bridge chip. The outer end faces of the peripheral metal pillar group of the silicon bridge chip, as well as the upper and lower surface metal pillars of the silicon bridge chip, are exposed on the upper or lower surface of the organic filling layer.

[0006] Its further characteristic is: A cured adhesive film is also provided around the metal pillars on the lower surface of the chip body. The first metal column group is composed of a first metal column formed by a single electroplating process, and the first metal column is obtained by a third electroplating process. Each metal pillar in the second metal pillar group is formed by stacking and combining a second metal pillar and a third metal pillar. The second metal pillar is located in the lower layer, and the third metal pillar is located in the upper layer. The second metal pillar is obtained by a second electroplating, and the third metal pillar is obtained by a third electroplating. Each metal pillar in the third metal pillar group is composed of a fourth metal pillar, a fifth metal pillar, and a sixth metal pillar stacked from bottom to top. The fourth metal pillar is obtained by a first electroplating, the fifth metal pillar is obtained by a second electroplating, and the sixth metal pillar is obtained by a third electroplating. Because the electroplating rate of the metal pillars around the silicon bridge chip gradually slows down, the original structure, which could not obtain a high metal pillar in a single electroplating process, was changed to a successive electroplating process that gradually compensates for the height of the metal pillars from the periphery to the inner periphery. Through the multi-step electroplating method and packaging structure, the problem of the difficulty in making the copper pillars high can be fundamentally solved.

[0007] A method for fabricating a semiconductor packaging structure is characterized by: firstly, a temporary bonding layer is coated on a carrier glass substrate, then a metal seed layer is deposited, and then metal pillars of nearly uniform height are formed on the seed layer through multi-step photolithography, electroplating, and resist removal. Then, a silicon bridge chip is attached to a designated position on the metal seed layer. After molding, the substrate is thinned until the metal pillars in different areas on the front side of the interposer are simultaneously exposed. Then, the carrier glass is removed, and the metal pillars on the back side of the interposer are simultaneously exposed through etching and thinning to achieve signal conduction.

[0008] Its further feature is that it includes the following steps: S1, a temporary bonding layer is made on the glass by coating, and then a metal seed layer is made on the temporary bonding layer by physical vapor deposition. S2, a photoresist opening is made on the surface of the metal seed layer by coating, exposure and development. The photoresist opening is located in several rings on the outermost side of the silicon bridge chip. Then, a fourth metal pillar is formed at the photoresist opening by the first electroplating. The photoresist is then removed by the photoresist removal solution. S3, photoresist openings are made on the surface of the metal seed layer and the fourth metal pillar by coating, exposure and development. Because the electroplating rate is slower at the second outer edge of the chip, the photoresist openings are located in several rings from the outermost to the second outer edge of the chip. Then, the fifth metal pillar and the second metal pillar are formed at the photoresist openings by the second electroplating. The photoresist is then removed by the photoresist removal solution. S4. Photoresist openings are made on the surface of the metal seed layer, the five metal pillars and the second metal pillar by coating, exposure and development. The electroplating rate is faster on the inner side of the chip. The photoresist openings are located at all positions that need to conduct signals from the outermost to the innermost side of the chip. Then, the first metal pillar, the third metal pillar and the sixth metal pillar are formed at the photoresist openings by a third electroplating. Then, the photoresist is removed by a photoresist remover. S5, using an adhesive film, the silicon bridge chip is attached to the center of the metal seed layer surface in a positive mounting manner, and then the adhesive film is cured by baking; S6, using organic filler material to seal the silicon bridge chip peripheral metal pillar group and silicon bridge chip together by plastic encapsulation, and then exposing the upper part of the silicon bridge chip peripheral metal pillar group and the upper surface metal pillars of the silicon bridge chip simultaneously by mechanical thinning. S7. A laser is used to modify the temporary bonding layer by passing through the glass. Then, a chuck is used to detach the glass under a certain pulling force. The modified temporary bonding layer is then removed by plasma dry etching. The metal seed layer is then removed by etching solution. Finally, the lower part of the metal pillar group around the silicon bridge chip and the metal pillars on the lower surface of the silicon bridge chip are exposed simultaneously by mechanical thinning to achieve signal conduction. This completes the preparation of the organic interposer.

[0009] Its further characteristic is: In step S5, the upper and lower surface metal pillars of the silicon bridge chip are formed by first depositing a transition metal seed layer on the upper surface through physical vapor deposition, then making photoresist openings on the corresponding transition metal seed layer surface through coating, exposure, and development, and then forming the corresponding upper and lower surface metal pillars at the photoresist openings through electroplating, then removing the photoresist with a photoresist remover, and finally removing the transition metal seed layer with a metal etching solution.

[0010] Compared to the existing semiconductor packaging structure's organic interposer layer, which uses a one-step electroplating technique and may cause a series of problems, such as the embedded silicon bridge chip being very thin after thinning, and the low yield of processes such as thinning, temporary bonding and debonding, and die mounting, the multi-step electroplating technique of this invention is simple, easy to implement, and has high process yield and mass production stability. At the same time, the interposer layer thickness is increased, and the structural strength and reliability are greatly improved. Attached Figure Description

[0011] Figure 1 A schematic diagram of the interposer structure in a prior art semiconductor packaging structure; Figure 2 This is a cross-sectional schematic diagram of the semiconductor packaging structure of the present invention and a simplified schematic diagram of step S7 of the preparation method; Figure 3 This is a schematic diagram of step S1 of the preparation method in a specific embodiment of the present invention; Figure 4 This is a simplified schematic diagram of step S2 of the preparation method in a specific embodiment of the present invention; Figure 5 This is a simplified schematic diagram of step S3 of the preparation method in a specific embodiment of the present invention; Figure 6 This is a simplified schematic diagram of step S4 of the preparation method in a specific embodiment of the present invention; Figure 7 This is a simplified schematic diagram of step S5 of the preparation method in a specific embodiment of the present invention; Figure 8 This is a schematic diagram of step S6 of the preparation method in a specific embodiment of the present invention. Detailed Implementation

[0012] A semiconductor packaging structure, see Figure 2 It includes a silicon bridge chip 700, an organic filling layer 800, and a metal pillar group surrounding the silicon bridge chip; The silicon bridge chip 700 includes a chip body, an upper surface metal pillar 701, and a lower surface metal pillar 702; The silicon bridge chip peripheral metal pillar group includes at least two groups of metal pillars from the radial inner perimeter to the radial outer perimeter; The silicon bridge chip 700 has N groups of metal pillars arranged from the inside out, where N is a natural number greater than or equal to 2. The metal pillars in the radial inner group are obtained in one electroplating process. The metal pillars in the metal pillar groups close to the radial inner group are obtained by combining the Nth and N-1th electroplating processes, and so on. The metal pillars in the outermost radial group are obtained by combining all N electroplating processes. An organic filling layer fills the three-dimensional space formed by the silicon bridge chip and the metal pillar groups around the silicon bridge chip. The outer end faces of the metal pillar groups around the silicon bridge chip, as well as the upper and lower surface metal pillars of the silicon bridge chip, are exposed on the upper or lower surface of the organic filling layer.

[0013] In a specific embodiment, N equals 3. At this time, the peripheral metal pillar group of the silicon bridge chip includes a first metal pillar group in the radial inner circle, a second metal pillar group in the radial middle circle, and a third metal pillar group in the radial outer circle. The first metal pillar group, the second metal pillar group, and the third metal pillar group are arranged from the inside to the outside of the silicon bridge chip. The metal pillars in the first metal pillar group are obtained in one go through a third electroplating. The metal pillars in the second metal pillar group are obtained by combining the second and third electroplating. The metal pillars in the third metal pillar group are obtained by combining the first, second, and third electroplating. The organic filling layer 800 fills the three-dimensional space formed by the silicon bridge chip 700 and the peripheral metal pillar group of the silicon bridge chip. The outer end faces of the peripheral metal pillar group of the silicon bridge chip, as well as the upper surface metal pillar 701 and the lower surface metal pillar 702 of the silicon bridge chip 700, are exposed on the upper or lower surface of the organic filling layer.

[0014] In practice, a cured adhesive film 703 is also provided around the metal pillars on the lower surface of the chip body. The first metal column group is composed of a first metal column 600 formed by electroplating in one step, and the first metal column 600 is obtained by a third electroplating. Each metal pillar in the second metal pillar group is formed by stacking and combining the second metal pillar 501 and the third metal pillar 601. The second metal pillar 501 is located in the lower layer and the third metal pillar 601 is located in the upper layer. The second metal pillar 501 is obtained by a second electroplating and the third metal pillar 601 is obtained by a third electroplating. Each metal column in the third metal column group is composed of a fourth metal column 400, a fifth metal column 500, and a sixth metal column 602 stacked from bottom to top. The fourth metal column 400 is obtained by the first electroplating, the fifth metal column 500 is obtained by the second electroplating, and the sixth metal column 602 is obtained by the third electroplating. Because the electroplating rate of the metal pillars around the silicon bridge chip 700 gradually slows down, the original structure that could not obtain a high metal pillar in a single electroplating process has been changed to a successive electroplating process that gradually compensates for the height of the metal pillars from the periphery to the inner periphery. Through the multi-step electroplating method and packaging structure, the problem of the difficulty in making the copper pillars high can be fundamentally solved.

[0015] A method for fabricating a semiconductor packaging structure, see Figures 2-8 First, a temporary bonding layer 200 is coated on the carrier glass 100, and then a metal seed layer 300 is deposited. Then, through multi-step photolithography, electroplating, and resist removal, metal pillars of nearly uniform height are formed on the seed layer. Then, the silicon bridge chip 700 is attached to the designated position on the metal seed layer 300. After molding, it is thinned until the metal pillars in different areas on the front side of the interposer are exposed simultaneously. Then, the carrier glass 100 is removed, and then the metal pillars on the back side of the interposer are exposed simultaneously through etching and thinning to achieve signal conduction.

[0016] It includes the following steps: S1, a temporary bonding layer 200 is formed on glass 100 by coating, and then a metal seed layer 300 is formed on the temporary bonding layer 200 by physical vapor deposition. S2, a photoresist opening is made on the surface of the metal seed layer 300 by coating, exposure and development. The photoresist opening is located in several rings on the outermost part of the chip. Then, a fourth metal pillar 400 is formed at the photoresist opening by the first electroplating. Then, the photoresist is removed by the photoresist removal solution. S3, photoresist openings are made on the surface of the metal seed layer 300 and the fourth metal pillar 400 by coating, exposure and development. Because the electroplating rate is slower at the second outer edge of the chip, the photoresist openings are located in several rings from the outermost to the second outer edge of the chip. Then, the fifth metal pillar 500 and the second metal pillar 501 are formed at the photoresist openings by a second electroplating. Then, the photoresist is removed by a photoresist remover. S4. Photoresist openings are made on the surface of the metal seed layer 300, the fifth metal pillar 500 and the second metal pillar 501 by coating, exposure and development. The electroplating rate is faster on the inner side of the chip. The photoresist openings are located at all positions that need to conduct signals from the outermost to the innermost side of the chip. Then, the first metal pillar 600, the third metal pillar 601 and the sixth metal pillar 602 are formed at the photoresist openings by a third electroplating. Then, the photoresist is removed by a photoresist remover solution. S5, using the adhesive film 703, the silicon bridge chip 700 is attached to the center of the metal seed layer 300 surface in a positive mounting manner, and then the adhesive film 703 is cured by baking. S6, using organic filler material 800 to seal the silicon bridge chip peripheral metal pillar group and silicon bridge chip 700 together by plastic encapsulation, and then exposing the upper part of the silicon bridge chip peripheral metal pillar group and the upper surface metal pillar 701 of the silicon bridge chip simultaneously by mechanical thinning. S7. A laser is used to penetrate the glass 100 to modify the temporary bonding layer 200. Then, a chuck is used to detach the glass 100 under a certain pulling force. The modified temporary bonding layer 200 is then removed by plasma dry etching. The metal seed layer 300 is then removed by etching solution. Finally, the lower part of the metal pillar group around the silicon bridge chip and the metal pillar 702 on the lower surface of the silicon bridge chip are simultaneously exposed by mechanical thinning to achieve signal conduction. This completes the preparation of the organic interposer.

[0017] In step S5, the upper surface metal pillars 701 and lower surface metal pillars 702 of the silicon bridge chip 700 are formed by first depositing a transition metal seed layer on the upper surface by physical vapor deposition, then making photoresist openings on the corresponding transition metal seed layer by coating, exposure and development, then forming the corresponding upper surface metal pillars 701 and lower surface metal pillars 702 at the photoresist openings by electroplating, then removing the photoresist by a photoresist remover, and finally removing the transition metal seed layer by a metal etching solution.

[0018] Compared to the existing semiconductor packaging structure's organic interposer layer, which uses a one-step electroplating technique and may cause a series of problems, such as the embedded silicon bridge chip being very thin after thinning, and the low yield of processes such as thinning, temporary bonding and debonding, and die mounting, the multi-step electroplating technique of this invention is simple, easy to implement, and has high process yield and mass production stability. At the same time, the interposer layer thickness is increased, and the structural strength and reliability are greatly improved.

[0019] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0020] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A semiconductor packaging structure, characterized in that, It includes: A silicon bridge chip, comprising a chip body, upper surface metal pillars, and lower surface metal pillars; Organic filler layer; And the peripheral metal pillar group of the silicon bridge chip, which includes at least two groups of metal pillar groups from the radial inner perimeter to the radial outer perimeter; The silicon bridge chip has N groups of metal pillars arranged from the inside out, where N is a natural number greater than or equal to 2. The metal pillars in the radially inner metal pillar group are obtained in one electroplating process. The metal pillars in the metal pillar group closer to the radially inner metal pillar group are obtained by combining the Nth and N-1th electroplating processes, and so on. The metal pillars in the outermost radial metal pillar group are obtained by combining all N electroplating processes. The organic filling layer fills the three-dimensional space formed by the silicon bridge chip and the metal pillar groups around the silicon bridge chip. The outer end faces of the metal pillar groups around the silicon bridge chip, as well as the upper and lower surface metal pillars of the silicon bridge chip, are exposed on the upper or lower surface of the organic filling layer.

2. The semiconductor packaging structure according to claim 1, characterized in that: When N equals 3, the peripheral metal pillar group of the silicon bridge chip includes a first metal pillar group in the radial inner perimeter, a second metal pillar group in the radial middle perimeter, and a third metal pillar group in the radial outer perimeter. The first metal pillar group, the second metal pillar group, and the third metal pillar group are arranged from the inside to the outside of the silicon bridge chip. The metal pillars in the first metal pillar group are obtained in one go through a third electroplating. The metal pillars in the second metal pillar group are obtained by a combination of a second electroplating and a third electroplating. The metal pillars in the third metal pillar group are obtained by a combination of a first electroplating, a second electroplating, and a third electroplating. The organic filling layer fills the three-dimensional space formed by the silicon bridge chip and the peripheral metal pillar group of the silicon bridge chip. The outer end faces of the peripheral metal pillar group of the silicon bridge chip, as well as the upper and lower surface metal pillars of the silicon bridge chip, are exposed on the upper or lower surface of the organic filling layer.

3. A semiconductor packaging structure according to claim 2, characterized in that: A cured adhesive film is also provided around the metal pillars on the lower surface of the chip body.

4. A semiconductor packaging structure according to claim 2, characterized in that: The first metal column group is composed of a first metal column formed by electroplating in one step, and the first metal column is obtained by a third electroplating.

5. A semiconductor packaging structure according to claim 2, characterized in that: The first metal column group is composed of a first metal column formed by electroplating in one step, and the first metal column is obtained by a third electroplating.

6. A semiconductor packaging structure according to claim 2, characterized in that: Each metal column in the third metal column group is composed of a fourth metal intermediate layer structure column, a fifth metal column, and a sixth metal column stacked from bottom to top. The fourth metal column is obtained by a first electroplating, the fifth metal column is obtained by a second electroplating, and the sixth metal column is obtained by a third electroplating.

7. A method for fabricating a semiconductor packaging structure, used to fabricate an interposer structure as described in any one of claims 1-6, characterized in that: First, a temporary bonding layer is coated on the carrier glass, and then a metal seed layer is deposited. Then, through multiple steps of photolithography, electroplating, and resist removal, metal pillars of nearly uniform height are formed on the seed layer. The silicon bridge chip is then attached to the designated position on the metal seed layer. After molding, the layer is thinned until the metal pillars in different areas on the front side of the interposer are exposed simultaneously. Then, the carrier glass is removed, and etching and thinning processes are used to expose the metal pillars on the back side of the interposer simultaneously to achieve signal conduction.

8. The method for fabricating a semiconductor packaging structure according to claim 7, characterized in that, It includes the following steps: S1, a temporary bonding layer is made on the glass by coating, and then a metal seed layer is made on the temporary bonding layer by physical vapor deposition. S2, a photoresist opening is made on the surface of the metal seed layer by coating, exposure and development. The photoresist opening is located in several rings on the outermost side of the silicon bridge chip. Then, a fourth metal pillar is formed at the photoresist opening by the first electroplating. The photoresist is then removed by the photoresist removal solution. S3, photoresist openings are made on the surface of the metal seed layer and the fourth metal pillar by coating, exposure and development. Because the electroplating rate is slower at the second outer edge of the chip, the photoresist openings are located in several rings from the outermost to the second outer edge of the chip. Then, the fifth metal pillar and the second metal pillar are formed at the photoresist openings by the second electroplating. The photoresist is then removed by the photoresist removal solution. S4. Photoresist openings are made on the surface of the metal seed layer, the fifth metal pillar and the second metal pillar by coating, exposure and development. The electroplating rate is faster on the inner side of the chip. The photoresist openings are located at all positions that need to conduct signals from the outermost to the innermost side of the chip. Then, the first metal pillar, the third metal pillar and the sixth metal pillar are formed at the photoresist openings by a third electroplating. Then, the photoresist is removed by a photoresist remover solution. S5, using an adhesive film, the silicon bridge chip is attached to the center of the metal seed layer surface in a positive mounting manner, and then the adhesive film is cured by baking; S6, using organic filler material to seal the silicon bridge chip peripheral metal pillar group and silicon bridge chip together by plastic encapsulation, and then exposing the upper part of the silicon bridge chip peripheral metal pillar group and the upper surface metal pillars of the silicon bridge chip simultaneously by mechanical thinning. S7. A laser is used to modify the temporary bonding layer by passing through the glass. Then, a chuck is used to detach the glass under a certain pulling force. The modified temporary bonding layer is then removed by plasma dry etching. The metal seed layer is then removed by etching solution. Finally, the lower part of the metal pillar group around the silicon bridge chip and the metal pillars on the lower surface of the silicon bridge chip are exposed simultaneously by mechanical thinning to achieve signal conduction. This completes the preparation of the organic interposer.

9. The method for fabricating a semiconductor packaging structure according to claim 8, characterized in that: In step S5, the upper and lower surface metal pillars of the silicon bridge chip are formed by first depositing a transition metal seed layer on the upper surface through physical vapor deposition, then making photoresist openings on the corresponding transition metal seed layer surface through coating, exposure, and development, and then forming the corresponding upper and lower surface metal pillars at the photoresist openings through electroplating, then removing the photoresist with a photoresist remover, and finally removing the transition metal seed layer with a metal etching solution.

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