Power module and power conversion device

Abstract

A power module and a power conversion device, the power module comprising a first substrate and a second substrate arranged at a distance from each other, a plurality of power chips, a plurality of connecting pieces corresponding to the plurality of power chips one by one, and a bonding wire, the first substrate being provided with the plurality of power chips. One end of the connecting piece is connected with the power chip away from one side of the first substrate, the other end of the connecting piece is connected with the second substrate, and the adjacent two power chips on the same substrate are connected by the bonding wire. The two parallel and adjacent power chips are connected by the bonding wire in a straight line path, which greatly reduces the parasitic inductance between the parallel chips, reduces the risk of high-frequency oscillation of the power module in the switching process and short-circuit working condition under high voltage and large current.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a power module and a power conversion device. Background Technology

[0002] With the rapid development of technologies such as electric vehicles and intelligent driving, the automotive industry's demand for power modules is increasing, driving the development of power modules towards higher integration, higher power density, and higher junction temperature, especially silicon carbide modules, which possess excellent performance characteristics such as high efficiency, high frequency, and high temperature. Power modules are the core of efficient energy conversion and driving in electric and hybrid vehicles, achieving efficient control and distribution of electrical energy through the integration of high-power semiconductor devices.

[0003] The current carrying capacity of a single power chip in a power module cannot meet the demand for high power output. In order to increase the rated current of the power module, multiple power chips are usually connected in parallel. However, the interconnection of multiple power chips inside the power module can easily lead to a high parasitic inductance, causing the power chip to withstand a high overvoltage during switching, which increases the risk of high-frequency oscillation of the power chip. Summary of the Invention

[0004] This application provides a power module and power conversion device that can reduce the parasitic inductance between power chips, thereby reducing the risk of high-frequency oscillation during switching under high voltage and high current conditions and under short-circuit conditions.

[0005] In a first aspect, this application provides a power module, which includes a first substrate and a second substrate spaced apart from each other, a plurality of power chips, a plurality of connecting pieces corresponding one-to-one with the plurality of power chips, and bonding wires. The first substrate is provided with the plurality of power chips. One end of the connecting piece is connected to the side of the power chip facing away from the first substrate, and the other end of the connecting piece is connected to the second substrate. Two adjacent power chips located on the same substrate are connected by bonding wires.

[0006] In this application, multiple chips on the same substrate are connected in parallel, and two adjacent power chips are connected in a straight path by bonding wires. This greatly reduces the parasitic inductance between the parallel power chips, thereby reducing the risk of high-frequency oscillation during the switching process under high voltage and high current and under short-circuit conditions. Furthermore, each connector only connects to one power chip, which reduces the stress on the power chips compared to a connector connecting multiple power chips.

[0007] In conjunction with the first aspect, in one implementation, the bonding wire is located at one end of the connector, facing away from the power chip.

[0008] It can significantly reduce parasitic inductance, thereby effectively suppressing voltage overshoot and switching losses. At the same time, compared to bonding wires being directly connected to the surface of the power chip, it can also reduce the surface stress on the power chip when the bonding wires are connected to the power chip.

[0009] In conjunction with the first aspect, in one implementation, the power module further includes a first metal pillar, which is disposed on the side of the power chip facing away from the first substrate, and the side of the first metal pillar facing away from the power chip is connected to one end of the connecting piece.

[0010] By adding a first metal pillar to the surface of the power chip, the transient heat dissipation capability of the power chip can be effectively improved, thereby effectively suppressing transient junction temperature fluctuations and reducing the occurrence of minor displacements in bonding lines or solder joints. Furthermore, the first metal pillar has a large heat capacity, which is beneficial for heat dissipation of the power chip. The interconnecting tabs are connected to the power chip via the first metal pillar. Compared to directly connecting the power chip surface via the interconnecting tabs, this significantly reduces surface stress on the power chip and lowers the risk of solder cracking on the power chip surface.

[0011] In conjunction with the first aspect, in one implementation, the coefficient of thermal expansion of the first metal column is less than that of the connecting piece.

[0012] The thermal expansion coefficient of the first metal pillar is close to that of the power chip. For example, the thermal expansion coefficient of the first metal pillar can be less than or greater than that of the power chip. However, the thermal expansion coefficient of the first metal pillar is always less than that of the connecting piece. This can efficiently dissipate heat while reducing the impact of thermal deformation on the power chip, effectively improving the transient heat dissipation capability of the power chip and thus suppressing transient junction temperature fluctuations.

[0013] In conjunction with the first aspect, in one implementation, the material of the metal pillar includes aluminum silicon carbide or molybdenum copper alloy.

[0014] In conjunction with the first aspect, in one implementation, the power module further includes a connection layer. The connection layer is disposed between the first metal pillar and the connecting piece and connects and fixes the first metal pillar and the connecting piece. The positive projection area of ​​the connection layer along the arrangement direction of the substrate and the power chip on the first substrate is less than or equal to the surface area of ​​the first metal pillar away from the first substrate.

[0015] The connecting piece is connected to the side of the first metal pillar facing away from the first substrate through a connecting layer. That is, the weldable area between the connecting piece and the first metal pillar is less than or equal to the surface area of ​​the first metal pillar facing away from the first substrate, thereby reducing the welding area between the first metal pillar and the connecting piece. This prevents excessive pressure on the power chip caused by welding too many connecting pieces, thus reducing the surface stress on the power chip and ensuring the structural life of the power chip.

[0016] In conjunction with the first aspect, in one implementation, the power module further includes a second metal pillar that connects the second substrate and the other end of the connecting piece.

[0017] The second metal pillar can absorb the stress generated by temperature changes at the other end of the connector and the second substrate, effectively reducing the risk of cracking of the connector and the substrate. In addition, the second metal pillar has good thermal conductivity, which can conduct heat from the connector to the second substrate, improving heat dissipation and thus improving the reliability of the power module.

[0018] In conjunction with the first aspect, in one implementation, the coefficient of thermal expansion of the second metal column is greater than that of the first metal column.

[0019] That is, the coefficient of thermal expansion of the first metal pillar is lower than that of the second metal pillar, which enables the first metal pillar to achieve efficient heat dissipation of the power chip, while also reducing the impact of thermal deformation on the power chip, improving the transient heat dissipation capability of the power chip and thus suppressing transient junction temperature fluctuations.

[0020] In conjunction with the first aspect, in one implementation, the connecting piece is provided with a first through hole, which penetrates two sides of the connecting piece opposite to the arrangement direction of the first substrate and the power chip, and the orthographic projection of the first through hole on the first substrate partially coincides with the orthographic projection of the first metal pillar on the first substrate.

[0021] Without affecting the connection and fixation between the connecting piece and the first metal post, a first through hole is provided at the connection position between the connecting piece and the first metal post. This reduces the stress on the connecting piece at the first metal post. The first through hole can absorb deformation, reducing the possibility of the connecting piece breaking due to excessive stress and ensuring the structural life of the connecting piece. Furthermore, the first through hole can reduce the loop area of ​​the current path, thereby reducing parasitic inductance and improving the performance of the power chip.

[0022] In conjunction with the first aspect, in one implementation, the connecting piece is further provided with a second through hole and a bending portion. The second through hole penetrates two sides of the connecting piece that are opposite to the arrangement direction of the first substrate and the power chip. One end of the connecting piece is further away from the first substrate than the other end of the connecting piece along the arrangement direction of the first substrate and the power chip. The bending portion is located between one end of the connecting piece and the other end of the connecting piece and is bent relative to one end of the connecting piece. The bending portion is provided with the second through hole.

[0023] Since one end of the connector is connected to the side of the power chip facing away from the first substrate, and the other end is connected to the first substrate, there is a height difference between the two ends. A bend is provided between the two ends of the connector to ensure the stability of the connection. A second through hole is provided at the bend of the connector to effectively reduce the bending stress at the bend, reduce or avoid the connector from breaking due to excessive stress, and ensure the overall performance and reliability of the power module.

[0024] In conjunction with the first aspect, in one implementation, the second substrate is provided with multiple power chips, each power chip on the second substrate is connected to a corresponding connecting piece, the power chips on the first substrate and the power chips on the second substrate are staggered, and the other end of the connecting piece connecting the power chips on the first substrate is located between two adjacent power chips on the second substrate.

[0025] The staggered arrangement of the power chips on the first substrate and the second substrate means that the orthographic projections of the power chips on the first substrate along the alignment direction of the first and second substrates do not overlap. This reduces the complexity of the connection process caused by the power chips on the first and second substrates being directly aligned, which is beneficial for miniaturization design. It also helps to even out the temperature distribution of different power chips, reducing or avoiding localized hotspot concentration and improving heat dissipation efficiency. Furthermore, the other end of the connector connecting the power chips on the first substrate is located between two adjacent power chips on the second substrate, which can effectively improve the integration of the power module.

[0026] In conjunction with the first aspect, in one implementation, the power module further includes a third substrate, with a second substrate disposed between the third substrate and the first substrate. The third substrate has multiple power chips, and each power chip on the third substrate is connected to the second substrate via a connecting piece. The other end of the connecting piece connecting the power chips on the third substrate is located between two adjacent power chips on the second substrate. The power chips on the first substrate and the third substrate are aligned.

[0027] The other end of the connector connecting the power chip on the third substrate is located between two adjacent power chips on the second substrate, which can improve the integration of the power module. Furthermore, the alignment of the power chips on the first and third substrates means that the power chips on the two substrates are symmetrically arranged, which is beneficial for improving the balance of dynamic current of each power chip.

[0028] In conjunction with the first aspect, in one implementation, the power chip on the third substrate is staggered from the power chip on the second substrate.

[0029] That is, the orthographic projection of the power chip on the third substrate along the arrangement direction of the first and second substrates does not overlap with the orthographic projection of the power chip on the second substrate along the arrangement direction of the first and second substrates. In this way, the connection process of the connector is less likely to be complicated due to the power chip on the third substrate being directly opposite the power chip on the second substrate, which is beneficial for miniaturization design. At the same time, it is also beneficial to balance the temperature distribution of different power chips, reduce or avoid local hot spot concentration, and improve heat dissipation efficiency.

[0030] In conjunction with the first aspect, in one implementation, the spacing between two adjacent power chips on the same substrate is equal.

[0031] This ensures that the bonding wires connecting two adjacent power chips have equal lead lengths, which helps to balance the current paths of each power chip, reduce the differences in parasitic parameters between power chips, and improve the dynamic current sharing characteristics of parallel power chips.

[0032] In conjunction with the first aspect, in one implementation, the second substrate includes two extension arms spaced apart from each other, with power chips on the different extension arms of the second substrate aligned.

[0033] The symmetrical arrangement of power chips on the two extension arms on the second substrate helps to reduce the difference in current paths of power chips on the same substrate, thereby improving the balance of dynamic current. At the same time, it makes the parasitic inductance of each branch more consistent, which helps to reduce the difference in current spikes during switching.

[0034] In conjunction with the first aspect, in one implementation, the power module further includes a fourth substrate, which is disposed between two extension arms of the second substrate, and the fourth substrate is connected to the power chip on the extension arm of the second substrate via a connecting piece.

[0035] Secondly, this application provides a power conversion device, which includes a circuit board and a power module as implemented in any of the first aspects, wherein the power module is disposed on the circuit board.

[0036] Thirdly, this application provides a powertrain including an electric motor and a power conversion device as provided in the second aspect, wherein the power converter is used to convert input direct current into alternating current and transmit the converted alternating current to the electric motor.

[0037] Fourthly, this application provides a vehicle including wheels and a powertrain as provided in the third aspect, the powertrain driving the wheels to rotate. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0039] Figure 1 This is a schematic diagram of the structure of a vehicle provided in one embodiment of this application;

[0040] Figure 2 This is a schematic diagram of the system architecture of a vehicle provided in an embodiment of this application;

[0041] Figure 3 This is a schematic diagram of the structure of a power module provided in one embodiment of this application;

[0042] Figure 4 This is a schematic diagram of another power module provided in an embodiment of this application;

[0043] Figure 5 This is a schematic diagram of the structure of a power chip provided in an embodiment of this application;

[0044] Figure 6 This is a schematic diagram of the structure of a power module provided in one embodiment of this application;

[0045] Figure 7 for Figure 6 A schematic diagram of the cross-sectional structure of the power module along line VII-VII;

[0046] Figure 8 This is a schematic diagram showing the power chip at points "A" and "B" in a power module of the prior art and the power chip at points "C" and "D" in the power module provided in this application;

[0047] Figure 9 for Figure 8 The stress comparison diagram of the two power modules is shown;

[0048] Figure 10 A comparison diagram of solder simulation at point "U" for a power module of the prior art and at points "V" and "W" for a power module provided in this application;

[0049] Figure 11 for Figure 10 A schematic diagram showing the changes in the plastic strain energy of the solder at points "U", "V", and "W" in the middle.

[0050] Figure 12 This is an enlarged schematic diagram of the power module portion provided in one embodiment of this application.

[0051] Explanation of reference numerals in the attached figures:

[0052] X - First direction; Y - Second direction; Z - Third direction; 10 - Circuit board; 20 - Power module; 21a - First substrate; 21b - Second substrate; 21c - Third substrate; 21d - Fourth substrate; 211 - Extension arm; 212 - Connector; 22 - Power chip; 221 - Source; 221a - First source; 221b - Second source; 222 - Gate; 2221 - Gate trace; 223 - Kelvin source; 224 - Upper bridge arm chip; 225 - Lower bridge arm chip; 23 - Connector piece; 231 232-First through hole; 233-Second through hole; 234-Bend; 235-Third through hole; 24-Bond wire; 25-First metal pillar; 251-First contact portion; 252-Allowing groove; 253-Second contact portion; 26-Connecting layer; 27-Second metal pillar; 30-Filter; 100-Power conversion device; 200-Motor; 201-Motor motor; 202-Heat exchanger; 300-Reducer; 1000-Vehicle; 1001-Power battery; 1002-Powertrain; 1003-Vehicle controller. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0054] Please see Figure 1 and Figure 2 , Figure 1 This is a structural schematic diagram of a vehicle 1000 provided in an embodiment of this application. Figure 2 This is a schematic diagram of the system architecture of a vehicle 1000 provided in an embodiment of this application. The vehicle 1000 includes a power battery 1001 and a powertrain 1002. The powertrain 1002 includes a power conversion device 100, a motor 200, and a reducer 300. During vehicle operation, the power conversion device 100 converts the direct current (DC) from the power battery 1001 into alternating current (AC) and supplies the converted AC to the motor 200. The motor 200 drives the wheels of the vehicle 1000 to rotate via the reducer 300. The power battery outputs DC power; for example, the power battery 1001 can be a storage battery, lithium battery, fuel cell, etc. The power conversion device 100 can be used in a motor controller, which can also be called a motor control unit (MCU). The motor 200 can be a permanent magnet synchronous motor, an asynchronous motor, a reluctance motor, or an electrically excited motor, etc.

[0055] In the embodiments of this application, vehicle 1000 may be a wheeled device driven or towed by a power unit. For example, vehicle 1000 includes passenger cars, commercial vehicles or emergency rescue vehicles, electric vehicles (EVs), pure electric vehicles (PEVs / BEVs), hybrid electric vehicles (HEVs), range-extended electric vehicles (REEVs), plug-in hybrid electric vehicles (PHEVs), and new energy vehicles, etc.

[0056] The vehicle 1000 integrates the signals (throttle, brake signals, battery power, vehicle speed and temperature, etc.) received by the vehicle control unit (VCU) 1003, and sends execution commands to the motor controller via the CAN bus. The motor controller controls the output torque and speed of the motor 200, and detects whether the motor controller accurately executes the command control through electric drive adjustment and testing to ensure that the motor 200 matches the motor controller.

[0057] The power conversion device 100 includes a circuit board 10, a power module 20, and a filter 30. The power module 20 is mounted on the circuit board 10. The number of power modules 20 may be one or more, and each power module 20 is used to convert direct current (DC) to alternating current (AC). The filter 30 is connected to the DC input terminal of the power module 20 and is used to smooth out input voltage fluctuations, providing a stable DC voltage for the power module 20. Additionally, the filter 30 can absorb voltage spikes or transient overvoltages at the DC input terminal, preventing damage to power semiconductor devices due to overvoltage or overcurrent, thus extending the lifespan of the power module 20.

[0058] For example, motor 200 includes motor 201 and heat exchanger 202, which is used to dissipate heat from motor 201 and reducer 300. When motor 201 operates under high load, its internal windings and magnets generate a large amount of heat due to current losses. Heat exchanger 202 can dissipate this heat through coolant circulation or airflow, preventing motor 201 from overheating, which could lead to decreased efficiency, insulation aging, or even burnout. Reducer 300 generates mechanical loss heat during gear meshing and bearing friction. Heat exchanger 202 absorbs this heat, preventing lubricating oil from failing at high temperatures (such as reduced viscosity or oxidation), ensuring adequate lubrication of gears and bearings, and reducing wear.

[0059] Please see Figure 3 , Figure 3 This is a schematic diagram of a power module 20 according to an embodiment of this application. The power module 20 includes a first substrate 21a, a second substrate 21b, power chips 22, connecting pieces 23, and bonding wires 24. The first substrate 21a and the second substrate 21b are spaced apart from each other. The first substrate 21a is provided with a plurality of power chips 22, wherein the number of power chips 22 corresponds one-to-one with the number of connecting pieces 23, that is, each power chip 22 on the first substrate 21a is connected to one connecting piece 23. One end of the connecting piece 23 is connected to the side of the power chip 22 facing away from the first substrate 21a, and the other end of the connecting piece 23 connecting the power chips 22 on the first substrate 21a is connected to the second substrate 21b. Two adjacent power chips 22 located on the same substrate are connected by bonding wires 24, for example, two adjacent power chips 22 on the first substrate 21a are connected by bonding wires 24.

[0060] Multiple chips on the same substrate are connected in parallel, and two adjacent power chips 22 are connected in a straight path by bonding wire 24. This greatly reduces the parasitic inductance between the parallel power chips 22, reducing the risk of high-frequency oscillation in the power module 20 during switching under high voltage and high current and under short-circuit conditions. Furthermore, in this application, each connecting piece 23 connects only one power chip 22, which reduces the stress on the power chip 22 compared to connecting multiple power chips 22 with one connecting piece 23.

[0061] The first substrate 21a and the second substrate 21b can be active metalbrazing (AMB), direct bonded copper (DBC), or direct plated copper (DPC) ceramic substrates. For example, the first substrate 21a and the second substrate 21b are AMB ceramic substrates, which include a ceramic layer and a metal layer. The ceramic layer and the metal layer are stacked along the arrangement direction of the first substrate 21a and the power chip 22. The metal layer can be a copper layer or an aluminum layer, and the specific type is not limited.

[0062] For ease of description, the arrangement direction of the first substrate 21a and the second substrate 21b is denoted as the first direction X, the arrangement direction of the plurality of power chips 22 on the first substrate 21a is denoted as the second direction Y, and the arrangement direction of the first substrate 21a and the power chips 22 on the first substrate 21a is denoted as the third direction Z. The first direction X, the second direction Y and the third direction Z are perpendicular to each other.

[0063] like Figure 3As shown, in one embodiment, each extension arm 211 of the first substrate 21a is provided with a set of chips, and a plurality of power chips 22 in the set of chips are arranged in a row at intervals along the second direction Y. Each power chip 22 is disposed on the first substrate 21a near the edge of the second substrate 21b, so that the size of the connecting piece 23 can be shortened, wherein the connecting piece 23 connects the power chips 22 on the first substrate 21a and the second substrate 21b.

[0064] like Figure 4 As shown, Figure 4 This is a schematic diagram of another power module 20 provided in one embodiment of this application. In other embodiments, a first substrate 21a is provided with multiple chip groups, which are arranged along a first direction X. Each chip group is provided with multiple power chips 22 arranged at intervals along a second direction Y. Adjacent power chips 22 in each chip group are connected by bonding wires 24. When the power chips 22 in two adjacent chip groups are staggered, the staggered arrangement means that the orthographic projection of a power chip 22 in one chip group along the first direction X does not overlap with the orthographic projection of a power chip 22 in an adjacent chip group along the first direction X. A power chip 22 in the same chip group is connected to a power chip 22 in an adjacent chip group by bonding wires 24, and these two power chips 22 are arranged adjacently along the second direction Y. Preferably, between two adjacent chipsets, a power chip 22 in one chipset is connected to a power chip 22 in the other chipset via a bonding wire 24. These two power chips 22 are arranged adjacently along the second direction Y and are the two power chips 22 with the shortest distance along the second direction Y. When each power chip 22 in the two chipsets is arranged opposite and aligned in the first direction X, the two power chips 22 opposite each other along the first direction X are connected via the bonding wire 24; in this way, the parallel power chips 22 are electrically connected through a short straight path, reducing the parasitic inductance between the parallel power chips 22.

[0065] For example, the second substrate 21b is provided with a plurality of power chips 22, and each power chip 22 on the second substrate 21b is connected to a corresponding connecting piece 23. The power chips 22 on the second substrate 21b are staggered from the power chips 22 on the first substrate 21a. The staggered arrangement of the power chips 22 on the first substrate 21a and the power chips 22 on the second substrate 21b means that the orthographic projection of the power chips 22 on the first substrate 21a along the first direction X does not overlap with the orthographic projection of the power chips 22 on the second substrate 21b along the first direction X. In this way, the connection process of the connecting piece 23 is less likely to be complicated due to the power chips 22 on the first substrate 21a and the power chips 22 on the second substrate 21b being directly aligned, which is beneficial for miniaturization design; at the same time, it is also beneficial to balance the temperature distribution of different power chips 22, reduce or avoid local hot spot concentration, and improve heat dissipation efficiency.

[0066] In this application, the other end of the connecting piece 23 that connects to the power chip 22 on the first substrate 21a is located between two adjacent power chips 22 on the second substrate 21b. That is, the other end of the connecting piece 23 is connected to the second substrate 21b, and the other end of the connecting piece 23 is located between two adjacent power chips 22 on the second substrate 21b along the second direction Y. In this way, the integration of the power module can be effectively improved.

[0067] In one embodiment, the second substrate 21b includes two spaced-apart extension arms 211, each with its long side extending along a second direction Y. The two extension arms 211 of the second substrate 21b may both be located on the same side of the first substrate 21a along the first direction X; that is, the first substrate 21a, one extension arm 211 of the second substrate 21b, and the other extension arm 211 of the second substrate 21b are arranged sequentially along the first direction X. The power chip 22 on the first substrate 21a is connected to the extension arm 211 closest to it.

[0068] The two extension arms 211 on the second substrate 21b extend about the central axis of the power module 20 along the second direction Y (e.g., ...). Figure 3 The symmetrical arrangement of the axes (as indicated by L) helps reduce the differences in current paths among the power chips 22, thereby improving the balance of dynamic current. Simultaneously, it makes the parasitic inductance of each branch more consistent, which helps reduce current spike differences during switching. The symmetrical arrangement of the two extension arms 211 on the second substrate 21b creates symmetrical current paths. If the current directions of the two extension arms 211 on the second substrate 21b are opposite, the generated magnetic fields cancel each other out, which helps reduce the parasitic inductance of the power circuit.

[0069] At least one of the two extension arms 211 of the second substrate 21b is provided with a power chip 22. For example, both extension arms 211 on the second substrate 21b are provided with power chips 22, and the power chips 22 on the two extension arms 211 are aligned, that is, the power chips 22 on the two extension arms 211 on the second substrate 21b are also symmetrically arranged, so that the parasitic parameters (resistance, inductance, capacitance, etc.) of each parallel branch on the same substrate are as consistent as possible, reducing the uneven current distribution caused by path differences, which is beneficial to improving dynamic current balance. At the same time, it makes the parasitic inductance of each branch tend to be consistent, which is beneficial to reducing the difference in current spikes during switching.

[0070] For example, the two extension arms 211 of the second substrate 21b are connected together by a connecting part 212. The connecting part 212 is located at one end of the two extension arms 211 of the second substrate 21b along the second direction Y. The two extension arms 211 of the second substrate 21b and the connecting part 212 can be an integral structure or a separate structure. The two extension arms 211 of the second substrate 21b are connected by a connector (copper busbar, copper wire or copper strip, etc.).

[0071] In one embodiment, the power module 20 further includes a third substrate 21c, a second substrate 21b is disposed between the third substrate 21c and the first substrate 21a, the third substrate 21c is provided with a plurality of power chips 22, and each power chip 22 on the third substrate 21c is connected to the second substrate 21b through a connecting piece 23.

[0072] When the second substrate 21b includes two extension arms 211, the first substrate 21a, one extension arm 211 of the second substrate 21b, the other extension arm 211 of the second substrate 21b, and the third substrate 21c are arranged sequentially along the first direction X. Each power chip 22 on the first substrate 21a is connected to one extension arm 211 of the second substrate 21b through a connecting piece 23, and each power chip 22 on the third substrate 21c is connected to the other extension arm 211 of the second substrate 21b through a connecting piece 23.

[0073] In this design, the power chip 22 on the third substrate 21c is staggered from the power chip 22 on the second substrate 21b. That is, the orthographic projection of the power chip 22 on the third substrate 21c along the first direction X does not overlap with the orthographic projection of the power chip 22 on the second substrate 21b along the first direction X. This reduces the complexity of the connection process of the connecting piece 23 due to the power chip 22 on the third substrate 21c being directly opposite the power chip 22 on the second substrate 21b, which is beneficial for miniaturization design. At the same time, it also helps to balance the temperature distribution of different power chips 22, reduce or avoid local hot spot concentration, and improve heat dissipation efficiency.

[0074] For example, the other end of the connecting piece 23 that connects to the power chip 22 on the third substrate 21c is located between two adjacent power chips 22 on the second substrate 21b to improve the integration of the power module 20.

[0075] Furthermore, the spacing between adjacent power chips 22 on the same substrate is equal. Specifically, the spacing between adjacent power chips 22 on the first substrate 21a along the second direction Y is equal, the spacing between adjacent power chips 22 on the second substrate 21b along the second direction Y is equal, and the spacing between adjacent power chips 22 on the third substrate 21c along the second direction Y is equal. This ensures that the lead lengths of the bonding wires 24 connecting adjacent power chips 22 are equal, which helps to balance the current paths of each power chip 22, reduce the differences in parasitic parameters between power chips 22, and improve the dynamic current sharing characteristics of the parallel power chips 22.

[0076] For example, the power chip 22 on the first substrate 21a and the power chip on the third substrate 21c are aligned, that is, the power chip 22 on the first substrate 21a and the power chip 22 on the third substrate 21c are symmetrically arranged about the central axis of the power module 20 extending in the second direction Y, which is beneficial to improving the balance of dynamic current of each power chip.

[0077] In one embodiment, the power module 20 further includes a fourth substrate 21d, which is disposed between two extension arms 211 of the second substrate 21b and is connected to the power chip 22 on the extension arms 211 of the second substrate 21b via a connecting piece 23.

[0078] In this application, the fourth substrate 21d is provided with an extension arm 211 of the second substrate 21b and the first substrate 21a on one side along the first direction X, and the fourth substrate 21d is provided with another extension arm 211 of the second substrate 21b and the third substrate 21c on the other side along the first direction X. That is, along the first direction X, the first substrate 21a, the extension arm 211 of the second substrate 21b, the fourth substrate 21d, the other extension arm 211 of the second substrate 21b and the third substrate 21c are arranged in a sequentially spaced manner.

[0079] Power chips 22 include MOSFET power chips, IGBT power chips, silicon carbide (SiC) power chips, and gallium nitride (GaN) power chips. Multiple power chips 22 can be of the same type; for example, multiple power chips 22 can all be SiC power chips, which helps to distribute current evenly. It is understood that multiple power chips 22 can be of different types; for example, by using a mixture of SiC power chips and IGBT power chips, high-frequency performance can be considered.

[0080] Please combine Figure 5 , Figure 5This is a schematic diagram of the structure of a power chip 22 provided in one embodiment of this application. Each power chip 22 includes a drain, a source 221, a gate 222, and a Kelvin source 223. The drain is located on the side of the power chip 22 facing the substrate and is directly soldered to the substrate. For example, the drain of the power chip 22 on the first substrate 21a is directly soldered to the first substrate 21a to achieve electrical connection. The gate 222 and the Kelvin source 223 are located on the same side of the source 221, and the gate 222 is used to connect to the gate drive pad of the substrate. In the embodiments of this application, the gate 222 and the Kelvin source 223 of each power chip 22 are located on the same substrate and face the same direction to facilitate wiring of the gate 222 and the Kelvin source 223. In other embodiments, the power chip 22 may not have a Kelvin source 223.

[0081] There are two sources 221, that is, the power chip 22 includes a first source 221a and a second source 221b, which are arranged alternately. Both the first source 221a and the second source 221b are connected to the connecting piece 23.

[0082] A gate trace 2221 is provided between the first source 221a and the second source 221b. Specifically, the gate trace 2221 is located inside the power chip 22.

[0083] Please see Figure 6 , Figure 6 This is a schematic diagram of a power module 20 according to an embodiment of this application. In one embodiment, a plurality of power chips 22 include a plurality of upper bridge arm chips 224 and a plurality of lower bridge arm chips 225. The plurality of upper bridge arm chips 224 are arranged along a second direction Y on a first substrate 21a and a third substrate 21c, and each upper bridge arm chip 224 is connected to a second substrate 21b via a connecting piece 23. The plurality of lower bridge arm chips 225 are arranged along a second direction Y on a second substrate 21b, and each lower bridge arm chip 225 is connected to a fourth substrate 21d via a connecting piece 23.

[0084] Since both the first substrate 21a and the third substrate 21c are provided with upper bridge arm chips 224, and the upper bridge arm chips 224 on the first substrate 21a and the upper bridge arm chips 224 on the third substrate 21c are symmetrically arranged, the parasitic parameters (resistance, inductance, capacitance, etc.) of each parallel branch are as consistent as possible, reducing the uneven current distribution caused by path differences, which is beneficial to improving dynamic current balance. At the same time, it makes the parasitic inductance of each branch more consistent, which is beneficial to reducing the difference in current spikes during switching.

[0085] Each power chip 22 is connected to a corresponding connector 23. Compared to connecting multiple power chips 22 with one connector 23, the electrical performance between power chips 22 is better, and it is also beneficial to reduce the surface stress of power chips 22, thereby reducing the risk of solder cracking on the surface of power chips 22 and ensuring the structural life of power chips 22.

[0086] The connecting piece 23 can be a copper clip, a copper alloy clip, an aluminum clip, or other metal clip, wherein the coefficient of thermal expansion of the connecting piece 23 is greater than the coefficient of thermal expansion of the power chip 22.

[0087] The positive projection area of ​​the connecting piece 23 along the third direction Z on the first substrate 21a is larger than the positive projection area of ​​the bonding line 24 along the third direction Z on the first substrate 21a. The connecting piece 23 can carry higher current, and the flat and compact layout of the connecting piece 23 helps to reduce parasitic inductance, thereby helping to achieve high reliability of the power module 20.

[0088] The bonding wire 24 can be a strip-shaped metal such as aluminum wire, copper wire, gold wire, aluminum strip, or copper strip. The parallel power chips 22 are interconnected through the bonding wire 24, so that the bonding wire 24 can connect the parallel power chips 22 with the shortest straight path, minimizing the parasitic inductance between the power chips 22, and significantly reducing the risk of high-frequency oscillation during switching processes and short-circuit conditions under high voltage and high current.

[0089] For example, the bonding wires 24 connecting adjacent power chips 22 on the same substrate can be one or more. When there are multiple bonding wires 24, the multiple bonding wires 24 are arranged at intervals along the first direction X.

[0090] Specifically, on the same substrate, the bonding wire 24 is located at one end of the connecting piece 23 (the end connecting the power chip 22) facing away from the power chip 22. The bonding wire 24 is connected to the connecting piece 23 facing away from the power chip 22. For example, on the first substrate 21a, one end of the bonding wire 24 is connected to the connecting piece 23 on one power chip 22 facing away from the power chip 22, and the other end of the bonding wire 24 is connected to the connecting piece 23 on an adjacent power chip 22 facing away from the power chip 22. The bonding wire 24 is connected to the power chip 22 through the connecting piece 23. The heat dissipation capacity of the connecting piece 23 is better than that of the bonding wire 24. Heat can be quickly dissipated through the connecting piece 23, which can effectively buffer instantaneous temperature rise and reduce the risk of the bonding wire 24 breaking due to excessive temperature rise. In addition, parasitic inductance can be significantly reduced, thereby effectively suppressing voltage overshoot and switching losses. At the same time, compared to the bonding wire 24 being directly connected to the surface of the power chip 22, it can also reduce the surface stress of the power chip 22 when the bonding wire 24 is connected to the power chip 22.

[0091] In other embodiments, the bonding wire 24 may also be directly connected to the surface of the power chip 22 facing the bonding pad 23.

[0092] Please see Figure 7 , Figure 7 for Figure 6 The diagram shows a cross-sectional view of the power module 20 along line VII-VII. In one embodiment, the power module 20 further includes a first metal pillar 25 and a connection layer 26. The first metal pillar 25 is disposed on the side of the power chip 22 facing away from the first substrate 21a. Specifically, the first metal pillar 25 is disposed on the source 221 of the power chip 22, and the side of the first metal pillar 25 facing away from the power chip 22 is connected to one end of the connection piece 23. The connection layer 26 is disposed between the first metal pillar 25 and the connection piece 23 and connects and fixes the first metal pillar 25 and the connection piece 23.

[0093] A first metal pillar 25 is added between the power chip 22 and the connector 23. The first metal pillar 25 can effectively improve the transient heat dissipation capability of the power chip 22, thereby effectively suppressing transient junction temperature fluctuations and reducing the occurrence of small displacements in the bonding wires 24 or solder joints. Furthermore, the first metal pillar 25 has a large heat capacity, which is beneficial for heat dissipation of the power chip 22. The connector 23 is interconnected with the power chip 22 through the first metal pillar 25. Compared to directly connecting the surface of the power chip 22 through the connector 23, this significantly reduces surface stress on the power chip 22 and lowers the risk of solder cracking on the surface of the power chip 22.

[0094] Specifically, please combine Figure 8 , Figure 8 This diagram illustrates the power chip at points "A" and "B" in a prior art power module and the power chip at points "C" and "D" in the power module provided in this application. Figure 8 The left half of the diagram is a schematic diagram of a power module in the prior art. In the left diagram, points "A" and "B" are the solder edge positions connecting the power chip 22 and the connecting piece 23. Figure 8 The right half of the diagram is a schematic diagram of the power module 20 provided in this application. The connecting piece 23 is connected to the power chip 22 through the first metal pillar 25. Points "C" and "D" are the solder edge positions of the power chip 22 and the first metal pillar 25. The position of point "C" corresponds to the position of point "A", and the position of point "D" corresponds to the position of point "B".

[0095] Please combine Figure 9 , Figure 9 for Figure 8 The stress comparison diagram of the two power modules shown is as follows: Figure 9 The dashed line in the figure represents the stress variation curve of the power chip 22 in the power module 20 of the prior art. Figure 9The solid line in the figure represents the stress variation curve of the power chip 22 in the power module 20 of this application. From... Figure 9 It can be seen that the power chip 22 of this application experiences a stress of 41.4 MPa at point "C", while the power chip 22 in the prior art experiences a stress of 137.2 MPa at point "A". The stress at point "C" is less than the stress at point "A", and the stress at point "C" is about 30% of the stress at point "A". The power chip 22 of this application experiences a stress of 42.1 MPa at point "D", while the power chip 22 in the prior art experiences a stress of 219.0 MPa at point "B". The stress at point "D" is less than the stress at point "B", and the stress at point "D" is about 19% of the stress at point "B". By connecting the power chip 22 and the connecting piece 23 through the first metal pillar 25, the stress on the surface of the power chip 22 at the solder edge is significantly reduced.

[0096] Please combine Figure 10 and Figure 11 , Figure 10 The image shows a comparison of solder simulations at point "U" of the power module in the prior art and at points "V" and "W" of the power module provided in this application. Figure 11 for Figure 10 A schematic diagram showing the changes in the plastic strain energy of the solder at points "U", "V", and "W". Among them, Figure 10 The "U" point in the text refers to a location at the interface between the solder (used to connect the power chip 22 and the connector 23) and the connector 23 in the prior art. Figure 10 The “V” point is a certain position at the interface between the connecting layer 26 and the connecting piece 23, and the “W” point is a certain position at the interface between the solder and the first metal pillar 25. Figure 11 "Cycle 3" refers to the third cycle. It's important to note that assessing the risk of solder cracking primarily depends on the change in plastic strain energy of the solder within one power cycle (PC). Since an intermetallic compound (IMC) exists at the interface between the solder and connector 23, the change in plastic strain energy at this interface is the primary focus. A higher IMC value indicates a greater risk of solder cracking. Figure 10 and Figure 11 It can be seen that the increase in plastic strain energy corresponding to points "W" and "V" is less than the increase in plastic strain energy corresponding to point "U", and from... Figure 11It can be seen that the increase in plastic strain energy at the interface between the solder and the first metal pillar 25 is W = 0.152 MPa, and the increase in plastic strain energy at the interface between the solder and the connecting piece 23 is V = 0.158 MPa. In the prior art, the increase in plastic strain energy at the interface between the solder and the connecting piece 23 is U = 0.218 MPa. The increase in plastic strain energy at point "W" in the power module 20 of this application is about 70% of the increase in plastic strain energy at point "U" in the prior art, and the increase in plastic strain energy at point "V" is about 72% of the increase in plastic strain energy at point "U" in the prior art.

[0097] In this application, the coefficient of thermal expansion of the first metal pillar 25 is less than that of the connecting piece 23. The coefficient of thermal expansion of the first metal pillar 25 is close to that of the power chip 22. For example, the coefficient of thermal expansion of the first metal pillar 25 can be less than or greater than that of the power chip 22, but it is always less than that of the connecting piece 23. This allows for efficient heat dissipation while reducing the impact of thermal deformation on the power chip 22, effectively improving the transient heat dissipation capability of the power chip 22 and thus suppressing transient junction temperature fluctuations.

[0098] The material of the first metal pillar 25 includes aluminum silicon carbide or molybdenum copper alloy. For example, when the first metal pillar 25 is aluminum silicon carbide, the thermal expansion coefficient of the first metal pillar 25 is less than that of the connecting piece 23 by adjusting the proportion of aluminum silicon carbide. Or, for example, when the first metal pillar 25 is molybdenum copper alloy, the thermal expansion coefficient of the first metal pillar 25 is less than that of the connecting piece 23 by adjusting the proportion of molybdenum copper alloy.

[0099] The dimension of the first metal pillar 25 along the third direction Z is approximately 1 mm. For example, the dimension of the first metal pillar 25 along the third direction Z is 0.85 mm, 0.88 mm, 0.90 mm, 0.92 mm, 0.95 mm, 0.98 mm, 1.00 mm, 1.02 mm, etc. The dimension of the first metal pillar 25 along the third direction Z is set to a thickness in the millimeter range, and the first metal pillar 25 has a large heat capacity, which allows heat to dissipate quickly, buffers instantaneous temperature rise, improves the transient heat dissipation capability of the power chip 22, and thus suppresses transient junction temperature fluctuations.

[0100] Specifically, a support member may be provided inside the first metal pillar 25. The dimension of the support member along the third direction Z is equal to the dimension of the first metal pillar 25 along the third direction Z, so as to control the dimension of the first metal pillar 25 along the third direction Z when it is combined with the power chip 22.

[0101] For example, the shape of the orthogonal projection of the first metal pillar 25 along the third direction Z onto the first substrate 21a can be rectangular, circular, or other irregular shape adapted to the shape of the power chip 22 pad, without any specific limitation.

[0102] One end of the first metal column 25 and the connecting piece 23 are connected and fixed by the connecting layer 26, for example, by reflow soldering, laser soldering or ultrasonic soldering.

[0103] Please see Figure 12 , Figure 12 This is a partially enlarged schematic diagram of a power module 20 provided in one embodiment of this application. When a gate trace 2221 is provided between the first source electrode 221a and the second source electrode 221b, the first metal pillar 25 includes a first contact portion 251, a clearance groove 252, and a second contact portion 253 arranged sequentially. The first contact portion 251 is disposed opposite to and fixedly connected to the first source electrode 221a. The clearance groove 252 is disposed opposite to the gate trace 2221, and the opening of the clearance groove 252 faces the gate trace 2221. The second contact portion 253 is disposed opposite to and fixedly connected to the second source electrode 221b.

[0104] Because the power chip 22 is very small, the gate trace 2221 is easily damaged by stress, rendering the power chip 22 unusable. In this application, the clearance groove 252 is disposed opposite to the gate trace 2221 along the third direction Z. The clearance groove 252 is formed at the position of the first metal pillar 25 corresponding to the gate trace 2221, so that the first metal pillar 25 is disposed away from the gate trace 2221 when connected to the power chip 22. This reduces the stress on the gate trace 2221 from the first metal pillar 25, which helps to reduce the possibility of damage to the gate trace 2221 and extend the service life of the power chip 22.

[0105] For example, the clearance groove 252 is a groove formed by the recess of the first metal pillar 25 in the third direction Z portion facing the power chip 22. The clearance groove 252 penetrates the opposite two sides of the first metal pillar 25 in the extension direction of the gate trace 2221 to increase the groove length of the clearance groove 252, which helps to reduce the stress of the first metal pillar 25 on the gate trace 2221.

[0106] The connecting layer 26 can be sintered silver or soft solder, etc. The orthogonal projection area of ​​the connecting layer 26 along the third direction Z on the first substrate 21a is less than or equal to the surface area of ​​the first metal pillar 25 away from the first substrate 21a. That is, the area that the first metal pillar 25 and the connecting piece 23 can be welded is less than or equal to the surface area of ​​the first metal pillar 25 away from the first substrate 21a, thereby reducing the welding area between the first metal pillar 25 and the connecting piece 23. This prevents excessive pressure on the power chip 22 due to welding too many connecting pieces 23, thus reducing the surface stress on the power chip 22 and ensuring the structural lifespan of the power chip 22.

[0107] The connecting piece 23 includes a first through hole 231, a second through hole 232, and a bent portion 233. Both the first through hole 231 and the second through hole 232 penetrate both opposite sides of the connecting piece 23 along a third direction (Z). Both the first through hole 231 and the second through hole 232 are used to reduce the structural stress of the connecting piece 23. The bent portion 233 is located between one end and the other end of the connecting piece 23 and is bent relative to one end of the connecting piece 23. The bent portion 233 is provided with the second through hole 232.

[0108] Specifically, the orthographic projection of the first through-hole 231 on the first substrate 21a partially coincides with the orthographic projection of the first metal pillar 25 on the first substrate 21a. That is, the portion of the first through-hole 231 directly opposite the first metal pillar 25 in the third direction Z is positioned. The orthographic projection area of ​​the first through-hole 231 on the first substrate 21a is smaller than the orthographic projection area of ​​the connecting layer 26 on the first substrate 21a, reducing the impact of the first through-hole 231 on the connection between the connecting piece 23 and the first metal pillar 25. Providing the first through-hole 231 at the connection point between the connecting piece 23 and the first metal pillar 25 reduces the stress on the connecting piece 23 at the first metal pillar 25. The first through-hole 231 can also absorb deformation, reducing the likelihood of breakage of the connecting piece 23 due to excessive stress and ensuring the structural lifespan of the connecting piece 23. Furthermore, the first through-hole 231 can reduce the loop area of ​​the current path, thereby reducing parasitic inductance and improving the performance of the power chip 22.

[0109] For example, the first via 231 is positioned directly opposite the relief groove 252 of the first metal pillar 25 in the third direction Z. This can further reduce the stress on the gate trace 2221 caused by the first metal pillar 25 and effectively ensure the service life of the power chip 22.

[0110] Since one end of the connecting piece 23 is connected to the side of the power chip 22 facing away from the substrate, and the other end of the connecting piece 23 is connected to an adjacent substrate, and one end of the connecting piece 23 is further away from the first substrate 21a along the third direction Z, there is a height difference between the two ends of the connecting piece 23. The setting of the bending portion 233 makes the connecting piece 23 have an overall "Z" shape structure, ensuring the stability of the connection between the two ends of the connecting piece 23. The second through hole 232 is provided at the bending portion 233 of the connecting piece 23, which can effectively reduce the bending stress at the bending portion 233, reduce or avoid the connecting piece 23 from breaking due to excessive stress, and ensure the overall performance and reliability of the power module 20. Similarly, the second through hole 232 can also reduce the loop area of ​​the current path and reduce parasitic inductance, thereby improving the performance of the power chip 22.

[0111] For example, the opening size of the second through hole 232 is larger than that of the first through hole 231. In this way, the setting of the first through hole 231 is less likely to affect the welding area between the connecting piece 23 and the connecting layer 26, ensuring the reliability of the connection between the connecting piece 23 and the connecting layer 26. The larger size of the second through hole 232 can greatly reduce the loop area of ​​the current path and reduce parasitic inductance.

[0112] In other embodiments, the connecting piece 23 may also be provided with a third through hole 234, which penetrates the two opposite sides of the connecting piece 23 along the third direction Z and is located between the first through hole 231 and the second through hole 232. The third through hole 234 can reduce the stress of the connecting piece 23 and reduce parasitic inductance.

[0113] In the embodiment where the connecting piece 23 has a first through hole 231, a second through hole 232 and a third through hole 234, since the power module 20 has a molding layer to mold the power chip 22, the setting of the three through holes makes it difficult for the molding layer to delaminate, reducing the stress of the molding layer at the connecting piece 23.

[0114] In one embodiment, the power module 20 further includes a second metal post 27, which is used to connect the other end of the fixing connecting piece 23 to the substrate. Specifically, for the connecting piece 23 connecting the power chip 22 on the first substrate 21a and the second substrate 21b, the other end of the connecting piece 23 is connected to the second substrate 21b via a second metal post 27. For the connecting piece 23 connecting the power chip 22 on the second substrate 21b and the fourth substrate 21d, the other end of the connecting piece 23 is connected to the fourth substrate 21d via a second metal post 27.

[0115] The second metal pillar 27 can absorb the stress generated by temperature changes at the other end of the connecting piece 23 and the second substrate 21b (or the fourth substrate 21d), effectively reducing the risk of cracking of the connecting piece 23 and the substrate. In addition, the second metal pillar 27 has good thermal conductivity, which can conduct heat from the connecting piece 23 to the second substrate 21b (or the fourth substrate 21d), improving the heat dissipation effect and thus improving the reliability of the power module 20.

[0116] For example, the dimension of the second metal column 27 along the third direction Z can be approximately 1 mm. For instance, the dimension of the second metal column 27 along the third direction Z can be 0.86 mm, 0.88 mm, 0.90 mm, 0.93 mm, 0.95 mm, 0.97 mm, 1.00 mm, 1.02 mm, etc., and will not be listed exhaustively. It can be understood that the dimension of the second metal column 27 along the third direction Z can be equal to the dimension of the first metal column 25 along the third direction Z.

[0117] The orthographic projection shape of the second metal pillar 27 along the third direction Z onto the second substrate 21b (or the fourth substrate 21d) can be rectangular, circular, or other shapes adapted to the pad shape at the other end of the connecting piece 23, without any specific limitation.

[0118] For example, the coefficient of thermal expansion of the second metal pillar 27 is greater than that of the first metal pillar 25. That is, the coefficient of thermal expansion of the first metal pillar 25 is lower than that of the second metal pillar 27, which enables the first metal pillar 25 to achieve efficient heat dissipation of the power chip 22, while also reducing the impact of thermal deformation on the power chip 22, improving the transient heat dissipation capability of the power chip 22 and thus suppressing transient junction temperature fluctuations.

[0119] In this application, unless otherwise expressly specified and limited, the terms "connection" and "fixed" shall be interpreted broadly. For example, "fixed" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal connection of two elements or the interaction between two elements, unless otherwise expressly limited.

[0120] Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. The use of "first," "second," and various numerical designations herein is for descriptive convenience only and is not intended to limit the scope of this application.

[0121] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0122] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A power module, characterized in that, include: A first substrate and a second substrate are spaced apart from each other, and the first substrate is provided with a plurality of power chips. Multiple connecting pieces, each of which corresponds to a power chip, with one end of each connecting piece connected to the side of the power chip facing away from the first substrate, and the other end of each connecting piece connected to the second substrate; as well as Bonding wires are used to connect two adjacent power chips located on the same substrate.

2. The power module according to claim 1, characterized in that, The bonding wire is located at one end of the connector, on the side facing away from the power chip.

3. The power module according to claim 1, characterized in that, The power module further includes a first metal pillar, which is disposed on the side of the power chip facing away from the first substrate, and the side of the first metal pillar facing away from the power chip is connected to one end of the connecting piece.

4. The power module according to claim 3, characterized in that, The coefficient of thermal expansion of the first metal column is less than that of the connecting piece.

5. The power module according to claim 3 or 4, characterized in that, The power module further includes a connection layer, which is disposed between the first metal pillar and the connecting piece and connects and fixes the first metal pillar and the connecting piece. The positive projection area of ​​the connection layer on the first substrate along the arrangement direction of the first substrate and the power chip is less than or equal to the surface area of ​​the first metal pillar away from the first substrate.

6. The power module according to any one of claims 3-5, characterized in that, The power module also includes a second metal pillar, which connects the second substrate and the other end of the connecting piece.

7. The power module according to claim 6, characterized in that, The coefficient of thermal expansion of the second metal column is greater than that of the first metal column.

8. The power module according to any one of claims 3-7, characterized in that, The connecting piece is provided with a first through hole, which penetrates the two sides of the connecting piece opposite to the arrangement direction of the first substrate and the power chip. The orthographic projection of the first through hole on the first substrate partially coincides with the orthographic projection of the first metal pillar on the first substrate.

9. The power module according to claim 8, characterized in that, The connecting piece is further provided with a second through hole and a bending portion. The second through hole penetrates the two sides of the connecting piece opposite to the arrangement direction of the first substrate and the power chip. One end of the connecting piece is further away from the first substrate relative to the other end of the connecting piece along the arrangement direction of the first substrate and the power chip. The bending portion is located between one end of the connecting piece and the other end of the connecting piece and is bent relative to one end of the connecting piece. The bending portion is provided with the second through hole.

10. The power module according to any one of claims 1-9, characterized in that, The second substrate is provided with a plurality of power chips, and each power chip on the second substrate is connected to a corresponding connecting piece. The power chips on the first substrate and the power chips on the second substrate are staggered. The other end of the connecting piece connecting the power chip on the first substrate is located between two adjacent power chips on the second substrate.

11. The power module according to claim 10, characterized in that, The power module further includes a third substrate, and a second substrate is disposed between the third substrate and the first substrate. The third substrate is provided with a plurality of power chips. Each power chip on the third substrate is connected to the second substrate through a connecting piece. The other end of the connecting piece connecting the power chip on the third substrate is located between two adjacent power chips on the second substrate. The power chips on the first substrate and the third substrate are aligned.

12. The power module according to claim 11, characterized in that, The spacing between two adjacent power chips on the same substrate is equal.

13. The power module according to claim 11 or 12, characterized in that, The second substrate includes two spaced-apart extension arms, and the power chips on the different extension arms of the second substrate are aligned.

14. The power module according to claim 13, characterized in that, The power module further includes a fourth substrate, which is disposed between two extension arms of the second substrate and is connected to the power chip on the extension arm of the second substrate via the connecting piece.

15. A power conversion device, characterized in that, It includes a circuit board and a power module as described in any one of claims 1-14, wherein the power module is disposed on the circuit board.

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