Chip packaging method and packaging structure

Abstract

The embodiment of the application provides a chip packaging method and packaging structure, and relates to the technical field of automobile accessory assembly. The chip packaging method comprises the following steps: selecting a heat dissipation substrate, and connecting a chip with the heat dissipation substrate; selecting a first wiring layer, and electrically connecting the chip and the heat dissipation substrate with the first wiring layer; detecting the electrical connection state between the chip, the heat dissipation substrate and the first wiring layer; when the chip and the heat dissipation substrate are electrically connected with the first wiring layer, arranging a packaging piece on the first wiring layer, so that the packaging piece encapsulates the chip and the heat dissipation substrate. The chip packaging method and packaging structure can reduce the situation that the chip is taken out and maintained after being packaged, and indirectly improve the reliability of the electrical connection between the chip, the heat dissipation substrate and the first wiring layer.

Description

Technical Field

[0001] This application relates to the field of automotive parts assembly technology, and in particular to a chip packaging method and packaging structure. Background Technology

[0002] A motor controller is an electronic device used to control the operation of a motor. It can adjust parameters such as the motor's speed, torque, and power according to input signals. Motor controllers are widely used in industrial automation, home appliances, and electric vehicles.

[0003] To protect the chips in the motor controller from the effects of temperature, dust, and mechanical shock, the chips need to be packaged. The relevant technology usually uses groove packaging technology to package the chips. Groove packaging technology involves processing grooves on the substrate using a laser cutting machine, fixing the chip in the groove with adhesive, and then encapsulating the chip in the groove. After the chip is encapsulated in the groove, the electrodes of the chip are connected to the conductive lines on the substrate through bonding wires.

[0004] However, if the chip has physical damage such as cracks or breaks, it may cause the electrical connection between the chip and the substrate to fail. In this case, the packaged chip needs to be removed for repair. However, the chip is already fixed in the groove, making it inconvenient to remove the chip for repair. Summary of the Invention

[0005] This application provides a chip packaging method and packaging structure to solve the technical problem in related technologies where electrical connection failure between the chip and the substrate requires the chip to be removed from the groove for repair.

[0006] In a first aspect, embodiments of this application provide a chip packaging method, including:

[0007] Select a heat dissipation substrate and connect the chip to the heat dissipation substrate;

[0008] Select a first wiring layer and electrically connect both the chip and the heat dissipation substrate to the first wiring layer;

[0009] Detect the electrical connection status between the chip and the heat dissipation substrate and the first wiring layer;

[0010] When both the chip and the heat dissipation substrate are electrically connected to the first wiring layer, a package is provided on the first wiring layer so that the package encapsulates both the chip and the heat dissipation substrate.

[0011] In some embodiments, selecting a first wiring layer and electrically connecting both the chip and the heat dissipation substrate to the first wiring layer includes:

[0012] A first wiring layer made of metal is selected, and a connection circuit is formed on the first wiring layer by chemical etching. The chip and the heat dissipation substrate are both electrically connected to the connection circuit of the first wiring layer.

[0013] In some embodiments, selecting a first wiring layer and electrically connecting both the chip and the heat dissipation substrate to the first wiring layer includes:

[0014] At least one first electrical connection layer is disposed on the chip;

[0015] At least one second electrical connection layer is provided on the heat dissipation substrate;

[0016] Both the first electrical connection layer and the second electrical connection layer are electrically connected to the first wiring layer, so that both the chip and the heat dissipation substrate are electrically connected to the first wiring layer.

[0017] In some embodiments, the provision of a first electrical connection layer on the chip includes:

[0018] A first metal paste is printed on the chip, and the first metal paste is sintered to solidify the first metal paste and form the first electrical connection layer.

[0019] In some embodiments, the provision of at least one second electrical connection layer on the heat dissipation substrate includes:

[0020] A second metal paste is printed on the heat dissipation substrate, and the second metal paste is sintered to solidify the second metal paste and form the second electrical connection layer.

[0021] In some embodiments, electrically connecting both the first electrical connection layer and the second electrical connection layer to the first wiring layer includes:

[0022] The first electrical connection layer and the second electrical connection layer are sintered onto the first wiring layer so that both the first electrical connection layer and the second electrical connection layer are electrically connected to the first wiring layer.

[0023] In some embodiments, after at least one second electrical connection layer is formed on the heat dissipation substrate, the following is included:

[0024] The end of the first electrical connection layer away from the chip and the end of the second electrical connection layer away from the heat dissipation substrate are controlled to be at the same height.

[0025] In some embodiments, when both the chip and the heat dissipation substrate are electrically connected to the first wiring layer, a package is disposed on the first wiring layer so that the package encapsulates both the chip and the heat dissipation substrate, including:

[0026] A flow medium is disposed on the first wiring layer, and the flow medium is cured so that the package formed by the flow medium encapsulates both the chip and the heat dissipation substrate.

[0027] In some embodiments, the step of distributing a flow medium on the first wiring layer and curing the flow medium to encapsulate both the chip and the heat dissipation substrate in the package formed by the flow medium includes:

[0028] A first fluid is disposed between the heat dissipation substrate and the first wiring layer, and the first fluid is solidified so that the fluid medium formed by the first fluid encapsulates the chip, the first electrical connection layer and the second electrical connection layer.

[0029] In some embodiments, the provision of a first fluid between the heat dissipation substrate and the first wiring layer includes:

[0030] A first fluid formed by a filler adhesive is disposed between the heat dissipation substrate and the first wiring layer.

[0031] In some embodiments, the step of distributing a flow medium on the first wiring layer and curing the flow medium to encapsulate both the chip and the heat dissipation substrate in the package formed by the flow medium includes:

[0032] A second fluid is disposed on the first wiring layer and the second fluid is cured such that the fluid medium formed by the second fluid encapsulates the first fluid and the heat dissipation substrate.

[0033] In some embodiments, the provisioning of the second fluid on the first wiring layer includes:

[0034] The second fluid is formed by providing an insulating medium on the first wiring layer.

[0035] In some embodiments, the step of providing a package on the first wiring layer to encapsulate both the chip and the heat dissipation substrate includes:

[0036] A plurality of encapsulation components formed by laminating multiple plates are disposed on the first wiring layer, so that the plurality of plates encapsulate the first fluid and the heat dissipation substrate.

[0037] In some embodiments, the step of providing a package formed by laminating multiple plates on the first wiring layer to encapsulate the first fluid and the heat dissipation substrate by the multiple plates includes:

[0038] Multiple plastic plates are selected as multiple plates, and the multiple plastic plates are cut to form a receiving opening for accommodating the first fluid and the heat dissipation substrate. The multiple plastic plates are placed on the first wiring layer, so that the heat dissipation substrate and the fluid medium are embedded in the receiving opening.

[0039] In some embodiments, when both the chip and the heat dissipation substrate are electrically connected to the first wiring layer, providing a package on the first wiring layer so that the package encapsulates both the chip and the heat dissipation substrate includes:

[0040] A second wiring layer is bonded to the side of the package away from the first wiring layer.

[0041] Secondly, embodiments of this application provide a chip packaging structure, which is produced by the chip packaging method described above.

[0042] This application provides a chip packaging method and packaging structure. The chip packaging method provided in this application first electrically connects the chip and heat sink substrate to a first wiring layer, and then detects the electrical connection status between the chip and heat sink substrate and the first wiring layer. This facilitates the timely detection and repair of circuit connection problems between the chip, heat sink substrate, and the first wiring layer before packaging. When a reliable electrical connection exists between the chip and heat sink substrate and the first wiring layer, the chip and heat sink substrate are then packaged using a packaging component. This reduces the need to destroy the packaging component to remove the chip and heat sink substrate after packaging due to electrical connection failure. Furthermore, it eliminates the need for laser windowing detection after packaging the chip and heat sink substrate, preventing... The high temperatures generated during laser windowing affect the chip and heat sink substrate, indirectly improving the reliability of the electrical connection between the chip and heat sink substrate and the first wiring layer. Furthermore, by directly encapsulating the chip and heat sink substrate on the first wiring layer using a package, compared to related recessed encapsulation technologies, there is no need to use high-precision equipment such as laser cutting equipment to cut recesses on the first wiring layer to accommodate the chip and heat sink substrate. This reduces the complexity of the chip and heat sink substrate encapsulation process and indirectly improves the encapsulation efficiency. Moreover, placing the chip and heat sink substrate on the first wiring layer facilitates direct encapsulation of the chip and heat sink substrate by the package, preventing defects such as voids that occur during recessed encapsulation, and indirectly improving the encapsulation strength of the chip and heat sink substrate by the package. Attached Figure Description

[0043] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0044] Figure 1 A schematic flowchart of the chip packaging method provided in this application;

[0045] Figure 2 Schematic diagram of the chip packaging structure provided in this application Figure 1 ;

[0046] Figure 3 Schematic diagram of the chip packaging structure provided in this application Figure 2 ;

[0047] Figure 4 Schematic diagram of the chip packaging structure provided in this application Figure 3 ;

[0048] Figure 5 Schematic diagram of the chip packaging structure provided in this application Figure 4 ;

[0049] Figure 6 Schematic diagram of the chip packaging structure provided in this application Figure 5 .

[0050] Explanation of reference numerals in the attached figures:

[0051] 100. Heat dissipation substrate; 110. Second electrical connection layer;

[0052] 200. Chip; 210. First electrical connection layer;

[0053] 300, First wiring layer;

[0054] 400, Package; 410, First flow medium; 420, Second flow medium; 430, Plate;

[0055] 500, Second wiring layer.

[0056] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0057] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0058] To protect the chips in the motor controller from the effects of temperature, dust, and mechanical shock, the chips need to be packaged. The relevant technology typically uses recessed encapsulation (UU) to encapsulate the chips. UU involves creating recesses on a substrate using a laser cutting machine, fixing the chip within the recesses with adhesive, and then encapsulating the chip within the recesses. After the chip is encapsulated in the recesses, bonding wires connect the chip's electrodes to the conductive lines on the substrate. If the chip's electrodes are connected to the substrate's conductive lines first using bonding wires, the bonding wires are relatively fragile, and the encapsulation material can exert pressure on the bonding wires during later encapsulation, potentially damaging the bonding wires and causing the chip to lose its effective electrical connection to the substrate.

[0059] However, if the chip has physical damage such as cracks or breaks, it may cause the electrical connection between the chip and the substrate to fail. This will render the entire chip package structure unusable, or the packaged chip may need to be removed for repair. Since the chip has been fixed in the recess, the packaging material needs to be destroyed, making it difficult to remove the chip for repair.

[0060] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0061] Combination Figures 1 to 4 This application provides a chip packaging method, including:

[0062] S101: Select the heat dissipation substrate 100 and connect the chip 200 to the heat dissipation substrate 100;

[0063] S102: Select the first wiring layer 300, and electrically connect both the chip 200 and the heat dissipation substrate 100 to the first wiring layer 300;

[0064] S103: Detect the electrical connection status between the chip 200 and the heat dissipation substrate 100 and the first wiring layer 300;

[0065] S104: When both the chip 200 and the heat dissipation substrate 100 are electrically connected to the first wiring layer 300, a package 400 is provided on the first wiring layer 300 so that the package 400 encapsulates both the chip 200 and the heat dissipation substrate 100.

[0066] In this embodiment, the heat dissipation substrate 100 is a high-performance substrate for packaging the chip 200. It is mainly made of high thermal conductivity materials such as copper, aluminum, or ceramics, and has good thermal conductivity and heat dissipation performance. The heat dissipation substrate 100 includes a substrate body, a thermally conductive layer, an insulating layer, and a surface treatment layer. It can quickly conduct and dissipate the heat generated by the chip 200, thereby ensuring the temperature stability of the chip 200 during high-power operation. The chip 200 is disposed between the heat dissipation substrate 100 and the first wiring layer 300. In other embodiments, the chip 200 may also be disposed on the side of the heat dissipation substrate 100 away from the first wiring layer 300.

[0067] In this embodiment, the chip 200 and the heat dissipation substrate 100 are bonded. Common bonding processes include flip chip bonding, thermoforming bonding, conductive adhesive bonding, and eutectic bonding. These processes typically involve the following steps: First, the chip 200 and the heat dissipation substrate 100 are cleaned and prepared to ensure the absence of impurities and oxide layers. Second, appropriate bonding materials, such as solder, conductive adhesive, or eutectic alloy, are selected according to the process and coated or formed on the electrodes of the chip 200 or the pads of the heat dissipation substrate 100. Next, the chip 200 is precisely aligned and placed on the heat dissipation substrate 100 using high-precision equipment. Then, bonding is performed under specific temperature, pressure, and time conditions to melt or solidify the bonding materials and form a strong connection. Finally, the quality of the bonding joint is inspected using methods such as X-ray inspection, ultrasonic inspection, or electrical testing to ensure that there are no defects.

[0068] In this embodiment, the integrity of the electrical connection can be verified by measuring the resistance value between the chip 200 and the heat dissipation substrate 100 and the first wiring layer 300. For example, the resistance value between the chip 200 and the heat dissipation substrate 100 and the first wiring layer 300 can be measured by a low resistance tester or a multimeter; or the contact resistance between the chip 200 and the heat dissipation substrate 100 and the first wiring layer 300 can be measured by a four-probe tester, thereby verifying the integrity of the electrical connection.

[0069] In this application, by first electrically connecting the chip 200 and the heat sink substrate 100 to the first wiring layer 300 and detecting the electrical connection status between the chip 200, the heat sink substrate 100, and the first wiring layer 300, it is convenient to promptly detect and repair any circuit connection problems between the chip 200, the heat sink substrate 100, and the first wiring layer 300 before packaging the chip 200 and the heat sink substrate 100. When a reliable electrical connection exists between the chip 200, the heat sink substrate 100, and the first wiring layer 300, the chip 200 and the heat sink substrate 100 are then packaged using the package 400. This reduces the need to destroy the package 400 to remove the chip 200 and the heat sink substrate 100 due to electrical connection failure after packaging. Furthermore, it eliminates the need for laser windowing detection after packaging the chip 200 and the heat sink substrate 100, preventing the high temperature generated during laser windowing from affecting the chip 200 and the heat sink substrate 100, thereby indirectly improving the performance of the chip 200 and the heat sink substrate 100. The reliability of the electrical connection between the substrate 100 and the first wiring layer 300 is improved. Furthermore, the chip 200 and the heat dissipation substrate 100 are directly packaged on the first wiring layer 300 via the package 400. Compared to the groove packaging technology of related technologies, this eliminates the need for high-precision equipment such as laser cutting equipment to cut grooves on the first wiring layer 300 to accommodate the chip 200 and the heat dissipation substrate 100, thereby reducing the process complexity of packaging the chip 200 and the heat dissipation substrate 100 and indirectly improving the packaging efficiency of the chip 200. Moreover, the chip 200 and the heat dissipation substrate 100 are positioned on the first wiring layer 300, facilitating direct packaging of the chip 200 and the heat dissipation substrate 100 by the package 400, preventing defects such as voids during groove potting, and indirectly improving the packaging strength of the chip 200 and the heat dissipation substrate 100 by the package 400. The heat dissipation substrate 100 not only provides mechanical support for the chip 200 to prevent loosening during packaging and use, but also achieves electrical isolation through an insulating layer, improving the reliability and safety of the packaging.

[0070] Combination Figures 1 to 4 Selecting a first wiring layer 300 and electrically connecting both the chip 200 and the heat sink substrate 100 to the first wiring layer 300 includes:

[0071] A first wiring layer 300 made of metal is selected, and a connection circuit is formed on the first wiring layer 300 by chemical etching. The chip 200 and the heat dissipation substrate 100 are both electrically connected to the connection circuit of the first wiring layer 300.

[0072] In this embodiment, the first wiring layer 300, made of metal, is copper. Chemical etching is a high-precision manufacturing process that selectively removes material from the surface of a copper plate through a chemical reaction, thereby forming the required connection lines or other patterns on the copper plate. Chemical etching includes the following steps: First, a photosensitive resist material, such as photoresist, is coated on the surface of the first wiring layer 300. Then, through exposure and development processes, the designed pattern is transferred onto the resist layer, exposing the copper plate area to be etched. Next, the treated copper plate is immersed in an etching solution, such as ferric chloride solution or ammonia etching solution. The etching solution reacts chemically with the exposed copper, dissolving it, while the area protected by the resist layer remains intact. Finally, the residual etching solution and resist layer are cleaned away to obtain a precise connection circuit. Chemical etching is a prior art technology, and its specific steps will not be described in detail.

[0073] In this application, chemical etching has the advantages of high precision, high complexity pattern production capability, wide material selection, strong environmental adaptability, high cost-effectiveness and strong scalability. In the chip 200 package, the electrodes of the chip 200 are electrically connected to the connection lines of the first wiring layer 300 after chemical etching, which can realize a precise electrical connection between the chip 200 and the first wiring layer 300.

[0074] Combination Figures 1 to 4 Selecting a first wiring layer 300 and electrically connecting both the chip 200 and the heat sink substrate 100 to the first wiring layer 300 includes:

[0075] At least one first electrical connection layer 210 is provided on the chip 200;

[0076] At least one second electrical connection layer 110 is provided on the heat dissipation substrate 100;

[0077] The first electrical connection layer 210 and the second electrical connection layer 110 are both electrically connected to the first wiring layer 300, so that the chip 200 and the heat dissipation substrate 100 are both electrically connected to the first wiring layer 300.

[0078] In this embodiment, two first electrical connection layers 210 are provided. One end of the first electrical connection layer 210 is electrically connected to the electrode of the chip 200, and the other end of the first electrical connection layer 210 is electrically connected to the connection line of the first wiring layer 300. One second electrical connection layer 110 is provided. One end of the second electrical connection layer 110 is connected to the surface treatment layer of the heat dissipation substrate 100, and the other end of the second electrical connection layer 110 is connected to the copper plate.

[0079] In this application, by employing a first electrical connection layer 210, the first electrical connection layer 210 can support the chip 200, thereby indirectly improving the stability of the chip 200 during packaging. By employing a second electrical connection layer 110, the second electrical connection layer 110 can support the heat dissipation substrate 100, thereby indirectly improving the stability of the heat dissipation substrate 100 during packaging. Since the chip 200 is connected to the heat dissipation substrate 100, the second electrical connection layer 110 can indirectly improve the stability of the chip 200 during packaging. By electrically connecting the heat dissipation substrate 100 to the first wiring layer 300, the heat dissipation path can be further optimized, so that the heat generated by the first wiring layer 300 can be transferred to the heat dissipation substrate 100 through the second electrical connection layer 110, thereby indirectly dissipating heat from the first wiring layer 300 and ensuring the temperature stability of the first wiring layer 300 during operation.

[0080] Combination Figures 1 to 4 A first electrical connection layer 210 is provided on the chip 200, including:

[0081] A first metal paste is printed on chip 200, and the first metal paste is sintered to solidify the first metal paste to form a first electrical connection layer 210.

[0082] In this embodiment, the first metal paste that is conductive and sinterable is mainly silver paste, copper paste, gold paste, nickel paste, composite metal paste, or silver-copper composite paste. These pastes are composed of metal powder, organic carrier, and additives, and have different conductivity and different sintering temperatures. Silver paste has high conductivity but high cost, copper paste has low cost but is easily oxidized, gold paste has good chemical stability but is expensive, nickel paste has balanced performance and is not easily oxidized, and the formulation of composite metal paste can be adjusted according to requirements.

[0083] In this embodiment, the sintering process of the first metal paste mainly includes steps such as preparation, heating, sintering, cooling, and testing and evaluation. First, the first metal paste is precisely coated onto the chip 200 and pre-dried to remove some organic solvents. Then, the temperature is slowly increased to decompose and volatilize the organic carrier, followed by holding at a specific high temperature for a period of time to allow the metal particles to bond together during the sintering process, forming a robust first electrical connection layer 210. After sintering, it is slowly cooled to room temperature to reduce defects caused by thermal stress. Finally, the quality of the sintered layer is tested and evaluated using methods such as electrical performance testing, visual inspection, and mechanical performance testing to ensure that its conductivity and mechanical properties meet the design requirements.

[0084] In this embodiment, the sintering temperature range varies depending on the type of the first metal paste and the specific application, but is generally between 150°C and 400°C; for example, the sintering temperature of silver paste is generally between 200°C and 300°C, while that of copper paste is between 250°C and 400°C.

[0085] In this application, the first electrical connection layer 210 formed by sintering a first metal paste has high conductivity and low resistance, which can ensure efficient current conduction between the chip 200 and the first wiring layer 300, reducing energy loss. Furthermore, the first electrical connection layer 210 formed by sintering the first metal paste has good hardness, mechanical strength, and adhesion. When the chip 200 and the first electrical connection layer 210 are packaged using a package 400, damage to the first electrical connection layer 210 can be prevented, thereby indirectly improving the electrical connection between the chip 200 and the first electrical connection layer 210. The first electrical connection layer 210 formed by sintering the first metal paste can also provide certain thermal management functions, helping to quickly conduct the heat generated by the chip 200 to the first wiring layer 300, thereby improving heat dissipation efficiency, ensuring the temperature stability of the chip 200 during high-power operation, and extending the service life of the chip 200.

[0086] Combination Figures 1 to 4 At least one second electrical connection layer 110 is provided on the heat dissipation substrate 100, including:

[0087] A second metal paste is printed on the heat dissipation substrate 100, and the second metal paste is sintered to solidify the second metal paste and form a second electrical connection layer 110.

[0088] In this embodiment, the conductive and sinterable second metal paste is mainly silver paste, copper paste, gold paste, nickel paste, composite metal paste, or silver-copper composite paste. These pastes are composed of metal powder, organic carrier, and additives, and have different conductivity and different sintering temperatures. Silver paste has high conductivity but high cost, copper paste has low cost but is easily oxidized, gold paste has good chemical stability but is expensive, nickel paste has balanced performance and is not easily oxidized, and the formulation of composite metal paste can be adjusted according to requirements.

[0089] In this embodiment, the sintering process of the second metal paste mainly includes steps such as preparation, heating, sintering, cooling, and testing and evaluation. First, the second metal paste is precisely coated onto the chip 200 and pre-dried to remove some organic solvents. Then, the temperature is slowly increased to decompose and volatilize the organic carrier, followed by holding at a specific high temperature for a period of time to allow the metal particles to bond together during the sintering process, forming a robust second electrical connection layer 110. After sintering, it is slowly cooled to room temperature to reduce defects caused by thermal stress. Finally, the quality of the sintered layer is tested and evaluated using methods such as electrical performance testing, visual inspection, and mechanical performance testing to ensure that its conductivity and mechanical properties meet the design requirements.

[0090] In this embodiment, the sintering temperature range varies depending on the type of the second metal paste and the specific application, but is generally between 150°C and 400°C; for example, the sintering temperature of silver paste is generally between 200°C and 300°C, while that of copper paste is between 250°C and 400°C.

[0091] In this application, the second electrical connection layer 110 formed by sintering a second metal paste has high conductivity and low resistance, which can ensure efficient current conduction between the chip 200 and the first wiring layer 300, reducing energy loss. Furthermore, the second electrical connection layer 110 formed by sintering the second metal paste has good hardness, mechanical strength, and adhesion. When the chip 200 and the second electrical connection layer 110 are packaged using the package 400, damage to the second electrical connection layer 110 can be prevented, thereby indirectly improving the electrical connection between the chip 200 and the second electrical connection layer 110. The second electrical connection layer 110 formed by sintering the second metal paste can also provide certain thermal management functions, helping to quickly conduct the heat generated by the chip 200 to the first wiring layer 300, thereby improving heat dissipation efficiency, ensuring the temperature stability of the chip 200 during high-power operation, and extending the service life of the chip 200.

[0092] Combination Figures 1 to 4 The first electrical connection layer 210 and the second electrical connection layer 110 are both electrically connected to the first wiring layer 300, including:

[0093] The first electrical connection layer 210 and the second electrical connection layer 110 are sintered onto the first wiring layer 300 so that both the first electrical connection layer 210 and the second electrical connection layer 110 are electrically connected to the first wiring layer 300.

[0094] In this embodiment, screen printing, dispensing, or inkjet printing techniques are used to precisely coat the first and second metal pastes onto designated locations on the chip 200 and the first wiring layer 300. A sintering furnace, such as a tube furnace, box furnace, or infrared sintering furnace, is then prepared to sinter the first and second metal pastes. When the first metal paste is sintered to form the first electrical connection layer 210 and the second metal paste is sintered to form the second electrical connection layer 110, the first and second metal pastes can be directly sintered onto the first wiring layer 300, thereby achieving electrical connection between the first and second electrical connection layers 210 and 110 and the first wiring layer 300. No other additional electrical connection methods are required to achieve electrical connection between the first and second electrical connection layers 210 and 110 and the first wiring layer 300, improving the packaging efficiency of the chip 200.

[0095] Combination Figures 1 to 4 After at least one second electrical connection layer 110 is provided on the heat dissipation substrate 100, the following is included:

[0096] The end of the first electrical connection layer 210 away from the chip 200 and the end of the second electrical connection layer 110 away from the heat dissipation substrate 100 are at the same height.

[0097] In this embodiment, the cross-sectional shapes of the first electrical connection layer 210 and the second electrical connection layer 110 can be adaptively adjusted as needed. For example, the cross-sections of the first electrical connection layer 210 and the second electrical connection layer 110 can be set to a circle or a rectangle. The length of the second electrical connection layer 110 is greater than the length of the first electrical connection layer 210. Both the first electrical connection layer 210 and the second electrical connection layer 110 are set perpendicular to the first wiring layer 300.

[0098] In this application, by setting the ends of the first electrical connection layer 210 and the second electrical connection layer 110 at the same height, both the first electrical connection layer 210 and the second electrical connection layer 110 can extend to the location of the first wiring layer 300, thereby indirectly improving the support strength of the first electrical connection layer 210 and the second electrical connection layer 110 for the chip 200 and the heat dissipation substrate 100, thereby further improving the packaging strength of the chip 200 and the heat dissipation substrate 100.

[0099] Combination Figures 1 to 4 When both the chip 200 and the heat dissipation substrate 100 are electrically connected to the first wiring layer 300, a package 400 is disposed on the first wiring layer 300 so that the package 400 encapsulates both the chip 200 and the heat dissipation substrate 100, including:

[0100] A flow medium is disposed on the first wiring layer 300 and cured so that the package 400 formed by the flow medium encapsulates both the chip 200 and the heat dissipation substrate 100.

[0101] In this application, a fluid medium with good flowability is used to encapsulate the chip 200 and the heat dissipation substrate 100. First, the fluid medium can efficiently fill the tiny gaps between the chip 200 and the heat dissipation substrate 100, forming a tight contact, thereby significantly improving heat dissipation performance. This ensures that the heat generated by the chip 200 during high-power operation can be quickly conducted to the heat dissipation substrate 100 and dissipated, maintaining the temperature stability of the chip 200 and extending its service life. Second, after curing, the fluid medium forms a robust protective layer that can effectively resist external mechanical shocks, vibrations, and physical damage, providing reliable mechanical protection for the chip 200 and the heat dissipation substrate 100, enhancing the stability and durability of the encapsulation. The fluidity of the fluid medium allows it to adapt to complex encapsulation shapes and irregular surfaces, ensuring the uniformity and integrity of the encapsulation. Even on complex-shaped chips 200 or heat dissipation substrates 100, good encapsulation results can be achieved. The cured fluid medium also has a certain degree of elasticity, which can buffer the stress generated by thermal expansion and contraction, reducing thermal stress damage to the chip 200 and improving the reliability of the encapsulation.

[0102] Combination Figures 1 to 4 A flow medium is disposed on the first wiring layer 300, and the flow medium is cured so that the package 400 formed by the flow medium encapsulates both the chip 200 and the heat dissipation substrate 100, including:

[0103] A first fluid 410 is disposed between the heat dissipation substrate 100 and the first wiring layer 300, and the first fluid 410 is cured so that the fluid medium formed by the first fluid 410 encapsulates the chip 200, the first electrical connection layer 210 and the second electrical connection layer 110.

[0104] Combination Figures 1 to 4 A first fluid 410 is disposed between the heat dissipation substrate 100 and the first wiring layer 300, comprising:

[0105] A first fluid 410 formed by filling adhesive is disposed between the heat dissipation substrate 100 and the first wiring layer 300.

[0106] In this embodiment, when structural adhesive is used to encapsulate the chip 200 and the heat dissipation substrate 100, manual dispensing and dip coating are suitable for small-batch production or simple applications, and are easy to operate and low in cost; automatic dispensing machines, screen printing and inkjet printing are suitable for filling requirements with high precision and complex shapes, and can achieve high efficiency and high consistency filling; injection molding and vacuum filling are suitable for large-scale production, and can ensure high filling rate and high precision.

[0107] In this application, since the chip 200, the first electrical connection layer 210, and the second electrical connection layer 110 are all disposed between the heat dissipation substrate 100 and the first wiring layer 300, the small gaps between the heat dissipation substrate 100, the chip 200, the first electrical connection layer 210, the second electrical connection layer 110, and the first wiring layer 300 are first filled with filler adhesive. The structural adhesive usually has a low initial viscosity, which allows the structural adhesive to flow like a liquid when applied and easily fill the small gaps. This fluidity allows the structural adhesive to penetrate into very narrow spaces, ensuring that all parts of the gaps are fully filled, thereby preventing the flow medium from failing to flow into the small gaps and causing voids, thereby indirectly improving the encapsulation strength of the chip 200, the first electrical connection layer 210, and the second electrical connection layer 110.

[0108] Combination Figures 1 to 4 A flow medium is disposed on the first wiring layer 300, and the flow medium is cured so that the package 400 formed by the flow medium encapsulates both the chip 200 and the heat dissipation substrate 100, including:

[0109] A second fluid 420 is disposed on the first wiring layer 300 and the second fluid 420 is cured so that the fluid medium formed by the second fluid 420 encapsulates the first fluid 410 and the heat dissipation substrate 100.

[0110] Combination Figures 1 to 4 A second flow body 420 is disposed on the first wiring layer 300, including;

[0111] A second fluid 420 formed of an insulating medium is disposed on the first wiring layer 300.

[0112] In this embodiment, the insulating medium is epoxy resin. When encapsulating the chip 200 and the heat dissipation substrate 100 with an insulating medium, manual dispensing and dip coating are suitable for small-batch production or simple applications, and are easy to operate and low in cost. Automatic dispensing machines, screen printing, and inkjet printing are suitable for filling requirements with high precision and complex shapes, and can achieve high efficiency and high consistency filling. Injection molding and vacuum filling are suitable for large-scale production and can ensure high filling rate and high precision.

[0113] In this application, epoxy resin is used to encapsulate the chip 200 and the heat dissipation substrate 100. Epoxy resin has excellent electrical insulation properties, which can effectively prevent short circuits between the chip 200 and the heat dissipation substrate 100, ensuring the electrical safety of the encapsulation. Secondly, after curing, it forms a robust protective layer that can resist external mechanical impacts and physical damage, improving the mechanical stability of the encapsulation. In addition, epoxy resin has good chemical stability and can resist the erosion of various chemicals, extending the service life of the encapsulation. It also has good adhesion, which can tightly adhere to the surfaces of the chip 200 and the heat dissipation substrate 100, ensuring the integrity and sealing of the encapsulation. Furthermore, epoxy resin has a low volume shrinkage rate during curing, further ensuring the stability and reliability of the encapsulation.

[0114] Combination Figure 2 and Figure 5 In some embodiments, a package 400 is disposed on the first wiring layer 300 so that the package 400 encapsulates both the chip 200 and the heat dissipation substrate 100, including:

[0115] A plurality of encapsulation components 400 formed by pressing together multiple plates 430 are disposed on the first wiring layer 300 so that the multiple plates 430 encapsulate the first fluid 410 and the heat dissipation substrate 100.

[0116] In this embodiment, when pressing multiple plates 430 together, hot pressing, lamination, vacuum lamination, adhesive bonding, or injection molding can be selected. Hot pressing, lamination, vacuum lamination, adhesive bonding, or injection molding are existing technologies, and their specific steps will not be described in detail. Hot pressing and lamination are suitable for large-scale production, with high efficiency and high strength. Vacuum lamination is suitable for manufacturing high-precision and complex structures, reducing air bubbles and voids, and improving pressing quality. Adhesive bonding is simple to operate and low in cost, making it suitable for small-scale production. Injection molding is suitable for manufacturing multi-layer structures with high efficiency and high precision, and has a short molding time.

[0117] Combination Figure 2 and Figure 5 A plurality of encapsulation components 400 formed by laminating multiple plates 430 are disposed on the first wiring layer 300, so that the multiple plates 430 encapsulate the first fluid 410 and the heat dissipation substrate 100, including:

[0118] Multiple plastic plates are selected as multiple plates 430. The multiple plastic plates are cut to form a receiving opening for accommodating the first fluid 410 and the heat dissipation substrate 100. The multiple plastic plates are placed on the first wiring layer 300 so that the heat dissipation substrate 100 and the fluid medium are embedded in the receiving opening.

[0119] In this embodiment, the plastic sheet is a PP sheet, and multiple PP sheets are used. First, PP sheets have excellent electrical insulation properties, which can effectively prevent short circuits between the chip 200 and the heat dissipation substrate 100, ensuring the electrical safety of the package. Second, the PP sheet structure after lamination is robust, providing good mechanical support and protecting the chip 200 and the heat dissipation substrate 100 from external mechanical impacts and vibrations, improving the reliability and durability of the package. In addition, PP sheets are lightweight and high-strength, enabling lightweight design while maintaining sufficient mechanical strength. PP sheets also have good chemical corrosion resistance, resisting the erosion of various chemicals and extending the service life of the package. The lamination of PP sheets can form a multi-layer structure to adapt to the needs of different thicknesses of the package. Finally, PP sheet materials have low cost and relatively simple processing technology, making them suitable for large-scale production and effectively reducing the cost of packaging.

[0120] In this embodiment, the methods for cutting PP boards mainly include manual cutting, mechanical cutting, laser cutting, CNC punching, and waterjet cutting. Manual cutting is suitable for small-batch production, is flexible in operation, and has low cost; mechanical cutting achieves high-precision and high-efficiency cutting through paper cutters or punching machines, and is suitable for large-scale production; laser cutting can achieve high-precision cutting of complex shapes, and is suitable for high-precision requirements; CNC punching uses computer-controlled punches for cutting, which is highly accurate and efficient; waterjet cutting uses high-pressure water jets for cutting, which is heat-free and highly accurate.

[0121] In this application, a receiving opening is cut out of a PP board to encapsulate the chip 200 and the heat dissipation substrate 100. Compared with related technologies that use laser cutting equipment to cut grooves on the substrate, firstly, the PP board cutting process is relatively simple and low-cost, making it suitable for small-batch production and rapid prototyping, while laser cutting equipment is usually expensive and requires professional operators; secondly, the size and shape of the receiving opening can be flexibly adjusted according to needs to adapt to different designs of the chip 200 and the heat dissipation substrate 100, while laser cutting requires precise programming and equipment adjustment, placing higher demands on the operator's skills; furthermore, the PP board cutting process does not create a heat-affected zone that may be caused by laser cutting, thus avoiding potential changes in material properties; finally, the PP board cutting process generates less waste, has less impact on the environment, and the PP board itself is a lightweight and chemically resistant material that can provide good protection for the chip 200 and the heat dissipation substrate 100.

[0122] Combination Figure 4 and Figure 5 When both the chip 200 and the heat dissipation substrate 100 are electrically connected to the first wiring layer 300, a package 400 is provided on the first wiring layer 300 so that the package 400 encapsulates both the chip 200 and the heat dissipation substrate 100, including:

[0123] The second wiring layer 500 is bonded to the side of the package 400 away from the first wiring layer 300.

[0124] In this embodiment, a second wiring layer 500 made of metal is selected, and a connection circuit is formed on the second wiring layer 500 by chemical etching.

[0125] In this embodiment, the second wiring layer 500, made of metal, is copper. Chemical etching is a high-precision manufacturing process that selectively removes material from the surface of a copper plate through a chemical reaction, thereby forming the required connection lines or other patterns on the copper plate. Chemical etching includes the following steps: First, a layer of photosensitive resist material, such as photoresist, is coated on the surface of the second wiring layer 500. Then, through exposure and development processes, the designed pattern is transferred onto the resist layer, exposing the copper plate area to be etched. Next, the treated copper plate is immersed in an etching solution, such as ferric chloride solution or ammonia etching solution. The etching solution reacts chemically with the exposed copper, dissolving it, while the area protected by the resist layer remains intact. Finally, the residual etching solution and resist layer are cleaned away to obtain a precise connection circuit. Chemical etching is a prior art technology, and its specific steps will not be described in detail.

[0126] In this application, by adopting the second wiring layer 500, other components such as chips 200 can be set on the second wiring layer 500 and packaged, so that the first wiring layer 300 and the second wiring layer 500 can overlap multiple times to form a more complex multi-layer interconnection structure, so that the chip packaging structure can package more components such as chips 200.

[0127] A chip packaging structure is obtained by the chip packaging method of any of the above embodiments.

[0128] The specific steps of the chip packaging method have been described in detail in the above embodiments, and will not be repeated here.

[0129] Combination Figure 4 and Figure 5 In this embodiment, the chip packaging structure includes a first wiring layer 300, a second wiring layer 500, a heat dissipation substrate 100, a chip 200, a first electrical connection layer 210, a second electrical connection layer 110, and a package 400. The package 400 includes a first fluid 410 and a second fluid 420. The first wiring layer 300 and the second wiring layer 500 are arranged opposite to each other and spaced apart. The heat dissipation substrate 100 is disposed between the first wiring layer 300 and the second wiring layer 500. The chip 200 is disposed on the surface of the heat dissipation substrate 100 facing the first wiring layer 300. Two first electrical connection layers 210 are provided, and one end of the first electrical connection layer 210 is connected to the chip 200. The first electrical connection layer 210 is connected to the first wiring layer 300 at one end. A second electrical connection layer 110 is provided, with one end of the second electrical connection layer 110 connected to the heat dissipation substrate 100 and the other end of the second electrical connection layer 110 connected to the first wiring layer 300. A first fluid 410 is disposed between the heat dissipation substrate 100 and the first wiring layer 300. The first fluid 410 is used to encapsulate the chip 200, the first electrical connection layer 210, and the second electrical connection layer 110. A second fluid 420 is disposed between the first wiring layer 300 and the second wiring layer 500. The second fluid 420 is used to encapsulate the first fluid 410 and the heat dissipation substrate 100.

[0130] In some embodiments, the package 400 includes a first fluid 410 and a plurality of plates 430. The first fluid 410 is disposed between the heat dissipation substrate 100 and the first wiring layer 300. The first fluid 410 is used to encapsulate the chip 200, the first electrical connection layer 210 and the second electrical connection layer 110. The plurality of plates 430 are disposed between the first wiring layer 300 and the second wiring layer 500. The plurality of plates 430 are provided with receiving openings. The heat dissipation substrate 100 and the first fluid 410 are embedded in the receiving openings.

[0131] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A chip packaging method, characterized in that, include: Select a heat dissipation substrate (100) and connect the chip (200) to the heat dissipation substrate (100); Select a first wiring layer (300), and electrically connect both the chip (200) and the heat dissipation substrate (100) to the first wiring layer (300); Detect the electrical connection status between the chip (200) and the heat dissipation substrate (100) and the first wiring layer (300); When both the chip (200) and the heat dissipation substrate (100) are electrically connected to the first wiring layer (300), a package (400) is provided on the first wiring layer (300) so that the package (400) encapsulates both the chip (200) and the heat dissipation substrate (100).

2. The chip packaging method according to claim 1, characterized in that, The step of selecting a first wiring layer (300) and electrically connecting both the chip (200) and the heat dissipation substrate (100) to the first wiring layer (300) includes: A first wiring layer (300) made of metal is selected, and a connection circuit is formed on the first wiring layer (300) by chemical etching. The chip (200) and the heat dissipation substrate (100) are both electrically connected to the connection circuit of the first wiring layer (300).

3. The chip packaging method according to claim 1, characterized in that, The step of selecting a first wiring layer (300) and electrically connecting both the chip (200) and the heat dissipation substrate (100) to the first wiring layer (300) includes: At least one first electrical connection layer (210) is disposed on the chip (200); At least one second electrical connection layer (110) is provided on the heat dissipation substrate (100); Both the first electrical connection layer (210) and the second electrical connection layer (110) are electrically connected to the first wiring layer (300) so that the chip (200) and the heat dissipation substrate (100) are both electrically connected to the first wiring layer (300).

4. The chip packaging method according to claim 3, characterized in that, The provision of a first electrical connection layer (210) on the chip (200) includes: A first metal paste is printed on the chip (200), and the first metal paste is sintered to solidify the first metal paste to form the first electrical connection layer (210).

5. The chip packaging method according to claim 3, characterized in that, The provision of at least one second electrical connection layer (110) on the heat dissipation substrate (100) includes: A second metal paste is printed on the heat dissipation substrate (100), and the second metal paste is sintered to solidify the second metal paste to form the second electrical connection layer (110).

6. The chip packaging method according to claim 3, characterized in that, The step of electrically connecting both the first electrical connection layer (210) and the second electrical connection layer (110) to the first wiring layer (300) includes: The first electrical connection layer (210) and the second electrical connection layer (110) are sintered on the first wiring layer (300) so that both the first electrical connection layer (210) and the second electrical connection layer (110) are electrically connected to the first wiring layer (300).

7. The chip packaging method according to claim 3, characterized in that, After at least one second electrical connection layer (110) is formed on the heat dissipation substrate (100), the following is included: The end of the first electrical connection layer (210) away from the chip (200) is controlled to be at the same height as the end of the second electrical connection layer (110) away from the heat dissipation substrate (100).

8. The chip packaging method according to any one of claims 3-7, characterized in that, When both the chip (200) and the heat dissipation substrate (100) are electrically connected to the first wiring layer (300), a package (400) is provided on the first wiring layer (300) so that the package (400) encapsulates both the chip (200) and the heat dissipation substrate (100), including: A flow medium is disposed on the first wiring layer (300), and the flow medium is cured so that the package (400) formed by the flow medium encapsulates both the chip (200) and the heat dissipation substrate (100).

9. The chip packaging method according to claim 8, characterized in that, The step of providing a flow medium on the first wiring layer (300) and curing the flow medium so that the package (400) formed by the flow medium encapsulates both the chip (200) and the heat dissipation substrate (100) includes: A first fluid (410) is disposed between the heat dissipation substrate (100) and the first wiring layer (300), and the first fluid (410) is cured so that the fluid medium formed by the first fluid (410) encapsulates the chip (200), the first electrical connection layer (210) and the second electrical connection layer (110).

10. The chip packaging method according to claim 9, characterized in that, The provision of a first flow body (410) between the heat dissipation substrate (100) and the first wiring layer (300) includes: A first fluid (410) formed of filler adhesive is disposed between the heat dissipation substrate (100) and the first wiring layer (300).

11. The chip packaging method according to claim 9, characterized in that, The step of providing a flow medium on the first wiring layer (300) and curing the flow medium so that the package (400) formed by the flow medium encapsulates both the chip (200) and the heat dissipation substrate (100) includes: A second fluid (420) is disposed on the first wiring layer (300), and the second fluid (420) is cured such that the fluid medium formed by the second fluid (420) encapsulates the first fluid (410) and the heat dissipation substrate (100).

12. The chip packaging method according to claim 11, characterized in that, The provision of a second fluid (420) on the first wiring layer (300) includes: The second fluid (420) formed by an insulating medium is disposed on the first wiring layer (300).

13. The chip packaging method according to claim 9, characterized in that, The step of providing a package (400) on the first wiring layer (300) so that the package (400) encapsulates both the chip (200) and the heat dissipation substrate (100) includes: The package (400) is formed by pressing multiple plates (430) on the first wiring layer (300) so that the multiple plates (430) encapsulate the first fluid (410) and the heat dissipation substrate (100).

14. The chip packaging method according to claim 13, characterized in that, The encapsulation (400) formed by pressing together multiple plates (430) on the first wiring layer (300) to encapsulate the first fluid (410) and the heat dissipation substrate (100) by the multiple plates (430) includes: Multiple plastic plates are selected as multiple plates, and the multiple plastic plates are cut to form a receiving opening for accommodating the first fluid (410) and the heat dissipation substrate (100). The multiple plastic plates are placed on the first wiring layer (300) so that the heat dissipation substrate (100) and the fluid medium are embedded in the receiving opening.

15. The chip packaging method according to any one of claims 3-7, characterized in that, When both the chip (200) and the heat dissipation substrate (100) are electrically connected to the first wiring layer (300), a package (400) is provided on the first wiring layer (300) so that the package (400) encapsulates both the chip (200) and the heat dissipation substrate (100), including: A second wiring layer (500) is bonded to the side of the package (400) away from the first wiring layer (300).

16. A chip packaging structure, characterized in that, The chip packaging structure is produced by the chip packaging method described in any one of claims 1-15.

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