Common-drain dual NMOS transistor and packaging method thereof

Abstract

A common-drain double NMOS and a packaging method thereof, comprising: a die having opposite front and back surfaces, the front surface of which is provided with gate and source pins of a first NMOS and gate and source pins of a second NMOS, and the back surface of which has drain pins of the first NMOS and the second NMOS shorted together; a metal frame having opposite front and back surfaces, the back surface of which is provided with a plurality of contact points; the die is mounted on the metal frame with the front surface downward, the gate and source pins of the first NMOS and the gate and source pins of the second NMOS are respectively connected to a contact point of the metal frame; and a plastic encapsulating glue covers the die and the metal frame; wherein the front surface of the metal frame is exposed from the plastic encapsulating glue, forming four pins corresponding to the gate and source pins of the first NMOS and the gate and source pins of the second NMOS respectively. The common-drain double NMOS can be compatible with popular CSP packaging products, reduce manufacturing process complexity, and realize efficient testing.

Description

Technical Field

[0001] This invention relates to semiconductor products, and more particularly to MOSFETs. Background Technology

[0002] In practical applications of current power management, dual NMOS transistors are commonly used to control the charging and discharging of lithium secondary batteries. Figure 1 A circuit of a common-drain dual NMOS transistor 10 is illustrated, comprising a first MOS transistor Q1 and a second MOS transistor Q2 combined together. The first MOS transistor Q1 has a gate pin G1, a source pin S1, and a drain pin D1. The second MOS transistor Q2 has a gate pin G2, a source pin S2, and a drain pin D2. The drain pin D2 of the second NMOS transistor Q2 is shorted to the drain pin D1 of the first NMOS transistor Q1. One of the two NMOS transistors Q1 and Q2 is used for discharge control, and the other is used for charge control.

[0003] The existing common-drain dual NMOS transistor 10 structure, when used in lithium battery protection scenarios for smartphones, is usually packaged in WLCSP (Wafer Level Chip Scale Packaging).

[0004] Chinese patent CN101071776A discloses a common-drain dual MOSFET chip-level package and a method for manufacturing the package, comprising the following steps: providing a wafer having a large number of common-drain dual MOSFET devices disposed thereon; isolating the back drain metal surface of the wafer; performing bottom bump metallization of the ball grid array region on each common-drain dual MOSFET device; printing a solder mask on the wafer to expose the ball grid array region; reflowing solder paste or pre-formed solder balls to form a ball grid array of solder bumps; and dicing the wafer into a large number of chip-level packages.

[0005] As smartphones consume increasingly more power, the on-resistance of common-drain dual NMOS transistors needs to be reduced. To address this trend, a viable technological approach is to minimize the thickness of the aforementioned chips.

[0006] Chinese patent CN116845045A discloses a chip-scale packaged (CSP) semiconductor device, comprising: a semiconductor substrate having a front surface and a rear surface opposite to the front surface of the substrate; a plurality of contact pads connected to the front surface of the substrate; a metal stack layer attached to the rear surface of the substrate; and a molding compound layer attached to the metal stack layer; wherein the thickness of the semiconductor substrate is equal to or less than 35 micrometers; wherein the metal stack layer comprises a first titanium layer, a first nickel layer, a silver layer, a second nickel layer, and a titanium-containing metal layer stacked sequentially.

[0007] This technological path has led to several consequences: manufacturing processes are becoming increasingly complex, and efficient testing of individual packaged products is becoming increasingly difficult. Summary of the Invention

[0008] The technical problem to be solved by the present invention is that, in view of the above-mentioned defects of the prior art, the present invention proposes a common-drain dual NMOS transistor and its packaging method, which can be compatible with popular CSP packages, reduce manufacturing process complexity, and achieve efficient testing.

[0009] The technical solution adopted by this invention to solve its technical problem includes: providing a packaging method for a common-drain dual NMOS transistor, comprising the following steps:

[0010] Prepare the die and metal frame: The die has a front and a back side with opposite sides. The front side is provided with the gate and source pins of the first NMOS and the gate and source pins of the second NMOS. The back side is provided with the drain pins of the first NMOS and the drain pins of the second NMOS shorted together. The metal frame has a front and a back side with opposite sides. The back side is provided with several contact points protruding.

[0011] The die is electrically connected to the metal frame: the die is mounted face down on the metal frame, and the gate and source pins of the first NMOS and the gate and source pins of the second NMOS are each electrically connected to a contact point of the metal frame.

[0012] A molding compound is formed to cover the die and the metal frame; the front side of the metal frame is exposed in the molding compound, forming four pins corresponding to the gate and source pins of the first NMOS and the gate and source pins of the second NMOS, respectively.

[0013] In some embodiments, the pin arrangement is compatible with the pin arrangement of at least one popular WLCSP type dual NMOS transistor.

[0014] In some embodiments, prior to electrical connection, the contact points of the metal frame are metallized, the gate and source pins of the first NMOS and the gate and source pins of the second NMOS are electroplated, and the portion of the die other than the gate and source pins of the first NMOS and the gate and source pins of the second NMOS is insulated.

[0015] In some embodiments, the drain pin is encapsulated in the encapsulant.

[0016] In some embodiments, the drain pin is exposed outside the encapsulation.

[0017] The technical solution adopted by the present invention to solve its technical problem also includes: providing a common-drain dual NMOS transistor, comprising:

[0018] The die has a front side and a back side. The front side has the gate and source pins of the first NMOS and the gate and source pins of the second NMOS, and the back side has the drain pins of the first NMOS and the drain pins of the second NMOS that are shorted together.

[0019] A metal frame has opposing front and back sides, with a plurality of contact points protruding from the back side; the die is mounted on the metal frame with its front side facing down; the gate and source pins of the first NMOS and the gate and source pins of the second NMOS are each electrically connected to a contact point of the metal frame; and

[0020] A molding compound is used to encapsulate the grain and the metal framework;

[0021] The front of the metal frame is exposed to the encapsulation, forming four pins corresponding to the gate and source pins of the first NMOS and the gate and source pins of the second NMOS, respectively.

[0022] Compared with existing technologies, the common-drain dual NMOS transistor and its packaging method of the present invention, through the ingenious combination of metal frame and die, can be compatible with popular CSP packages, reduce manufacturing process complexity, and achieve efficient testing. Attached Figure Description

[0023] Figure 1 The circuit diagram of the common-drain dual NMOS transistor of the present invention is shown.

[0024] Figure 2 The packaging method of the common-drain dual NMOS transistor of the present invention is illustrated.

[0025] Figure 3 The die of the common-drain dual NMOS transistor of the present invention is shown.

[0026] Figure 4 The metal frame of the common-drain dual NMOS transistor of the present invention is illustrated.

[0027] Figure 5 This illustration shows the combination of the die and the metal frame of the common-drain dual NMOS transistor of the present invention.

[0028] Figure 6 The diagram illustrates the cross-sectional structure of the common-drain dual NMOS transistor of the present invention.

[0029] Figure 7 The diagram illustrates the top view of the common-drain dual NMOS transistor structure of the present invention.

[0030] Figure 8 The diagram illustrates the bottom view of the common-drain dual NMOS transistor structure of the present invention.

[0031] The reference numerals in the attached figures are explained as follows: 10 Common-drain dual NMOS transistor Q1 First MOS G1 Gate pin S1 Source pin D1 Drain pin Q2 Second MOS G2 Gate pin S2 Source pin D2 Drain pin; 1 Die 15 Front side 16 Back side 151 Gate pin of the first MOS 152 Source pin of the first MOS 153 Gate pin of the second MOS 154 Source pin of the second MOS 2 Metal frame 25 Front side 26 Back side 261, 262, 263, 264 Contact points 3 Plastic body. Detailed Implementation

[0032] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0033] See Figures 2 to 8 , Figure 2 The packaging method of the common-drain dual NMOS transistor of the present invention is illustrated. Figure 3 The die of the common-drain dual NMOS transistor of the present invention is shown. Figure 4 The metal frame of the common-drain dual NMOS transistor of the present invention is illustrated. Figure 5 This illustration shows the combination of the die and the metal frame of the common-drain dual NMOS transistor of the present invention. Figure 6 The diagram illustrates the cross-sectional structure of the common-drain dual NMOS transistor of the present invention. Figure 7 The diagram illustrates the top view of the common-drain dual NMOS transistor structure of the present invention. Figure 8 The diagram illustrates the bottom view of the common-drain dual NMOS transistor structure of the present invention.

[0034] This invention proposes a packaging method for a common-drain dual NMOS transistor, comprising the following steps:

[0035] S201, Prepare grain 1 and metal framework 2: See [link] Figure 3 , Figure 5 , Figure 6 The die 1 has a front side 15 and a back side 16. The front side 15 has a gate pin 151 and a source pin 152 of a first NMOS and a gate pin 153 and a source pin 154 of a second NMOS. The back side has a drain pin (not shown) of the first NMOS and a drain pin (not shown) of the second NMOS connected together. See also... Figure 4 , Figure 5 , Figure 6 The metal frame 2 has a front side 25 and a back side 26, with a plurality of contact points 261, 262, 263 and 264 protruding from the back side 26.

[0036] In this embodiment, the grain 1 is rectangular, with a length of 1.75 mm and a width of 1.20 mm. The thickness of the grain 1 is 75 µm. The metal frame 2 is rectangular, with a length of 2.20 mm and a width of 1.60 mm. The thickness of the metal frame 2 is 250 µm, which includes the thickness of contact points 261, 262, 263, and 264.

[0037] The term "die 1" refers to an independent circuit unit (DIE) on a wafer that integrates two NMOS transistors. These two NMOS transistors can be identical, such as in a typical dual-NMOS structure. Alternatively, they can be different, for example, as disclosed in Chinese patent CN117747616A, or in Chinese patent CN117497572A.

[0038] S203. Electrically connect the grain 1 to the corresponding metal frame 2: See [link / reference] Figure 5 , Figure 6 The die 1 is mounted face down on the metal frame 2. The gate pin 151 and source pin 152 of the first NMOS and the gate pin 153 and source pin 154 of the second NMOS are respectively electrically connected to a contact point 261, 262, 263, and 264 of the metal frame 2. That is, the gate pin 151 is aligned with the contact point 261, the source pin 152 is aligned with the contact point 262, the gate pin 153 is aligned with the contact point 263, and the source pin 154 is aligned with the contact point 264.

[0039] Before electrical connection, the contact points 261, 262, 263, and 264 of the metal frame 2 are metal-plated, for example, silver-plated, to increase the electrical connectivity between the die 1 and the metal frame 2. The gate pin 151 and source pin 152 of the first NMOS and the gate pin 153 and source pin 154 of the second NMOS are electroless plated. The portion of the die 1 other than the gate pin 151 and source pin 152 of the first NMOS and the gate pin 153 and source pin 154 of the second NMOS is insulated.

[0040] In this embodiment, the electroplating treatment on the front side 15 of die 1 refers to plating a nickel-palladium-gold alloy. The back side 16 of die 1 has a silver-plated metal layer. It can be understood that this silver-plated metal layer constitutes the drain pins of the first NMOS and the drain pins of the second NMOS shorted together.

[0041] In this embodiment, the die 1 and the metal frame 2 are connected using solder paste and then fixed by reflow soldering. In other embodiments, the die 1 and the metal frame 2 are connected using conductive adhesive.

[0042] In this embodiment, the boundary of the grain 1 is at least 150 micrometers away from the boundary of the metal frame 2.

[0043] S205, Forming a molding compound 3 that encapsulates the grain 1 and the metal framework 2; see also Figure 6 , Figure 7 , Figure 8 The front of the metal frame 2 is exposed through the encapsulant 3, forming four pins 251, 252, 253, and 254, respectively corresponding to the gate pin 151 and source pin 152 of the first NMOS and the gate pin 153 and source pin 154 of the second NMOS. The four pins 251, 252, 253, and 254 respectively correspond to... Figure 1 G1, S1, G2, and S2 in the example.

[0044] In this embodiment, the drain pins of the first NMOS and the drain pins of the second NMOS are encapsulated in the encapsulating adhesive 3. Figure 1 The two pins D1 and D2, which correspond to the drain pins of the first NMOS and the drain pin of the second NMOS, are omitted. In other words, although the common-drain dual NMOS transistor 10 is composed of two MOS transistors, considering that the drain pins of the two MOS transistors are shorted together on the back side 16 of the die 1 and do not need to be connected to external circuits, these two pins are unnecessary and are omitted.

[0045] Understandably, considering heat dissipation requirements, in some other embodiments, the drain pins of the first NMOS and the second NMOS may be entirely or partially exposed outside the encapsulant 3. For example, the encapsulant 3 may have partial openings. In other embodiments, a metal component such as a copper sheet may also be attached to the back of the die 1.

[0046] In this embodiment, the thickness of the common-drain dual NMOS transistor 10 does not exceed 400 micrometers. The common-drain dual NMOS transistor 10 is ultimately presented in a DFN (Dual Flat No-lead) package. It is understood that in other embodiments, depending on the specific application / customer requirements, the thickness of the common-drain dual NMOS transistor 10 can be limited in various ways, such as: 750 micrometers, the thickness of a conventional DFN package; 450 micrometers, a thickness specified for a particular application / customer; and 350 micrometers, a thickness specified for another application / customer.

[0047] The pin arrangement of the four pins 251, 252, 253, and 254 is compatible with the pin arrangement of at least one popular WLCSP type common-drain dual NMOS transistor, such as the Nuvoton KFCAB21B30L. That is, the common-drain dual NMOS transistor 10, using its four pins 251, 252, 253, and 254, can be surface-mounted onto a printed circuit board, directly replacing the specific WLCSP type common-drain dual NMOS transistor, the KFCAB21B30L.

[0048] It is worth mentioning that this common-drain dual NMOS transistor 10, while being compatible with popular CSP packages, significantly reduces manufacturing process complexity and greatly increases the testing efficiency of individual packages. Specifically, this common-drain dual NMOS transistor 10 can be tested as a single package, just like a conventional DFN device, promptly removing defective products that occur during manufacturing and ensuring the reliability of devices mounted on the circuit board.

[0049] Conversely, popular CSP packages, specifically WLCSP type common-drain dual NMOS transistors, can only be tested at the beginning of the manufacturing process, and efficient testing is not possible in subsequent processes, especially after the dicing operation, which physically separates the individual chips on the wafer into individual finished products for subsequent tape and reel processing.

[0050] Imagine if a mistake occurs during these processes, such as during dicing, where deviations in precision control cause damage to some of the chips, leading to the failure of the entire finished product. Moreover, this problem cannot be detected beforehand and can only be exposed when the finished product is mounted on the circuit board and subjected to circuit board-level testing.

[0051] It is worth mentioning that the length and width of the metal frame 2 of the common-drain dual NMOS transistor 10 are larger than the length and width of the die 1. This will result in the length and width of the common-drain dual NMOS transistor 10 being slightly larger than the length and width of the corresponding CSP package that it can replace.

[0052] Considering that: on the one hand, when the corresponding CSP package is mounted onto the circuit board, a dike needs to be installed around it to apply adhesive to ensure that the CSP package is reliably mounted onto the corresponding circuit board; on the other hand, the common-drain dual NMOS transistor 10 can be directly mounted onto the corresponding circuit board.

[0053] It is understandable that when both are mounted on a circuit board, they occupy roughly the same length and width. In other words, for applications mounted on a circuit board, the aforementioned "slightly larger" does not constitute a substantial negative impact.

[0054] Furthermore, in terms of mounting efficiency, this common-drain dual NMOS transistor 10 offers a significant improvement over its compatible CSP package counterparts.

[0055] It is worth mentioning that, with the help of the metal frame 2, the size and arrangement of the four pins 251, 252, 253, and 254 of the common-drain dual NMOS transistor 10 are not strictly limited by the size and arrangement of the gate pin 151 and source pin 152 of the first NMOS and the gate pin 153 and source pin 154 of the second NMOS on the die 1. Compared with the existing CSP type common-drain dual NMOS transistor, the packaging process can be greatly simplified.

[0056] It is understandable that although the starting point of the packaging method of the present invention is to replace the existing rather complex CSP packaging process with a simpler packaging process, the application of the packaging method of the present invention is not limited to this. For example, the packaging method of the present invention can be used to produce a common-drain dual NMOS transistor 10, which is in the form of DFN2050, DFN2040, DFN2030 or DFN2020. On the other hand, the arrangement of the four pins 251, 252, 253, 254 is not compatible with the pin arrangement of at least one existing WLCSP type dual NMOS transistor.

[0057] It should be understood that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Those skilled in the art can modify the technical solutions described in the above embodiments, or make equivalent substitutions for some of the technical features; and these modifications and substitutions should all fall within the protection scope of the appended claims of the present invention.

Claims

1. A packaging method for a common-drain dual NMOS transistor, characterized in that, Includes the following steps: Prepare the die and metal frame: The die has a front and a back side with opposite sides. The front side is provided with the gate and source pins of the first NMOS and the gate and source pins of the second NMOS. The back side is provided with the drain pins of the first NMOS and the drain pins of the second NMOS shorted together. The metal frame has a front and a back side with opposite sides. The back side is provided with several contact points protruding. The die is electrically connected to the metal frame: the die is mounted face down on the metal frame, and the gate and source pins of the first NMOS and the gate and source pins of the second NMOS are each electrically connected to a contact point of the metal frame. A molding compound is formed to cover the die and the metal frame; the front side of the metal frame is exposed in the molding compound, forming four pins corresponding to the gate and source pins of the first NMOS and the gate and source pins of the second NMOS, respectively.

2. The packaging method for a common-drain dual NMOS transistor according to claim 1, characterized in that, The pin arrangement of these four pins is compatible with the pin arrangement of at least one popular WLCSP type dual NMOS transistor.

3. The packaging method for a common-drain dual NMOS transistor according to claim 1, characterized in that, Prior to electrical connection, the contact points of the metal frame were plated with metal, the gate and source pins of the first NMOS and the gate and source pins of the second NMOS were electroplated, and the portion of the die except for the gate and source pins of the first NMOS and the gate and source pins of the second NMOS was insulated.

4. The packaging method for a common-drain dual NMOS transistor according to claim 1, characterized in that, The drain pin is encapsulated in the encapsulant.

5. The packaging method for a common-drain dual NMOS transistor according to claim 1, characterized in that, The drain pin is exposed in the encapsulation.

6. A common-drain dual NMOS transistor, characterized in that, include: The die has a front side and a back side. The front side has the gate and source pins of the first NMOS and the gate and source pins of the second NMOS, and the back side has the drain pins of the first NMOS and the drain pins of the second NMOS that are shorted together. A metal frame has a front and a back side facing each other, and a number of contact points are protruding on the back side. The die is mounted on the metal frame with its front side facing down. The gate and source pins of the first NMOS and the gate and source pins of the second NMOS are each electrically connected to a contact point of the metal frame. as well as A molding compound is used to encapsulate the grain and the metal framework; The front of the metal frame is exposed to the encapsulation, forming four pins corresponding to the gate and source pins of the first NMOS and the gate and source pins of the second NMOS, respectively.

7. The common-drain dual NMOS transistor according to claim 6, characterized in that, The pin arrangement of these four pins is compatible with the pin arrangement of at least one existing WLCSP type common-drain dual NMOS transistor.

8. The common-drain dual NMOS transistor according to claim 6, characterized in that, Prior to electrical connection, the contact points of the metal frame were plated with metal, the gate and source pins of the first NMOS and the gate and source pins of the second NMOS were electroplated, and the portion of the die except for the gate and source pins of the first NMOS and the gate and source pins of the second NMOS was insulated.

9. The common-drain dual NMOS transistor according to claim 6, characterized in that, The drain pin is encapsulated in the encapsulant.

10. The common-drain dual NMOS transistor according to claim 6, characterized in that, The drain pin is exposed in the encapsulation.

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