A method and structure for packaging stacked chips

Abstract

This invention provides a packaging method and structure for stacked chips, which can significantly reduce the occurrence rate of molding voids and improve the yield and long-term reliability of stacked packaged products. The method includes the following steps: Step S1: Prepare a substrate and attach an adhesive film to the substrate; Step S2: Stack multiple layers of chips sequentially from bottom to top on the substrate, with the chips stacked in a staggered manner. The orthographic projections of adjacent layers of chips overlap and are partially offset, forming a staggered step. A gap is formed between the staggered steps on the sides of adjacent layers of chips; Step S3: Apply a bottom filler adhesive to the side edges of the multilayer chips. The bottom filler adhesive fills the gap between the staggered steps under capillary action, and then cures the bottom filler adhesive; Step S4: Moldulate the filled and cured multilayer chips, so that the molding compound covers the multilayer chips.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip packaging technology, and more specifically to a packaging method and structure for stacked chips. Background Technology

[0002] As semiconductor packaging technology advances towards higher density, thinner profiles, and three-dimensional stacking, multi-layer vertical chip stacking structures are widely used in high-density memory, artificial intelligence chips, automotive high-reliability packaging, and chiplet integrated packaging. In this method, adjacent chips are stacked using a non-aligned, staggered arrangement. Compared to conventional aligned stacking, this avoids chip bump interference, optimizes wiring space, reduces interlayer stress, and improves packaging integration and structural design flexibility.

[0003] However, in the molding process, the staggered arrangement of multi-layer chips will form a large number of alternating steps, narrow gaps and dead corners on the sides of the chip, which will make the flow path of the molding compound complicated, the melt flow uneven, and the internal gas difficult to be discharged smoothly, making it easy to form molding voids at the chip edge and step position.

[0004] Existing molding processes typically employ uniform injection speeds, injection pressures, and conventional vacuum venting methods. While suitable for regular, aligned stacked structures, they are ill-suited for filling irregularly shaped flow channels created by misaligned stacking. Common problems include incomplete venting, delayed local filling, and severe gas entrapment in the melt, resulting in large, numerous, and randomly distributed voids within the package. These voids not only increase thermal resistance and cause localized chip overheating but also affect the stability of the device's electrical performance. Under conditions of temperature cycling, thermal shock, and mechanical vibration, these voids can induce stress concentration, further leading to delamination, cracking, or the popcorn effect, significantly reducing product yield and long-term reliability. Summary of the Invention

[0005] To address the aforementioned issues, this invention provides a packaging method and structure for stacked chips, which can significantly reduce the occurrence rate of voids in the plastic encapsulation and improve the yield and long-term reliability of stacked packaged products.

[0006] The technical solution is as follows: a method for packaging stacked chips, characterized by comprising the following steps: Step S1: Prepare the substrate and attach the adhesive film to the substrate. Step S2: Multiple layers of chips are stacked sequentially from bottom to top on the substrate. The chips are stacked in a staggered manner, and the orthographic projections of two adjacent layers of chips overlap and are partially offset to form a staggered step. The sides of two adjacent layers of chips form a staggered step gap between layers. Step S3: Apply bottom filler adhesive to the side edge of the multilayer chip. The bottom filler adhesive fills the gap between the interlayer misalignment steps under capillary action, and then cures the bottom filler adhesive. Step S4: Moldulate the filled and cured multilayer chip so that the molding compound covers the multilayer chip.

[0007] Furthermore, in step S3, the viscosity of the underfill adhesive at the spot application temperature is selected based on the interlayer misalignment step gap: when the interlayer misalignment step gap is a conventional misalignment stacking gap, the viscosity is 2000 mPa·s to 6000 mPa·s; when there are micro gaps and local narrow gaps in the interlayer misalignment step gap, the viscosity is 800 mPa·s to 2500 mPa·s; when large gaps and local narrow gaps coexist in the interlayer misalignment step gap, the underfill adhesive is a thixotropic underfill adhesive, and the static viscosity of the thixotropic underfill adhesive is higher than its dynamic viscosity.

[0008] Furthermore, the maximum particle size of the filler in the bottom filler is no greater than 1 / 5 of the minimum gap of the interlayer misalignment step gap.

[0009] Furthermore, the contact angle between the underfill adhesive and the chip and the substrate is less than 30°, and the surface tension of the underfill adhesive is 32mN / m to 38mN / m.

[0010] Furthermore, the glass transition temperature of the cured underfill adhesive is more than 25°C higher than the maximum operating temperature of the packaged product, and the coefficient of thermal expansion of the cured underfill adhesive in the glass state is 20ppm / °C to 35ppm / °C.

[0011] Furthermore, in step S3, before applying the bottom filler adhesive, the substrate and the chip are preheated to 50°C to 85°C, and the temperature deviation of each point on the surface of the substrate during the preheating process is less than ±3°C.

[0012] Furthermore, the stacked chips form a rectangular chip stack when viewed from above. The chip stack has at least two stepped portions, each stepped portion having multiple staggered steps. The staggered steps have step gaps and connection gaps located on both sides of the step gaps. The bottom filler is applied using any of the following methods: Method 1: Apply adhesive lines to the two connection gaps, extending the adhesive lines into the step gaps; Method 2: Apply an L-shaped adhesive line between the step gap and one of the connecting gaps; Method 3: Apply a continuous adhesive line to the gap between the steps. The length of the continuous adhesive line should be 80%-95% of the side length of the gap between the steps.

[0013] Furthermore, in step S3, the volume of the applied bottom filler adhesive is determined by the following formula: Volume = Total bottom volume × Redundancy factor Wherein, the redundancy coefficient is taken as 1.08 to 1.15, and the bottom total volume is the total volume of the interlayer misaligned step gap.

[0014] Furthermore, in step S3, after the bottom filler adhesive is applied, it is left to stand for 3 to 12 minutes at room temperature or under heat preservation conditions, and then cured after X-ray inspection confirms that there are no voids in the filler.

[0015] Furthermore, in step S4, the molding compound is an epoxy resin molding compound. The workpiece processed in step S3 is placed into the molding mold, the epoxy resin molding compound is injected, the overall encapsulation and filling is completed, and the mold is cured at a constant temperature. Then the mold is opened, the flash is removed, and the mold is cooled.

[0016] A stacked chip package structure, characterized in that it is fabricated using the packaging method described above, comprising: Substrate; an adhesive film is bonded to the substrate; Multiple chips are stacked sequentially on the substrate from bottom to top. Adjacent chips are stacked in a non-aligned and staggered manner. The projection areas of adjacent chips partially overlap and partially offset. The sides of the stacked chips form interlayer staggered step gaps. Bottom filler adhesive is used to fill the gaps between the interlayer misaligned steps and then cured. Molding compound, used to encapsulate multiple layers of chips.

[0017] This invention utilizes bottom filler adhesive before molding to fill the gaps between misaligned steps under capillary action. This transforms the steps and tiny gaps that are prone to gas stagnation into solidified filling areas before molding, allowing subsequent molding to only cover the smooth outer contour. This significantly reduces the possibility of voids being generated between layers due to complex flow channels, melt gas encapsulation, and incomplete venting of the molding compound. With fewer voids between layers, the thermal resistance of the encapsulation is reduced, which can prevent local overheating of the chip, improve the stability of the device's electrical performance, and increase the yield of finished products. In this invention, the bottom filler adhesive automatically penetrates, self-levels, fills and completely removes gas from the gaps between the interlayer misalignment steps by relying on its own capillary force. It does not require high-pressure injection, the process is gentle, will not damage the chip, and has good adaptability to misalignment gaps of varying widths. In this invention, the viscosity of the bottom filler is matched according to the gap width, and the filler particle size is limited according to the minimum gap of the interlayer misaligned step gap. At the same time, it has a low contact angle and suitable surface tension, which can ensure that the misaligned stacked chip stack can penetrate into the narrow gap when the wide and narrow gaps coexist, without the filler getting stuck and blocking the pores, so that the gaps are filled evenly. Attached Figure Description

[0018] Figure 1 This is a schematic diagram illustrating the steps of the stacked chip packaging method in the embodiment.

[0019] Figure 2 This is a schematic diagram of the structure of the substrate after the adhesive film is bonded to it in the embodiment. Figure 3 This is a top view of multiple chips stacked in a staggered manner on a substrate in the embodiment. Figure 4 This is a side view of multiple chips stacked in a staggered manner in the embodiment. Figure 5 This is a top view of the chip stack after the bottom filler adhesive has been applied to the side edge of the chip stack in the embodiment. Figure 6 This is a schematic diagram of applying the bottom filler adhesive using method one in the embodiment; Figure 7 This is a schematic diagram illustrating the application of bottom filler adhesive using method two in the embodiment; Figure 8 This is a schematic diagram of the bottom filler adhesive applied in method three in the embodiment. Detailed Implementation

[0020] See Figure 1 The present invention provides a method for packaging stacked chips, comprising at least the following steps: Step S1: Prepare the substrate and attach the adhesive film to the substrate; Step S2: Stack multiple layers of chips sequentially from bottom to top on the substrate. The orthographic projections of two adjacent layers of chips overlap and are partially offset. The sides of two adjacent layers of chips form interlayer misalignment step gaps. Step S3: Apply underfill adhesive to the side edge of the multilayer chip. The underfill adhesive fills the gap between the interlayer misalignment steps under capillary action, and then cures the underfill adhesive. Step S4: Moldulate the filled and cured multilayer chip so that the molding compound covers the multilayer chip.

[0021] In one embodiment of the present invention, the provided method for packaging stacked chips includes the following steps: Step S1: Provide a substrate and attach an adhesive film to the surface of the substrate; the adhesive film refers to the film attached to the surface of the substrate to support and bond the chip. For example... Figure 2 As shown, first prepare a qualified substrate, clean the board surface of impurities and oil stains, check the specifications, and then accurately attach the adhesive film to the surface of the substrate, press it firmly and remove air bubbles to ensure that the adhesion is flat, without voids or misalignment. The adhesive film provides a flat bearing and bonding base for subsequent chip stacking, which helps to ensure the positional accuracy of multi-layer stacking and the regularity of subsequent misaligned steps.

[0022] Step S2: Stack multiple chips sequentially from bottom to top on the substrate, such as... Figure 3Top view and Figure 4 As shown in the side view, multiple chips are sequentially aligned and fixed onto the adhesive film according to process requirements. Adjacent chips are stacked in a non-aligned, staggered manner, so that the projection area of ​​the upper chip partially overlaps and partially offsets the projection area of ​​the lower chip, forming a staggered step. The sides of adjacent chip layers form interlayer staggered step gaps. Interlayer staggered step gaps refer to the high and low step-like gaps formed on the sides of adjacent chips due to staggered stacking. Using staggered stacking can avoid chip bump interference, optimize wiring space, and reduce interlayer stress. At the same time, the high and low steps and narrow gaps formed on the sides of the chips by staggered stacking place higher requirements on subsequent uniform filling, which is met by the following step S3 in this embodiment.

[0023] Step S3: Apply underfill adhesive to the side edges of the stacked chips. The underfill adhesive fills the gaps between the interlayer misalignments under capillary action and then cures. Figure 5 As shown, the side edge area of ​​the chip stack is positioned, and a dispensing device is used to apply underfill adhesive to the outer edge points of the chip. Utilizing the capillary wetting effect of the adhesive itself, the underfill adhesive applied at the edge automatically flows and penetrates into the gaps between the interlayer misalignment steps of the chip, relying on capillary force to fully fill all the gaps between the interlayer misalignment steps. The entire process is natural leveling and filling of the gaps between the interlayer misalignment steps. After standing, the self-leveling filling of the adhesive is completed, and the air in the gaps is completely removed, which can prevent the generation of voids and air bubbles in the interlayer filling. Finally, the underfill adhesive is cured according to the process conditions. After curing, the misaligned chip stack is stabilized, and the overall adhesion, sealing and structural strength of the chip are improved. Since the misalignment steps are filled in step S3 before molding, the molding compound does not need to enter the chip stack during subsequent molding, which can avoid voids in the package caused by incomplete venting, local filling delay, and melt gas entrapment.

[0024] To accommodate the uneven gaps in the chip stack, this embodiment matches the properties of the bottom filler adhesive in the following manner, thereby ensuring that the wide and narrow gaps are filled synchronously and completely.

[0025] Regarding viscosity, in the embodiments, for gaps in conventional staggered stacking, the viscosity is taken as 2000 mPa·s to 6000 mPa·s; for cases with micro gaps and severe local narrow gaps, an ultra-low viscosity adhesive with a viscosity of 800 mPa·s to 2500 mPa·s is used to ensure that the adhesive can smoothly penetrate into the narrow gaps; for cases where large gaps and local narrow gaps coexist, a thixotropic bottom filler adhesive is used, which has a higher viscosity in a static state to prevent flow collapse and a lower viscosity in a flowing state to facilitate penetration; in the embodiments, the viscosity is matched according to the gap width, which can avoid the lag in filling narrow gaps or the flow collapse and lack of adhesive in large gaps, so as to make the filling more uniform.

[0026] In practice, to accommodate the gap characteristics of different stacking designs, those skilled in the art can classify stacking scenarios based on the following quantitative criteria: Conventional staggered stacking: The uniform gap between layers is 20μm to 50μm, the lateral displacement of the staggered steps is 0.5mm to 2mm, the size deviation of the step gap between each layer does not exceed ±20%, and there are no narrow gap areas with sharp local narrowing. It is commonly found in the standard staggered stacking structure of 2 to 4 layers of memory chips of the same specification.

[0027] Misaligned stacking with micro-gap and local narrow gap: The minimum interlayer gap of the stack is 5μm to 20μm, and there are local narrow gap regions with a length of 10% to 30% of the total length of the misaligned step. The gap at the narrow gap is less than 10μm. This is common in scenarios where gap narrowing is caused by misaligned stacking of high-density bump chips and ultra-thin chips.

[0028] Misaligned stacking with large gaps and local narrow slits: The interlayer gap in the main stacked area is 30μm to 80μm, while there are local narrow slit areas with gaps less than 15μm. The ratio of the maximum gap to the minimum gap is ≥3, and the gap width varies significantly. This is common in scenarios where heterogeneous chips are mixed and stacked, or chips of different thicknesses are stacked in a misaligned manner.

[0029] Regarding the filler, the maximum particle size of the filler in the bottom filler is no greater than 1 / 5 of the minimum gap of the misaligned step; for example, when the minimum gap is 20μm, the maximum particle size of the filler is less than 4μm, which can prevent the filler from getting stuck and blocking the pores at the misaligned narrow gap, thus avoiding voids. The limitation in the example allows the colloid to maintain good flowability in the narrow gap.

[0030] In terms of wetting performance, the contact angle between the bottom filler and the chip and the substrate is less than 30°, and the surface tension is 32mN / m~38mN / m. This ensures that the adhesive can capillarily climb synchronously in wide and narrow gaps, making the filling progress of each gap more consistent and avoiding air entrapment due to differences in climbing speed.

[0031] In terms of thermomechanical parameters, the glass transition temperature of the underfill adhesive is more than 25°C higher than the maximum operating temperature of the packaging structure, and the coefficient of thermal expansion in the glass state is 20ppm / °C to 35ppm / °C, which matches the coefficient of thermal expansion of the chip (approximately 2.6ppm / °C) and the substrate. This is used to offset the local stress concentration caused by the misalignment structure. The substrate is usually an organic substrate, and the coefficient of thermal expansion of the underfill adhesive is between that of silicon and the substrate. This can alleviate the stress caused by the thermal mismatch between the two and improve the reliability of the structure under temperature alternation conditions.

[0032] The dispensing process conditions in this embodiment are as follows, thereby further ensuring the sufficiency and absence of voids in the capillary filling.

[0033] Before applying the underfill adhesive, the substrate is preheated to a constant temperature of 50-85°C, commonly 60-70°C, to reduce the viscosity of the underfill adhesive, increase the capillary flow rate, and make the flow rate of the wide and narrow slits more uniform. At the same time, the temperature deviation of various parts of the substrate is controlled to be less than ±3°C to prevent air entrapment due to local flow rate differences. In the embodiment, the preheating and temperature control are uniform, so that the capillary filling is faster and more even.

[0034] The stacked chips form a rectangular chip stack when viewed from above. The chip stack has at least two stepped portions with multiple staggered steps. The staggered steps have a step gap C and connection gaps B and D located on both sides of the step gap. The bottom filler is applied using any of the following methods: Method 1: Apply adhesive lines to both connection gaps B and D, extending the lines to the step gap C, as shown. Figure 6 As shown; Method 2: Apply an L-shaped adhesive line between the step gap C and one of the connecting gaps D, such as... Figure 7 As shown; Method 3: Apply a continuous adhesive line to the step gap C, with the length of the continuous adhesive line being 80%-95% of the side length of step gap C, such as... Figure 8 As shown.

[0035] All three dispensing paths described above utilize open sides to guide the adhesive from one side into the interior of the misaligned step via gradual capillary filling. The path can be flexibly selected according to the misalignment direction and gap distribution, ensuring sufficient filling and preventing excess adhesive from overflowing beyond the edge.

[0036] In this embodiment, the volume of the dotted bottom filler is equal to the product of the total bottom volume of the misaligned step and the redundancy coefficient. The volume of the applied bottom filler is determined by the following formula: Volume = Total bottom volume × Redundancy factor; The redundancy coefficient is set to 1.08 to 1.15 to compensate for local missing adhesive in the chip stack, while preventing adhesive overflow beyond the edge. The total volume at the bottom of the misaligned step refers to the sum of the volumes of all misaligned step cavities formed by the stacked chips. Appropriate adhesive redundancy makes the filling more reliable and avoids voids caused by local missing adhesive.

[0037] In this embodiment, after applying the bottom filler adhesive, the mixture is left to stand at room temperature or under heat preservation conditions for 3 to 12 minutes to allow the gas in the narrow gap to slowly and fully escape. X-ray inspection is then used to confirm that the misaligned step is completely filled and free of voids before the mixture is oven-cured. In this embodiment, X-ray inspection confirms the absence of voids after adhesive application before curing, ensuring that void defects are detected and eliminated before curing, thus guaranteeing a void-free process.

[0038] Step S4 involves encapsulating multiple filled and cured chips, cleaning the cured component, precisely placing the workpiece into the encapsulation mold, injecting epoxy resin encapsulating material, controlling temperature and pressure to complete the overall encapsulation and filling, and then curing at a constant temperature. The mold is then opened, the finished product is removed, flash and waste are cleaned, and it is allowed to cool naturally. After a full inspection of appearance, structure, and sealing, it is stored and transferred to the next process. Because the misalignment steps have been pre-filled with the bottom filler in step S3, the encapsulating material only needs to uniformly cover the smooth shape of the chip stack, avoiding air entrapment and voids in complex interlayer dead corners. This significantly reduces the encapsulation void rate, lowers the thermal resistance of the package, and improves reliability.

[0039] Through steps S1 to S4, this embodiment first applies cured bottom filler at the misaligned step position, and then performs molding compound encapsulation. The sequence in this embodiment is different from traditional direct molding, which can eliminate the main gas stagnation space before the molding compound enters the encapsulation cavity, reduce the size and number of voids, and improve the reliability of stacked encapsulation under temperature cycling, thermal shock and mechanical vibration conditions.

[0040] In another embodiment of the present invention, a specific numerical example of the method of the present invention is provided. This embodiment is used to illustrate that the above method can be repeatedly implemented. The embodiment provides an organic substrate with an adhesive backing film. Eight layers of memory chips are stacked on the adhesive backing film in a staggered manner from bottom to top. Adjacent chips are staggered in the same direction, forming eight staggered steps on the side of the stacked chips. The minimum gap between the steps is approximately 20 μm. Before dispensing, the substrate is preheated to 65°C, and the temperature deviation at each location is controlled within ±3°C. A bottom filler adhesive with a viscosity of approximately 2000 mPa·s is selected. The maximum particle size of the filler is less than 4 μm, the contact angle with silicon and the substrate is approximately 20°, the surface tension is approximately 35 mN / m, the glassy thermal expansion coefficient after curing is approximately 28 ppm / °C, and the glass transition temperature is more than 25°C higher than the maximum operating temperature. In this embodiment, the method is... The third method involves applying adhesive on one side of the long side, with a continuous adhesive line applied to the step gap C. The length of the adhesive line is approximately 90% of the length of step gap C. The amount of adhesive applied is determined by multiplying the total volume of the misaligned steps by a redundancy factor of 1.10. After application, the mixture is kept at 65°C for approximately 10 minutes. X-ray inspection confirms that all eight misaligned steps are completely filled without voids. The mixture is then cured. Finally, the component is cleaned and placed in a molding die, epoxy resin is injected, and the entire assembly is encapsulated under controlled temperature and pressure and cured at a constant temperature. After mold opening, deflashing, cooling, and final inspection, the package is stored. X-ray re-inspection shows no visible voids between layers, and the thermal resistance of the encapsulation is significantly lower than that of conventional direct molding processes. No delamination or cracking is observed after temperature cycling. This embodiment demonstrates that, using the above parameters, multilayer misaligned stacked chip packages without interlayer voids can be stably and repeatedly obtained.

[0041] In embodiments of the present invention, a stacked chip packaging structure is also provided, specifically a packaging structure prepared by the method of Embodiment 1 or 2. Combined with... Figures 1 to 3 -4 and the encapsulated structure, in the embodiment, the encapsulation structure includes a substrate 1, an adhesive film 5, multiple chips 2, an underfill adhesive 6, and a molding compound. The adhesive film is attached to the surface of the substrate 1. Multiple chips 2 are stacked on the substrate 1 in a staggered manner from bottom to top. Adjacent chips are stacked in a non-aligned staggered manner. The projection area of ​​the chip on the upper layer partially overlaps and partially offsets the projection area of ​​the chip on the lower layer. The sides of the stacked chips 2 form staggered steps 3. The cured underfill adhesive 6 fills the gaps 4 between the staggered steps. The molding compound covers multiple chips, which protects the chips as a whole.

[0042] like Figure 3 and Figure 5 As shown, multiple chip stacks spaced apart from each other can be disposed on the substrate. Each chip stack consists of multiple staggered chips 2. The interlayer staggered step gaps of each chip stack are filled with bottom filler glue, thereby realizing board-level packaging and improving the output of single packaging.

[0043] In the embodiments, the coefficient of thermal expansion of the cured bottom filler is 20ppm / ℃ to 35ppm / ℃, which is between the coefficients of thermal expansion of the chip and the substrate. The maximum particle size of the filler is no greater than 1 / 5 of the minimum gap of the misaligned step. In the stacked chip packaging structure of the embodiments, there are no voids in the misaligned step area due to insufficient filling of the molding compound. Therefore, the thermal resistance of this packaging structure is low, the stress concentration is small, and it has stronger resistance to delamination and cracking under temperature cycling, thermal shock and mechanical vibration conditions.

[0044] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention.

[0045] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for packaging stacked chips, characterized in that, Includes the following steps: Step S1: Prepare the substrate and attach the adhesive film to the substrate; Step S2: Multiple layers of chips are stacked sequentially from bottom to top on the substrate. The chips are stacked in a staggered manner, and the orthographic projections of two adjacent layers of chips overlap and are partially offset to form a staggered step. The sides of two adjacent layers of chips form a staggered step gap between layers. Step S3: Apply underfill adhesive to the side edge of the multilayer chip. The underfill adhesive fills the gap between the interlayer misalignment steps under capillary action, and then cures the underfill adhesive. Step S4: Moldulate the filled and cured multilayer chip so that the molding compound covers the multilayer chip.

2. The packaging method for stacked chips according to claim 1, characterized in that: In step S3, the viscosity of the underfill adhesive at the spot application temperature is selected based on the interlayer misalignment step gap: when the interlayer misalignment step gap is a conventional misalignment stacking gap, the viscosity is 2000 mPa·s to 6000 mPa·s; when there are micro gaps and local narrow gaps in the interlayer misalignment step gap, the viscosity is 800 mPa·s to 2500 mPa·s; when large gaps and local narrow gaps coexist in the interlayer misalignment step gap, the underfill adhesive is a thixotropic underfill adhesive, and the static viscosity of the thixotropic underfill adhesive is higher than its dynamic viscosity.

3. The packaging method for stacked chips according to claim 1, characterized in that: The maximum particle size of the filler in the bottom filler adhesive is no greater than 1 / 5 of the minimum gap between the interlayer misalignment steps.

4. The packaging method for stacked chips according to claim 1, characterized in that: The contact angle between the underfill adhesive and the chip and the substrate is less than 30°, and the surface tension of the underfill adhesive is 32mN / m to 38mN / m.

5. The packaging method for stacked chips according to claim 1, characterized in that: The glass transition temperature of the underfill adhesive after curing is more than 25°C higher than the maximum operating temperature of the packaged product, and the coefficient of thermal expansion of the underfill adhesive in the glass state after curing is 20ppm / °C to 35ppm / °C.

6. The packaging method for stacked chips according to claim 1, characterized in that: In step S3, before applying the bottom filler adhesive, the substrate and the chip are preheated to 50°C to 85°C, and the temperature deviation of each point on the surface of the substrate is less than ±3°C during the preheating process.

7. The packaging method for stacked chips according to claim 1, characterized in that: The stacked chips form a rectangular chip stack when viewed from above. The chip stack has at least two stepped portions, each stepped portion having multiple staggered steps. The staggered steps have step gaps and connection gaps on both sides of the step gaps. The bottom filler is applied using any of the following methods: Method 1: Apply adhesive lines to the two connection gaps, extending the adhesive lines into the step gaps; Method 2: Apply an L-shaped adhesive line between the step gap and one of the connecting gaps; Method 3: Apply a continuous adhesive line to the gap between the steps. The length of the continuous adhesive line should be 80%-95% of the side length of the gap between the steps.

8. The packaging method for stacked chips according to claim 1, characterized in that: In step S3, the volume of the applied bottom filler adhesive is determined by the following formula: Volume = Total bottom volume × Redundancy factor; Wherein, the redundancy coefficient is taken as 1.08 to 1.15, and the bottom total volume is the total volume of the interlayer misaligned step gap.

9. The packaging method for stacked chips according to claim 1, characterized in that: In step S3, after the bottom filler adhesive is applied, it is left to stand for 3 to 12 minutes at room temperature or under heat preservation conditions, and then cured after X-ray inspection confirms that there are no voids in the filler.

10. The packaging method for stacked chips according to claim 1, characterized in that: In step S4, the molding compound is an epoxy resin molding compound. The workpiece processed in step S3 is placed into the molding mold, the epoxy resin molding compound is injected, the overall encapsulation and filling is completed, and the mold is cured at a constant temperature. Then the mold is opened, the flash is removed, and the mold is cooled.

11. A stacked chip packaging structure, characterized in that, The product is manufactured using the packaging method described in any one of claims 1 to 10, comprising: Substrate; an adhesive film is bonded to the substrate; Multiple chips are stacked sequentially on the substrate from bottom to top. Adjacent chips are stacked in a non-aligned and staggered manner. The projection areas of adjacent chips partially overlap and partially offset, forming a staggered step. The sides of adjacent layers of chips form an interlayer staggered step gap. Bottom filler adhesive is filled into the gaps between the interlayer misaligned steps and cured. Molding compound, used to encapsulate multiple layers of chips.

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