Embedded chip packaging method and embedded chip packaging structure

Abstract

The application provides an embedded chip packaging method and an embedded chip packaging structure. The method comprises the following steps: fixing a circuit substrate with a reserved hole and at least one semiconductor chip on a first carrier plate, so that a first electrode of the semiconductor chip and a second electrode of the circuit substrate face the first carrier plate; filling a gap between the semiconductor chip and the reserved hole with plastic packaging material, and covering the back surface, and solidifying to form a packaging body; fixing a second carrier plate and peeling off the first carrier plate to expose a working surface formed by the first electrode and the second electrode; forming a mask layer with a window on the working surface; and growing a bridge metal layer in situ in the window by using an additive manufacturing process, so that the first electrode and the second electrode are electrically bonded. The bridge metal layer grown in situ directly connects the electrodes along the flush surface, reduces the overall thickness of the device, and improves the reliability of the structure and the stability of the electrical connection.

Description

Technical Field

[0001] This invention relates to the field of semiconductor and circuit board integrated packaging technology, and specifically to an embedded chip packaging method and embedded chip packaging structure. Background Technology

[0002] As electronic products become thinner, lighter, and more integrated, embedded chip packaging technology has become an important way to improve interconnect density. In traditional printed circuit board (PCB) embedded processes, semiconductor chips are usually placed directly into through-holes in the substrate and then fixed by laminating insulating dielectric layers (such as prepregs) or by directly dispensing adhesive to fill the gaps.

[0003] Due to the thickness difference between the chip and the substrate, a significant step difference inevitably occurs between the electrode surface of the chip and the substrate surface, resulting in a non-coplanar state. This non-coplanar state poses challenges for subsequent electrical interconnection. To achieve electrical connection, wire bonding or blind via copper filling after laser drilling is required to establish a conductive path. These connection methods not only increase the package thickness and parasitic inductance of high-frequency signals, but also, under long-term thermal conditions, the wires or complex internal structures are prone to fatigue cracking due to stress concentration, reducing overall reliability. Summary of the Invention

[0004] In view of the aforementioned problems, this application is made to provide an embedded chip packaging method and embedded chip packaging structure that overcomes or at least partially solves the aforementioned problems, comprising: An embedded chip packaging method, comprising: The circuit board with pre-drilled holes is fixed onto the first carrier plate; At least one semiconductor chip is fixed in the reserved hole, with the electrode surface of the semiconductor chip facing the first carrier plate. A first electrode is provided on the electrode surface, and a second electrode is provided on the circuit board. The gap between the semiconductor chip and the reserved hole is filled with molding compound, and the semiconductor chip and the side of the circuit board facing away from the first carrier are covered. After curing, a package body is formed. The packaging body is fixed to the second carrier plate on the side facing away from the first carrier plate, and the first carrier plate is peeled off to expose the first electrode of the semiconductor chip and the second electrode of the circuit board. A patterned mask layer is formed on the working surface where the first electrode and the second electrode are exposed, the mask layer having windows that expose the areas of the electrodes to be connected; An additive manufacturing process is used to grow a bridging metal layer in situ within the window, so that the first electrode and the second electrode are electrically bonded through the bridging metal layer.

[0005] According to one embodiment of the present invention, the circuit board is fixed to the first carrier plate by a first temporary adhesive layer; the semiconductor chip is partially fixed to the first carrier plate by the adhesive properties of the first temporary adhesive layer, so that the first electrode of the semiconductor chip is coplanar with the second electrode of the circuit board.

[0006] According to one embodiment of the present invention, filling the gap between the semiconductor chip and the reserved hole with a molding compound and covering the side of the semiconductor chip and the circuit board facing away from the first carrier plate includes: In a vacuum environment, a compression molding process is used to fill the gap between the semiconductor chip and the reserved hole with the encapsulating material, and to cover the side of the semiconductor chip and the circuit board that is away from the first carrier board. The circuit board covered with molding compound is cured using a curing molding process to form the encapsulation body.

[0007] According to one embodiment of the present invention, after the first carrier plate is stripped away and before the patterned mask layer is formed, the method further includes: using a plasma cleaning process to remove residual organic matter on the exposed working surface.

[0008] According to one embodiment of the present invention, forming a patterned mask layer on the working surface exposing the first electrode and the second electrode includes: A photoresist is coated on the working surface as the mask layer; Alignment is performed using alignment marks on the circuit board and / or the semiconductor chip, and after exposure and development, the opening that exposes the first electrode and the second electrode is formed.

[0009] According to one embodiment of the present invention, the additive manufacturing process is an electroplating process, and before forming the patterned mask layer, it further includes: A conductive seed layer is deposited on the entire working surface using a physical vapor deposition process. The in-situ growth of the bridging metal layer within the window includes: Using the conductive seed layer exposed by the window as a substrate, a thickened copper layer is grown in situ within the window using an electroplating process to form the bridging metal layer. The mask layer is removed using a stripping solution, and the conductive seed layer covered by the mask layer is flash-etched using a micro-etching process, thereby electrically isolating each of the bridging metal layers from each other.

[0010] According to one embodiment of the present invention, the additive manufacturing process is a chemical plating process, and the in-situ growth of a bridging metal layer within the window includes: In the area where the first electrode and the second electrode are exposed by the window, a thickened metal layer is formed by in-situ growth of a metal layer through autocatalytic electroless plating.

[0011] According to one embodiment of the present invention, after the bridging metal layer is grown in situ within the window, the method further includes: An insulating material is applied to the bridging metal layer and the area where the working surface is exposed, and then cured to form an insulating protective layer. The surface of the external electrodes configured on the circuit board is subjected to tin plating or nickel-palladium-gold plating for surface anti-oxidation treatment.

[0012] According to one embodiment of the present invention, after the bridging metal layer is grown in situ within the window, the method further includes: The packaging body is divided into multiple independent packaging units by dicing along the preset cutting lines on the packaging body. The second carrier board is peeled off to obtain the packaged device.

[0013] An embedded chip packaging structure, comprising: The circuit board has pre-drilled holes, and a second electrode is provided on the working surface of the circuit board; A semiconductor chip is fixed in the reserved hole, and a first electrode is provided on the working surface of the semiconductor chip; The packaging body fills the lateral gap between the semiconductor chip and the reserved hole, and covers the side of the semiconductor chip and the circuit board away from their respective working surfaces; A bridging metal layer covers the working surface of the semiconductor chip and the working surface of the circuit substrate; An insulating protective layer covers the surface of the bridging metal layer and the area above the gap between the semiconductor chip and the circuit board; The working surface of the semiconductor chip and the working surface of the circuit substrate are on the same plane; the first electrode and the second electrode are electrically bonded in situ without leads through the bridging metal layer.

[0014] This application has the following advantages: In the embodiments of this application, the circuit board and semiconductor chip are jointly fixed on a first carrier plate for molding. Using the flat surface of the first carrier plate as a reference, the interface height difference caused by the size difference between the chip and the substrate, as well as the shrinkage of the molding compound during curing, is effectively absorbed and eliminated. After peeling off the first carrier plate, a flat working surface with the first and second electrodes being highly coplanar is obtained. Based on this, a bridging metal layer spanning both electrodes can be directly grown in situ on the exposed working surface using patterned masks and additive manufacturing processes. This achieves a leadless, integrated in-situ bonding electrical connection. Compared to traditional wire bonding and via interconnection methods, this further reduces the overall package thickness and high-frequency interconnect parasitic inductance, while enhancing the electrical connection stability and long-term operational reliability of the packaged device under complex thermodynamic cycling conditions. Attached Figure Description

[0015] To more clearly illustrate the technical solution of this application, the drawings used in the description of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic flowchart of an embedded chip packaging method provided in an embodiment of this application; Figure 2 This is a schematic flowchart of additional steps in an embodiment of the embedded chip packaging method provided in this application; Figure 3 This is a cross-sectional schematic diagram of a structure in one embodiment of this application, in which the circuit board is fixed to the first carrier plate; Figure 4 This is a cross-sectional schematic diagram of a structure in which a semiconductor chip is fixed in a reserved hole according to an embodiment of this application; Figure 5 This is a schematic cross-sectional view of the structure forming the encapsulation body in one embodiment of this application; Figure 6 This is a schematic cross-sectional view of the structure after the first carrier plate is peeled off and the second carrier plate is fixed in one embodiment of this application; Figure 7 This is a schematic cross-sectional view of a structure in which a mask layer is formed on the working surface according to an embodiment of this application; Figure 8 This is a schematic cross-sectional view of the structure in which the mask layer is exposed according to an embodiment of this application; Figure 9 This is a schematic cross-sectional view of the structure after the mask layer has been developed and a window has been formed in one embodiment of this application; Figure 10 This is a schematic cross-sectional view of a structure in which a bridging metal layer is grown in situ within a window, according to one embodiment of this application. Figure 11 This is a schematic cross-sectional view of the structure after removing the mask layer in one embodiment of this application; Figure 12 This is a schematic cross-sectional view of the structure forming the insulating protective layer in one embodiment of this application; Figure 13 This is a schematic cross-sectional view of the structure of the external electrode after surface anti-oxidation treatment in one embodiment of this application.

[0017] Figure 14 This is a cross-sectional schematic diagram of the embedded chip package structure obtained after removing the second carrier board in one embodiment of this application.

[0018] Figure label: 10. Circuit board; H10. Reserved hole; 101. Second electrode; 11. Semiconductor chip; 111. First electrode; 12. Packaging body; 13. Mask layer; 14. Bridging metal layer; 15. Insulating protective layer; 16. External electrode; 20. First carrier plate; 30. Second carrier plate. Detailed Implementation

[0019] To make the objectives, features, and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] The inventors, through analysis of existing technologies, discovered that in traditional embedded chip manufacturing processes, the lack of a unified constraint benchmark during assembly leads to the superposition of chip thickness tolerances, substrate processing deviations, and the curing shrinkage effect of molding compound. This inevitably results in a step difference between the electrode surface of the packaged chip and the working surface of the substrate. This non-coplanar state across the interface directly hinders circuit growth, forcing existing processes to resort to indirect bridging methods such as wire bonding or laser drilling for copper filling. However, these three-dimensional bridging structures not only increase parasitic inductance in the signal transmission path, leading to degradation of high-frequency electrical performance, but also make interconnect nodes prone to fatigue cracking due to stress concentration during repeated thermodynamic cycles.

[0021] Reference Figure 1This illustration shows an embedded chip packaging method provided in an embodiment of the present application, used to realize embedded packaging of a chip on a circuit board 10. The method includes: S101. Fix the circuit board 10 with the reserved hole H10 onto the first carrier plate 20.

[0022] In this step, the circuit board 10 and the first carrier plate 20 can be fixed by adhesive bonding, ensuring that one surface of the circuit board 10 is in contact with the surface of the first carrier plate 20, thereby forming a planar constraint in spatial position. The reserved hole H10 penetrates along the thickness direction of the circuit board 10 to accommodate the semiconductor chip 11, and the surface of the first carrier plate 20 closes the bottom opening of the reserved hole H10.

[0023] S102. At least one semiconductor chip 11 is fixed in the reserved hole H10, and the electrode surface of the semiconductor chip 11 faces the first carrier plate 20. A first electrode 111 is provided on the electrode surface, and a second electrode 101 is provided on the circuit board 10.

[0024] For example, the semiconductor chip 11 can be fixed to the first carrier plate 20 by adhesive bonding. In terms of spatial relative position, a lateral gap is left between the outer peripheral sidewall of the semiconductor chip 11 and the inner sidewall of the reserved hole H10 to allow the fluid medium to enter. The semiconductor chip 11 and the circuit board 10 are held together on the surface of the first carrier plate 20, and the first electrode 111 and the second electrode 101 both abut against the same surface of the first carrier plate 20.

[0025] S103. Fill the gap between the semiconductor chip 11 and the reserved hole H10 with molding compound, and cover the side of the semiconductor chip 11 and the circuit board 10 facing away from the first carrier board 20, and form the encapsulation body 12 after curing.

[0026] Preferably, the molding compound can be an epoxy molding compound with high filler content, low coefficient of thermal expansion, and low curing shrinkage. The molding material, in a fluid state, is injected along the lateral gap and spreads to the surfaces of the semiconductor chip 11 and the circuit board 10 opposite to the first carrier 20. Upon completion of curing, the molding material undergoes a physical state transformation and forms a package body 12 with overall structural strength. In this state, the relative position between the semiconductor chip 11 and the circuit board 10 is fixed using the package body 12.

[0027] S104. Fix the side of the packaging body 12 away from the first carrier plate 20 onto the second carrier plate 30, and peel off the first carrier plate 20 to expose the first electrode 111 of the semiconductor chip 11 and the second electrode 101 of the circuit board 10. The second carrier plate 30 is attached to the surface of the encapsulation body 12 opposite to the first carrier plate 20, providing reverse support for the entire structure to facilitate subsequent process steps. With the removal of the first carrier plate 20, the first electrode 111, the second electrode 101, and the surface between them made of molding compound are exposed, forming a continuous and exposed working surface.

[0028] S105. A patterned mask layer 13 is formed on the working surface exposing the first electrode 111 and the second electrode 101, the mask layer 13 having windows that expose the areas of the electrodes to be connected.

[0029] In other words, the mask layer 13 is attached to and covers the unbonded areas of the working surface to form physical isolation. The opening directly exposes the surfaces of the corresponding first electrode 111 and second electrode 101, thereby defining the metal additive region on the working surface.

[0030] S106. Using additive manufacturing process, a bridging metal layer 14 is grown in situ within the window so that the first electrode 111 and the second electrode 101 are electrically bonded through the bridging metal layer 14.

[0031] The added metal material is confined within the metal additive region defined by the window, and continuous mass accumulation and extension occur from the surface of the bottom electrode outward. The grown metal material spans the gap region between the semiconductor chip 11 and the circuit board 10, so that the first electrode 111 and the second electrode 101 can achieve direct physical connection and electrical conduction through the in-situ formed bridging metal layer 14.

[0032] In the embodiments of this application, the circuit board 10 and the semiconductor chip 11 are jointly fixed on the first carrier 20 for molding. Using the flat surface of the first carrier 20 as a reference, the interface height difference caused by the size difference between the chip and the substrate and the shrinkage of the molding compound during curing is effectively absorbed and eliminated. After peeling off the first carrier 20, a flat working surface is obtained where the first electrode 111 and the second electrode 101 are highly coplanar. Based on this, a bridging metal layer 14 spanning both electrodes can be grown in situ on the exposed working surface using patterned masks and additive manufacturing processes. This achieves a leadless, integrated in-situ bonding electrical connection. Compared to traditional wire bonding and via interconnection methods, this further reduces the overall package thickness and high-frequency interconnect parasitic inductance, while enhancing the electrical connection stability and long-term operational reliability of the packaged device under complex thermodynamic cycling conditions.

[0033] In one embodiment of the present invention, in the above steps, the circuit board 10 is fixed to the first carrier plate 20 by a first temporary adhesive layer. The semiconductor chip 11 is partially fixed to the first carrier plate 20 by the adhesive properties of the first temporary adhesive layer, so that the first electrode 111 of the semiconductor chip 11 is coplanar with the second electrode 101 of the circuit board 10.

[0034] Specifically, the first carrier plate 20 is a solid support plate with high flatness and high rigidity. The material of the first carrier plate 20 can be glass or a rigid silicon substrate, such as high borosilicate glass, quartz glass, or polished single crystal silicon wafer. A first temporary adhesive layer continuously and uniformly covers the surface of the first carrier plate 20, and this first temporary adhesive layer can be a heat-release adhesive or a laser release adhesive.

[0035] When assembling the semiconductor chip 11, the semiconductor chip 11 is grasped and placed into the pre-drilled hole H10 in a direction perpendicular to the first carrier plate 20. By applying a preset downward pressure, the electrode surface of the semiconductor chip 11 is directly pressed against the first temporary adhesive layer exposed at the bottom of the pre-drilled hole H10. Under the surface constraint of the first carrier plate 20, the first electrode 111 and the second electrode 101 can be kept on the same horizontal plane.

[0036] In this embodiment, the local adhesion of the first temporary adhesive layer at the reserved hole H10 is directly reused to position and solidify the chip, so that the first electrode 111 and the second electrode 101 maintain a better coplanar state, which provides a stable flatness guarantee for the subsequent direct growth of the high-precision bridging metal layer 14 across the gap.

[0037] In one embodiment of the present invention, step S103 includes: 1) In a vacuum environment, a compression molding process is used to fill the gap between the semiconductor chip 11 and the reserved hole H10 with the encapsulating material, and to cover the side of the semiconductor chip 11 and the circuit board 10 that is away from the first carrier board 20.

[0038] Specifically, the first carrier board 20, which carries the circuit board 10 and the semiconductor chip 11, is moved entirely into the molding cavity of the compression molding equipment, maintaining a vacuum environment. The molding compound used is an epoxy molding compound or liquid molding compound with low coefficient of thermal expansion and low curing shrinkage.

[0039] During the molding process, a predetermined mold temperature and compression pressure are applied to the molding material, and a certain holding time is maintained. Driven by the closing pressure, the molding material, in a molten or low-viscosity fluid state, spreads evenly from top to bottom, covering not only the back surface of the semiconductor chip 11 and the circuit board 10, but also flowing along the outer sidewalls of the semiconductor chip 11 until it fills the lateral gap between the sidewall of the semiconductor chip 11 and the inner wall of the pre-drilled hole H10. Because the vacuum environment eliminates the obstruction of residual gas, the molding material avoids the formation of cavitation or void defects during flow and filling, ensuring a dense fit at the component interface.

[0040] 2) The circuit board 10 covered with the molding compound is cured using a curing molding process to form the encapsulation body 12.

[0041] After demolding, the molding compound is in a preliminary formed state. The component covered with the molding compound is then transferred along with the first carrier plate 20 to a heat treatment device for post-curing. During curing, the first carrier plate 20 provides constraint through large-area bonding, limiting the deformation freedom of the circuit board 10 and the semiconductor chip 11 in the horizontal dimension, allowing the internal stress generated during curing to be released gradually. After the curing process is complete, the molding compound is fully cured, fixing the semiconductor chip 11 and the circuit board 10 into an integrated package body 12.

[0042] Vacuum compression molding and curing processes reduce air bubbles in the gaps between components, resulting in a dense encapsulation structure. The constraint of the first carrier plate 20 suppresses warping caused by the curing shrinkage of the molding material, further minimizing the coplanar height difference of the encapsulation body 12.

[0043] In one embodiment of the present invention, after the first carrier plate 20 is stripped away and before the patterned mask layer 13 is formed, the method further includes: using a plasma cleaning process to remove residual organic matter on the exposed working surface.

[0044] Specifically, after the first carrier plate 20 is detached, the working surface formed by the first electrode 111 of the semiconductor chip 11, the second electrode 101 of the circuit board 10, and the packaging body 12 is exposed. The packaging body 12, to which the second carrier plate 30 is fixed, is placed in the vacuum reaction chamber of a plasma cleaning device. A mixture of oxygen and argon is introduced into the chamber as the working gas to perform directional plasma treatment on the working surface, thereby cleaning the residue of the temporary adhesive. It is understood that chemical wet adhesive removal processes can also be used for cleaning.

[0045] By cleaning the working surface, the adhesion between the subsequent layer structure and the working surface is improved, and the potential risks such as coating peeling and abnormal contact impedance of interconnect nodes caused by local interface contamination are reduced.

[0046] In one embodiment of the present invention, step S104 specifically includes: 1) The surface of the encapsulation body 12 is flatly attached to and fixed onto the second carrier plate 30 through the second temporary adhesive layer.

[0047] For example, the second temporary adhesive layer may be an ultraviolet light-emitting film or a temporary bonding adhesive with high thermal stability, thereby enabling the second carrier plate 30 to replace the first carrier plate 20 in subsequent processes and provide reverse support and flatness maintenance for the encapsulation body 12.

[0048] 2) Based on the material properties of the first temporary adhesive layer, perform a peeling operation to remove the first carrier plate 20.

[0049] When the first temporary adhesive layer is a heat-release adhesive, the entire structure is heated. When the temperature reaches the set debonding temperature threshold, the first temporary adhesive layer undergoes a phase change and loses its adhesive force, thereby separating the first carrier plate 20 without mechanical stress. When the first temporary adhesive layer is a laser-release adhesive, a laser of a predetermined wavelength is transmitted from the back of the first carrier plate 20 for scanning and irradiation, directly vaporizing the adhesive interface to achieve the detachment of the first carrier plate 20.

[0050] The non-contact peeling method using thermal debonding or laser vaporization prevents damage to the interface between the semiconductor chip 11, the circuit board 10, and the packaging body 12 caused by forced removal of external force, ensuring that the exposed working surface after the first carrier board 20 is removed maintains its integrity and high-precision coplanarity.

[0051] In one embodiment of the present invention, step S105 includes: 1) A photoresist is coated on the working surface as the mask layer 13.

[0052] For example, a layer of photoresist is uniformly covered on the working surface by spin coating or spray coating process. After the coating operation is completed, the photoresist adhering to the working surface is pre-baked to cure it into a mask layer 13 that is tightly adhered to the entire working surface.

[0053] 2) Alignment is performed using alignment marks on the circuit substrate 10 and / or the semiconductor chip 11, and after exposure and development, the opening that exposes the first electrode 111 and the second electrode 101 is formed.

[0054] For example, the packaging body 12 coated with the mask layer 13 is transferred to an exposure device, and after optical alignment, the mask layer 13 is selectively irradiated with an i-line light source. Subsequently, it is immersed in a developing solution to dissolve the unexposed areas, forming an opening above the first electrode 111 and the second electrode 101 to expose the metal surfaces of the first electrode 111 and the second electrode 101.

[0055] By employing optical alignment based on preset marks and using an exposure and development process, a high-precision mask pattern can be formed on the working surface, providing a precise boundary for metal growth across gaps, ensuring the accuracy of the morphology of the bridging metal layer 14, and the reliability of the electrical connection between the first electrode 111 and the second electrode 101.

[0056] In one embodiment of the present invention, the additive manufacturing process is an electroplating process, and before forming the patterned mask layer 13, it further includes: using a physical vapor deposition process to deposit a conductive seed layer on the entire working surface.

[0057] Specifically, the encapsulation body 12 with the second carrier plate 30 is transferred to the vacuum magnetron sputtering reaction chamber of a physical vapor deposition (PVD) apparatus. Under vacuum conditions, target material is sputtered onto the entire working surface of the encapsulation body 12 to deposit a conductive seed layer. Specifically, first, a certain thickness of titanium or titanium-tungsten alloy is sputtered as the underlayer to form a barrier adhesion layer that can tightly adhere to the molding compound, the first electrode 111, and the second electrode 101. Then, in a continuous process without disrupting the vacuum environment, copper is sputtered in situ as the conductive layer. Together, these two elements constitute the conductive seed layer. This provides a uniformly distributed current conduction path for the subsequent electroplating process, which needs to be performed in a liquid phase environment.

[0058] Step S106 includes: 1) Using the conductive seed layer exposed by the window as a substrate, a thickened copper layer is grown in situ within the window using an electroplating process to form the bridging metal layer 14.

[0059] For example, after the photolithography windowing of the mask layer 13 is completed, the conductive seed layer is exposed at the bottom of the windowed area, while the conductive seed layer in the remaining non-bonded areas is covered and shielded by the mask layer 13. The aforementioned package body 12 is immersed in an electroplating solution and connected to an external DC power supply to deposit copper on the surface of the conductive seed layer to thicken it, so that the thickness of the in-situ grown thickened copper layer reaches a predetermined size, for example, 5 μm to 20 μm, thereby forming the bridging metal layer 14.

[0060] 2) Use stripping solution to remove the mask layer 13, and use micro-etching process to flash remove the conductive seed layer covered by the mask layer 13, so that each of the bridging metal layers 14 is electrically isolated from each other.

[0061] For example, the encapsulation body 12 is first washed with deionized water, and then placed in a stripping solution for cleaning, so that the mask layer 13 is completely peeled off from the surface of the conductive seed layer, thereby re-exposing the conductive seed layer in the non-bonded area. Finally, a short-time micro-etching process is performed, using copper etchant and titanium / titanium-tungsten etchant in sequence to perform rapid flash etching on the surface, thereby eroding and washing away the conductive seed layer in the non-bonded area and ensuring the reliability of the bonding of the bridging metal layer 14.

[0062] The bridging metal layer 14 was grown and formed by using a process that combines sputtering a conductive seed layer with local electroplating. At the same time, the conductive seed layer enhanced the bonding force between the bridging metal layer 14 and the packaging body 12.

[0063] In another embodiment of the present invention, the additive manufacturing process is a chemical plating process, and step S106 includes: In the area where the window exposes the first electrode 111 and the second electrode 101, the metal layer is thickened by in-situ growth of a self-catalytic chemical plating to form the bridging metal layer 14.

[0064] After opening a window in the mask layer 13, the first electrode 111 and the second electrode 101 are exposed. The package body 12 is immersed in a chemical plating solution (such as copper or nickel plating) without the need for an external power supply or conductive seed layer. Relying on the catalytic activity of the exposed electrodes, metal ions are reduced and precipitated on the electrode surface. The deposited metal grows directionally along the window opening, spanning the lateral gap between the semiconductor chip 11 and the circuit substrate 10, with a thickness of 5 μm to 20 μm, forming a bridging metal layer 14. Finally, the mask layer 13 is peeled off to expose the individual bridging metal layers 14.

[0065] The bridging metal layer 14 is grown in situ through a self-catalytic chemical plating process, which eliminates the need for physical vapor deposition of the conductive seed layer and subsequent micro-etching to remove the seed layer in conventional electroplating processes, thus simplifying the packaging process.

[0066] Reference Figure 2 As shown, in one embodiment of the present invention, after the bridging metal layer 14 is grown in situ within the window, the method further includes: S107. An insulating material is covered on the bridging metal layer 14 and the area exposing the working surface, and after curing, an insulating protective layer 15 is formed.

[0067] For example, a fluid insulating material is uniformly applied to the outer surface of the bridging metal layer 14 using a screen printing or spin coating process, simultaneously filling the exposed area above the gap between the semiconductor chip 11 and the circuit board 10. The package body 12 covered with the insulating material is then baked and cured to form a continuous insulating protective layer 15.

[0068] S108. The surface of the external electrode 16 disposed on the circuit board 10 is subjected to tin plating or nickel-palladium-gold plating for surface anti-oxidation treatment.

[0069] The surface of the external electrode 16 on the circuit board 10 for external electrical connection is exposed. Exemplarily, the package body 12 is immersed in a chemical plating bath, and a metal layer, such as tin plating or nickel-palladium-gold plating, is sequentially deposited on the exposed metal substrate of the external electrode 16 using a chemical plating process.

[0070] By adding an insulating protective layer 15 to the bridging metal layer 14, dielectric leakage between bridging traces is limited, ensuring the reliability of the electrical connection. Furthermore, the anti-oxidation treatment on the surface of the external electrode 16 suppresses the formation of metal oxides, which is beneficial to the electrical stability of the device in subsequent surface mount processes.

[0071] Reference Figure 2 As shown, in some embodiments of the present invention, after the bridging metal layer 14 is grown in situ within the window, the method further includes: S109. Divide the packaged body 12 along the preset cutting lines to form multiple independent packaged units.

[0072] S110. Peel off the second carrier plate 30 to obtain the packaged device.

[0073] If the second temporary adhesive layer is an ultraviolet light-emitting film, then an ultraviolet light source is used to irradiate the second carrier plate 30 from the side facing away from the packaging unit, causing the second temporary adhesive layer to lose its adhesiveness. Then, the second carrier plate 30 is removed to obtain the separated packaged device.

[0074] Reference Figures 3 to 14 One embodiment of this application provides an embedded chip packaging method, specifically including the following steps: Step 1: Temporarily fix the circuit board 10 with the reserved hole H10 onto the first carrier board 20.

[0075] Step 2: Fix at least one semiconductor chip 11 in the reserved hole H10, and make the first electrode 111 of the semiconductor chip 11 face the first carrier plate 20.

[0076] Step 3: Fill the gaps between components with molding compound and cover the back of semiconductor chip 11 and circuit board 10. After curing, form package body 12.

[0077] Step 4: Fix the side of the encapsulation body 12 away from the first carrier plate 20 onto the second carrier plate 30, and peel off the first carrier plate 20 to expose the working surface to be connected.

[0078] Step 5: Use plasma cleaning process to clean the exposed working surface and remove residual organic matter from the interface.

[0079] Step 6: If electroplating is to be used subsequently, a conductive seed layer is first deposited on the entire working surface using physical vapor deposition (if chemical plating is to be used, proceed directly to the next step 7).

[0080] Step 7: Coat the working surface with photoresist, and perform photolithography, exposure and development to form a patterned mask layer 13 and expose the electrode area to be connected.

[0081] Step 8: Using electroplating or autocatalytic chemical plating processes, a bridging metal layer 14 is grown in situ within the window to achieve leadless electrical bonding between the semiconductor chip 11 and the circuit board 10.

[0082] Step 9: After bonding is completed, use stripping solution to remove the mask layer 13 on the surface; if a conductive seed layer exists, use micro-etching process to flash remove the excess conductive seed layer to achieve electrical isolation of each bridging metal layer 14.

[0083] Step 10: Cover the bridging metal layer 14 and the gap area exposed on the working surface with insulating material, and after curing, form an insulating protective layer 15.

[0084] Step 11: Perform chemical tin plating or nickel-palladium-gold plating on the surface of the external electrode 16 disposed on the circuit board 10 to prevent oxidation.

[0085] Step 12: Divide the package body 12 along the preset cutting lines, then unattach and remove the second carrier plate 30 that provides support at the bottom to obtain the final independent packaged device.

[0086] Reference Figure 14 As shown, this embodiment of the invention also provides an embedded chip packaging structure, which can be manufactured by the packaging method described in the above embodiments. It includes a circuit board 10, a semiconductor chip 11, a packaging body 12, a bridging metal layer 14, and an insulating protective layer 15.

[0087] The circuit board 10 has a reserved hole H10, and a second electrode 101 is provided on the working surface of the circuit board 10.

[0088] The semiconductor chip 11 is fixed in the reserved hole H10, and the working surface of the semiconductor chip 11 is provided with a first electrode 111.

[0089] The encapsulation body 12 fills the lateral gap between the semiconductor chip 11 and the reserved hole H10, and covers the side of the semiconductor chip 11 and the circuit board 10 away from their respective working surfaces.

[0090] A bridging metal layer 14 covers the working surface of the semiconductor chip 11 and the working surface of the circuit substrate 10; An insulating protective layer 15 covers the surface of the bridging metal layer 14 and the area above the gap between the semiconductor chip 11 and the circuit board 10.

[0091] The working surface of the semiconductor chip 11 is on the same plane as the working surface of the circuit substrate 10; the first electrode 111 and the second electrode 101 are electrically bonded in situ without leads through the bridging metal layer 14.

[0092] The embedded chip packaging structure of this embodiment, through the back and side coverage and fixation of the packaging body 12, combined with the coplanar state of the front side, allows the bridging metal layer 14 to directly connect the first electrode 111 and the second electrode 101 on both sides along the flush surface. This structure avoids the three-dimensional space and bump soldering required by traditional wire bonding and via filling bonding, reduces the overall thickness of the device, and shortens the electrical signal transmission path. At the same time, it reduces the risk of interface stress concentration caused by thermal expansion and contraction of different components during temperature changes, and improves the stability of the structure and electrical connections.

[0093] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0094] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0095] The above provides a detailed description of an embedded chip packaging method and embedded chip packaging structure provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An embedded chip packaging method, characterized in that, include: The circuit board with pre-drilled holes is fixed onto the first carrier plate; At least one semiconductor chip is fixed in the reserved hole, with the electrode surface of the semiconductor chip facing the first carrier plate. A first electrode is provided on the electrode surface, and a second electrode is provided on the circuit board. The gap between the semiconductor chip and the reserved hole is filled with molding compound, and the semiconductor chip and the side of the circuit board facing away from the first carrier are covered. After curing, a package body is formed. The packaging body is fixed to the second carrier plate on the side facing away from the first carrier plate, and the first carrier plate is peeled off to expose the first electrode of the semiconductor chip and the second electrode of the circuit board. A patterned mask layer is formed on the working surface where the first electrode and the second electrode are exposed, the mask layer having windows that expose the areas of the electrodes to be connected; An additive manufacturing process is used to grow a bridging metal layer in situ within the opening, so that the first electrode and the second electrode are electrically bonded through the bridging metal layer.

2. The embedded chip packaging method according to claim 1, characterized in that, The circuit board is fixed to the first carrier plate by a first temporary adhesive layer; the semiconductor chip is fixed to the first carrier plate by the partial adhesion of the first temporary adhesive layer, so that the first electrode of the semiconductor chip is coplanar with the second electrode of the circuit board.

3. The embedded chip packaging method according to claim 1, characterized in that, The step of filling the gap between the semiconductor chip and the pre-drilled hole with a molding compound, and covering the side of the semiconductor chip and the circuit board facing away from the first carrier board, includes: In a vacuum environment, a compression molding process is used to fill the gap between the semiconductor chip and the reserved hole with the encapsulating material, and to cover the side of the semiconductor chip and the circuit board that is away from the first carrier board. The circuit board covered with molding compound is cured using a curing molding process to form the encapsulation body.

4. The embedded chip packaging method according to claim 1, characterized in that, After the first carrier plate is stripped away and before the patterned mask layer is formed, the process further includes: using a plasma cleaning process to remove residual organic matter from the exposed working surface.

5. The embedded chip packaging method according to claim 1, characterized in that, The process of forming a patterned mask layer on the working surface exposing the first electrode and the second electrode includes: A photoresist is coated on the working surface as the mask layer; Alignment is performed using alignment marks on the circuit board and / or the semiconductor chip, and after exposure and development, the opening that exposes the first electrode and the second electrode is formed.

6. The embedded chip packaging method according to claim 1, characterized in that, The additive manufacturing process is an electroplating process, and before forming the patterned mask layer, it further includes: A conductive seed layer is deposited on the entire working surface using a physical vapor deposition process. The in-situ growth of the bridging metal layer within the window includes: Using the conductive seed layer exposed by the window as a substrate, a thickened copper layer is grown in situ within the window using an electroplating process to form the bridging metal layer. The mask layer is removed using a stripping solution, and the conductive seed layer covered by the mask layer is flash-etched using a micro-etching process, thereby electrically isolating each of the bridging metal layers from each other.

7. The embedded chip packaging method according to claim 1, characterized in that, The additive manufacturing process is a chemical plating process, and the in-situ growth of the bridging metal layer within the window includes: In the area where the first electrode and the second electrode are exposed by the window, a thickened metal layer is formed by in-situ growth of a metal layer through autocatalytic electroless plating.

8. The embedded chip packaging method according to claim 1, characterized in that, After the bridging metal layer is grown in situ within the window, the process further includes: An insulating material is applied to the bridging metal layer and the area where the working surface is exposed, and then cured to form an insulating protective layer. The surface of the external electrodes configured on the circuit board is subjected to tin plating or nickel-palladium-gold plating for surface anti-oxidation treatment.

9. The embedded chip packaging method according to claim 1, characterized in that, After the bridging metal layer is grown in situ within the window, the process further includes: The packaging body is divided into multiple independent packaging units by dicing along the preset cutting lines on the packaging body. The second carrier board is peeled off to obtain the packaged device.

10. An embedded chip packaging structure, characterized in that, include: The circuit board has pre-drilled holes, and a second electrode is provided on the working surface of the circuit board; A semiconductor chip is fixed in the reserved hole, and a first electrode is provided on the working surface of the semiconductor chip; The packaging body fills the lateral gap between the semiconductor chip and the reserved hole, and covers the side of the semiconductor chip and the circuit board away from their respective working surfaces; A bridging metal layer covers the working surface of the semiconductor chip and the working surface of the circuit substrate; An insulating protective layer covers the surface of the bridging metal layer and the area above the gap between the semiconductor chip and the circuit board; The working surface of the semiconductor chip and the working surface of the circuit substrate are on the same plane; the first electrode and the second electrode are electrically bonded in situ without leads through the bridging metal layer.

Images