Chip packaging structure and its fabrication method, storage system and electronic device

Abstract

This disclosure provides a chip packaging structure and its fabrication method, a storage system, and an electronic device, relating to the field of semiconductor technology. The aim is to improve the stability and reliability of the chip packaging structure, as well as its yield. The chip packaging structure includes a first semiconductor structure, a first stacked structure, a second stacked structure, a second packaging layer, and a first packaging layer. The first stacked structure is located on one side of the first semiconductor structure along a first direction. The first stacked structure includes a plurality of second semiconductor structures stacked along the first direction. The second stacked structure is located on the side of the first stacked structure away from the first semiconductor structure. The second stacked structure includes a plurality of third semiconductor structures stacked along the first direction. The second packaging layer covers the second stacked structure. The first packaging layer covers the first semiconductor structure, the first stacked structure, and the second packaging layer. The above-described chip packaging structure is applied to a storage system to realize data read and write operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a chip packaging structure and its fabrication method, a storage system, and an electronic device. Background Technology

[0002] Planar memory cells can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly, pushing the memory density for planar memory cells close to its upper limit. Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells.

[0003] It should be noted that the information disclosed in the background section is only used to enhance the understanding of the background art of the technology described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0004] Embodiments of this disclosure provide a chip packaging structure and its fabrication method, a storage system, and an electronic device.

[0005] On the one hand, a method for fabricating a chip packaging structure is provided. The method for fabricating the chip packaging structure includes the following steps:

[0006] Multiple first semiconductor structures are arranged in an array on one side of the first carrier layer.

[0007] A first stacked structure is formed on the side of the first semiconductor structure away from the first carrier layer. The first stacked structure includes a plurality of second semiconductor structures stacked along a first direction, which is the thickness direction of the first semiconductor structure.

[0008] An initial first packaging layer is formed. The initial first packaging layer covers a plurality of first semiconductor structures and a plurality of first stacked structures, and fills the gaps between adjacent first semiconductor structures and between adjacent first stacked structures.

[0009] The initial first packaging layer is cut to obtain multiple first packaging layers. Each first packaging layer encapsulates a first semiconductor structure and a first stacked structure located on one side of the first semiconductor structure along a first direction.

[0010] In the above-mentioned method for fabricating a chip packaging structure, when forming the chip packaging structure, multiple first semiconductor structures are first arrayed on one side of the first carrier layer, and then a first stacked structure is formed on the side of the first semiconductor structures away from the first carrier layer. Compared with wafer-level packaging (WLP) process, on the one hand, the size of a single first semiconductor structure and a single second semiconductor structure in the first stacked structure is smaller, which can reduce the stress between the first semiconductor structure and the second semiconductor structure, as well as between two adjacent second semiconductor structures in the first stacked structure. This can avoid or reduce the probability of warping problems in the chip packaging structure, and is beneficial to improving the stability and reliability of the chip packaging structure.

[0011] On the other hand, when forming a chip packaging structure, forming multiple first semiconductor structures first allows for the detection and screening of multiple first semiconductor structures before forming the first stacked structure on the side of the first semiconductor structure away from the first carrier layer. This is beneficial for improving the yield of the chip packaging structure and reducing the manufacturing cost of the chip packaging structure.

[0012] In some embodiments, after forming the initial first packaging layer, the method for fabricating the chip packaging structure further includes removing the first carrier layer.

[0013] In some embodiments, after forming the initial first encapsulation layer and before removing the first carrier layer, the method for fabricating the chip package structure further includes the following steps:

[0014] A first cleavage is formed by cutting the first carrier layer from the side away from the first semiconductor structure. The first cleavage is located between adjacent first semiconductor structures along a direction perpendicular to a first direction. The first cleavage penetrates at least the first carrier layer along the first direction.

[0015] In some embodiments, along a first direction, the first cut also extends into the interior of the initial first encapsulation layer.

[0016] In some embodiments, a plurality of first semiconductor structures are arrayed on one side of the first carrier layer, including the following steps:

[0017] Multiple first semiconductor structures are arrayed on one side of the initial second carrier layer.

[0018] The initial second carrier layer is cut to obtain multiple second carrier layers. A first semiconductor structure is disposed on one side of each second carrier layer, and a second carrier layer and the first semiconductor structure located on one side of the second carrier layer form a transition stack structure.

[0019] Multiple transition stacked structures are arranged in an array on one side of the first bearing layer.

[0020] In some embodiments, after forming the initial first packaging layer, the method for fabricating the chip packaging structure further includes removing the first carrier layer and the second carrier layer.

[0021] In some embodiments, after forming the initial first encapsulation layer and before removing the first carrier layer and the second carrier layer, the method for fabricating the chip package structure further includes the following steps:

[0022] A first cleavage is formed by cutting the first carrier layer and the second carrier layer from the side of the first carrier layer away from the first semiconductor structure. The first cleavage is located between adjacent first semiconductor structures in a direction perpendicular to a first direction. The first cleavage penetrates at least the first carrier layer and the second carrier layer in the first direction.

[0023] In some embodiments, the method for fabricating the chip package structure further includes forming a second stacked structure. The second stacked structure includes a plurality of third semiconductor structures stacked along a first direction.

[0024] After forming a first stacked structure on the side of the first semiconductor structure away from the first carrier layer, and before forming an initial first packaging layer, the method for fabricating a chip packaging structure further includes setting a second stacked structure on the side of the first stacked structure away from the first semiconductor structure.

[0025] When forming the initial first encapsulation layer, the initial first encapsulation layer also covers the second stacked structure and fills the gaps between adjacent second stacked structures.

[0026] In some embodiments, forming a second stacked structure includes the following steps:

[0027] Multiple third semiconductor structures are arranged in an array on one side of the third carrier layer.

[0028] At least one third semiconductor structure is stacked along the first direction on the side of the third semiconductor structure away from the third carrier layer to form a second stacked structure.

[0029] An initial second encapsulation layer is formed. The initial second encapsulation layer covers multiple second stacked structures and fills the gaps between adjacent second stacked structures.

[0030] Remove the third load-bearing layer.

[0031] The initial second encapsulation layer is trimmed to obtain multiple second encapsulation layers. Each second encapsulation layer encapsulates a second stacked structure.

[0032] In some embodiments, the type of the third semiconductor structure is the same as the type of the second semiconductor structure.

[0033] In some embodiments, the second semiconductor structure is a dynamic random access memory or a flash memory.

[0034] In some embodiments, the second semiconductor structure includes a memory array layer and a peripheral device layer. The peripheral device layer is coupled to the memory array layer.

[0035] In some embodiments, the first stacked structure further includes a plurality of first connection portions located between adjacent second semiconductor structures. The second semiconductor structures are electrically connected to the first semiconductor structures via the first connection portions.

[0036] In some embodiments, the first stacked structure includes a first surface and a second surface opposite to each other in a first direction. The first stacked structure also includes at least one first conductive post located within the first stacked structure and extending along a first direction. The first conductive post includes a first end and a second end opposite to each other in the first direction, the first end located on the first surface, and the second end located within the target die corresponding to the conductive post. A second semiconductor structure is electrically connected to the first semiconductor structure via the first conductive post.

[0037] In some embodiments, the method for fabricating the chip package structure further includes forming a third stacked structure. The third stacked structure includes a plurality of fourth semiconductor structures stacked along a first direction.

[0038] After the second stacked structure is disposed on the side of the first stacked structure away from the first semiconductor structure, and before the initial first packaging layer is formed, the method for fabricating the chip packaging structure further includes disposing a third stacked structure on the side of the second stacked structure away from the first semiconductor structure.

[0039] When forming the initial first encapsulation layer, the initial first encapsulation layer also covers the third stack structure and fills the gaps between adjacent third stack structures.

[0040] In some embodiments, the first carrier layer includes an arrangement area and a peripheral area, the peripheral area surrounding the arrangement area. The arrangement area is transparent, and a plurality of first semiconductor structures are located in the arrangement area.

[0041] In some embodiments, a first alignment mark is provided in the peripheral area.

[0042] On the other hand, a chip packaging structure is provided. The chip packaging structure includes a first semiconductor structure, a first stacked structure, a second stacked structure, a second packaging layer, and a first packaging layer. The first stacked structure is located on one side of the first semiconductor structure along a first direction, where the first direction is the thickness direction of the first semiconductor structure. The first stacked structure includes a plurality of second semiconductor structures stacked along the first direction. The second stacked structure is located on the side of the first stacked structure away from the first semiconductor structure. The second stacked structure includes a plurality of third semiconductor structures stacked along the first direction. The second packaging layer covers the second stacked structure. The first packaging layer covers the first semiconductor structure, the first stacked structure, and the second packaging layer.

[0043] In some embodiments, the chip packaging structure further includes a first bonding layer, which is located between a first stacked structure and a second stacked structure. The first bonding layer is in contact with the first packaging layer.

[0044] In some embodiments, the second semiconductor structure is a dynamic random access memory (DRAM) or a flash memory. And / or, the third semiconductor structure is a DRAM or a flash memory.

[0045] In some embodiments, the second semiconductor structure includes a memory array layer and a peripheral device layer, wherein the peripheral device layer is coupled to the memory array layer. And / or, the third semiconductor structure includes a memory array layer and a peripheral device layer, wherein the peripheral device layer is coupled to the memory array layer.

[0046] In some embodiments, the chip package structure further includes a plurality of first connection portions located between adjacent second semiconductor structures. The second semiconductor structures are electrically connected to the first semiconductor structures via the first connection portions. And / or,

[0047] The chip package structure also includes multiple second interconnects located between adjacent third semiconductor structures. The third semiconductor structures are electrically connected to the first stacked structure via the second interconnects.

[0048] In some embodiments, the first stacked structure includes a first surface and a second surface opposite each other in a first direction. The first stacked structure also includes at least one first conductive pillar located within the first stacked structure and extending along the first direction. The first conductive pillar includes a first end and a second end opposite each other in the first direction, the first end located on the first surface, and the second end located within the target die corresponding to the first conductive pillar. The second semiconductor structure is electrically connected to the first semiconductor structure through the first conductive pillar. And / or,

[0049] The second stacked structure includes a third surface and a fourth surface opposite each other in the first direction. The second stacked structure also includes at least one second conductive pillar located within the second stacked structure and extending along the first direction. The second conductive pillar includes a third end and a fourth end opposite each other in the first direction, the third end located on the third surface, and the fourth end located within the target die corresponding to the second conductive pillar. The third semiconductor structure is electrically connected to the first stacked structure via the second conductive pillar.

[0050] In some embodiments, the chip package structure further includes a third stacked structure and a third encapsulation layer. The third stacked structure is located on the side of the second stacked structure away from the first semiconductor structure. The third stacked structure includes a plurality of fourth semiconductor structures stacked along a first direction. The third encapsulation layer covers the third stacked structure. The first encapsulation layer also covers the third encapsulation layer.

[0051] In some embodiments, the chip package structure further includes a fourth bonding layer. The fourth bonding layer is located between the second stack structure and the third stack structure. The fourth bonding layer is in contact with the first package layer.

[0052] In some embodiments, the fourth semiconductor structure is a dynamic random access memory or a flash memory.

[0053] In another aspect, a storage system is provided. The storage system includes a chip package structure and a controller as described in any of the above embodiments. The controller is electrically connected to the chip package structure.

[0054] In another aspect, an electronic device is provided. The electronic device includes a storage system and a processor as described in the above embodiments. The processor is coupled to the storage system.

[0055] It is understood that the beneficial effects of the chip packaging structure, storage system and electronic device provided by the above embodiments of this disclosure can be referred to the beneficial effects of the chip packaging structure preparation method described above, and will not be repeated here. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0057] Figure 1 This is a structural diagram of an electronic device provided according to some embodiments;

[0058] Figure 2 This is a structural diagram of a storage system provided according to some embodiments;

[0059] Figure 3 This is a structural diagram of a chip packaging structure provided according to some embodiments;

[0060] Figure 4 This is another structural diagram of the chip packaging structure provided according to some embodiments;

[0061] Figure 5 This is yet another structural diagram of a chip packaging structure provided according to some embodiments;

[0062] Figure 6 This is yet another structural diagram of a chip packaging structure provided according to some embodiments;

[0063] Figure 7 A structural diagram of a second semiconductor structure within a first stacked structure or a third semiconductor structure within a second stacked structure according to some embodiments;

[0064] Figure 8 This is a structural diagram of a storage array layer according to some embodiments;

[0065] Figure 9 This is a flowchart of a method for fabricating a chip packaging structure according to some embodiments;

[0066] Figure 10 This is another flowchart illustrating a method for fabricating a chip packaging structure according to some embodiments;

[0067] Figure 11 for Figure 9 and Figure 10 A structural diagram of the chip packaging structure corresponding to step S1 in the flowchart of the chip packaging structure fabrication method shown;

[0068] Figure 12 for Figure 11 A cross-sectional view of the chip packaging structure along section line AA;

[0069] Figure 13 for Figure 9 and Figure 10 A structural diagram of the chip packaging structure corresponding to step S2 in the flowchart of the chip packaging structure fabrication method shown;

[0070] Figure 14 for Figure 9 and Figure 10 Another structural diagram of the chip packaging structure corresponding to step S2 in the flowchart of the chip packaging structure fabrication method shown;

[0071] Figure 15 for Figure 9 and Figure 10 A structural diagram of the chip packaging structure corresponding to step S3 in the flowchart of the chip packaging structure fabrication method shown.

[0072] Figure 16 for Figure 9 and Figure 10 A structural diagram of the chip packaging structure corresponding to step S4 in the flowchart of the chip packaging structure fabrication method shown;

[0073] Figure 17 for Figure 11 A cross-sectional view of the chip packaging structure along section line BB;

[0074] Figure 18 for Figure 11A cross-sectional view of the chip packaging structure along section line CC;

[0075] Figure 19 for Figure 9 or Figure 10 A structural diagram of the chip packaging structure corresponding to steps S5 and S6 in the flowchart of the chip packaging structure fabrication method shown.

[0076] Figure 20 for Figure 9 and Figure 10 A structural diagram of the chip packaging structure corresponding to step S7 in the flowchart of the chip packaging structure fabrication method shown.

[0077] Figure 21 for Figure 9 and Figure 10 A structural diagram of the chip packaging structure corresponding to step S8 in the flowchart of the chip packaging structure fabrication method shown.

[0078] Figure 22 for Figure 9 and Figure 10 Another structural diagram of the chip packaging structure corresponding to step S3 in the flowchart of the chip packaging structure fabrication method shown;

[0079] Figure 23 for Figure 9 and Figure 10 Another structural diagram of the chip packaging structure corresponding to step S4 in the flowchart of the chip packaging structure fabrication method shown;

[0080] Figure 24 for Figure 9 or Figure 10 Another structural diagram of the chip packaging structure corresponding to steps S5 and S6 in the flowchart of the chip packaging structure fabrication method shown.

[0081] Figure 25 for Figure 9 and Figure 10 A structural diagram of the chip packaging structure corresponding to step S71 in the flowchart of the chip packaging structure fabrication method shown.

[0082] Figure 26 for Figure 25 A cross-sectional view of the chip packaging structure along section line DD;

[0083] Figure 27 for Figure 9 and Figure 10 A structural diagram of the chip packaging structure corresponding to step S72 in the flowchart of the chip packaging structure fabrication method shown;

[0084] Figure 28 for Figure 9 and Figure 10 A structural diagram of the chip packaging structure corresponding to step S73 in the flowchart of the chip packaging structure fabrication method shown.

[0085] Figure 29 for Figure 9 and Figure 10 A structural diagram of the chip packaging structure corresponding to step S74 in the flowchart of the chip packaging structure fabrication method shown.

[0086] Figure 30 for Figure 9 and Figure 10 A structural diagram of the chip packaging structure corresponding to step S75 in the flowchart of the chip packaging structure fabrication method shown.

[0087] Figure 31 for Figure 25 A cross-sectional view of the chip packaging structure along section line EE;

[0088] Figure 32 for Figure 25 A cross-sectional view of the chip packaging structure along section line FF;

[0089] Figure 33 This is yet another structural diagram of a chip packaging structure provided according to some embodiments;

[0090] Figure 34 This is yet another structural diagram of a chip packaging structure provided according to some embodiments;

[0091] Figure 35 A structural diagram of a chip packaging structure corresponding to step S9 in a chip packaging structure fabrication method according to some embodiments;

[0092] Figure 36 This is a structural diagram of a chip packaging structure corresponding to step S10 in a chip packaging structure fabrication method according to some embodiments;

[0093] Figure 37 A structural diagram of a chip packaging structure corresponding to step S3 in a chip packaging structure fabrication method according to some embodiments;

[0094] Figure 38 This is yet another structural diagram of a chip packaging structure provided according to some embodiments;

[0095] Figure 39 This is another structural diagram of a chip packaging structure provided according to some embodiments. Detailed Implementation

[0096] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0097] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0098] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0099] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0100] In this disclosure, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned, or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0101] In this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper structure, or may have a extent smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect vias (vias) are formed) and one or more dielectric layers.

[0102] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0103] It should be noted that, for example, 12 / 1F in the accompanying drawings of this disclosure indicates that the component is both 12 and 1F. Other similar reference numerals appearing in the drawings also follow the above description.

[0104] like Figure 1 As shown, this application provides an electronic device 1000. The electronic device 1000 may include a mobile phone, a tablet computer, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) devices, augmented reality (AR) devices, etc. This application does not impose any special limitations on the specific form of the aforementioned electronic device 1000.

[0105] In some embodiments, please continue reading Figure 1 The aforementioned electronic device 1000 may include a storage system 100 and a processor 200. The processor 200 is coupled to the storage system 100 to interact with the storage system 100.

[0106] For example, the processor 200 within the electronic device 1000 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0107] The storage system 100 described above will be described in detail below.

[0108] In some embodiments, such as Figure 2 As shown, Figure 2 This is a structural diagram of a storage system 100 provided according to some embodiments. The storage system 100 may include a chip package structure 10 and a controller 20. The controller 20 is electrically connected to the chip package structure 10 and can control the chip package structure 10 to store data.

[0109] For example, the storage system 100 described above can be integrated into a memory card. For instance, the memory card may include any of the following: Personal Computer Memory Card International Association (PCMCIA) card, Compact Flash (CF) card, Smart Media (SM) card, Memory Stick, Multimedia Card (MMC), Secure Digital Memory Card (SD), and Universal Flash Storage (UFS) card.

[0110] The storage system 100 described above can also be integrated into various types of storage devices. For example, the storage system 100 can be applied to and packaged into different types of electronic devices.

[0111] The aforementioned storage system 100 can also be integrated into a solid state drive (SSD).

[0112] For example, the controller 20 within the storage system 100 can be configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0113] The controller 20 within the storage system 100 can also be configured to operate in high duty cycle environments using SSDs or eMMCs, which are used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0114] For example, the controller 20 within the storage system 100 can be configured to manage data stored in the chip package structure 10 and communicate with external devices (e.g., a host).

[0115] The controller 20 within the storage system 100 can also be configured to control the operation of the chip package structure 10, such as read, erase, and program operations.

[0116] The controller 20 within the storage system 100 can also be configured to manage various functions related to data stored or to be stored in the chip package structure 10, including at least one of bad block management, garbage collection, logic-to-physical address translation, and wear leveling.

[0117] The controller 20 within the storage system 100 can also be configured to process error correction codes for data read from or written to the chip package structure 10.

[0118] Of course, the controller 20 within the storage system 100 can also perform any other suitable functions. For example, the controller 20 within the storage system 100 can format the chip package structure 10. As another example, the controller 20 within the storage system 100 can communicate with external devices (e.g., a host) via at least one of various interface protocols.

[0119] It should be noted that the aforementioned interface protocols may include at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0120] The chip packaging structure 10 described above will be explained in detail below.

[0121] In some embodiments, such as Figure 3and Figure 4 As shown, Figure 3 and Figure 4 These are all structural diagrams of a chip package structure 10 provided according to some embodiments. The chip package structure 10 may include a first semiconductor structure 11.

[0122] For example, please continue reading Figure 3 and Figure 4 The first semiconductor structure 11 can be a device that has been cut and tested from a wafer but has not been packaged. The first semiconductor structure 11 may not be directly applicable to actual circuits, but it can be applied to actual circuits after the first semiconductor structure 11 is formed into a chip package structure 10 through a packaging process.

[0123] For example, please continue reading Figure 3 and Figure 4 The first semiconductor structure 11 can be a logic device.

[0124] For example, a logic device can implement several logic functions. A logic device can include a circuit region. The circuit region can be an area comprising a wafer and circuitry provided by elements formed on the wafer. Some circuitry can constitute physical layer circuitry. When the physical layer circuitry is a transmitting circuit, it can be configured as a driver; when it is a receiving circuit, it can be configured as a buffer. The circuit region can be formed from silicon or the like.

[0125] In some embodiments, please continue reading Figure 3 and Figure 4 The chip packaging structure 10 may further include a first stacked structure D1. The first stacked structure D1 is located on one side of the first semiconductor structure 11 along a first direction Z, where the first direction Z is the thickness direction of the first semiconductor structure 11.

[0126] The first stacked structure D1 may include a plurality of second semiconductor structures 12 stacked along the first direction Z.

[0127] It should be noted that, Figure 3 and Figure 4 The illustrated embodiment only uses the example of the first stacked structure D1 within the chip package structure 10 including eight second semiconductor structures 12 for illustration. However, the number of second semiconductor structures 12 within the first stacked structure D1 is not limited to this. The number of second semiconductor structures 12 within the first stacked structure D1 can be set according to actual needs. For example, the number of second semiconductor structures 12 within the first stacked structure D1 can be 2, 3, 4, 12, 16, or 20, etc.

[0128] For example, please continue reading Figure 3 and Figure 4The second semiconductor structure 12 can be a bare die. A bare die is a device that has been cut and tested but has not been packaged. A bare die may not be directly applicable to an actual circuit, but it can be applied to an actual circuit after being packaged into a chip package structure 10 through a packaging process.

[0129] For example, please continue reading Figure 3 and Figure 4 The stacking method of the multiple second semiconductor structures 12 within the first stacked structure D1 can be 3D vertical stacking.

[0130] In the chip packaging structure 10 described above, the stacking method of the multiple second semiconductor structures 12 in the first stacking structure D1 is 3D vertical stacking, which can reduce the size of the first stacking structure D1, which is beneficial to the miniaturization of the first stacking structure D1 and the improvement of the integration of the first stacking structure D1. This can further reduce the size of the chip packaging structure 10 including the first stacking structure D1, thereby benefiting the miniaturization of the chip packaging structure 10 and the improvement of the integration of the chip packaging structure 10.

[0131] For example, please continue reading Figure 3 and Figure 4 The second semiconductor structure 12 within the first stacked structure D1 can be a memory.

[0132] When the second semiconductor structure 12 within the first stacked structure D1 is a memory, the storage density of the single first stacked structure D1 can be increased by providing multiple second semiconductor structures 12 within a single first stacked structure D1. The increased number of second semiconductor structures 12 relative to a single second semiconductor structure 12 will correspondingly increase the storage capacity.

[0133] For example, if the second semiconductor structure 12 within the first stacked structure D1 is a memory, the second semiconductor structure 12 within the first stacked structure D1 can be one of the following: ferroelectric random access memory (FRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), phase change memory (PCM), dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory.

[0134] In the case where the second semiconductor structure 12 is a dynamic random access memory (DRAM), the first stacked structure D1, comprising multiple stacked second semiconductor structures 12, can be a high-bandwidth memory (HBM). A high-bandwidth memory is a high-performance random access memory (RAM) that is a 3D stack of multiple DRAMs. HBMs are typically used in conjunction with high-performance graphics accelerators and network devices that access large datasets. HBMs generally achieve higher bandwidth while using less power in smaller form factors.

[0135] In the case where the second semiconductor structure 12 is a flash memory, the first stacked structure D1, which includes multiple stacked second semiconductor structures 12, can be a hybrid bonded flash memory (HBF) memory.

[0136] In some embodiments, please continue reading Figure 3 In the case where the first stacked structure D1 within the chip package structure 10 includes a plurality of second semiconductor structures 12, and the plurality of second semiconductor structures 12 are stacked along the first direction Z, the chip package structure 10 may further include a plurality of first connection portions 31. The first connection portions 31 are located between adjacent second semiconductor structures 12 within the first stacked structure D1.

[0137] The second semiconductor structure 12 within the first stacked structure D1 can be electrically connected to the first semiconductor structure 11 within the chip package structure 10 via the first connection portion 31.

[0138] For example, please continue reading Figure 3 The material of the first connection portion 31 within the chip package structure 10 may include a conductive material.

[0139] For example, the material of the first connection portion 31 within the chip package structure 10 may include one or more (two or more) of copper (Cu), nickel (Ni) and gold (Au).

[0140] For example, please continue reading Figure 3 The first connection portion 31 within the chip package structure 10 can be a micro bump.

[0141] For example, please continue reading Figure 3 The second semiconductor structure 12 within the first stacked structure D1 may include a plurality of first connection structures 41. The first connection structures 41 are located within the second semiconductor structure 12 and extend along the first direction Z (i.e., the thickness direction of the first semiconductor structure 11).

[0142] Along the first direction Z, the first connection structure 41 in two adjacent second semiconductor structures 12 can be electrically connected through the first connection portion 31.

[0143] In the chip packaging structure 10 described above, a plurality of second semiconductor structures 12 are stacked in the first stacking structure D1, and the first connection structure 41 extending along the first direction Z in two adjacent second semiconductor structures 12 is electrically connected through the first connection portion 31 located between the two adjacent second semiconductor structures 12, so that the second semiconductor structures 12 in the first stacking structure D1 can transmit signals through the first connection structure 41. On the one hand, since the first connection structure 41 extends along the first direction Z, the first connection structure 41 is arranged in a straight line, which makes the length of the first connection structure 41 smaller. This is beneficial to reducing the production cost of the first connection structure 41, and thus the production cost of the first stacked structure D1 and the chip packaging structure 10. It can also shorten the signal transmission distance of the second semiconductor structure 12 in the first stacked structure D1 when transmitting signals through the first connection structure 41. This is beneficial to reducing the transmission delay of the second semiconductor structure 12 in the first stacked structure D1 when transmitting signals, and reducing the signal attenuation of the second semiconductor structure 12 in the first stacked structure D1 when transmitting signals. This is beneficial to improving the signal transmission quality of the second semiconductor structure 12 in the first stacked structure D1, thereby improving the performance of the first stacked structure D1.

[0144] On the other hand, since the first connection structure 41 extending along the first direction Z in two adjacent second semiconductor structures 12 within the first stacked structure D1 is electrically connected through the first connection portion 31 located between the two adjacent second semiconductor structures 12, a direct short-distance (e.g., micrometer-level) electrical connection can be achieved between the first connection structures 41 extending along the first direction Z in the two adjacent second semiconductor structures 12, which is beneficial to reduce the power consumption of the first stacked structure D1 and achieve high-speed I / O throughput.

[0145] On the other hand, the first connection structure 41 in the first stacked structure D1 is located in the second semiconductor structure 12, and the first connection structures 41 extending along the first direction Z in two adjacent second semiconductor structures 12 are electrically connected through the first connection portion 31 located between the two adjacent second semiconductor structures 12, so that the multiple second semiconductor structures 12 in the first stacked structure D1 can be stacked vertically, thereby reducing the size of the first stacked structure D1, which is beneficial to the miniaturization of the first stacked structure D1 and the improvement of the integration of the first stacked structure D1. This can reduce the size of the chip package structure 10 including the first stacked structure D1, thereby benefiting the miniaturization of the chip package structure 10 and the improvement of the integration of the chip package structure 10.

[0146] For example, please continue reading Figure 3 The material of the first connection structure 41 within the second semiconductor structure 12 may include a conductive material.

[0147] For example, the material of the first connection structure 41 within the second semiconductor structure 12 may include one or more (two or more) of copper (Cu), nickel (Ni) and gold (Au).

[0148] For example, please continue reading Figure 3 When the second semiconductor structure 12 within the first stacked structure D1 includes a plurality of first connection structures 41, the chip package structure 10 may further include a first conductive unit M1. The first conductive unit M1 includes a plurality of first connection structures 41 located within the plurality of second semiconductor structures 12, and a first connection portion 31 located between any two adjacent second semiconductor structures 12 among the plurality of second semiconductor structures 12.

[0149] The first conductive unit M1 in the chip package structure 10 includes a plurality of first connection structures 41 and a plurality of first connection portions 31 connected in series in the first direction Z, so that the first conductive unit M1 in the chip package structure 10 can be connected to a plurality of second semiconductor structures 12 in the first stacked structure D1 along the first direction Z.

[0150] By connecting multiple first connection structures 41 and multiple first connection portions 31 included in the first conductive unit M1 within the chip package structure 10 in series along the first direction Z, the first conductive unit M1 within the chip package structure 10 extends along the first direction Z. When multiple second semiconductor structures 12 connected to the first conductive unit M1 along the first direction Z transmit signals through the first conductive unit M1, the signal transmission distance of the multiple second semiconductor structures 12 connected to the first conductive unit M1 along the first direction Z can be shortened. This helps to reduce the transmission delay of the multiple second semiconductor structures 12 connected to the first conductive unit M1 along the first direction Z during signal transmission and also helps to reduce the signal attenuation of the multiple second semiconductor structures 12 connected to the first conductive unit M1 along the first direction Z during signal transmission. This, in turn, helps to improve the signal transmission quality of the multiple second semiconductor structures 12 connected to the first conductive unit M1 along the first direction Z during signal transmission, thereby improving the performance of the chip package structure 10.

[0151] For example, please continue reading Figure 3In the case where the chip package structure 10 includes a first semiconductor structure 11, the first conductive unit M1 within the chip package structure 10, along the first direction Z, connects to a plurality of second semiconductor structures 12, and the first semiconductor structure 11, through which signal transmission can occur between the first conductive unit M1 and the first semiconductor structure 11. By extending the first conductive unit M1 within the chip package structure 10 along the first direction Z, when signal transmission occurs between the plurality of second semiconductor structures 12 connected to the first conductive unit M1 along the first direction Z and the first semiconductor structure 11, the length of the distance between the first conductive unit M1 and the first semiconductor structure 11 can be shortened. The reduced signal transmission distance between semiconductor structures 11 helps to reduce the transmission delay between the multiple second semiconductor structures 12 connected to the first conductive unit M1 along the first direction Z and the first semiconductor structure 11 during signal transmission, and also helps to reduce the signal attenuation between the multiple second semiconductor structures 12 connected to the first conductive unit M1 along the first direction Z and the first semiconductor structure 11 during signal transmission. This, in turn, helps to improve the signal transmission quality between the multiple second semiconductor structures 12 connected to the first conductive unit M1 along the first direction Z and the first semiconductor structure 11 during signal transmission, thereby improving the performance of the chip packaging structure 10.

[0152] For example, please continue reading Figure 3 In the case where the chip package structure 10 includes a first semiconductor structure 11 and a first stacked structure D1, and the first stacked structure D1 is located on one side of the first semiconductor structure 11 along the first direction Z, the chip package structure 10 may further include a third connection portion 33. The third connection portion 33 is located between the first semiconductor structure 11 and the first stacked structure D1. The first stacked structure D1 can be electrically connected to the first semiconductor structure 11 through the third connection portion 33.

[0153] For example, please continue reading Figure 3 In the case where the chip package structure 10 includes a first conductive unit M1, and the first conductive unit M1 includes a plurality of first connection structures 41 located within a plurality of second semiconductor structures 12, and a first connection portion 31 located between any two adjacent second semiconductor structures 12, the first conductive unit M1 can be electrically connected to the third connection portion 33, so that the plurality of second semiconductor structures 12 connected to the first conductive unit M1 along the first direction Z and the first semiconductor structure 11 can transmit signals through the first conductive unit M1 and the third connection portion 33.

[0154] For example, please continue reading Figure 3 The material of the third connection portion 33 within the chip package structure 10 may include a conductive material.

[0155] For example, the material of the third connection portion 33 within the chip package structure 10 may include one or more (two or more) of copper (Cu), nickel (Ni) and gold (Au).

[0156] For example, please continue reading Figure 3 The third connection portion 33 within the chip package structure 10 can be a micro bump.

[0157] In other embodiments, please continue to refer to Figure 4 In the case where the chip packaging structure 10 includes a first stacked structure D1, and the first stacked structure D1 includes a plurality of second semiconductor structures 12, and the plurality of second semiconductor structures 12 are stacked along the first direction Z, the first stacked structure D1 may include a first surface D1a and a second surface D1b that are opposite each other in the first direction Z.

[0158] The first stacked structure D1 may further include at least one first conductive post D11. The first conductive post D11 is located within the first stacked structure D1 and extends along the first direction Z.

[0159] The first conductive post D11 may include a first end D11a and a second end D11b opposite to each other in the first direction Z. The first end D11a of the first conductive post D11 is located on the first surface D1a of the first stacked structure D1, and the second end D11b of the first conductive post D11 is located within the target die 1F corresponding to the first conductive post D11. The second semiconductor structure 12 within the first stacked structure D1 can be electrically connected to the first semiconductor structure 11 within the chip package structure 10 through the first conductive post D11.

[0160] In the aforementioned chip packaging structure 10, the first conductive post D11 is located within the first stacked structure D1 and extends along the first direction Z. The first end D11a of the first conductive post D11 is located on the first surface D1a of the first stacked structure D1, and the second end D11b of the first conductive post D11 is located within the target die 1F corresponding to the first conductive post D11. This allows the target die 1F corresponding to the first conductive post D11 within the first stacked structure D1 to transmit signals through the first conductive post D11. On the one hand, since the first conductive post D11 extends along the first direction Z, the first conductive post D11 is arranged in a straight line, resulting in a smaller length of the first conductive post D11. This reduces the production cost of the first conductive post D11, thereby reducing the production cost of the chip packaging structure 10. It also shortens the signal transmission distance of the target die 1F corresponding to the first conductive post D11 when transmitting signals through the first conductive post D11, which helps reduce the transmission delay of the target die 1F corresponding to the first conductive post D11 and reduces the signal attenuation of the target die 1F corresponding to the first conductive post D11 during signal transmission. This, in turn, helps improve the signal transmission quality of the target die 1F corresponding to the first conductive post D11, thereby improving the performance of the chip packaging structure 10.

[0161] On the other hand, since the first conductive post D11 is located within the first stacked structure D1, the multiple second semiconductor structures 12 within the first stacked structure D1 can be stacked vertically, which can reduce the size of the first stacked structure D1, which is beneficial for miniaturization of the first stacked structure D1 and for improving the integration of the first stacked structure D1. This can further reduce the size of the chip package structure 10 including the first stacked structure D1, thereby benefiting the miniaturization of the chip package structure 10 and improving the integration of the chip package structure 10.

[0162] For example, please continue reading Figure 4When the chip package structure 10 includes a first semiconductor structure 11, the first end D11a of the first conductive post D11 can be electrically connected to the first semiconductor structure 11 in the chip package structure 10, so that the target die 1F corresponding to the first conductive post D11 and the first semiconductor structure 11 in the chip package structure 10 can transmit signals through the first conductive post D11. By extending the first conductive post D11 along the first direction Z, when signal transmission occurs between the target die 1F corresponding to the first conductive post D11 and the first semiconductor structure 11 through the first conductive post D11, the signal transmission distance between the target die 1F corresponding to the first conductive post D11 and the first semiconductor structure 11 can be shortened. This helps to reduce the transmission delay between the target die 1F corresponding to the first conductive post D11 and the first semiconductor structure 11 during signal transmission, and also helps to reduce the signal attenuation between the target die 1F corresponding to the first conductive post D11 and the first semiconductor structure 11 during signal transmission. This, in turn, helps to improve the signal transmission quality between the target die 1F corresponding to the first conductive post D11 and the first semiconductor structure 11 during signal transmission, thereby improving the performance of the chip packaging structure 10.

[0163] For example, please continue reading Figure 4 In the case where the chip packaging structure 10 includes a third connection portion 33, the third connection portion 33 is located between the first semiconductor structure 11 and the first stacked structure D1, and the first stacked structure D1 is electrically connected to the first semiconductor structure 11 through the third connection portion 33, the first conductive post D11 in the first stacked structure D1 can be electrically connected to the first semiconductor structure 11 through the third connection portion 33, so that the target die 1F corresponding to the first conductive post D11 and the first semiconductor structure 11 can transmit signals through the first conductive post D11 and the third connection portion 33.

[0164] For example, please continue reading Figure 4 The second semiconductor structure 12 within the first stacked structure D1 may include a first conductive layer 121. The first conductive layer 121 may extend along a second direction X, which is perpendicular to the first direction Z.

[0165] The aforementioned "the first end D11a of the first conductive post D11 is located on the first surface D1a of the first stacked structure D1, and the second end D11b of the first conductive post D11 is located within the target die 1F corresponding to the first conductive post D11" can be specifically defined as follows: the first end D11a of the first conductive post D11 is located on the first surface D1a of the first stacked structure D1, and the second end D11b of the first conductive post D11 is located within the target die 1F corresponding to the first conductive post D11, and is electrically connected to the first conductive layer 121 within the target die 1F, so that the first conductive post D11 and the target die 1F are electrically connected, thereby enabling the target die 1F corresponding to the first conductive post D11 within the first stacked structure D1 to transmit signals through the first conductive post D11.

[0166] For example, please continue reading Figure 4 The material of the first conductive post D11 may include a conductive material.

[0167] For example, please continue reading Figure 4 The material of the first conductive post D11 may include one or more of the following: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), and titanium nitride (TiN).

[0168] For example, please continue reading Figure 4 When the first end D11a of the first conductive post D11 is located on the first surface D1a of the first stacked structure D1, and the second end D11b of the first conductive post D11 is located within the target die 1F corresponding to the first conductive post D11, the connection between two adjacent second semiconductor structures 12 within the first stacked structure D1 can be direct bonding.

[0169] Direct bonding refers to the process of directly contacting the surfaces of two adjacent second semiconductor structures 12 within the first stacked structure D1 after cleaning and planing, and then subjecting them to heat and pressure. This allows atoms or molecules on both sides of the interface between the two adjacent second semiconductor structures 12 to diffuse into each other or form chemical bonds, thereby achieving a strong connection. This bonding method relies on the micromechanical forces (e.g., van der Waals forces) on the material surface and the possibility of chemical bonding.

[0170] In some embodiments, please continue reading Figure 3 and Figure 4 The chip package structure 10 may further include a first package layer 51. The first package layer 51 covers a first semiconductor structure 11 and a first stacked structure D1 located on one side of the first semiconductor structure 11 along the first direction Z.

[0171] In the chip packaging structure 10 described above, the first packaging layer 51 covers the first semiconductor structure 11 and the first stacked structure D1. On the one hand, it can increase the strength of the first semiconductor structure 11 and the first stacked structure D1, thereby reducing the risk of damage to the first semiconductor structure 11 and the first stacked structure D1 caused by external stress (e.g., thermal stress and mechanical shock), which is beneficial to improving the stability and reliability of the chip packaging structure 10.

[0172] On the other hand, the first packaging layer 51 can protect the first semiconductor structure 11 and the first stacked structure D1, and can reduce or avoid the influence of the external environment (e.g., moisture, temperature and pollution) on the first semiconductor structure 11 and the first stacked structure D1, which is conducive to further improving the stability and reliability of the chip packaging structure 10.

[0173] For example, please continue reading Figure 3 and Figure 4 The material of the first encapsulation layer 51 within the chip packaging structure 10 may include one or more (two or more) of epoxy resin, expanding monomer and curing agent.

[0174] In some embodiments, such as Figure 5 and Figure 6 As shown, Figure 5 and Figure 6 These are all structural diagrams of a chip package structure 10 provided according to some embodiments. The chip package structure 10 may also include a second stacking structure D2.

[0175] In the case where the chip package structure 10 includes a first stacked structure D1 and a first semiconductor structure 11, the second stacked structure D2 can be located on the side of the first stacked structure D1 away from the first semiconductor structure 11. That is, the first stacked structure D1 can be closer to the first semiconductor structure 11 than the second stacked structure D2.

[0176] The second stacked structure D2 may include a plurality of third semiconductor structures 13 stacked along the first direction Z.

[0177] It should be noted that, Figure 5 and Figure 6The illustrated embodiment only uses the example of the second stacked structure D2 within the chip package structure 10 including four third semiconductor structures 13 for illustration. However, the number of third semiconductor structures 13 within the second stacked structure D2 is not limited to this. The number of third semiconductor structures 13 within the second stacked structure D2 can be set according to actual needs. For example, the number of third semiconductor structures 13 within the second stacked structure D2 can be 2, 3, 8, 12, 16, or 20, etc.

[0178] For example, please continue reading Figure 5 and Figure 6 The third semiconductor structure 13 can be a bare die. A bare die is a device that has been cut and tested but has not been packaged. A bare die may not be directly applicable to an actual circuit, but it can be applied to an actual circuit after being packaged into a chip package structure 10 through a packaging process.

[0179] For example, please continue reading Figure 5 and Figure 6 The stacking method of the multiple third semiconductor structures 13 within the second stacked structure D2 can be 3D vertical stacking.

[0180] In the chip packaging structure 10 described above, the stacking method of the multiple third semiconductor structures 13 in the second stacking structure D2 is 3D vertical stacking, which can reduce the size of the second stacking structure D2, which is beneficial to the miniaturization of the second stacking structure D2 and the integration of the second stacking structure D2. This can reduce the size of the chip packaging structure 10 including the second stacking structure D2, thereby benefiting the miniaturization of the chip packaging structure 10 and the integration of the chip packaging structure 10.

[0181] For example, please continue reading Figure 5 and Figure 6 The third semiconductor structure 13 within the second stacked structure D2 can be a memory.

[0182] When the third semiconductor structure 13 within the second stacked structure D2 is a memory, the storage density of the single second stacked structure D2 can be increased by providing multiple third semiconductor structures 13 within a single second stacked structure D2. The increased number of third semiconductor structures 13 compared to a single third semiconductor structure 13 will correspondingly increase the storage capacity.

[0183] For example, if the third semiconductor structure 13 in the second stacked structure D2 is a memory, the third semiconductor structure 13 in the second stacked structure D2 can be one of ferroelectric random access memory, resistive random access memory, magnetic random access memory, phase change memory, dynamic random access memory, static random access memory, and flash memory.

[0184] When the third semiconductor structure 13 is a dynamic random access memory, the second stacked structure D2, which includes multiple stacked third semiconductor structures 13, can be a high-bandwidth memory.

[0185] In the case where the third semiconductor structure 13 is a flash memory, the second stacked structure D2, which includes multiple stacked third semiconductor structures 13, can be a hybrid bonded flash memory.

[0186] For example, please continue reading Figure 5 and Figure 6 In the case where the first stacked structure D1 within the chip package structure 10 includes a plurality of second semiconductor structures 12 stacked along the first direction Z, the type of the third semiconductor structure 13 within the second stacked structure D2 may be different from the type of the second semiconductor structure 12.

[0187] Alternatively, the type of the third semiconductor structure 13 within the second stacked structure D2 can be the same as the type of the second semiconductor structure 12.

[0188] For example, when the type of the third semiconductor structure 13 is the same as that of the second semiconductor structure 12, both the third semiconductor structure 13 and the second semiconductor structure 12 can be dynamic random access memory or flash memory.

[0189] In some embodiments, please continue reading Figure 5 In the case where the second stacked structure D2 within the chip package structure 10 includes a plurality of third semiconductor structures 13, and the plurality of third semiconductor structures 13 are stacked along the first direction Z, the chip package structure 10 may further include a plurality of second connection portions 32. The second connection portions 32 are located between adjacent third semiconductor structures 13 within the second stacked structure D2.

[0190] The third semiconductor structure 13 within the second stacked structure D2 can be electrically connected to the first stacked structure D1 within the chip package structure 10 via the second connection portion 32.

[0191] For example, please continue reading Figure 5 The material of the second connection portion 32 within the chip package structure 10 may include a conductive material.

[0192] For example, the material of the second connection portion 32 within the chip package structure 10 may include one or more (two or more) of copper (Cu), nickel (Ni) and gold (Au).

[0193] For example, please continue reading Figure 5 The second connection portion 32 within the chip package structure 10 can be a micro bump.

[0194] For example, please continue reading Figure 5 The third semiconductor structure 13 within the second stacked structure D2 may include a plurality of second connection structures 42. The second connection structures 42 are located within the third semiconductor structure 13 and extend along the first direction Z.

[0195] Along the first direction Z, the second connection structures 42 within two adjacent third semiconductor structures 13 can be electrically connected through the second connection portion 32.

[0196] In the chip packaging structure 10 described above, a plurality of third semiconductor structures 13 are stacked in the second stack structure D2, and the second connection structure 42 extending along the first direction Z in two adjacent third semiconductor structures 13 is electrically connected through the second connection portion 32 located between the two adjacent third semiconductor structures 13, so that the third semiconductor structures 13 in the second stack structure D2 can transmit signals through the second connection structure 42. On the one hand, since the second connection structure 42 extends along the first direction Z, the second connection structure 42 is arranged in a straight line, which makes the length of the second connection structure 42 smaller. This is beneficial to reducing the production cost of the second connection structure 42, and thus the production cost of the second stacked structure D2 and the chip packaging structure 10. It can also shorten the signal transmission distance of the third semiconductor structure 13 in the second stacked structure D2 when transmitting signals through the second connection structure 42. This is beneficial to reducing the transmission delay of the third semiconductor structure 13 in the second stacked structure D2 when transmitting signals, and reducing the signal attenuation of the third semiconductor structure 13 in the second stacked structure D2 when transmitting signals. This is beneficial to improving the signal transmission quality of the third semiconductor structure 13 in the second stacked structure D2, thereby improving the performance of the second stacked structure D2.

[0197] On the other hand, since the second connection structures 42 extending along the first direction Z in two adjacent third semiconductor structures 13 within the second stacked structure D2 are electrically connected through the second connection portion 32 located between the two adjacent third semiconductor structures 13, a direct short-distance (e.g., micrometer-level) electrical connection can be achieved between the second connection structures 42 extending along the first direction Z in the two adjacent third semiconductor structures 13, which is beneficial to reduce the power consumption of the second stacked structure D2 and achieve high-speed I / O throughput.

[0198] On the other hand, the second connection structure 42 within the second stacked structure D2 is located within the third semiconductor structure 13, and the second connection structures 42 extending along the first direction Z within two adjacent third semiconductor structures 13 are electrically connected through the second connection portion 32 located between the two adjacent third semiconductor structures 13. This allows multiple third semiconductor structures 13 within the second stacked structure D2 to be stacked vertically, thereby reducing the size of the second stacked structure D2, which is beneficial for miniaturization of the second stacked structure D2 and for improving the integration of the second stacked structure D2. This, in turn, reduces the size of the chip package structure 10 including the second stacked structure D2, which is beneficial for miniaturization of the chip package structure 10 and for improving the integration of the chip package structure 10.

[0199] For example, please continue reading Figure 5 The material of the second connection structure 42 within the third semiconductor structure 13 may include a conductive material.

[0200] For example, the material of the second connection structure 42 within the third semiconductor structure 13 may include one or more (two or more) of copper (Cu), nickel (Ni) and gold (Au).

[0201] For example, please continue reading Figure 5 When the third semiconductor structure 13 within the second stacked structure D2 includes a plurality of second connection structures 42, the chip package structure 10 may further include a second conductive unit M2. The second conductive unit M2 includes a plurality of second connection structures 42 located within the plurality of third semiconductor structures 13, and a second connection portion 32 located between any two adjacent third semiconductor structures 13 among the plurality of third semiconductor structures 13.

[0202] The second conductive unit M2 in the chip package structure 10 includes a plurality of second connection structures 42 and a plurality of second connection portions 32 connected in series in the first direction Z, so that the second conductive unit M2 in the chip package structure 10 can be connected to a plurality of third semiconductor structures 13 in the second stacked structure D2 along the first direction Z.

[0203] By connecting multiple second connection structures 42 and multiple second connection portions 32 included in the second conductive unit M2 within the chip package structure 10 in series along the first direction Z, the second conductive unit M2 within the chip package structure 10 extends along the first direction Z. When multiple third semiconductor structures 13 connected to the second conductive unit M2 along the first direction Z transmit signals through the second conductive unit M2, the signal transmission distance of the multiple third semiconductor structures 13 connected to the second conductive unit M2 along the first direction Z can be shortened. This helps to reduce the transmission delay of the multiple third semiconductor structures 13 connected to the second conductive unit M2 along the first direction Z during signal transmission and also helps to reduce the signal attenuation of the multiple third semiconductor structures 13 connected to the second conductive unit M2 along the first direction Z during signal transmission. This, in turn, helps to improve the signal transmission quality of the multiple third semiconductor structures 13 connected to the second conductive unit M2 along the first direction Z during signal transmission, thereby improving the performance of the chip package structure 10.

[0204] For example, please continue reading Figure 5 In the case where the chip package structure 10 includes a first stacked structure D1, the plurality of third semiconductor structures 13 connected to the second conductive unit M2 along the first direction Z within the chip package structure 10 and the first stacked structure D1 can transmit signals through the second conductive unit M2. By extending the second conductive unit M2 within the chip package structure 10 along the first direction Z, when signal transmission occurs between the plurality of third semiconductor structures 13 connected to the second conductive unit M2 along the first direction Z and the first stacked structure D1 through the second conductive unit M2, the length of the plurality of third semiconductor structures 13 connected to the second conductive unit M2 along the first direction Z and the first stacked structure D1 can be shortened. The signal transmission distance between the first stacked structures D1 is beneficial to reducing the transmission delay between the multiple third semiconductor structures 13 connected to the second conductive unit M2 along the first direction Z and the first stacked structure D1 during signal transmission. It is also beneficial to reduce the signal attenuation between the multiple third semiconductor structures 13 connected to the second conductive unit M2 along the first direction Z and the first stacked structure D1 during signal transmission. This is beneficial to improving the signal transmission quality between the multiple third semiconductor structures 13 connected to the second conductive unit M2 along the first direction Z and the first stacked structure D1 during signal transmission, thereby improving the performance of the chip packaging structure 10.

[0205] For example, please continue reading Figure 5In the case where the chip package structure 10 includes a first stacked structure D1 and a first semiconductor structure 11, and the second stacked structure D2 is located on the side of the first stacked structure D1 away from the first semiconductor structure 11, the chip package structure 10 may further include a first bonding layer 34a. The first bonding layer 34a is located between the first stacked structure D1 and the second stacked structure D2.

[0206] The first bonding layer 34a may include a plurality of fourth connecting portions 34. The second stacked structure D2 may be electrically connected to the first stacked structure D1 through the fourth connecting portions 34.

[0207] For example, please continue reading Figure 5 In the case where the chip package structure 10 includes a second conductive unit M2, and the second conductive unit M2 includes a plurality of second connection structures 42 located within a plurality of third semiconductor structures 13, and a second connection portion 32 located between any two adjacent third semiconductor structures 13, the second conductive unit M2 can be electrically connected to the fourth connection portion 34, so that the plurality of third semiconductor structures 13 connected by the second conductive unit M2 along the first direction Z and the first stacked structure D1 can transmit signals through the second conductive unit M2 and the fourth connection portion 34.

[0208] For example, please continue reading Figure 5 In the case where the chip packaging structure 10 includes a first packaging layer 51 and a first bonding layer 34a, the first bonding layer 34a can contact the first packaging layer 51.

[0209] For example, please continue reading Figure 5 The material of the fourth connection portion 34 within the first bonding layer 34a may include a conductive material.

[0210] For example, the material of the fourth connection portion 34 within the first bonding layer 34a may include one or more (two or more) of copper (Cu), nickel (Ni) and gold (Au).

[0211] For example, please continue reading Figure 5 The fourth connection portion 34 within the first bonding layer 34a can be a micro bump.

[0212] In other embodiments, please continue to refer to Figure 6 In the case where the chip package structure 10 includes a second stacked structure D2, and the second stacked structure D2 includes a plurality of third semiconductor structures 13, and the plurality of third semiconductor structures 13 are stacked along the first direction Z, the second stacked structure D2 may include a third surface D2a and a fourth surface D2b opposite to each other in the first direction Z.

[0213] The second stacked structure D2 may further include at least one second conductive post D12. The second conductive post D12 is located within the second stacked structure D2 and extends along the first direction Z.

[0214] The second conductive post D12 may include a third end D12a and a fourth end D12b opposite to each other in the first direction Z. The third end D12a of the second conductive post D12 is located on the third surface D2a of the second stacked structure D2, and the fourth end D12b of the second conductive post D12 is located within the target die 1F corresponding to the second conductive post D12. The third semiconductor structure 13 within the second stacked structure D2 can be electrically connected to the first stacked structure D1 within the chip package structure 10 through the second conductive post D12.

[0215] In the aforementioned chip packaging structure 10, the second conductive post D12 is located within the second stacked structure D2 and extends along the first direction Z. The third end D12a of the second conductive post D12 is located on the third surface D2a of the second stacked structure D2, and the fourth end D12b of the second conductive post D12 is located within the target die 1F corresponding to the second conductive post D12. This allows the target die 1F corresponding to the second conductive post D12 within the second stacked structure D2 to transmit signals through the second conductive post D12. On the one hand, since the second conductive post D12 extends along the first direction Z, the second conductive post D12 is arranged in a straight line, resulting in a smaller length for the second conductive post D12. This reduces the production cost of the second conductive post D12, thereby reducing the production cost of the chip packaging structure 10. It also shortens the signal transmission distance of the target die 1F corresponding to the second conductive post D12 when transmitting signals through the second conductive post D12, which helps reduce the transmission delay of the target die 1F corresponding to the second conductive post D12 during signal transmission and reduces the signal attenuation of the target die 1F corresponding to the second conductive post D12 during signal transmission. This, in turn, helps improve the signal transmission quality of the target die 1F corresponding to the second conductive post D12 during signal transmission, thereby improving the performance of the chip packaging structure 10.

[0216] On the other hand, since the second conductive post D12 is located within the second stacked structure D2, the multiple third semiconductor structures 13 within the second stacked structure D2 can be stacked vertically, which can reduce the size of the second stacked structure D2, which is beneficial for miniaturization of the second stacked structure D2 and for improving the integration of the second stacked structure D2. This can further reduce the size of the chip package structure 10 including the second stacked structure D2, thereby benefiting the miniaturization of the chip package structure 10 and improving the integration of the chip package structure 10.

[0217] For example, please continue reading Figure 6When the chip package structure 10 includes a first stacked structure D1, the third end D12a of the second conductive post D12 can be electrically connected to the first stacked structure D1 within the chip package structure 10, so that the target die 1F corresponding to the second conductive post D12 and the first stacked structure D1 within the chip package structure 10 can transmit signals through the second conductive post D12. By extending the second conductive post D12 along the first direction Z, when signal transmission occurs between the target die 1F corresponding to the second conductive post D12 and the first stacked structure D1 via the second conductive post D12, the signal transmission distance between the target die 1F corresponding to the second conductive post D12 and the first stacked structure D1 can be shortened. This helps to reduce the transmission delay between the target die 1F corresponding to the second conductive post D12 and the first stacked structure D1 during signal transmission, and also helps to reduce the signal attenuation between the target die 1F corresponding to the second conductive post D12 and the first stacked structure D1 during signal transmission. This, in turn, helps to improve the signal transmission quality between the target die 1F corresponding to the second conductive post D12 and the first stacked structure D1 during signal transmission, thereby improving the performance of the chip package structure 10.

[0218] For example, please continue reading Figure 6 In a chip packaging structure 10, a first bonding layer 34a is included. The first bonding layer 34a is located between a first stacked structure D1 and a second stacked structure D2. The first bonding layer 34a includes a plurality of fourth connection portions 34. When the second stacked structure D2 is electrically connected to the first stacked structure D1 through the fourth connection portions 34, the second conductive post D12 in the second stacked structure D2 can be electrically connected to the first stacked structure D1 through the fourth connection portions 34. This allows signal transmission between the target die 1F corresponding to the second conductive post D12 and the first stacked structure D1 through the second conductive post D12 and the fourth connection portions 34.

[0219] For example, please continue reading Figure 6 The third semiconductor structure 13 within the second stacked structure D2 may include a second conductive layer 122. The second conductive layer 122 may extend along the second direction X.

[0220] The aforementioned "the third end D12a of the second conductive post D12 is located on the third surface D2a of the second stacked structure D2, and the fourth end D12b of the second conductive post D12 is located within the target die 1F corresponding to the second conductive post D12" can be specifically defined as follows: the third end D12a of the second conductive post D12 is located on the third surface D2a of the second stacked structure D2, and the fourth end D12b of the second conductive post D12 is located within the target die 1F corresponding to the second conductive post D12, and is electrically connected to the second conductive layer 122 within the target die 1F, so that the second conductive post D12 and the target die 1F are electrically connected, thereby enabling the target die 1F corresponding to the second conductive post D12 within the second stacked structure D2 to transmit signals through the second conductive post D12.

[0221] For example, please continue reading Figure 6 The material of the second conductive post D12 may include a conductive material.

[0222] For example, please continue reading Figure 6 The material of the second conductive post D12 may include one or more of the following: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), and titanium nitride (TiN).

[0223] For example, please continue reading Figure 6 When the second conductive post D12 is located within the second stacked structure D2 and extends along the first direction Z, the third end D12a of the second conductive post D12 is located on the third surface D2a of the second stacked structure D2, and the fourth end D12b of the second conductive post D12 is located within the target die 1F corresponding to the second conductive post D12, the connection between two adjacent third semiconductor structures 13 within the second stacked structure D2 can be direct bonding.

[0224] Direct bonding refers to the process of directly contacting the surfaces of two adjacent third semiconductor structures 13 within the second stacked structure D2 after cleaning and planing, and then subjecting them to heat and pressure. This allows atoms or molecules on both sides of the interface between the two adjacent third semiconductor structures 13 to diffuse into each other or form chemical bonds, thereby achieving a strong connection. This bonding method relies on the micromechanical forces (e.g., van der Waals forces) on the material surface and the possibility of chemical bonding.

[0225] In some embodiments, please continue reading Figure 5 and Figure 6 When the chip package structure 10 includes a second stacked structure D2, the chip package structure 10 may further include a second packaging layer 52. The second packaging layer 52 covers the second stacked structure D2.

[0226] In the chip packaging structure 10 described above, the second packaging layer 52 covers the second stacked structure D2. On the one hand, it can increase the strength of the second stacked structure D2, thereby reducing the risk of damage to the second stacked structure D2 caused by external stress (e.g., thermal stress and mechanical shock), which is beneficial to improving the stability and reliability of the chip packaging structure 10.

[0227] On the other hand, the second encapsulation layer 52 can protect the second stacked structure D2, and can reduce or avoid the influence of the external environment (e.g., moisture, temperature and pollution) on the second stacked structure D2, which is conducive to further improving the stability and reliability of the chip packaging structure 10.

[0228] For example, please continue reading Figure 5 and Figure 6 The material of the second encapsulation layer 52 within the chip packaging structure 10 may include one or more (two or more) of epoxy resin, expanding monomer, and curing agent.

[0229] For example, please continue reading Figure 5 and Figure 6 In the case where the chip packaging structure 10 includes a first packaging layer 51 and the first packaging layer 51 covers the first semiconductor structure 11 and the first stacked structure D1, the first packaging layer 51 may also cover the second packaging layer 52.

[0230] For example, please continue reading Figure 5 and Figure 6 The materials of the first encapsulation layer 51 and the second encapsulation layer 52 can be different.

[0231] Alternatively, the materials of the first encapsulation layer 51 and the second encapsulation layer 52 can be the same.

[0232] It should be noted that when the materials of the first encapsulation layer 51 and the second encapsulation layer 52 are the same, since the first encapsulation layer 51 and the second encapsulation layer 52 are formed in steps, there is a time interval between the forming process of the first encapsulation layer 51 and the forming process of the second encapsulation layer 52. This may result in differences between the molecular structures of the first encapsulation layer 51 and the second encapsulation layer 52, or differences between the crosslink density of the first encapsulation layer 51 and the crosslink density of the second encapsulation layer 52. This may result in a connection interface between the first encapsulation layer 51 and the second encapsulation layer 52.

[0233] In some embodiments, such as Figure 33 and Figure 34 As shown, Figure 33 and Figure 34These are all structural diagrams of a chip package structure 10 provided according to some embodiments. The chip package structure 10 may also include a third stacking structure D3.

[0234] In the case where the chip package structure 10 includes a first stacked structure D1, a second stacked structure D2, and a first semiconductor structure 11, the third stacked structure D3 can be located on the side of the second stacked structure D2 away from the first semiconductor structure 11. That is, the second stacked structure D2 can be closer to the first semiconductor structure 11 than the third stacked structure D3.

[0235] The third stacked structure D3 may include a plurality of fourth semiconductor structures 14 stacked along the first direction Z.

[0236] It should be noted that, Figure 33 and Figure 34 The illustrated embodiment only uses the example of a third stacked structure D3 within the chip package structure 10 containing four fourth semiconductor structures 14 for illustration. However, the number of fourth semiconductor structures 14 within the third stacked structure D3 is not limited to this. The number of fourth semiconductor structures 14 within the third stacked structure D3 can be set according to actual needs. For example, the number of fourth semiconductor structures 14 within the third stacked structure D3 can be 2, 3, 8, 12, 16, or 20, etc.

[0237] For example, please continue reading Figure 33 and Figure 34 The fourth semiconductor structure 14 can be a bare die. A bare die is a device that has been cut and tested but has not been packaged. A bare die may not be directly applicable to an actual circuit, but it can be applied to an actual circuit after being packaged into a chip package structure 10 through a packaging process.

[0238] For example, please continue reading Figure 33 and Figure 34 The stacking method of multiple fourth semiconductor structures 14 within the third stacked structure D3 can be 3D vertical stacking.

[0239] In the chip packaging structure 10 described above, the stacking method of the multiple fourth semiconductor structures 14 in the third stacking structure D3 is 3D vertical stacking, which can reduce the size of the third stacking structure D3, which is beneficial to the miniaturization of the third stacking structure D3 and the improvement of the integration of the third stacking structure D3. This can reduce the size of the chip packaging structure 10 including the third stacking structure D3, thereby benefiting the miniaturization of the chip packaging structure 10 and the improvement of the integration of the chip packaging structure 10.

[0240] For example, please continue reading Figure 33 and Figure 34The fourth semiconductor structure 14 within the third stacked structure D3 can be a memory.

[0241] When the fourth semiconductor structure 14 within the third stacked structure D3 is a memory, the storage density of the single third stacked structure D3 can be increased by providing multiple fourth semiconductor structures 14 within a single third stacked structure D3. The increased number of fourth semiconductor structures 14 compared to a single fourth semiconductor structure 14 will correspondingly increase the storage capacity.

[0242] For example, if the fourth semiconductor structure 14 in the third stacked structure D3 is a memory, the fourth semiconductor structure 14 in the third stacked structure D3 can be one of ferroelectric random access memory, resistive random access memory, magnetic random access memory, phase change memory, dynamic random access memory, static random access memory, and flash memory.

[0243] When the fourth semiconductor structure 14 is a dynamic random access memory, the third stacked structure D3, which includes multiple stacked fourth semiconductor structures 14, can be a high-bandwidth memory.

[0244] In the case where the fourth semiconductor structure 14 is a flash memory, the third stacked structure D3, which includes multiple stacked fourth semiconductor structures 14, can be a hybrid bonded flash memory.

[0245] For example, please continue reading Figure 33 and Figure 34 In the case where the first stacked structure D1 within the chip package structure 10 includes a plurality of second semiconductor structures 12 stacked along the first direction Z, the type of the fourth semiconductor structure 14 within the third stacked structure D3 may be different from the type of the second semiconductor structures 12.

[0246] Alternatively, the type of the fourth semiconductor structure 14 within the third stacked structure D3 can be the same as the type of the second semiconductor structure 12.

[0247] For example, when the type of the fourth semiconductor structure 14 is the same as that of the second semiconductor structure 12, both the fourth semiconductor structure 14 and the second semiconductor structure 12 can be dynamic random access memory or flash memory.

[0248] For example, please continue reading Figure 33 and Figure 34 In the case where the second stacked structure D2 within the chip package structure 10 includes a plurality of third semiconductor structures 13 stacked along the first direction Z, the type of the fourth semiconductor structure 14 within the third stacked structure D3 may be different from the type of the third semiconductor structure 13.

[0249] Alternatively, the type of the fourth semiconductor structure 14 within the third stacked structure D3 can be the same as the type of the third semiconductor structure 13.

[0250] For example, if the fourth semiconductor structure 14 and the third semiconductor structure 13 are of the same type, both the fourth semiconductor structure 14 and the third semiconductor structure 13 can be dynamic random access memory or flash memory.

[0251] For example, please continue reading Figure 33 and Figure 34 In the case where the chip package structure 10 includes a second stacked structure D2 and a third stacked structure D3, and the third stacked structure D3 is located on the side of the second stacked structure D2 away from the first semiconductor structure 11, the chip package structure 10 may further include a fourth bonding layer 34d. The fourth bonding layer 34d is located between the second stacked structure D2 and the third stacked structure D3.

[0252] The fourth bonding layer 34d may include multiple fifth connecting portions 35. The third stacked structure D3 can be electrically connected to the second stacked structure D2 through the fifth connecting portions 35.

[0253] For example, please continue reading Figure 33 and Figure 34 In the case where the chip packaging structure 10 includes a first packaging layer 51 and a fourth bonding layer 34d, the fourth bonding layer 34d can contact the first packaging layer 51.

[0254] For example, please continue reading Figure 33 and Figure 34 The material of the fifth connection portion 35 within the fourth bonding layer 34d may include a conductive material.

[0255] For example, the material of the fifth connection portion 35 within the fourth bonding layer 34d may include one or more of copper, nickel, and gold.

[0256] For example, please continue reading Figure 33 and Figure 34 The fifth connector 35 within the fourth bonding layer 34d can be a microbump.

[0257] Please continue reading. Figure 33 and Figure 34 and combined Figure 5 and Figure 6In the case where the chip package structure 10 includes a third stacked structure D3, and the third stacked structure D3 includes a plurality of fourth semiconductor structures 14 stacked along the first direction Z, the connection method between the plurality of fourth semiconductor structures 14 in the third stacked structure D3 can be the same as or similar to the connection method between the plurality of third semiconductor structures 13 in the second stacked structure D2, and will not be described again here.

[0258] In some embodiments, please continue reading Figure 33 and Figure 34 In the case where the chip package structure 10 includes a third stacked structure D3, the chip package structure 10 may further include a third packaging layer 53. The third packaging layer 53 covers the third stacked structure D3.

[0259] In the chip packaging structure 10 described above, the third packaging layer 53 covers the third stacked structure D3. On the one hand, this can increase the strength of the third stacked structure D3, thereby reducing the risk of damage to the third stacked structure D3 caused by external stress (e.g., thermal stress and mechanical shock), which is beneficial to improving the stability and reliability of the chip packaging structure 10.

[0260] On the other hand, the third packaging layer 53 can protect the third stacked structure D3, and can reduce or avoid the influence of the external environment (e.g., moisture, temperature and pollution) on the third stacked structure D3, which is conducive to further improving the stability and reliability of the chip packaging structure 10.

[0261] For example, please continue reading Figure 33 and Figure 34 The material of the third encapsulation layer 53 within the chip packaging structure 10 may include one or more (two or more) of epoxy resin, expanding monomer, and curing agent.

[0262] For example, please continue reading Figure 33 and Figure 34 In the case where the chip packaging structure 10 includes a first packaging layer 51, and the first packaging layer 51 covers the first semiconductor structure 11, the first stacked structure D1, and the second packaging layer 52, the first packaging layer 51 may also cover a third packaging layer 53.

[0263] For example, please continue reading Figure 33 and Figure 34 The materials of the first encapsulation layer 51 and the third encapsulation layer 53 can be different.

[0264] Alternatively, the materials of the first encapsulation layer 51 and the third encapsulation layer 53 can be the same.

[0265] It should be noted that when the materials of the first encapsulation layer 51 and the third encapsulation layer 53 are the same, since the first encapsulation layer 51 and the third encapsulation layer 53 are formed in steps, there is a time interval between the forming process of the first encapsulation layer 51 and the forming process of the third encapsulation layer 53. This may result in differences between the molecular structures of the first encapsulation layer 51 and the third encapsulation layer 53, or differences between the crosslink density of the first encapsulation layer 51 and the crosslink density of the third encapsulation layer 53. Consequently, there may be a connection interface between the first encapsulation layer 51 and the third encapsulation layer 53.

[0266] It should be noted that, Figure 33 and Figure 34 The illustration only uses a chip package structure 10 including a first stacked structure D1, a second stacked structure D2, and a third stacked structure D3 as an example. In some embodiments, in addition to the first stacked structure D1, the second stacked structure D2, and the third stacked structure D3, the chip package structure 10 may also include at least one of a fourth stacked structure, a fifth stacked structure, and a sixth stacked structure, etc., and the fourth stacked structure, the fifth stacked structure, and the sixth stacked structure, etc., may be located on the side of the third stacked structure D3 away from the first semiconductor structure 11, and stacked along the first direction Z. The structures of the fourth stacked structure, the fifth stacked structure, and the sixth stacked structure, etc., may be the same as or similar to the structure of the second stacked structure D2 or the structure of the third stacked structure D3, and will not be described in detail here.

[0267] The structure of the second semiconductor structure 12 within the first stacked structure D1 described above will be explained in detail below.

[0268] In some embodiments, such as Figure 7 As shown, Figure 7 This is a structural diagram of a second semiconductor structure 12 within a first stacked structure D1 or a third semiconductor structure 13 within a second stacked structure D2, according to some embodiments. The second semiconductor structure 12 within the first stacked structure D1 may include a memory array layer 12m and a peripheral device layer 12n. The peripheral device layer 12n is coupled to the memory array layer 12m.

[0269] By coupling the peripheral device layer 12n within the second semiconductor structure 12 to the memory array layer 12m, the peripheral device layer 12n can be configured to operate on the memory array layer 12m (e.g., the peripheral device layer 12n can be configured to perform write or read operations on the memory array layer 12m).

[0270] For example, please continue reading Figure 7The memory array layer 12m and the peripheral device layer 12n in the second semiconductor structure 12 can be fabricated separately (and in some embodiments, the memory array layer 12m and the peripheral device layer 12n in the second semiconductor structure 12 can be fabricated in parallel), so that the thermal budget of one of the memory array layer 12m and the peripheral device layer 12n in the second semiconductor structure 12 does not limit the process of fabricating the other.

[0271] In some embodiments, such as Figure 8 As shown, Figure 8 This is a structural diagram of a storage array layer 12m according to some embodiments. The storage array layer 12m may include a plurality of storage cells MC arranged in an array.

[0272] The storage cell MC may include a capacitor C for storing data bits as positive or negative charges, and one or more transfer transistors T1 for controlling (e.g., switching and selecting) access to the capacitor C.

[0273] For example, please continue reading Figure 8 The capacitor C inside the storage cell MC can be set to a charging state or a discharging state. These two states are used to represent the two values ​​of the data bits, which are usually referred to as zero and one.

[0274] For example, please continue reading Figure 8 The transfer transistor T1 within the memory cell MC can be a vertical transistor. For example, the transfer transistor T1 within the memory cell MC can be a vertical metal-oxide-semiconductor field-effect transistor (MOSFET).

[0275] Using a vertical transistor as the transmission transistor T1 within the memory cell MC can reduce the area occupied by the transmission transistor T1, the coupling capacitance, and the complexity of the interconnect wiring.

[0276] The following uses a vertical transistor as an example to illustrate some embodiments of this disclosure. However, the type of the transmission transistor T1 in the memory cell MC is not limited to this. The type of the transmission transistor T1 in the memory cell MC can also be other suitable transistor types.

[0277] For example, please continue reading Figure 8 The transfer transistor T1 within the storage cell MC may include a semiconductor pillar TC extending along the first direction Z.

[0278] The semiconductor pillar TC within the transmission transistor T1 can have any suitable 3D shape. For example, the semiconductor pillar TC within the transmission transistor T1 can have a polyhedral shape or a cylindrical shape.

[0279] For example, please continue reading Figure 8 The transfer transistor T1 within the memory cell MC may also include a gate G.

[0280] When the transmission transistor T1 includes a semiconductor pillar TC, the gate G of the transmission transistor T1 may be located on at least one side of the semiconductor pillar TC.

[0281] The gate G of the transmission transistor T1 may be made of a conductive material. For example, the gate G of the transmission transistor T1 may be made of one or more of polysilicon, metal, metal compound, and silicide.

[0282] The gate G of the transmission transistor T1 may include multiple conductive layers. For example, the gate G of the transmission transistor T1 may include a titanium nitride (TiN) layer and a tungsten (W) layer stacked together.

[0283] In some embodiments, please continue reading Figure 8 The 12m storage array layer can also include multiple word lines (WL).

[0284] For example, please continue reading Figure 8 In the case where the memory array layer 12m includes a memory cell MC and the memory cell MC includes a transmission transistor T1, the word line WL in the memory array layer 12m can be coupled to the gate G of the transmission transistor T1 to control the transmission transistor T1 to turn on or turn off.

[0285] The gate G of the transmission transistor T1 and the word line WL within the memory array layer 12m can be a continuous conductive structure. That is, the gate G of the transmission transistor T1 can be regarded as part of forming the word line WL, or the word line WL can be regarded as an extension of the gate G of the transmission transistor T1.

[0286] In some embodiments, please continue reading Figure 8 The 12m storage array layer can also include multiple bit lines (BL).

[0287] For example, please continue reading Figure 8 In the case where the memory array layer 12m includes a memory cell MC, and the memory cell MC includes a transmission transistor T1 and a capacitor C, the bit line BL in the memory array layer 12m can be coupled to the source region or drain region of the semiconductor pillar TC in the transmission transistor T1 for charging or discharging the capacitor C in the memory cell MC.

[0288] For example, please continue reading Figure 8 The material of the bit lines BL within the 12m storage array layer may include conductive materials.

[0289] For example, the material of the bit line BL within the 12m layer of the storage array may include one or more (two or more) of copper (Cu), tungsten (W) and aluminum (Al).

[0290] In some embodiments, please continue reading Figure 7 The peripheral device layer 12n may include peripheral circuits 121n.

[0291] For example, please continue reading Figure 7 The peripheral circuitry 121n within the peripheral device layer 12n can be any suitable digital, analog, and / or mixed-signal circuitry used to facilitate the operation of the memory array layer 12m. The peripheral circuitry 121n within the peripheral device layer 12n may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0292] For example, please continue reading Figure 7 and combined Figure 8 In the case where the peripheral circuit 121n in the peripheral device layer 12n includes a row decoder and the storage array layer 12m includes a storage cell MC and a word line WL, the row decoder can be coupled to the word line WL in the storage array layer 12m and can be configured to control the turn-on or turn-off of the transmission transistor T1 in the storage cell MC.

[0293] For example, please continue reading Figure 7 and combined Figure 8 In the case where the peripheral circuit 121n in the peripheral device layer 12n includes a column decoder and the storage array layer 12m includes a storage cell MC and a bit line BL, the column decoder can be coupled to the bit line BL in the storage array layer 12m and can be configured to perform write or read operations on the storage cell MC.

[0294] For example, please continue reading Figure 7 and combined Figure 8In the case where the peripheral circuitry 121n within the peripheral device layer 12n includes a sense amplifier, and the memory array layer 12m includes memory cells MC and bit lines BL, the sense amplifier can be configured to sense a low-power signal from the bit line BL within the memory array layer 12m, representing a data bit (zero or one) stored in the memory cell MC within the memory array layer 12m, and can amplify a small voltage swing to a recognizable logic level.

[0295] For example, please continue reading Figure 7 When the peripheral device layer 12n includes peripheral circuitry 121n, the peripheral circuitry 121n within the peripheral device layer 12n can utilize Complementary Metal-Oxide-Semiconductor (CMOS) technology. The peripheral circuitry 121n within the peripheral device layer 12n can be implemented using logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0296] The structure of the third semiconductor structure 13 within the second stacked structure D2 described above will be explained in detail below.

[0297] In some embodiments, please continue reading Figure 7 and Figure 8 The third semiconductor structure 13 within the second stacked structure D2 may include a memory array layer 12m and a peripheral device layer 12n. The peripheral device layer 12n is coupled to the memory array layer 12m.

[0298] By coupling the peripheral device layer 12n within the third semiconductor structure 13 to the memory array layer 12m, the peripheral device layer 12n can be configured to operate on the memory array layer 12m (e.g., the peripheral device layer 12n can be configured to perform write or read operations on the memory array layer 12m).

[0299] It should be noted that the structure of the memory array layer 12m in the third semiconductor structure 13 can be the same as or similar to the structure of the memory array layer 12m in the second semiconductor structure 12, and will not be described in detail here.

[0300] The structure of the peripheral device layer 12n in the third semiconductor structure 13 can be the same as or similar to the structure of the peripheral device layer 12n in the second semiconductor structure 12, and will not be described in detail here.

[0301] The structure of the fourth semiconductor structure 14 within the third stacked structure D3 described above will be explained in detail below.

[0302] In some embodiments, please continue reading Figure 7 and Figure 8 The fourth semiconductor structure 14 within the third stacked structure D3 may include a memory array layer 12m and a peripheral device layer 12n. The peripheral device layer 12n is coupled to the memory array layer 12m.

[0303] It should be noted that the structure of the memory array layer 12m in the fourth semiconductor structure 14 can be the same as or similar to the structure of the memory array layer 12m in the second semiconductor structure 12, and will not be described in detail here.

[0304] The structure of the peripheral device layer 12n in the fourth semiconductor structure 14 can be the same as or similar to the structure of the peripheral device layer 12n in the second semiconductor structure 12, and will not be described in detail here.

[0305] The following provides a detailed description of the fabrication method of the chip packaging structure 10 described above.

[0306] In some embodiments, such as Figure 9 and Figure 10 As shown, Figure 9 and Figure 10 These are flowcharts illustrating the fabrication methods of the chip packaging structure 10 provided according to some embodiments. It should be noted that... Figure 9 and Figure 10 The method for fabricating the chip packaging structure 10 shown is not exclusive and can also be used in... Figure 9 and Figure 10 Other steps may be performed before, after, or between any step in the fabrication method of the chip package structure 10 shown.

[0307] The method for fabricating the chip package structure 10 may include steps S1 to S4.

[0308] S1: As Figure 11 and Figure 12 As shown, Figure 11 for Figure 9 and Figure 10 The flowchart of the fabrication method of the chip package structure 10 shown presents a structural diagram of the chip package structure 10 corresponding to step S1. Figure 12 for Figure 11 The chip packaging structure 10 is shown in cross-section along section line AA. Multiple first semiconductor structures 11 are arranged in an array on one side of the first carrier layer 21.

[0309] S2: As Figure 13 and Figure 14 As shown, Figure 13 and Figure 14 All Figure 9 and Figure 10The flowchart of the fabrication method of the chip package structure 10 shown presents a structural diagram of the chip package structure 10 corresponding to step S2. A first stacked structure D1 is formed on the side of the first semiconductor structure 11 away from the first carrier layer 21. The first stacked structure D1 includes a plurality of second semiconductor structures 12 stacked along a first direction Z, where the first direction Z is the thickness direction of the first semiconductor structure 11.

[0310] S3: As Figure 15 As shown, Figure 15 for Figure 9 and Figure 10 The flowchart of the fabrication method of the chip package structure 10 shown presents a structural diagram of the chip package structure 10 corresponding to step S3. An initial first packaging layer 511 is formed. The initial first packaging layer 511 covers a plurality of first semiconductor structures 11 and a plurality of first stacked structures D1, and fills the gaps between adjacent first semiconductor structures 11 and between adjacent first stacked structures D1.

[0311] S4: As Figure 16 As shown, and in combination Figure 15 , Figure 16 for Figure 9 and Figure 10 The flowchart of the fabrication method of the chip package structure 10 shown presents a structural diagram of the chip package structure 10 corresponding to step S4. The initial first package layer 511 is cut to obtain multiple first package layers 51. Each first package layer 51 encapsulates a first semiconductor structure 11 and a first stacked structure D1 located on one side of the first semiconductor structure 11 along the first direction Z.

[0312] It should be noted that, Figure 13 The embodiment shown illustrates the case by using the first stacked structure D1 within the chip package structure 10, which includes eight second semiconductor structures 12, as an example. Figure 14 The embodiment shown is illustrated by taking the first stacked structure D1 within the chip package structure 10, which includes four second semiconductor structures 12, as an example.

[0313] In the above-mentioned method for fabricating the chip package structure 10, when forming the chip package structure 10, a plurality of first semiconductor structures 11 are first arrayed on one side of the first carrier layer 21, and then a first stacked structure D1 is formed on the side of the first semiconductor structures 11 away from the first carrier layer 21. Compared with the wafer-level packaging (WLP) process, on the one hand, the size of a single first semiconductor structure 11 and a single second semiconductor structure 12 in the first stacked structure D1 is smaller, which can reduce the stress between the first semiconductor structure 11 and the second semiconductor structure 12, and between two adjacent second semiconductor structures 12 in the first stacked structure D1. This can avoid or reduce the probability of warping problems in the chip package structure 10, and is beneficial to improving the stability and reliability of the chip package structure 10.

[0314] On the other hand, when forming the chip packaging structure 10, multiple first semiconductor structures 11 are formed first. Before the first stacked structure D1 is formed on the side of the first semiconductor structure 11 away from the first carrier layer 21, the multiple first semiconductor structures 11 can be tested and screened, which is beneficial to improving the yield of the chip packaging structure 10 and reducing the manufacturing cost of the chip packaging structure 10.

[0315] For example, please continue reading Figure 11 The first load-bearing layer 21 can be rectangular.

[0316] It should be noted that the phrase "the first bearing layer 21 is rectangular" means that the shape of the boundary of the first bearing layer 21 is generally rectangular, but it is not limited to a standard rectangle. That is, "rectangle" here includes not only the shape of a standard rectangle, but also shapes similar to rectangles, taking into account process conditions. For example, the long and short sides of the rectangle can be curved at each intersection (i.e., at the corner), so that the boundary of the first bearing layer 21 is a rounded rectangle in the plan view.

[0317] Alternatively, the first bearing layer 21 can be circular or other shapes with corners.

[0318] For example, please continue reading Figure 11 and Figure 12 The first carrier layer 21 may include an arrangement area 211 and a peripheral area 212. The peripheral area 212 surrounds the arrangement area 211. A plurality of first semiconductor structures 11 may be located in the arrangement area 211 of the first carrier layer 21.

[0319] For example, please continue reading Figure 11 and Figure 12 A first alignment mark N1 may be provided in the peripheral area 212 of the first bearing layer 21.

[0320] The first alignment mark N1 can be used for alignment in processes such as die attach, wire bonding (W / B), and marking, which helps to improve process accuracy and efficiency.

[0321] For example, please continue reading Figure 11 A second alignment mark N2 may be provided in the arrangement area 211 of the first bearing layer 21.

[0322] Please continue reading. Figure 11 and combined Figure 9 and Figure 10 In step S1 (i.e., arranging multiple first semiconductor structures 11 in an array on one side of the first carrier layer 21) in the flowchart of the method for fabricating the chip package structure 10, when arranging multiple first semiconductor structures 11 in an array in the arrangement area 211 of the first carrier layer 21, the second alignment mark N2 in the arrangement area 211 can play an alignment role, which is beneficial to improving the arrangement efficiency of multiple first semiconductor structures 11 and improving the arrangement accuracy of multiple first semiconductor structures 11 in the arrangement area 211 of the first carrier layer 21.

[0323] For example, please continue reading Figure 11 and Figure 12 The arrangement area 211 of the first bearing layer 21 can be set to be transparent.

[0324] For example, please continue reading Figure 11 and Figure 12 A second bonding layer 34b may be disposed between the first semiconductor structure 11 and the first carrier layer 21.

[0325] Please continue reading. Figure 11 and Figure 12 and combined Figure 9 and Figure 10 In step S1 (i.e., arranging multiple first semiconductor structures 11 in an array on one side of the first carrier layer 21) in the flowchart of the method for fabricating the chip package structure 10, when arranging multiple first semiconductor structures 11 in an array on one side of the first carrier layer 21, the multiple first semiconductor structures 11 can be fixed to one side of the first carrier layer 21 by the second bonding layer 34b. This is beneficial to improving the connection stability between the first semiconductor structure 11 and the first carrier layer 21, thereby reducing the probability of the first semiconductor structure 11 being displaced or falling off in subsequent processes, which is beneficial to improving the fabrication efficiency of the chip package structure 10.

[0326] In some embodiments, please continue reading Figure 10The flowchart of the method for fabricating the chip package structure 10 includes step S1 (i.e., arranging multiple first semiconductor structures 11 in an array on one side of the first carrier layer 21), which may include steps S11, S12 and S13.

[0327] S11: As Figure 17 As shown, and in combination Figure 11 , Figure 17 for Figure 11 The chip package structure 10 is shown in cross-section along section line BB. Multiple first semiconductor structures 11 are arranged in an array on one side of the initial second carrier layer 221.

[0328] S12: As Figure 18 As shown, and in combination Figure 11 and Figure 17 , Figure 18 for Figure 11 The image shows a cross-sectional view of the chip package structure 10 along the section line CC. The initial second carrier layer 221 is cut to obtain multiple second carrier layers 22. A first semiconductor structure 11 is disposed on one side of each second carrier layer 22, and a second carrier layer 22 and the first semiconductor structure 11 located on one side of the second carrier layer 22 form a transition stack structure D3.

[0329] S13: Please continue reading Figure 12 and combined Figure 11 Multiple transition stacked structures D3 arrays are arranged on one side of the first carrier layer 21.

[0330] In the above-described method for fabricating the chip package structure 10, a second carrier layer 22 and a first semiconductor structure 11 located on one side of the second carrier layer 22 form a transition stack structure D3, and multiple transition stack structures D3 arrays are arranged on one side of the first carrier layer 21, so that both the first carrier layer 21 and the second carrier layer 22 can be used to support the first semiconductor structure 11, which can provide stronger mechanical support for the first semiconductor structure 11, thereby reducing the probability of deformation or damage to the first semiconductor structure 11 due to external stress in subsequent processes, thus improving the yield of the chip package structure 10 fabricated by the above-described method for fabricating the chip package structure 10.

[0331] For example, please continue reading Figure 17 A third alignment mark N3 may be set on the initial second bearing layer 221.

[0332] Please continue reading. Figure 17 and combined Figure 10 and Figure 11In step S11 of the flowchart of the method for fabricating the chip package structure 10 (i.e., arranging multiple first semiconductor structures 11 in an array on one side of the initial second carrier layer 221), when arranging multiple first semiconductor structures 11 in an array on one side of the initial second carrier layer 221, the third alignment mark N3 can play an alignment role, which is beneficial to improving the arrangement efficiency of multiple first semiconductor structures 11 and improving the arrangement accuracy of multiple first semiconductor structures 11 on one side of the initial second carrier layer 221.

[0333] For example, please continue reading Figure 12 , Figure 17 and Figure 18 When both the first carrier layer 21 and the second carrier layer 22 are used to carry the first semiconductor structure 11, and a second bonding layer 34b is provided between the first semiconductor structure 11 and the first carrier layer 21, the second bonding layer 34b can be provided between the first semiconductor structure 11 and the second carrier layer 22, as well as between the first semiconductor structure 11 and the initial second carrier layer 221.

[0334] Please continue reading. Figure 12 , Figure 17 and Figure 18 and combined Figure 10 and Figure 11 In step S11 of the flowchart of the method for fabricating the chip package structure 10 (i.e., arranging multiple first semiconductor structures 11 in an array on one side of the initial second carrier layer 221), when arranging multiple first semiconductor structures 11 in an array on one side of the initial second carrier layer 221, the multiple first semiconductor structures 11 can be fixed to one side of the initial second carrier layer 221 by the second bonding layer 34b. This is beneficial to improving the connection stability between the first semiconductor structure 11 and the initial second carrier layer 221, thereby reducing the probability of the first semiconductor structure 11 being displaced or detached in subsequent processes, which is beneficial to improving the fabrication efficiency of the chip package structure 10.

[0335] For example, please continue reading Figure 17 The material of the initial second bearing layer 221 may include glass, etc.

[0336] Please continue reading. Figure 12 , Figure 17 and Figure 18 and combined Figure 10 and Figure 11 It is understandable that when the material of the initial second carrier layer 221 includes glass or the like, in step S12 of the flowchart of the method for preparing the chip package structure 10, the material of the second carrier layer 22 obtained by cutting the initial second carrier layer 221 also includes glass or the like.

[0337] In some embodiments, please continue reading Figure 9 After step S3 (i.e., forming the initial first packaging layer 511) in the flowchart of the method for fabricating the chip packaging structure 10, the method for fabricating the chip packaging structure 10 may further include step S5.

[0338] S5: As Figure 19 As shown, and in combination Figure 15 , Figure 19 for Figure 9 or Figure 10 The flowchart of the fabrication method of the chip package structure 10 shown presents a structural diagram of the chip package structure 10 corresponding to steps S5 and S6. The first carrier layer 21 is removed.

[0339] For example, please continue reading Figure 15 and Figure 19 When a second bonding layer 34b is provided between the first semiconductor structure 11 and the first carrier layer 21, and multiple first semiconductor structures 11 are fixed to one side of the first carrier layer 21 by the second bonding layer 34b, the first carrier layer 21 can be removed by a release bonding process.

[0340] For example, please continue reading Figure 15 and Figure 19 The first carrier layer 21 can be removed by laser debonding.

[0341] Please continue reading. Figure 15 and Figure 19 When the first carrier layer 21 includes an arrangement area 211, and multiple first semiconductor structures 11 are located in the arrangement area 211 of the first carrier layer 21, and the arrangement area 211 of the first carrier layer 21 is transparent, the transparent arrangement area 211 within the first carrier layer 21 allows the laser beam to penetrate directly during the removal of the first carrier layer 21 by laser debonding. This allows the laser beam to directly act on the bonding interface between the first carrier layer 21 and the first semiconductor structure 11 (e.g., the second bonding layer 34b located between the first semiconductor structure 11 and the first carrier layer 21), thereby reducing the energy loss of the laser beam on the first carrier layer 21. This allows the laser beam energy to be more concentratedly transferred to the bonding interface between the first carrier layer 21 and the first semiconductor structure 11 (e.g., the second bonding layer 34b located between the first semiconductor structure 11 and the first carrier layer 21), which is beneficial for improving the efficiency of laser debonding.

[0342] For example, please continue reading Figure 19 and combined Figure 9After step S5 (i.e., removing the first carrier layer 21) in the flowchart of the method for fabricating the chip package structure 10, the surface of the first semiconductor structure 11 away from the first stacked structure D1 can be cleaned by plasma cleaning process to remove residues on the surface of the first semiconductor structure 11 away from the first stacked structure D1.

[0343] And / or, please continue reading Figure 19 and combined Figure 9 After step S5 (i.e., removing the first carrier layer 21) in the flowchart of the method for fabricating the chip package structure 10, the surface of the first semiconductor structure 11 away from the first stacked structure D1 can also be cleaned with a chemical solution to remove residues on the surface of the first semiconductor structure 11 away from the first stacked structure D1.

[0344] For example, please continue reading Figure 9 and combined Figure 15 , Figure 16 and Figure 19 In the flowchart of the method for fabricating the chip package structure 10, step S5 (i.e., removing the first carrier layer 21) can be performed before step S4 (i.e., cutting the initial first package layer 511 to obtain multiple first package layers 51).

[0345] In the above-described method for fabricating the chip package structure 10, before cutting the initial first package layer 511 to obtain multiple first package layers 51, the first carrier layer 21 is removed first. This ensures that after removing the first carrier layer 21, the initial first package layer 511 still covers the multiple first semiconductor structures 11 and the multiple first stacked structures D1, and fills the gaps between adjacent first semiconductor structures 11 and adjacent first stacked structures D1. In other words, after removing the first carrier layer 21, the initial first package layer 511, the multiple first semiconductor structures 11, and the multiple first stacked structures D1 remain a single, integrated structure.

[0346] After removing the first carrier layer 21, the surface of the first semiconductor structure 11 away from the first stacked structure D1 is cleaned by a cleaning process (e.g., plasma cleaning process, chemical cleaning process, etc.) to remove the residue on the surface of the first semiconductor structure 11 away from the first stacked structure D1. This process can clean the entire surface of multiple first semiconductor structures 11 away from the first stacked structure D1, which is beneficial to improving cleaning efficiency and thus improving the fabrication efficiency of the chip packaging structure 10.

[0347] For example, please continue reading Figure 9After step S3 (i.e., forming the initial first packaging layer 511) and before step S5 (i.e., removing the first carrier layer 21) in the flowchart of the method for fabricating the chip packaging structure 10, the method for fabricating the chip packaging structure 10 may further include step S6.

[0348] S6: Please continue reading Figure 19 The first carrier layer 21 is cut along the side away from the first semiconductor structure 11 to form a first cleavage channel Q1. The first cleavage channel Q1 is located between adjacent first semiconductor structures 11 along the first direction Z, and it penetrates at least through the first carrier layer 21 along the first direction Z.

[0349] In the above-described method for fabricating the chip package structure 10, before removing the first carrier layer 21, the first carrier layer 21 is cut along the side away from the first semiconductor structure 11 to form a first cutting path Q1, which divides the first carrier layer 21 into multiple small units. When removing the first carrier layer 21, the small units within it are independently stressed, which disperses the peel stress between the first carrier layer 21 and the first semiconductor structure 11. This avoids the peel stress from concentrating in a localized area, facilitating the removal of the first carrier layer 21 and improving the fabrication efficiency of the chip package structure 10. Furthermore, it reduces the probability of damage to the first semiconductor structure 11 during the removal of the first carrier layer 21, thus improving the yield of the chip package structure 10 fabricated using the above-described method.

[0350] For example, along the first direction Z, the first cutting channel Q1 can penetrate the first load-bearing layer 21.

[0351] For example, please continue reading Figure 19 Along the first direction Z, the first cutting channel Q1 can penetrate the first carrier layer 21, and the first cutting channel Q1 can also extend into the interior of the initial first encapsulation layer 511.

[0352] In some embodiments, please continue reading Figure 10 and combined Figure 11 , Figure 12 , Figure 17 and Figure 18In the flowchart of the method for fabricating the chip package structure 10, step S1 (i.e., arranging a plurality of first semiconductor structures 11 in an array on one side of the first carrier layer 21) includes step S11 (i.e., arranging a plurality of first semiconductor structures 11 in an array on one side of the initial second carrier layer 221), step S12 (i.e., cutting the initial second carrier layer 221 to obtain a plurality of second carrier layers 22) and step S13 (i.e., arranging a plurality of transition stacked structures D3 in an array on one side of the first carrier layer 21), after step S3 (i.e., forming the initial first package layer 511) in the flowchart of the method for fabricating the chip package structure 10, the method for fabricating the chip package structure 10 may further include step S5.

[0353] S5: Please continue reading Figure 19 Remove the first bearing layer 21 and the second bearing layer 22.

[0354] For example, please continue reading Figure 15 and Figure 19 When a second bonding layer 34b is provided between the first semiconductor structure 11 and the second carrier layer 22, and the first semiconductor structure 11 is fixed to the side of the second carrier layer 22 away from the first carrier layer 21 by the second bonding layer 34b, the first carrier layer 21 and the second carrier layer 22 can be removed by a debonding process.

[0355] For example, please continue reading Figure 15 and Figure 19 The first carrier layer 21 and the second carrier layer 22 can be removed by laser debonding process.

[0356] For example, please continue reading Figure 19 and combined Figure 10 After step S5 (i.e., removing the first carrier layer 21 and the second carrier layer 22) in the flowchart of the method for fabricating the chip package structure 10, the surface of the first semiconductor structure 11 away from the first stacked structure D1 can also be cleaned by plasma cleaning process to remove the residue on the surface of the first semiconductor structure 11 away from the first stacked structure D1.

[0357] And / or, please continue reading Figure 19 and combined Figure 10 After step S5 (i.e., removing the first carrier layer 21 and the second carrier layer 22) in the flowchart of the method for fabricating the chip package structure 10, the surface of the first semiconductor structure 11 away from the first stacked structure D1 can also be cleaned with a chemical solution to remove residues on the surface of the first semiconductor structure 11 away from the first stacked structure D1.

[0358] For example, please continue reading Figure 10 and combined Figure 15 , Figure 16 and Figure 19 In the flowchart of the method for fabricating the chip package structure 10, step S5 (i.e., removing the first carrier layer 21 and the second carrier layer 22) can be performed before step S4 (i.e., cutting the initial first package layer 511 to obtain multiple first package layers 51).

[0359] In the above-described method for fabricating the chip package structure 10, before cutting the initial first package layer 511 to obtain multiple first package layers 51, the first carrier layer 21 and the second carrier layer 22 are removed. This ensures that after removing the first carrier layer 21 and the second carrier layer 22, the initial first package layer 511 still covers the multiple first semiconductor structures 11 and the multiple first stacked structures D1, and fills the gaps between adjacent first semiconductor structures 11 and adjacent first stacked structures D1. That is, after removing the first carrier layer 21 and the second carrier layer 22, the initial first package layer 511, the multiple first semiconductor structures 11, and the multiple first stacked structures D1 still form a single integrated structure.

[0360] After removing the first carrier layer 21 and the second carrier layer 22, the surface of the first semiconductor structure 11 away from the first stacked structure D1 is cleaned by a cleaning process (e.g., plasma cleaning process, chemical cleaning process, etc.) to remove the residue on the surface of the first semiconductor structure 11 away from the first stacked structure D1. This process can clean the entire surface of multiple first semiconductor structures 11 away from the first stacked structure D1, which is beneficial to improving the cleaning efficiency and thus improving the fabrication efficiency of the chip packaging structure 10.

[0361] For example, please continue reading Figure 10 After step S3 (i.e., forming the initial first packaging layer 511) in the flowchart of the method for fabricating the chip packaging structure 10, and before step S5 (i.e., removing the first carrier layer 21 and the second carrier layer 22), the method for fabricating the chip packaging structure 10 may further include step S6.

[0362] S6: Please continue reading Figure 19 A first cleavage path Q1 is formed by cutting the first carrier layer 21 and the second carrier layer 22 from the side of the first carrier layer 21 away from the first semiconductor structure 11. The first cleavage path Q1 is located between adjacent first semiconductor structures 11 in the direction perpendicular to the first direction Z. The first cleavage path Q1 penetrates at least the first carrier layer 21 and the second carrier layer 22 in the first direction Z.

[0363] In the above-described method for fabricating the chip package structure 10, before removing the first carrier layer 21 and the second carrier layer 22, the first carrier layer 21 and the second carrier layer 22 are cut along the side of the first carrier layer 21 away from the first semiconductor structure 11 to form a first cutting path Q1. This divides the first carrier layer 21 and the second carrier layer 22 into multiple small units. When removing the first carrier layer 21 and the second carrier layer 22, the small units within the first carrier layer 21 and the second carrier layer 22 are independently stressed, which can disperse the peel stress between the first carrier layer 21, the second carrier layer 22, and the first semiconductor structure 11. This avoids the peel stress from concentrating in local areas. On the one hand, it facilitates the removal of the first carrier layer 21 and the second carrier layer 22, which is beneficial to improving the fabrication efficiency of the chip package structure 10. On the other hand, it can reduce the probability of damage to the first semiconductor structure 11 during the removal of the first carrier layer 21 and the second carrier layer 22, which is beneficial to improving the yield of the chip package structure 10 fabricated by the above-described method.

[0364] For example, along the first direction Z, the first cutting channel Q1 can penetrate the first bearing layer 21 and the second bearing layer 22.

[0365] For example, please continue reading Figure 19 Along the first direction Z, the first cutting channel Q1 can penetrate the first carrier layer 21 and the second carrier layer 22, and the first cutting channel Q1 can also extend into the interior of the initial first encapsulation layer 511.

[0366] In some embodiments, please continue reading Figure 9 and Figure 10 The method for preparing the chip packaging structure 10 may further include step S7.

[0367] S7: As Figure 20 As shown, Figure 20 for Figure 9 and Figure 10 The flowchart illustrating the fabrication method of the chip package structure 10 shows a structural diagram of step S7 corresponding to one of the chip package structures 10. A second stacked structure D2 is formed. The second stacked structure D2 includes a plurality of third semiconductor structures 13 stacked along the first direction Z.

[0368] Please continue reading. Figure 9 and Figure 10 After step S2 (i.e., forming a first stacked structure D1 on the side of the first semiconductor structure 11 away from the first carrier layer 21) in the flowchart of the method for fabricating the chip package structure 10, and before step S3 (i.e., forming the initial first package layer 511), the method for fabricating the chip package structure 10 may further include step S8.

[0369] S8: As Figure 21 As shown, Figure 21 for Figure 9 and Figure 10 The flowchart of the fabrication method of the chip package structure 10 shown presents a structural diagram of the chip package structure 10 corresponding to step S8. The second stacked structure D2 is disposed on the side of the first stacked structure D1 away from the first semiconductor structure 11.

[0370] like Figure 22 As shown, and in combination Figure 9 and Figure 10 , Figure 22 for Figure 9 and Figure 10 The flowchart of the method for fabricating the chip package structure 10 shows a structural diagram of the chip package structure 10 corresponding to step S3. In step S3 (i.e., forming the initial first package layer 511) of the method for fabricating the chip package structure 10, when forming the initial first package layer 511, the initial first package layer 511 also covers the second stacked structure D2 and fills the gaps between adjacent second stacked structures D2.

[0371] In other words, when the method for preparing the chip package structure 10 includes step S8 (i.e., setting the second stacked structure D2 on the side of the first stacked structure D1 away from the first semiconductor structure 11), the initial first package layer 511 covers multiple first semiconductor structures 11 and multiple first stacked structures D1, and fills the gaps between adjacent first semiconductor structures 11 and adjacent first stacked structures D1, and also covers multiple second stacked structures D2, and fills the gaps between adjacent second stacked structures D2.

[0372] For example, please continue reading Figure 9 and Figure 10 and combined Figure 23 , Figure 23 for Figure 9 and Figure 10 The flowchart of the method for fabricating the chip package structure 10 shows a structural diagram of the chip package structure 10 corresponding to step S4. When the method for fabricating the chip package structure 10 includes steps S7 (forming the second stacked structure D2) and S8 (setting the second stacked structure D2 on the side of the first stacked structure D1 away from the first semiconductor structure 11), step S4 in the flowchart of the method for fabricating the chip package structure 10 (cutting the initial first packaging layer 511 to obtain multiple first packaging layers 51) is similar to step S4 in the flowchart of the aforementioned method for fabricating the chip package structure 10, and will not be described again here.

[0373] For example, please continue reading Figure 9 and Figure 10 and combined Figure 24 , Figure 24 for Figure 9 or Figure 10 The flowchart of the method for fabricating the chip package structure 10 shows a structural diagram of the chip package structure 10 corresponding to steps S5 and S6. When the method for fabricating the chip package structure 10 includes steps S7 (i.e., forming the second stacked structure D2) and S8 (i.e., placing the second stacked structure D2 on the side of the first stacked structure D1 away from the first semiconductor structure 11), step S5 in the flowchart of the method for fabricating the chip package structure 10 is similar to step S5 in the aforementioned flowchart of the method for fabricating the chip package structure 10, and will not be described again here.

[0374] Step S6 in the flowchart of the method for fabricating chip package structure 10 is similar to step S6 in the flowchart of the aforementioned method for fabricating chip package structure 10, and will not be repeated here.

[0375] In some embodiments, please continue reading Figure 9 and Figure 10 The flowchart of the method for fabricating the chip package structure 10 includes step S7 (i.e. forming the second stacked structure D2), which may include steps S71, S72, S73, S74 and S75.

[0376] S71: As Figure 25 and Figure 26 As shown, Figure 25 for Figure 9 and Figure 10 The flowchart of the fabrication method of the chip package structure 10 shown presents a structural diagram of the chip package structure 10 corresponding to step S71. Figure 26 for Figure 25 The chip package structure 10 is shown in cross-section along section line DD. Multiple third semiconductor structures 13 are arranged in an array on one side of the third carrier layer 23.

[0377] S72: As Figure 27 As shown, Figure 27 for Figure 9 and Figure 10 The flowchart of the fabrication method of the chip package structure 10 shown presents a structural diagram of the chip package structure 10 corresponding to step S72. At least one third semiconductor structure 13 is stacked along the first direction Z on the side of the third semiconductor structure 13 away from the third carrier layer 23 to form a second stacked structure D2.

[0378] S73: As Figure 28 As shown, Figure 28 for Figure 9 and Figure 10The flowchart of the fabrication method of the chip package structure 10 shown presents a structural diagram of the chip package structure 10 corresponding to step S73. An initial second packaging layer 521 is formed. The initial second packaging layer 521 covers a plurality of second stacked structures D2 and fills the gaps between adjacent second stacked structures D2.

[0379] S74: As Figure 29 As shown, and in combination Figure 28 , Figure 29 for Figure 9 and Figure 10 The flowchart of the fabrication method of the chip package structure 10 shown presents a structural diagram of the chip package structure 10 corresponding to step S74. The third carrier layer 23 is removed.

[0380] S75: As Figure 30 As shown, and in combination Figure 29 , Figure 30 for Figure 9 and Figure 10 The flowchart illustrating the fabrication method of the chip package structure 10 shows a structural diagram of the chip package structure 10 corresponding to step S75. The initial second packaging layer 521 is cut to obtain multiple second packaging layers 52. Each second packaging layer 52 covers a second stacked structure D2.

[0381] It should be noted that, Figure 27 The embodiment shown is illustrated by taking the second stacked structure D2 within the chip package structure 10, which includes four third semiconductor structures 13, as an example.

[0382] In the above-mentioned method for fabricating the chip package structure 10, when forming the second stacked structure D2 within the chip package structure 10, a plurality of third semiconductor structures 13 are first arrayed on one side of the third carrier layer 23, and then at least one third semiconductor structure 13 is stacked along the first direction Z on the side of the third semiconductor structure 13 away from the third carrier layer 23 to form the second stacked structure D2. Compared with wafer-level packaging process, the size of a single third semiconductor structure 13 within the second stacked structure D2 is smaller, which can reduce the stress between two adjacent third semiconductor structures 13 within the second stacked structure D2, thereby avoiding or reducing the probability of warping problems in the second stacked structure D2, thus avoiding or reducing the probability of warping problems in the chip package structure 10, which is beneficial to improving the stability and reliability of the chip package structure 10.

[0383] For example, please continue reading Figure 25 and combined Figure 11 The shape of the third support layer 23 can be the same as or similar to the shape of the first support layer 21, which will not be described in detail here.

[0384] For example, please continue reading Figure 25 and Figure 26 and combined Figure 11 and Figure 12 The structure of the third support layer 23 can be the same as or similar to that of the first support layer 21. For example, the third support layer 23 may also include an arrangement area 211 and a peripheral area 212, which will not be described in detail here.

[0385] For example, please continue reading Figure 25 and Figure 26 A third bonding layer 34c may be disposed between the third semiconductor structure 13 and the third carrier layer 23.

[0386] Please continue reading. Figure 25 and Figure 26 and combined Figure 9 and Figure 10 In step S71 (i.e., arranging multiple third semiconductor structures 13 in an array on one side of the third carrier layer 23) in the flowchart of the method for fabricating the chip package structure 10, when arranging multiple third semiconductor structures 13 in an array on one side of the third carrier layer 23, the multiple third semiconductor structures 13 can be fixed to one side of the third carrier layer 23 by the third bonding layer 34c. This is beneficial to improving the connection stability between the third semiconductor structure 13 and the third carrier layer 23, thereby reducing the probability of the third semiconductor structure 13 being displaced or falling off in subsequent processes, which is beneficial to improving the fabrication efficiency of the chip package structure 10.

[0387] For example, please continue reading Figure 26 and Figure 29 When a third bonding layer 34c is provided between the third semiconductor structure 13 and the third carrier layer 23, and multiple third semiconductor structures 13 are fixed to one side of the third carrier layer 23 by the third bonding layer 34c, the third carrier layer 23 can be removed by a debonding process.

[0388] For example, please continue reading Figure 29 The third carrier layer 23 can be removed by laser debonding process.

[0389] For example, please continue reading Figure 29 After step S74 (i.e., removing the third carrier layer 23) in the flowchart of the method for fabricating the chip package structure 10, the surface of the third semiconductor structure 13 near the third carrier layer 23 can be cleaned by plasma cleaning process to remove residues on the surface of the third semiconductor structure 13 near the third carrier layer 23.

[0390] And / or, please continue reading Figure 29After step S74 (i.e., removing the third carrier layer 23) in the flowchart of the method for fabricating the chip package structure 10, the surface of the third semiconductor structure 13 near the third carrier layer 23 can be cleaned with a chemical solution to remove residues on the surface of the third semiconductor structure 13 near the third carrier layer 23.

[0391] In some implementations, please refer to [the relevant documentation]. Figure 25 The flowchart of the method for fabricating the chip package structure 10 includes step S71 (i.e., arranging multiple third semiconductor structures 13 in an array on one side of the third carrier layer 23), which may include steps S711, S712 and S713.

[0392] S711: such as Figure 31 As shown, and in combination Figure 25 , Figure 31 for Figure 25 The chip package structure 10 is shown in cross-section along section line EE. Multiple third semiconductor structures 13 are arrayed on one side of the initial fourth carrier layer 241.

[0393] S712: such as Figure 32 As shown, and in combination Figure 25 and Figure 31 , Figure 32 for Figure 25 The chip packaging structure 10 is shown in cross-section along section line FF. The initial fourth carrier layer 241 is cut to obtain multiple fourth carrier layers 24. A third semiconductor structure 13 is disposed on one side of each fourth carrier layer 24, and a fourth carrier layer 24 and the third semiconductor structure 13 located on one side of the fourth carrier layer 24 form an intermediate stack structure D4.

[0394] S713: Please refer to further details. Figure 26 and combined Figure 25 Multiple intermediate stacked structure D4 arrays are arranged on one side of the third carrier layer 23.

[0395] In the above-mentioned method for fabricating the chip package structure 10, a fourth carrier layer 24 and a third semiconductor structure 13 located on one side of the fourth carrier layer 24 form an intermediate stacked structure D4, and multiple intermediate stacked structures D4 are arranged in an array on one side of the third carrier layer 23, so that both the third carrier layer 23 and the fourth carrier layer 24 can be used to support the third semiconductor structure 13, which can provide stronger mechanical support for the third semiconductor structure 13. This can reduce the probability of deformation or damage to the third semiconductor structure 13 due to external stress in subsequent processes, thereby improving the yield of the chip package structure 10 fabricated by the above-mentioned method for fabricating the chip package structure 10.

[0396] For example, please continue reading Figure 25 and combined Figure 26 , Figure 31 and Figure 32 In the case where the method for fabricating the chip package structure 10 includes step S713 (that is, arranging a plurality of intermediate stacked structures D4 arrays on one side of the third carrier layer 23), the fourth carrier layer 24 may also be removed in step S74 (that is, removing the third carrier layer 23) of the method for fabricating the chip package structure 10.

[0397] For example, please continue reading Figure 31 and Figure 17 The structure and material of the initial fourth bearing layer 241 can be the same as or similar to the structure and material of the initial second bearing layer 221, and will not be described in detail here.

[0398] Please continue reading. Figure 32 and Figure 18 The structure and material of the fourth bearing layer 24 can be the same as or similar to the structure and material of the second bearing layer 22, and will not be described in detail here.

[0399] For example, please continue reading Figure 26 , Figure 31 and Figure 32 When both the third carrier layer 23 and the fourth carrier layer 24 are used to carry the third semiconductor structure 13, and a third bonding layer 34c is provided between the third semiconductor structure 13 and the third carrier layer 23, the third bonding layer 34c can be provided between the third semiconductor structure 13 and the fourth carrier layer 24, and between the third semiconductor structure 13 and the initial fourth carrier layer 241.

[0400] In some embodiments, please continue reading Figure 29 and combined Figure 28 After step S73 (i.e., forming the initial second packaging layer 521) in the flowchart of the method for fabricating the chip package structure 10, and before step S74 (i.e., removing the third carrier layer 23), the method for fabricating the chip package structure 10 may further include step S76.

[0401] S76: Please continue reading Figure 29 A second cleavage path Q2 is formed by cutting the third carrier layer 23 from the side away from the third semiconductor structure 13. The second cleavage path Q2 is located between adjacent third semiconductor structures 13 along the first direction Z, and it penetrates at least through the third carrier layer 23 along the first direction Z.

[0402] In the fabrication method of the chip package structure 10 described above, before removing the third carrier layer 23, the third carrier layer 23 is first cut along the side away from the third semiconductor structure 13 to form a second cutting path Q2, which divides the third carrier layer 23 into multiple small units. When removing the third carrier layer 23, the small units within the third carrier layer 23 are independently stressed, which can disperse the peel stress between the third carrier layer 23 and the third semiconductor structure 13. This avoids the peel stress between the third carrier layer 23 and the third semiconductor structure 13 from concentrating in a localized area. On the one hand, this facilitates the removal of the third carrier layer 23, which is beneficial to improving the fabrication efficiency of the chip package structure 10. On the other hand, it reduces the probability of damage to the third semiconductor structure 13 during the removal of the third carrier layer 23, which is beneficial to improving the yield of the chip package structure 10 fabricated by the above-described fabrication method.

[0403] For example, please continue reading Figure 29 Along the first direction Z, the second cutting channel Q2 can penetrate the third load-bearing layer 23.

[0404] For example, please continue reading Figure 29 When both the third carrier layer 23 and the fourth carrier layer 24 are used to support the third semiconductor structure 13, the second cleaving channel Q2 can penetrate through the third carrier layer 23 and the fourth carrier layer 24 along the first direction Z.

[0405] For example, please continue reading Figure 29 Along the first direction Z, the second cutting channel Q2 can penetrate the third carrier layer 23 and the fourth carrier layer 24, and the second cutting channel Q2 can also extend into the interior of the initial second encapsulation layer 521.

[0406] In some embodiments, the method for fabricating the chip package structure 10 may further include step S9.

[0407] S9: As Figure 35 As shown, Figure 35 This is a structural diagram of a chip package structure 10 corresponding to step S9 in a method for fabricating a chip package structure 10 according to some embodiments. A third stacked structure D3 is formed. The third stacked structure D3 includes a plurality of fourth semiconductor structures 14 stacked along a first direction Z.

[0408] After step S8 (i.e., setting the second stacked structure D2 on the side of the first stacked structure D1 away from the first semiconductor structure 11) in the flowchart of the method for fabricating the chip package structure 10, and before step S3 (i.e., forming the initial first package layer 511), the method for fabricating the chip package structure 10 may also include step S10.

[0409] S10: As Figure 36 As shown, Figure 36 This is a structural diagram of a chip package structure 10 corresponding to step S10 in a method for fabricating a chip package structure 10 according to some embodiments. A third stacked structure D3 is disposed on the side of the second stacked structure D2 away from the first semiconductor structure 11.

[0410] like Figure 37 As shown, Figure 37 This is a structural diagram of a chip package structure 10 corresponding to step S3 in a method for fabricating a chip package structure 10 according to some embodiments. In step S3 (i.e., forming an initial first package layer 511) of the flowchart of the method for fabricating a chip package structure 10, when forming the initial first package layer 511, the initial first package layer 511 also covers a third stacked structure D3 and fills the gaps between adjacent third stacked structures D3.

[0411] In other words, when the method for fabricating the chip package structure 10 includes step S10 (that is, setting the third stacked structure D3 on the side of the second stacked structure D2 away from the first semiconductor structure 11), the initial first package layer 511 covers multiple first semiconductor structures 11, multiple first stacked structures D1 and multiple second stacked structures D2, and fills the gaps between adjacent first semiconductor structures 11, between adjacent first stacked structures D1 and between adjacent second stacked structures D2, and also covers multiple third stacked structures D3, and fills the gaps between adjacent third stacked structures D3.

[0412] For example, when the method for fabricating the chip package structure 10 includes step S9 (i.e., forming the third stacked structure D3) and step S10 (i.e., setting the third stacked structure D3 on the side of the second stacked structure D2 away from the first semiconductor structure 11), step S4 in the flowchart of the method for fabricating the chip package structure 10 (i.e., cutting the initial first package layer 511 to obtain multiple first package layers 51) is similar to step S4 in the flowchart of the aforementioned method for fabricating the chip package structure 10, and will not be repeated here.

[0413] Steps S5 and S6 in the flowchart of the method for fabricating chip package structure 10 are similar to steps S5 and S6 in the flowchart of the aforementioned method for fabricating chip package structure 10, and will not be repeated here.

[0414] For example, the method of forming the third stacked structure D3 can be the same as or similar to the method of forming the second stacked structure D2 described above, and will not be repeated here.

[0415] In some embodiments, when the chip package structure 10 includes a first stacked structure D1, the method for forming the first stacked structure D1 may be the same as or similar to the method for forming the aforementioned second stacked structure D2.

[0416] like Figure 38 and Figure 39 As shown, Figure 38 and Figure 39 These are all structural diagrams of a chip packaging structure 10 provided according to some embodiments. The chip packaging structure 10 may further include a fourth packaging layer 54. The fourth packaging layer 54 covers the first stacked structure D1.

[0417] For example, please continue reading Figure 38 and Figure 39 The material of the fourth encapsulation layer 54 within the chip packaging structure 10 may include one or more of epoxy resin, expanding monomer, and curing agent.

[0418] For example, please continue reading Figure 38 and Figure 39 In the case where the chip packaging structure 10 includes a first packaging layer 51, the first packaging layer 51 can also cover a fourth packaging layer 54.

[0419] For example, please continue reading Figure 38 and Figure 39 The materials of the first encapsulation layer 51 and the fourth encapsulation layer 54 can be different.

[0420] Alternatively, the materials of the first encapsulation layer 51 and the fourth encapsulation layer 54 can be the same.

[0421] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip packaging structure, characterized in that, include: First semiconductor structure; A first stacked structure is located on one side of the first semiconductor structure along a first direction, wherein the first direction is the thickness direction of the first semiconductor structure; The first stacked structure includes a plurality of second semiconductor structures stacked along the first direction; The second stacked structure is located on the side of the first stacked structure that is away from the first semiconductor structure; The second stacked structure includes a plurality of third semiconductor structures stacked along the first direction; A second encapsulation layer covers the second stacked structure; The first encapsulation layer covers the first semiconductor structure, the first stacked structure, and the second encapsulation layer.

2. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes a first bonding layer located between the first stacked structure and the second stacked structure; The first bonding layer and the first encapsulation layer are in contact.

3. The chip packaging structure according to claim 1, characterized in that, The second semiconductor structure is a dynamic random access memory or a flash memory; and / or, The third semiconductor structure is a dynamic random access memory or a flash memory.

4. The chip packaging structure according to claim 1, characterized in that, The second semiconductor structure includes a memory array layer and a peripheral device layer, wherein the peripheral device layer is coupled to the memory array layer; and / or, The third semiconductor structure includes a memory array layer and a peripheral device layer, wherein the peripheral device layer is coupled to the memory array layer.

5. The chip packaging structure according to any one of claims 1-4, characterized in that, The chip packaging structure further includes a plurality of first connection portions located between adjacent second semiconductor structures; the second semiconductor structures are electrically connected to the first semiconductor structures through the first connection portions; and / or, The chip packaging structure also includes a plurality of second connection portions located between adjacent third semiconductor structures; the third semiconductor structures are electrically connected to the first stacked structure through the second connection portions.

6. The chip packaging structure according to any one of claims 1-4, characterized in that, The first stacked structure includes a first surface and a second surface opposite each other in the first direction; the first stacked structure further includes at least one first conductive pillar located within the first stacked structure and extending along the first direction; the first conductive pillar includes a first end and a second end opposite each other in the first direction, the first end being located on the first surface and the second end being located within the target die corresponding to the first conductive pillar; the second semiconductor structure is electrically connected to the first semiconductor structure through the conductive pillar; and / or, The second stacked structure includes a third surface and a fourth surface opposite to each other in the first direction; the second stacked structure also includes at least one second conductive pillar located within the second stacked structure and extending along the first direction; the second conductive pillar includes a third end and a fourth end opposite to each other in the first direction, the third end being located on the third surface and the fourth end being located within the target die corresponding to the second conductive pillar; the third semiconductor structure is electrically connected to the first stacked structure through the second conductive pillar.

7. The chip packaging structure according to any one of claims 1-4, characterized in that, The chip packaging structure also includes: A third stacked structure is located on the side of the second stacked structure away from the first semiconductor structure; the third stacked structure includes a plurality of fourth semiconductor structures stacked along the first direction. A third encapsulation layer covers the third stacked structure; the first encapsulation layer also covers the third encapsulation layer.

8. The chip packaging structure according to claim 7, characterized in that, The chip packaging structure further includes a fourth bonding layer, located between the second stacked structure and the third stacked structure; The fourth bonding layer is in contact with the first encapsulation layer.

9. The chip packaging structure according to claim 7, characterized in that, The fourth semiconductor structure is a dynamic random access memory or a flash memory.

10. A method for fabricating a chip packaging structure, characterized in that, include: Multiple first semiconductor structures are arranged in an array on one side of the first carrier layer; A first stacked structure is formed on the side of the first semiconductor structure away from the first carrier layer; The first stacked structure includes a plurality of second semiconductor structures stacked along a first direction, wherein the first direction is the thickness direction of the first semiconductor structure; Form the initial first encapsulation layer; The initial first packaging layer covers a plurality of the first semiconductor structures and a plurality of the first stacked structures, and fills the gaps between adjacent first semiconductor structures and between adjacent first stacked structures. Cut the initial first encapsulation layer to obtain multiple first encapsulation layers; Each of the first encapsulation layers covers a first semiconductor structure and a first stacked structure located on one side of the first semiconductor structure along the first direction.

11. The method for fabricating a chip packaging structure according to claim 10, characterized in that, After forming the initial first encapsulation layer, the fabrication method further includes: Remove the first support layer.

12. The method for fabricating a chip packaging structure according to claim 11, characterized in that, After the initial first encapsulation layer is formed, and before the first carrier layer is removed, the fabrication method further includes: The first carrier layer is cut along the side of the first carrier layer away from the first semiconductor structure to form a first cleavage; the first cleavage is located between adjacent first semiconductor structures in the direction perpendicular to the first direction; the first cleavage penetrates at least the first carrier layer in the first direction.

13. The method for fabricating a chip packaging structure according to claim 12, characterized in that, Along the first direction, the first cut also extends into the interior of the initial first encapsulation layer.

14. The method for fabricating a chip packaging structure according to claim 10, characterized in that, The array of multiple first semiconductor structures arranged on one side of the first carrier layer includes: Multiple first semiconductor structures are arrayed on one side of the initial second carrier layer; The initial second carrier layer is cut to obtain a plurality of second carrier layers; a first semiconductor structure is disposed on one side of each second carrier layer, and a second carrier layer and the first semiconductor structure located on one side of the second carrier layer form a transition stack structure; Multiple arrays of the transition stacked structures are arranged on one side of the first bearing layer.

15. The method for fabricating a chip packaging structure according to claim 14, characterized in that, After forming the initial first encapsulation layer, the fabrication method further includes: Remove the first support layer and the second support layer.

16. The method for fabricating a chip packaging structure according to claim 15, characterized in that, After the initial first encapsulation layer is formed, and before the first carrier layer and the second carrier layer are removed, the fabrication method further includes: A first cleavage is formed by cutting the first carrier layer and the second carrier layer from the side of the first carrier layer away from the first semiconductor structure; the first cleavage is located between adjacent first semiconductor structures in the direction perpendicular to the first direction; the first cleavage penetrates at least the first carrier layer and the second carrier layer in the first direction.

17. The method for fabricating a chip packaging structure according to claim 10, characterized in that, The preparation method further includes: A second stacked structure is formed; the second stacked structure includes a plurality of third semiconductor structures stacked along the first direction; After forming the first stacked structure on the side of the first semiconductor structure away from the first carrier layer, and before forming the initial first packaging layer, the fabrication method further includes: The second stacked structure is disposed on the side of the first stacked structure that is away from the first semiconductor structure; When forming the initial first encapsulation layer, the initial first encapsulation layer also covers the second stacked structure and fills the gaps between adjacent second stacked structures.

18. The method for fabricating a chip packaging structure according to claim 17, characterized in that, The formation of the second stacked structure includes: Multiple third semiconductor structures are arranged in an array on one side of the third carrier layer; At least one third semiconductor structure is stacked along the first direction on the side of the third semiconductor structure away from the third carrier layer to form a second stacked structure; An initial second encapsulation layer is formed; the initial second encapsulation layer covers a plurality of the second stacked structures and fills the gaps between adjacent second stacked structures; Remove the third load-bearing layer; The initial second encapsulation layer is cut to obtain a plurality of second encapsulation layers; each second encapsulation layer covers one of the second stacked structures.

19. The method for fabricating a chip packaging structure according to claim 17, characterized in that, The type of the third semiconductor structure is the same as the type of the second semiconductor structure.

20. The method for preparing a chip packaging structure according to any one of claims 10-19, characterized in that, The second semiconductor structure is a dynamic random access memory or a flash memory.

21. The method for preparing a chip packaging structure according to any one of claims 10-19, characterized in that, The second semiconductor structure includes: Storage array layer; The peripheral device layer is coupled to the memory array layer.

22. The method for preparing a chip packaging structure according to any one of claims 10-19, characterized in that, The first stacked structure further includes a plurality of first interconnects located between adjacent second semiconductor structures; The second semiconductor structure is electrically connected to the first semiconductor structure through the first connecting portion.

23. The method for preparing a chip packaging structure according to any one of claims 10-19, characterized in that, The first stacked structure includes a first surface and a second surface opposite to each other in the first direction; The first stacked structure further includes at least one first conductive post located within the first stacked structure and extending along the first direction; the first conductive post includes a first end and a second end opposite to each other in the first direction, the first end being located on the first surface, and the second end being located within the target die corresponding to the conductive post; The second semiconductor structure is electrically connected to the first semiconductor structure through the first conductive pillar.

24. The method for fabricating a chip packaging structure according to any one of claims 17-19, characterized in that, The preparation method further includes: A third stacked structure is formed; the third stacked structure includes a plurality of fourth semiconductor structures stacked along the first direction; After the second stacked structure is disposed on the side of the first stacked structure away from the first semiconductor structure, and before the initial first packaging layer is formed, the fabrication method further includes: The third stacking structure is disposed on the side of the second stacking structure away from the first semiconductor structure; When forming the initial first encapsulation layer, the initial first encapsulation layer also covers the third stack structure and fills the gaps between adjacent third stack structures.

25. The method for preparing a chip packaging structure according to any one of claims 10-19, characterized in that, The first support layer includes an arrangement area and a peripheral area, wherein the peripheral area surrounds the arrangement area; The arrangement area is transparent, and multiple first semiconductor structures are located in the arrangement area.

26. The method for fabricating a chip packaging structure according to claim 25, characterized in that, A first alignment mark is set within the surrounding area.

27. A storage system, characterized in that, include: The chip packaging structure as described in any one of claims 1-9; The controller is electrically connected to the chip package structure.

28. An electronic device, characterized in that, include: The storage system as described in claim 27; The processor is coupled to the storage system.

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