Electronic device, packaging structure, chip stacking structure, chip and manufacturing method

Abstract

The embodiment of the application discloses an electronic device, a packaging structure, a chip stacking structure, a chip and a manufacturing method, relates to the technical field of integrated circuits, and solves the problem that the existing passivation layer is prone to cracking in a thermal process to cause electric leakage or failure. The chip comprises a chip main body, a buffer layer and a passivation layer. The chip main body comprises a top layer metal interconnection layer, and the top layer metal interconnection layer is provided with a groove structure and a groove. The groove structure is located in a groove wall region close to the groove. The groove width of the groove is greater than the groove width of the groove structure. The buffer layer fills the groove structure and covers the top layer metal interconnection layer and the groove. The passivation layer covers a side surface of the buffer layer away from the top layer metal interconnection layer.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an electronic device, a packaging structure, a chip stacking structure, a chip, and a method for manufacturing the same. Background Technology

[0002] Semiconductor devices are susceptible to performance degradation or failure due to external environmental factors such as moisture and mobile ions. Therefore, a protective surface film, or passivation layer, needs to be deposited during chip manufacturing. The passivation layer protects the semiconductor device from the effects of the external environment.

[0003] However, during subsequent thermal processing of the chip, thermal stress can cause stress concentration in areas of the passivation layer where there is metal underneath, leading to cracking of the passivation layer. This crack can propagate through the passivation layer to the underlying metal interconnect layer. Moisture can seep into the chip through these cracks, potentially corroding internal metallized structures (such as copper wires), causing leakage or failure risks, and affecting the chip's reliability. Summary of the Invention

[0004] This application provides an electronic device, a packaging structure, a chip stacking structure, a chip, and a manufacturing method, which solves the problem that existing passivation layers are prone to cracking during thermal processing, resulting in leakage or failure.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] In a first aspect, this application provides a chip comprising a chip body, a buffer layer, and a passivation layer. The chip body is the film structure of the chip before the buffer layer and passivation layer are fabricated. The chip body may include most of the circuit devices (such as transistors), inter-device films (such as dielectric layers, isolation layers, etc.), and interconnecting lines. The chip body includes a top metal film layer, which may be called a top metal interconnect layer. This top metal interconnect layer may include multiple electrodes. Furthermore, the top metal interconnect layer has trenches, and the number of trenches can be one or more. One or more trenches can isolate multiple electrodes. A buffer layer covers the top metal interconnect layer and the trench structure. The passivation layer can be made of silicon nitride (Si3N4). The passivation layer covers the surface of the buffer layer away from the top metal interconnect layer. Stress concentration is prone to occur at the edges of the trenches, i.e., at the trench walls. In particular, stress concentration is severe at the corners of the trenches. During thermal processing, the trench walls are prone to cracking.

[0007] The top metal interconnect layer of this application also includes a trench structure located near the trench wall region. Furthermore, the width of the trench structure is smaller than the width of the trench. The aforementioned buffer layer can completely fill the trench structure. During thermal processing, the buffer layer within the trench structure effectively buffers the thermal stress concentration of the top metal interconnect layer on the passivation layer at the trench sidewall, making the passivation layer less prone to tearing due to the thermal stress of the top metal interconnect layer. This reduces the risk of chip leakage and failure, and improves chip reliability.

[0008] It should be noted that in some embodiments of this application, the thickness of a portion of the buffer layer covering the trench is greater than the opening of the trench. That is, the buffer layer can fill the entire trench and protrude beyond it. The increased thickness of the buffer material within the trench provides better buffering for the areas on the passivation layer corresponding to the trench (especially the trench walls and corners).

[0009] Furthermore, stress concentration issues can occur at the openings of both the trench and the groove structure. Therefore, to avoid these problems, in some embodiments, chamfers can be provided at the openings of both the trench and the groove structure to reduce stress concentration caused by the groove shape design, further preventing cracking of the passivation layer at the groove and groove structure walls due to thermal stress. Specifically, the chamfer can be a rounded corner. Grooves with rounded corners exhibit more uniform stress distribution.

[0010] The aforementioned groove structure can include various groove structures. In some embodiments of this application, the groove structure includes a first groove that penetrates the top metal interconnect layer along its thickness direction. The buffer layer can completely fill the first groove. The first groove effectively alleviates stress concentration in the top metal interconnect layer.

[0011] Furthermore, in some other embodiments of this application, the aforementioned groove structure further includes a second groove, which is provided to penetrate a portion of the thickness of the top metal interconnect layer along the thickness direction. The buffer layer can fill the second groove. The groove structure including the first groove and the second groove has a better stress relief effect.

[0012] The number of first trenches and the number of second trenches can be the same or different. Furthermore, there can be one first trench and multiple second trenches; this application does not impose any limitation on this. In some embodiments of this application, the trench structure includes multiple first trenches, which are spaced apart along the extension direction of the trench. Multiple first trenches provide a more uniform stress relief effect on the entire trench wall region of the trench structure located in the top metal interconnect layer on the passivation layer.

[0013] Based on this, in some other embodiments of this application, the aforementioned trench structure includes a plurality of second trenches, which are spaced apart along the extension direction of the trench. Similarly, the plurality of second trenches provide a more uniform stress relief effect on the entire trench wall of the trench structure located in the top metal interconnect layer on the passivation layer.

[0014] In one embodiment, which includes multiple first grooves and multiple second grooves, the multiple first grooves and multiple second grooves can be staggered along the extension direction of the grooves. Alternatively, the multiple first grooves and multiple second grooves can be distributed sequentially. That is, the multiple first grooves are distributed sequentially at intervals. Then, multiple second grooves are distributed sequentially at one end of the multiple first grooves.

[0015] Furthermore, the shapes of the first and second grooves can both be varied. The shape of the first groove can be the same as or different from that of the second groove.

[0016] In some embodiments, the first groove can be a square groove, a round groove, a polygonal groove, or a long strip groove. The second groove can also be a square groove, a round groove, a polygonal groove, or a long strip groove. The processing technology for these shapes of grooves is relatively simple.

[0017] Furthermore, in the embodiments of this application, the surface of the buffer layer that contacts the passivation layer is planar. The planar contact between the buffer layer and the passivation layer avoids stress concentration between the two film layers, thus preventing cracking of the passivation layer.

[0018] Secondly, this application also provides a method for manufacturing a chip. The method includes the following steps:

[0019] A top-layer metal interconnect structure and a buffer structure are fabricated on a wafer. Trench and slot structures are formed within the top-layer metal interconnect structure. The slot structures are located near the slot wall region of the trenches. The width of the trenches is greater than the width of the slot structures. The buffer structure fills the slot structures and covers the top-layer metal interconnect structure and the trenches.

[0020] A passivation structure is formed on the buffer structure to obtain the first stacked structure.

[0021] Cut the first stacked structure to obtain multiple chips.

[0022] Therefore, the chip obtained after dicing includes a chip body, a buffer layer, and a passivation layer. The chip body includes a top metal interconnect layer with internal trenches and slot structures. The buffer layer fills the trenches and slot structures and covers the top metal interconnect layer. The passivation layer covers the buffer layer. This yields multiple chips as described in the first aspect.

[0023] Based on the above method, in some embodiments of this application, the top-layer metal interconnect structure includes a first sub-metal interconnect structure and a second sub-metal interconnect structure. The buffer structure includes a first sub-buffer structure and a second sub-buffer structure. The fabrication of the top-layer metal interconnect structure and buffer structure on the wafer specifically includes:

[0024] The first sub-metal interconnect structure is fabricated on the wafer.

[0025] Trenches are formed within the first sub-metal interconnect structure.

[0026] Create the first sub-buffer structure. The first sub-buffer structure must at least fill the trench.

[0027] A second sub-metal interconnect structure is formed on the first sub-metal interconnect structure and the first sub-buffer structure, and a groove structure is formed within the top-level metal interconnect structure.

[0028] Fabricate a second sub-buffer structure. This second sub-buffer structure fills the groove structure and covers the top metal interconnect structure.

[0029] Therefore, trench and channel structures can be formed through two grooving processes, and specifically, top-layer metal interconnect structure and buffer structure can be formed through two deposition processes.

[0030] Furthermore, in some embodiments of this application, the fabrication of the first sub-buffer structure specifically includes:

[0031] A first sub-buffer layer is formed on the first sub-metal interconnect structure and within the trench.

[0032] The first sub-buffer structure is obtained by removing a portion of the first sub-buffer layer located on the first sub-metal interconnect structure and a portion of the first sub-buffer layer in the trench that is higher than the upper surface of the first sub-metal interconnect structure.

[0033] Based on the above method, in some embodiments, forming a trench structure within the top-level metal interconnect structure specifically includes: forming a trench structure within the top-level metal interconnect structure and removing a portion of the second sub-metal interconnect layer within the trench.

[0034] Furthermore, in some embodiments of this application, the fabrication of the second sub-buffer structure specifically includes:

[0035] Fabricate a second sub-buffer layer. This second sub-buffer layer is disposed at least on the second sub-metal interconnect structure and within the slot structure.

[0036] The second sub-buffer layer of the first part is removed to obtain a second sub-buffer structure with a planar upper surface. The second sub-buffer layer of the first part includes a second sub-buffer layer of a first predetermined thickness located on the second sub-metal interconnect structure, and a second sub-buffer layer of a second predetermined thickness within the groove structure that is higher than the upper surface of the second sub-metal interconnect structure.

[0037] Thirdly, this application also provides a chip stacking structure, including multiple chips, one or more of which are the chips described in the first aspect. The multiple chips are stacked, and the stacking direction can be the thickness direction of the chips. Since at least one chip in the chip stacking structure of this application is the same as the chip structure described in the first aspect, and both can solve the same technical problem and achieve the same technical effect, further details are omitted here.

[0038] Fourthly, this application also provides a packaging structure, including a packaging substrate and the chip stacking structure described in the third aspect above, wherein the chip stacking structure is disposed on the packaging substrate. Since the chip stacking structure in this application is identical in structure to the chip stacking structure described in the third aspect above, and both can solve the same technical problem and achieve the same technical effect, further details are omitted here.

[0039] Fifthly, this application also provides an electronic device, including a circuit board and the packaging structure described in the fourth aspect above. The packaging structure is connected to the circuit board. Since the packaging structure in the electronic device of this application is the same as the packaging structure described in the fourth aspect above, and both can solve the same technical problem and achieve the same technical effect, further details are omitted here. Attached Figure Description

[0040] To illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be described below.

[0041] Figure 1 This is a three-dimensional structural diagram of a mobile phone as an embodiment of this application;

[0042] Figure 2 This is a schematic diagram of an explosion of a mobile phone according to an embodiment of this application;

[0043] Figure 3 This is a schematic diagram of the circuit board assembly in a mobile phone according to an embodiment of this application;

[0044] Figure 4 This is a cross-sectional schematic diagram of the packaging structure in the circuit board assembly according to an embodiment of this application;

[0045] Figure 5a This is a partial cross-sectional schematic diagram of the chip according to the first embodiment of this application;

[0046] Figure 5b for Figure 5aEnlarged view of part A in the image;

[0047] Figure 6 This is a three-dimensional schematic diagram of the chip body in the first type of chip according to the embodiments of this application;

[0048] Figure 7 This is a three-dimensional schematic diagram of a partial cross-section of a chip in a related technology;

[0049] Figure 8 for Figure 7 Enlarged view of part B in the image;

[0050] Figure 9a This is a partial cross-sectional schematic diagram of the second type of chip according to an embodiment of this application;

[0051] Figure 9b for Figure 9a Enlarged view of section C in the image;

[0052] Figure 10a This is a partial cross-sectional schematic diagram of the third type of chip according to an embodiment of this application;

[0053] Figure 10b for Figure 10a Enlarged view of part D in the image;

[0054] Figure 10c This is a partial cross-sectional schematic diagram of the fourth type of chip in the embodiments of this application;

[0055] Figure 10d for Figure 10c Enlarged view of part E in the image;

[0056] Figure 10e This is a partial cross-sectional schematic diagram of the fifth type of chip in this application embodiment;

[0057] Figure 10f This is a partial cross-sectional schematic diagram of the sixth type of chip in this application embodiment;

[0058] Figure 11a This is a partial perspective view of a first type of chip body having a first groove according to an embodiment of this application;

[0059] Figure 11b This is a partial perspective view of a second type of chip body having a first slot, according to an embodiment of this application.

[0060] Figure 12a This is a partial perspective view of the chip body with a first groove having a square groove according to an embodiment of this application;

[0061] Figure 12b This is a partial perspective view of the chip body with a first groove having a circular groove according to an embodiment of this application;

[0062] Figure 13This is a partial perspective view of the chip body with a first slot having a hexagonal groove, according to an embodiment of this application.

[0063] Figure 14 This is a partial three-dimensional schematic diagram of a chip body having multiple spaced-apart first slots according to an embodiment of this application;

[0064] Figure 15 This is a partial cross-sectional schematic diagram of a chip having a plurality of first slots and a plurality of second slots spaced apart according to an embodiment of this application;

[0065] Figure 16 This is a partial cross-sectional schematic diagram of a chip having a plurality of first slots and a plurality of second slots arranged sequentially according to an embodiment of this application;

[0066] Figure 17 To Figure 8 Stress distribution diagram obtained from simulation of the chip;

[0067] Figure 18 To Figure 10a Stress distribution diagram obtained from simulation of the chip;

[0068] Figure 19 To Figure 8 Stress distribution diagram on the XZ section obtained from simulation of the chip;

[0069] Figure 20 To Figure 10a Stress distribution diagram on the XZ section obtained from simulation of the chip;

[0070] Figure 21 To Figure 10f Stress distribution diagram obtained from simulation of the chip;

[0071] Figure 22 To Figure 10f The stress distribution diagram on the XZ section obtained by simulation of the chip;

[0072] Figure 23 To Figure 10e The stress distribution diagram on the XZ section obtained by simulation of the chip;

[0073] Figure 24 To Figure 10b The stress distribution diagram on the XZ section obtained by simulation of the chip;

[0074] Figure 25 To Figure 11a The stress distribution diagram on the XZ section obtained by simulation of the chip;

[0075] Figure 26 To Figure 11b The stress distribution diagram on the XZ section obtained by simulation of the chip;

[0076] Figure 27 To Figure 12b Stress distribution diagram obtained from simulation of the chip;

[0077] Figure 28 To Figure 12b Stress distribution diagram on the XZ section obtained from simulation of the chip;

[0078] Figure 29 To Figure 12b Stress curve distribution diagram of the passivation layer in the chip;

[0079] Figure 30 To Figure 14 Stress distribution diagram obtained from simulation of the chip;

[0080] Figure 31 To Figure 14 Stress distribution diagram on the XZ section obtained from simulation of the chip;

[0081] Figure 32 To Figure 14 Stress curve distribution diagram of the passivation layer in the chip;

[0082] Figure 33 In the diagrams (a), (b), (c), (d), (e), (f), (g), (h), (i), and (j), respectively, it is a structural diagram of each process in the chip fabrication method in Example 1.

[0083] Figure 34 In the diagrams (a), (b), (c), (d), (e), (f), (g), (h), (i), (j), and (k), respectively, it is a structural diagram of each process in the chip fabrication method in Example 2.

[0084] Icon labels:

[0085] 1000 - Electronic device; 100 - Screen; 200 - Mid-frame; 300 - Back cover; 400 - Circuit board assembly; 10 - Motherboard; 20 - Packaging structure; 20S - First stacked structure; 201 - Packaging substrate; 202 - Chip; 1 - Chip body; 1S - First wafer; 11 - Top metal interconnect layer; 11S - Top metal interconnect structure; 11aS - First sub-metal interconnect structure; 11bS - Second sub-metal interconnect structure; 111 - Electrode; P - Edge; R - Corner; 112 - Groove; 1120 - Second chamfer; 113 - Groove structure; 1130 - First chamfer; 1131 - First groove; 1132 - Second groove; 2 - Buffer layer; 2S - Buffer structure; 211S - First sub-buffer layer; 21S - First sub-buffer structure; 221S - Second sub-buffer layer; 22S - Second sub-buffer structure; 2a - Upper surface; 3 - Passivation layer; 3S - Passivation structure; 4 - Blocking layer; 4S - Blocking structure; 500 - Camera. Detailed Implementation

[0086] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0087] In the following description, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0088] Furthermore, in this application, directional terms such as "upper," "lower," "left," "right," "horizontal," and "vertical" are defined relative to the indicated placement of the components in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the placement of the components in the accompanying drawings.

[0089] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can refer to a mechanical or physical connection. It can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. It can also be understood as the physical contact and electrical conduction of components, or as the form of connection between different components in a circuit structure through physical lines capable of transmitting electrical signals, such as PCB copper foil or wires.

[0090] This application provides an electronic device, which may include various terminals such as consumer electronics, home electronics, and in-vehicle electronics. The embodiments of this application do not limit the specific form of the electronic device. For illustrative purposes, the aforementioned consumer electronics may include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics may include smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronics may be in-vehicle terminals equipped with intelligent driving chips. The embodiments of this application do not impose special limitations on the specific form of the aforementioned electronic device. For ease of explanation, the following description uses this electronic device as an example. Figure 1 The example shown is a mobile phone.

[0091] Please refer to Figure 1 and Figure 2 , Figure 1 A perspective view of a mobile phone provided in some embodiments of this application. Figure 2 for Figure 1 An exploded view of the electronic device is shown. As described above, in this embodiment, the electronic device 1000 is a mobile phone. The electronic device 1000 may include a screen 100, a mid-frame 200, a back cover 300, and a circuit board assembly 400 fixed on the mid-frame 200.

[0092] Understandable, Figure 1 and Figure 2 The electronic device 1000 is shown only schematically, and the actual shape, size, location, and construction of these components are not subject to change. Figure 1 and Figure 2 The limitations. In some other examples, the electronic device 1000 may also not include the screen 100. Alternatively, the electronic device 1000 may also include, for example... Figure 2 The camera shown is 500.

[0093] The aforementioned circuit board assembly 400 includes a motherboard 10 and various electronic components disposed on the motherboard 10, such as... Figure 3 As shown. Specifically, the motherboard 10 can be a printed circuit board. Multiple electronic components are connected to the motherboard 10. These electronic components may include a central processing unit chip, memory chip, power management chip, wireless network chip, Bluetooth chip, various sensor chips, and various interfaces. These chips are all specifically packaged in a package structure 20.

[0094] Among them, such as Figure 4 As shown, the packaging structure 20 may include a packaging substrate 201 and a chip 202, and the chip 202 may be disposed on the packaging substrate 201. There may be one or more chips 202 in the packaging structure 20, and this application does not limit this. For example, multiple chips 202 may be spaced apart on the packaging substrate 201, or they may be arranged along the thickness direction of the chip 202 (within the same direction as the thickness of the substrate). Figure 4 The chips (with the same Z-axis direction) are stacked sequentially, and this application does not limit this. For example, the package structure 20 is a high bandwidth memory (HBM) and includes multiple chips 202. The multiple chips 202 are stacked along the thickness direction of the chip 202.

[0095] by Figure 5a Taking chip 202 as an example, chip 202 includes a chip body 1, a buffer layer 2, and a passivation layer 3 (PV). The chip body 1 is the film structure of chip 202 before the buffer layer 2 and passivation layer 3 are fabricated. For example, the chip body 1 is a structure obtained from a silicon wafer through front-end of line (FEOL) and part of back-end of the line (BEOL) processes. The chip body 1 may include most of the circuit devices (such as transistors), inter-device films (such as dielectric layers, isolation layers, etc.), and interconnecting lines in chip 202. The chip body 1 includes a top metal film layer. This metal film layer can be called the top metal interconnect layer 11. The material of the top metal interconnect layer 11 can be aluminum (Al), copper (Cu), platinum (Pt), chromium (Cr), titanium (Ti), or other metals, etc., and this application does not limit this. In subsequent fabrication processes of chip 202, bumps can be fabricated on the top metal interconnect layer 11 to facilitate the connection of chip 202 with other devices. In addition, pin puncture tests can be performed on the top metal interconnect layer 11.

[0096] In some embodiments of this application, the top metal interconnect layer 11 may include multiple electrodes 111 and slots 112. The electrodes 111 may specifically be aluminum pads (ALPA). The slots 112 are used to isolate adjacent electrodes 111. Therefore, there may be one or more slots 112, and the specific number can be selected according to the number and distribution of the electrodes 111. Multiple slots 112 can isolate multiple electrodes 111.

[0097] It should be noted that the main function of setting the trench 112 is to isolate the circuits in the top metal interconnect layer 11 and reduce the density of the large area metal region. Figure 5a This is only a schematic diagram of a partial structure of the top metal interconnect layer 11.

[0098] Example, Figure 6 Only a portion of the top metal interconnect layer 11 is shown. Within this region, four electrodes 111 and two trenches 112 are shown. The four electrodes 111 are arranged in a rectangular array. The two trenches 112 intersect each other in a cross shape, isolating the four electrodes 111 from each other.

[0099] The material of the aforementioned buffer layer 2 can be silicon dioxide (SiO2). The material of the passivation layer 3 can be silicon nitride (Si3N4). Furthermore, as... Figure 7 and Figure 8 As shown, buffer layer 2 and passivation layer 3 can be sequentially stacked on the four electrodes 111 and two trenches 112 of the top metal interconnect layer 11. Both buffer layer 2 and passivation layer 3 have a uniform thickness. During subsequent thermal processing, due to the difference in thermal expansion coefficients between passivation layer 3 and the top metal interconnect layer 11, the top metal interconnect layer 11 will generate tensile stress on passivation layer 3. Since buffer layer 2 is also provided, buffer layer 2 can buffer part of the tensile stress generated on passivation layer 3, thereby reducing the occurrence of cracks in passivation layer 3.

[0100] However, stress concentration areas exist in the top metal interconnect layer 11, such as the edge P and corner R of the electrode 111, that is, on the trench wall or corner of the trench wall 112. In these areas, the buffer layer 2 has a poor buffering effect, and the passivation layer 3 is prone to developing more cracks under stress. These cracks can propagate through the passivation layer 3 to the top metal interconnect layer 11, and even penetrate into other underlying film layers. Moisture can penetrate into the chip 202 through these cracks, which may cause corrosion of the metallized structures inside the chip 202 (such as electrodes 111, circuits, devices, etc.), resulting in leakage or failure risks and affecting the reliability of the chip 202.

[0101] Therefore, to address this problem, this application proposes a chip 202 with an improved structure. Compared to Figure 8 The passivation layer 3 in the chip shown is less prone to cracking during the thermal process.

[0102] Reference Figure 5a and Figure 5b In this embodiment, the top metal interconnect layer 11 of the chip 202 also has a trench structure 113, which is located near the trench wall region of the trench 112. That is, the trench structure 113 can be disposed adjacent to the trench 112. The trench structure 113 can be completely filled by the buffer layer 2. Furthermore, the buffer layer 2 can still cover the entire top metal interconnect layer 11 and the trench 112. Moreover, the coverage of the buffer layer 2 on the top metal interconnect layer 11 and the trench 112 can still be maintained. Figure 8The thickness is shown. The amount of buffer layer 2 filling the groove structure 113 is larger than the amount covering the top metal interconnect layer 11.

[0103] During the thermal processing, the buffer layer 2 located within the trench structure 113 effectively buffers the thermal stress exerted by the top metal interconnect layer 11 on the passivation layer 3 at the sidewall of the trench 112, making the passivation layer 3 less prone to being torn apart by the thermal stress of the top metal interconnect layer 11. This reduces the risk of leakage current in the chip 202 and improves its reliability.

[0104] It should be noted that the groove structure 113 is designed to alleviate the thermal stress of the passivation layer 3 on the sidewall of the trench 112. Therefore, the groove width of the groove structure 113 (the direction of the groove width is...) Figure 5b The X-axis direction (in the X-axis direction) should generally be smaller than the groove width of groove 112. Furthermore, for grooves 112 with corners, i.e. Figure 6 The intersection of the two grooves 112 has four corners R. Stress concentration is a serious problem at these corners R. Therefore, the buffer grooves in this embodiment should preferably be located at these corners R.

[0105] In addition, in some embodiments of this application, the thickness of a portion of the buffer layer 2 located within the trench 112 can be as follows: Figure 8 The thickness shown is equal to that of a portion of the area covering the top metal interconnect layer 11.

[0106] Or, it can be like Figure 9a and Figure 9b As shown, the thickness of a portion of the buffer layer 2 located within the trench 112 is higher than the opening of the trench 112. That is, the buffer layer 2 can fill the entire trench 112 and protrude beyond it. The increased amount of buffer material within the trench 112 results in a better buffering effect on the area of ​​the passivation layer 3 corresponding to the trench 112.

[0107] Furthermore, considering that stress concentration problems can exist in the groove opening of the slot structure 113 or the groove opening of the trench 112, this application can avoid this problem by changing the shape of the groove opening.

[0108] For example, such as Figure 10a , Figure 10b , Figure 10c , Figure 10d The groove opening of the groove structure 113 can be provided with a first chamfer 1130, which can reduce stress concentration at the groove opening of the groove structure 113. This avoids cracking of the passivation layer 3 at the groove wall of the groove structure 113 due to thermal stress. Furthermore, the first chamfer 1130 can be a right angle or a rounded corner (i.e., a rounded chamfer). Among these, the groove opening with a rounded chamfer exhibits more uniform stress.

[0109] Similarly, such as Figure 10a , Figure 10b , Figure 10c , Figure 10d , Figure 10e and Figure 10f The groove 112 can have a second chamfer 1120 at its opening. Furthermore, the second chamfer 1120 can also be a right angle or a rounded corner (i.e., an arc-shaped chamfer). This application does not impose any limitations on this.

[0110] Furthermore, the groove structure 113 in this application embodiment may include grooves of different depths or grooves of different shapes, and this application does not impose any limitations on this.

[0111] For example, the slot structure 113 in this application embodiment includes as follows: Figure 11a and Figure 11b The first groove 1131 shown penetrates the top metal interconnect layer 11 along the thickness direction (parallel to the Z-axis direction in Figure 11). The buffer layer 2 can fill the first groove 1131. The first groove 1131 has a good stress relief effect on the top metal interconnect layer 11.

[0112] The shape of the first groove 1131 can be varied. In some embodiments, such as... Figure 12a As shown, the cross-section (i.e., the XY plane) of the first groove 1131 is rectangular, that is, the first groove 1131 is a square groove.

[0113] In some other embodiments, such as Figure 12b As shown, the cross-section of the first groove 1131 is circular, that is, the first groove 1131 is a circular groove.

[0114] In other embodiments, such as Figure 13 As shown, the cross-section of the first groove 1131 is polygonal, that is, the first groove 1131 is a polygonal groove.

[0115] In some other embodiments, such as Figure 6 As shown, the cross-section of the first groove 1131 is elongated. Therefore, the first groove 1131 is an elongated through groove. The length of the first groove 1131 can be less than the sidewall length of the groove 112.

[0116] The processing technology for the first grooves 1131 of the aforementioned shapes is relatively simple. Furthermore, the number of first grooves 1131 in the groove structure 113 can be one or more; this application does not impose any limitation on this. For square, circular, or polygonal first grooves 1131, if there are multiple first grooves 1131, they can be distributed at intervals along the sidewall extension direction of the groove 112. The shapes of the multiple first grooves 1131 can be the same or different; this application does not impose any limitation on this. First grooves 1131 of different shapes can be staggered or distributed sequentially; this application also does not impose any limitation on this.

[0117] For example, the slot structure 113 in this embodiment may also include, as shown below: Figure 10b The second groove 1132 shown penetrates a portion of the thickness of the top metal interconnect layer 11 along its thickness direction. The buffer layer 2 can completely fill the second groove 1132. It should be noted that the groove structure 113 may include only the second groove 1132, or it may include both the first groove 1131 and the second groove 1132. The groove structure 113, which includes both the first groove 1131 and the second groove 1132, also has a better stress relief effect.

[0118] Similarly, the shape of the second groove 1132 can also be various. For example, the second groove 1132 can also be a square groove, a round groove, a polygonal groove, or a long strip groove. The processing technology of these shapes of the second groove 1132 is also relatively simple.

[0119] Furthermore, there can be one or more second grooves 1132. In some examples, there are multiple second grooves 1132, which can be spaced apart along the sidewall extension direction of the groove 112, such as... Figure 14 As shown. Multiple second grooves 1132 can be identical or different; this application does not impose any restrictions on this. Second grooves 1132 of different shapes can be staggered or sequentially distributed; this application does not impose any restrictions on this.

[0120] It should be noted that for the groove structure 113 including the first groove 1131 and the second groove 1132, the first groove 1131 and the second groove 1132 can be as follows: Figure 15 The staggered distribution shown can also be as follows: Figure 16 The distribution shown is sequential, and this application does not impose any restrictions on it.

[0121] The above describes the relevant parameters such as the depth, shape, number, and distribution of the groove structure 113. The surface of the buffer layer 2 that contacts the passivation layer 3 can be... Figure 16 The upper surface 2a is shown. When fabricating the buffer layer 2, the upper surface 2a of the buffer layer 2 can be ground flat. This results in the upper surface 2a of the buffer layer 2 being a plane. The buffer layer 2 and the passivation layer 3 are connected in a planar manner, which avoids stress concentration problems between the buffer layer 2 and the passivation layer 3, and further avoids stress concentration problems in the passivation layer 3.

[0122] To further illustrate the stress improvement effect of the passivation layer 3 in chip 202 of this application embodiment, this application also... Figure 8 The chip 202 shown and Figure 10a Stress simulations were performed on the chip 202 shown. The simulation results are as follows: Figure 17 , Figure 18 , Figure 19 and Figure 20 As shown.

[0123] Figure 17 It shows Figure 8 Stress distribution of chip 202. Figure 18 It shows Figure 10a Stress distribution of chip 202. Figure 19 It shows Figure 8 Stress distribution of chip 202 on the XZ section. Figure 20 It shows Figure 10a Stress distribution of chip 202 on the XZ section. Figure 17 and Figure 19 3. Middle passivation layer Figure 18 and Figure 20 The stress on the surface of the intermediate passivation layer 3 is at the corner of the trench 112 (the position circled in the figure) where the stress is the maximum.

[0124] Figure 17 The maximum tensile stress on the upper surface of the intermediate passivation layer 3 at this corner is 2908 MPa. Figure 18 The maximum tensile stress on the upper surface of the passivation layer 3 at this corner is 1010 MPa. Therefore, in this embodiment, the maximum tensile stress on the surface of the passivation layer 3 at the corner of the trench 112 is reduced by 1898 MPa, and the stress is optimized by 65.3%. Figure 19 The maximum tensile stress at the corner of the passivation layer 3 is 1520 MPa. Figure 20 The maximum tensile stress of the passivation layer 3 at the corner is 1000 MPa. Therefore, the maximum tensile stress of the passivation layer 3 at the corner of the trench 112 in this application is reduced by 520 MPa, and the stress is optimized by 34.2%. Therefore, the stress concentration problem of the passivation layer 3 in this embodiment is effectively alleviated.

[0125] Furthermore, to illustrate the stress buffering effect of setting buffer layers 2 of different thicknesses within the trench 112, embodiments of this application also provide... Figure 10f Stress simulation was performed on chip 202. The simulation results are as follows: Figure 21 and Figure 22 As shown. Similarly, Figure 10f The stress on the surface of the passivation layer 3 in the chip 202 shown is the maximum stress at the corner of the trench 112 (the position circled in the figure).

[0126] Figure 21 It shows Figure 10f Stress distribution of chip 202. Figure 21 The maximum tensile stress on the upper surface of the intermediate passivation layer 3 at this corner is 2372 MPa. (Compared to...) Figure 17 contrast, Figure 10f The maximum tensile stress on the surface of the passivation layer 3 of the middle chip 202 at the corner of the trench 112 decreased by 536 MPa, and the stress was optimized by 18.43%.

[0127] Figure 22 It shows Figure 10a Stress distribution of chip 202 on the XZ section. Figure 19 The maximum tensile stress at the corner section of the intermediate passivation layer 3 is 1440 MPa. (Compared to...) Figure 19 contrast, Figure 10f The maximum tensile stress on the surface of the passivation layer 3 at the corner of the trench 112 of the chip 202 decreased by 80 MPa, and the stress was optimized by 5.26%. Therefore, simply adding the trench structure 113 to the chip 202 can achieve a good stress buffering effect. Increasing the amount of buffering material in the trench 112 can further improve the stress buffering effect on the passivation layer 3.

[0128] To illustrate the stress buffering effect of the groove structure 113 with different depths and chamfer structures, the embodiments of this application also provide... Figure 10e , Figure 10b , Figure 11a and Figure 11b Stress simulations were performed on the chips in the simulation. The simulation results are as follows: Figure 23 , Figure 24 , Figure 25 and Figure 26 As shown. Similarly, Figure 10e , Figure 10b , Figure 11a and Figure 11b The stress on the surface of the passivation layer 3 in the chip shown is the maximum stress at the corner of trench 112 (circled in the figure).

[0129] Figure 23 It shows Figure 10e Stress distribution of chip 202 on the XZ section. Figure 24 It shows Figure 10b Stress distribution of chip 202 on the XZ section. Figure 23 The maximum tensile stress at the corner of the passivation layer 3 is 986 MPa. Figure 24 The maximum tensile stress of the passivation layer 3 at the corner is 959 MPa. Therefore, for the chip 202 with the second groove, after adding the first chamfer 1130, the maximum tensile stress of the passivation layer 3 at the corner is reduced by 27 MPa, which has a certain stress improvement effect.

[0130] Figure 25 It shows Figure 11a Stress distribution of chip 202 on the XZ section. Figure 26 It shows Figure 11b Stress distribution of chip 202 on the XZ section. Figure 25 The maximum tensile stress at the corner section of the intermediate passivation layer 3 is 956 MPa. Figure 26 The maximum tensile stress at the corner section of the intermediate passivation layer 3 is 940 MPa. Therefore, compared to... Figure 23and Figure 25 In the chip 202 with the first groove, the passivation layer 3 reduces the maximum tensile stress at the corner section by 30 MPa, exhibiting better stress buffering effect. (Comparison) Figure 25 and Figure 26 For chip 202 with the first groove, after adding the first chamfer 1130, the maximum tensile stress of the passivation layer 3 at the corner section is reduced by 16MPa.

[0131] Furthermore, to illustrate the stress-improvement effect of the first groove 1131 or the second groove 1132 with different shapes, numbers, and distribution patterns, Figure 12b The chip shown and Figure 14 Taking the chip shown as an example, this application embodiment uses... Figure 12b Chip 202 and Figure 14 Stress simulations were also performed on chip 202. The simulation results are as follows: Figure 27 , Figure 28 , Figure 29 , Figure 30 , Figure 31 and Figure 32 As shown.

[0132] Figure 27 It shows Figure 12b Stress distribution in the chip. Figure 28 It shows Figure 12b Stress distribution of the chip on the XZ section. Figure 29 It shows Figure 12b The stress distribution curve of passivation layer 3 in the chip. From Figure 29 As can be seen, the maximum stress at the corner of passivation layer 3 decreased from 769 MPa (point N) to 750 MPa (point M), and the stress was optimized by 2.5%.

[0133] Figure 30 It shows Figure 14 Stress distribution in the chip. Figure 31 It shows Figure 14 Stress distribution of the chip on the XZ section. Figure 32 It shows Figure 14 The stress distribution curve of passivation layer 3 in the chip. From Figure 32 As can be seen, the maximum stress at the corner of the passivation layer 3 decreased from 766 MPa (Y point) to 711 MPa (X point), and the stress was optimized by 7.2%.

[0134] Regarding the chip 202 in the above embodiments, this application also provides a method for manufacturing the chip. The following description uses two specific examples.

[0135] Example 1

[0136] In this example, the chip fabrication method includes the following steps:

[0137] S10: Fabricate the top-level metal interconnect structure and buffer structure.

[0138] After completing the front-end and part of the back-end processes, the first wafer is obtained. Then, the top-layer metal interconnect structure and buffer structure are fabricated on the first wafer.

[0139] In some examples of this application, reference is made to Figure 33 The specific steps of S100 above are as follows:

[0140] S101: Fabricate the first sub-metal interconnect structure on the first wafer.

[0141] For example, a deposition process can be used to form such a wafer on the first wafer 1S. Figure 33 The first sub-metal interconnect structure 11aS is shown in (a).

[0142] S102: A trench is formed within the first sub-metal interconnect structure.

[0143] For example, a dry etching process can be used to form such a structure within the first sub-metal interconnect structure 11aS. Figure 33 Groove 112 shown in (b).

[0144] S103: Create the first sub-buffer structure.

[0145] For example, the specific steps in S103 can be as follows:

[0146] S1031: Fabricate a first sub-buffer layer on the first sub-metal interconnect structure and within the trench.

[0147] For example, a deposition process can be used to form, such as, on the first sub-metal interconnect structure 11aS and within the trench 112. Figure 33 The first sub-buffer layer 211S is shown in (c).

[0148] S1032: Remove a portion of the first sub-buffer layer to obtain the aforementioned first sub-buffer structure.

[0149] For example, the first sub-buffer layer 211S can be ground flat using a grinding process (such as chemical mechanical polishing). The portion of the first sub-buffer layer 211S located on the first sub-metal interconnect structure 11aS, and the portion of the first sub-buffer layer 211S within the trench 112 that is above the upper surface of the first sub-metal interconnect structure 11aS, are all ground away. Thus, a... Figure 33 The first sub-buffer structure 21S is shown in (d).

[0150] S104: Fabricate the second sub-metal interconnect structure.

[0151] In some embodiments, the first sub-buffer structure 21S and the first sub-metal interconnect structure 11aS can be formed by a deposition process. Figure 33 The second sub-metal interconnect structure 11bS is shown in (e). Thus, a top-level metal interconnect structure 11S including the first sub-buffer structure 21S and the second sub-buffer structure 22S is obtained.

[0152] S105: A groove structure is formed within the top-level metal interconnect structure.

[0153] For example, a trench structure 113 can be formed within the top-layer metal interconnect structure 11S by etching, and a portion of the second sub-metal interconnect structure 11bS within the trench 112 can be removed, such as... Figure 33 As shown in (f). The width of the groove 112 is greater than the width of the groove structure 113.

[0154] S106: Create the second sub-buffer structure.

[0155] For example, the specific steps in S106 can be as follows:

[0156] S1061: Create the second sub-buffer layer.

[0157] For example, such as... can be formed on the second sub-metal interconnect structure 11bS and within the trench structure 113 by a deposition process. Figure 33 The second sub-buffer layer 221S is shown in (g).

[0158] S1062: Remove the second sub-buffer layer of the first part to obtain a second sub-buffer structure with a planar upper surface.

[0159] For example, a grinding process can be used to remove the second sub-buffer layer 221S in the first part. The second sub-buffer layer 221S in the first part includes a second sub-buffer layer 221S of a first preset thickness on the second sub-metal interconnect structure 11bS, a second sub-buffer layer 221S of a second preset thickness within the trench 112 that is higher than the upper surface of the second sub-metal interconnect structure 11bS, and a second sub-buffer layer 221S of a second preset thickness within the groove structure 113 that is higher than the upper surface of the second sub-metal interconnect structure 11bS. The second preset thickness can be less than the first preset thickness. After the grinding process, the upper surface of the second sub-buffer structure 22S is flat, thus obtaining... Figure 33 The second sub-buffer structure 22S is shown in (h). Thus, the above-mentioned buffer structure 2S is obtained.

[0160] S20: Create a passivation structure.

[0161] For example, a deposition process can be used to form a buffer structure 2S, such as Figure 33The passivation structure 3S is shown in (i). Thus, the first stacked structure 20S is obtained.

[0162] S30: Cut the first stacked structure to obtain multiple chips.

[0163] For example, the first stacked structure can be cut along a preset cutting path for 20 seconds using mechanical or laser methods. This yields, as shown... Figure 33 Chip 202 is shown in (j). The chip 202 obtained after dicing includes a chip body 1, a buffer layer 2, and a passivation layer 3. The chip body includes a top metal interconnect layer 11 with internal trenches 112 and groove structures 113. The buffer layer 2 fills the trenches 112 and groove structures 113 and covers the top metal interconnect layer 11. The passivation layer 3 covers the buffer layer 2. This is the chip 202 in the above embodiment.

[0164] Example 2

[0165] In this example, the chip is fabricated using a method similar to that in Example 1. Figure 34 In (a), (b), (c), (d), (h), (i), (j), and (k), the chip fabrication method in this example also includes S101, S102, S103, S105, S106, S20, and S30 of S10 in Example 1. The difference lies in the different fabrication processes used in S104 for fabricating the second sub-metal interconnect structure 11bS and in S105 for forming the trench structure 113 within the top-layer metal interconnect structure 11S.

[0166] In this example, the fabrication of the second sub-metal interconnect structure 11bS in S104 and the formation of the groove structure 113 within the top-layer metal interconnect structure 11S in S105 are specifically carried out using the following steps:

[0167] S1041: Construct a barrier structure.

[0168] For example, it can be formed first on the first sub-buffer structure 21S and the first sub-metal interconnect structure 11aS by a deposition process. Figure 34 The barrier layer 4 shown in (e) is then removed from the upper portion of the first sub-metal interconnect structure 11aS, excluding the groove structure 113, to obtain... Figure 34 The blocking structure 4S shown in (f) covers the area where the first sub-buffer structure 21S and the preset slot structure 113 are located.

[0169] S1042: Fabricate a second sub-metal interconnect structure on the first sub-metal interconnect structure, the barrier layer and the first sub-buffer structure, and fabricate a groove structure to obtain a top-layer metal interconnect structure.

[0170] For example, it can also be formed on the first sub-metal interconnect structure 11aS, the barrier layer 4, and the first sub-buffer structure 21S by a deposition process. Figure 34 The second sub-metal interconnect structure 11bS shown in (g) is used to obtain the top metal interconnect structure 11S. At the same time, the second sub-metal interconnect structure 11bS will not be deposited on the barrier structure 4S, thereby forming the trench structure 113.

[0171] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized in that, include: The chip body includes a top metal interconnect layer, which has a groove structure and trenches. The groove structure is located near the groove wall region; the groove width is greater than the groove width of the groove structure; A buffer layer that fills the trench structure and covers the top metal interconnect layer and the trench; A passivation layer covers the buffer layer on the side surface away from the top metal interconnect layer.

2. The chip according to claim 1, characterized in that, The thickness of the buffer layer covering a portion of the trench is higher than the opening of the trench.

3. The chip according to claim 1 or 2, characterized in that, The groove structure has a chamfer at the groove opening.

4. The chip according to any one of claims 1-3, characterized in that, The groove structure includes: The first groove extends through the top metal interconnect layer along its thickness direction.

5. The chip according to claim 4, characterized in that, There are multiple first grooves, and the multiple first grooves are distributed at intervals along the extension direction of the groove.

6. The chip according to claim 4 or 5, characterized in that, The first groove is a square groove, a round groove, a polygonal groove, or a long strip groove.

7. The chip according to any one of claims 1-6, characterized in that, The groove structure also includes: The second groove is provided to penetrate a portion of the thickness of the top metal interconnect layer along the thickness direction.

8. The chip according to claim 7, characterized in that, There are multiple second grooves, and the multiple second grooves are distributed at intervals along the extension direction of the groove.

9. The chip according to claim 7 or 8, characterized in that, The second groove is a square groove, a round groove, a polygonal groove, or a long strip groove.

10. The chip according to any one of claims 1-9, characterized in that, The surface of the buffer layer that contacts the passivation layer is a plane.

11. A method for manufacturing a chip, characterized in that, Includes the following steps: A top-level metal interconnect structure and a buffer structure are fabricated on a wafer; wherein, trenches and slot structures are formed within the top-level metal interconnect structure; the slot structures are located near the slot wall region of the trenches; the slot width of the trenches is greater than the slot width of the slot structures; the buffer structure fills the slot structures and covers the top-level metal interconnect structure and the trenches; A passivation structure is formed on the buffer structure to obtain a first stacked structure; Cut the first stacked structure to obtain multiple chips.

12. The method for manufacturing a chip according to claim 11, characterized in that, The top-layer metal interconnect structure includes a first sub-metal interconnect structure and a second sub-metal interconnect structure; the buffer structure includes a first sub-buffer structure and a second buffer structure; the fabrication of the top-layer metal interconnect structure and the buffer structure on the wafer specifically includes: A first sub-metal interconnect structure is fabricated on the wafer; A trench is formed within the first sub-metal interconnect structure; Fabricate the first sub-buffer structure; wherein the first sub-buffer structure at least fills the groove; A second sub-metal interconnect structure is formed on the first sub-metal interconnect structure and the first sub-buffer structure; A groove structure is formed within the top-layer metal interconnect structure; Fabricate the second sub-buffer structure; wherein the second sub-buffer structure fills the slot structure and covers the top metal interconnect structure.

13. The method for manufacturing a chip according to claim 12, characterized in that, The specific steps involved in creating the first sub-buffer structure are as follows: A first sub-buffer layer is formed on the first sub-metal interconnect structure and within the trench; The first sub-buffer layer is obtained by removing a portion of the first sub-buffer layer located on the first sub-metal interconnect structure and a portion of the first sub-buffer layer in the trench that is higher than the upper surface of the first sub-metal interconnect structure.

14. The method for manufacturing a chip according to claim 12 or 13, characterized in that, The specific steps involved in creating the second sub-buffer structure are as follows: Fabricate a second sub-buffer layer; wherein the second sub-buffer layer is disposed at least on the second sub-metal interconnect structure and within the groove structure; Remove the second sub-buffer layer of the first part to obtain the second sub-buffer structure with a planar upper surface; wherein, the second sub-buffer layer of the first part includes a second sub-buffer layer with a first preset thickness located on the second sub-metal interconnect structure, and a second sub-buffer layer with a second preset thickness inside the groove structure that is higher than the upper surface of the second sub-metal interconnect structure.

15. A chip stacking structure, characterized in that, include: Multiple chips, at least one of which is the chip according to any one of claims 1-10; The multiple chips are stacked together.

16. A packaging structure, characterized in that, include: Packaging substrate; The chip stacking structure according to claim 15 is disposed on the packaging substrate.

17. An electronic device, characterized in that, include: Circuit board; The packaging structure according to claim 16 is connected to the circuit board.

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