Semiconductor element stack and method of manufacturing the same

Abstract

A semiconductor element stack and a method of manufacturing a semiconductor element stack are disclosed. The semiconductor element stack includes: a bottom element layer, at least one intermediate element layer, and a surface element layer stacked in sequence; a plurality of substrate vias respectively located in the element layers; a plurality of interlayer connection vias respectively electrically connecting the substrate vias and the element layers; a first carrier contacting a back side of the bottom element layer and covering the bottom substrate vias; and a second carrier covering a front side of the surface element layer.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 19 / 185,509 (i.e., priority date "April 22, 2025"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device stack and a method for manufacturing semiconductor devices, and more specifically, to a semiconductor device stack comprising multiple carriers. Background Technology

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the ever-increasing demands for computing power. However, this shrinkage process also introduces many problems, and these problems are constantly increasing. Therefore, challenges remain in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The discussion in the preceding technical paragraphs is for background information only. The statements in the discussion in the preceding technical paragraphs are not an admission that the content disclosed in these paragraphs constitutes prior art of this disclosure, and nothing in the discussion in the preceding technical paragraphs shall be construed as an admission that any part of this application, including the parts in the discussion in the preceding technical paragraphs, constitutes prior art of this disclosure. Summary of the Invention

[0005] One aspect of this disclosure provides a semiconductor device stack, comprising: a bottom device layer, at least one intermediate device layer, and a surface device layer stacked sequentially; a bottom substrate via located in the bottom device layer, wherein a bottom surface of the bottom substrate via is coplanar with a back side of the bottom device layer; at least one intermediate substrate via located in the at least one intermediate device layer, wherein a bottom surface of the at least one intermediate substrate via is coplanar with a back side of the at least one intermediate device layer that contacts the bottom device layer; a surface substrate via located in the surface device layer, wherein a bottom surface of the surface substrate via is coplanar with a back side of the surface device layer that contacts the at least one intermediate device layer; a plurality of interlayer interconnect vias electrically connecting the bottom substrate via and the at least one intermediate device layer, and electrically connecting the surface substrate via and the at least one intermediate device layer; a first carrier contacting the back side of the bottom device layer and covering the bottom substrate via; and a second carrier covering a front side of the surface device layer.

[0006] Another aspect of this disclosure provides a semiconductor device stack, comprising: a bottom device layer, at least one intermediate device layer, and a surface device layer stacked sequentially; a bottom substrate via located in the bottom device layer, wherein a bottom surface of the bottom substrate via is coplanar with a back side of the bottom device layer; at least one intermediate substrate via located in the at least one intermediate device layer, wherein a bottom surface of the at least one intermediate substrate via is coplanar with a back side of the at least one intermediate device layer that contacts the bottom device layer; a surface substrate via located in the surface device layer, wherein a bottom surface of the surface substrate via is coplanar with a back side of the surface device layer that contacts the at least one intermediate device layer; a plurality of interlayer connection vias electrically connecting the bottom substrate via and the at least one intermediate device layer, and electrically connecting the surface substrate via and the at least one intermediate device layer; a front side of a functional element layer located on the back side of the bottom device layer; and a second carrier covering the front side of the surface device layer.

[0007] Another aspect of this disclosure provides a method for manufacturing a semiconductor device stack, comprising: providing an intermediate stack including a bottom device layer, at least one intermediate device layer and a surface device layer stacked sequentially, and a bottom substrate via located in the bottom device layer, wherein a bottom surface of the bottom substrate via is coplanar with a back side of the bottom device layer; forming a first carrier covering the back side of the bottom device layer and the bottom surface of the bottom substrate via; performing a wafer probing process through an opening in the surface device layer and filling the opening; forming a second carrier covering a front side of the surface device layer; separating the intermediate stack from the first carrier; and flipping the intermediate stack and bonding a functional device layer to the back side of the bottom device layer.

[0008] Due to the semiconductor device stacking design disclosed herein, functional element layers can be bonded to the bottom vias under the support of a second carrier, thereby avoiding induced parasitic inductance caused by the suspended (or floating) bottom vias. This improves the performance of the semiconductor device stacking.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0010] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the drawings that combine the embodiments and claims. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features can be arbitrarily increased or decreased.

[0011] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device stack according to an embodiment of the present disclosure;

[0012] Figure 2 This is a cross-sectional view illustrating an intermediate stage in manufacturing a semiconductor device stack according to an embodiment of the present disclosure;

[0013] Figure 3 This is a close-up view illustrating a through-hole in a substrate according to an embodiment of the present disclosure;

[0014] Figures 4 to 8 This is a close-up view illustrating a first adhesive structure according to some embodiments of the present disclosure;

[0015] Figure 9 and Figure 10 This is a cross-sectional view illustrating an intermediate stage in manufacturing a semiconductor device stack according to an embodiment of the present disclosure;

[0016] Figures 11 to 16 This is a close-up view illustrating a second adhesive structure according to some embodiments of the present disclosure; and

[0017] Figures 17 to 19 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor device stack 1 according to an embodiment of the present disclosure.

[0018] The reference numerals in the attached figures are explained as follows:

[0019] 1: Semiconductor component stacking

[0020] 10: Method

[0021] 100: Middle stacking

[0022] 110: Bottom Component Layer

[0023] 110BS: Dorsal side

[0024] 110FS: Front

[0025] 111: Substrate

[0026] 113: Dielectric layer

[0027] 115: Backside overlay

[0028] 117: Passivation layer

[0029] 119: Electrical conductivity characteristics

[0030] 120: Intermediate Component Layer

[0031] 120BS: Dorsal side

[0032] 120FS: Front

[0033] 121: Substrate

[0034] 123: Dielectric layer

[0035] 127: Passivation layer

[0036] 129: Electrical conductivity characteristics

[0037] 130: Intermediate Component Layer

[0038] 130BS: Dorsal side

[0039] 130FS: Front

[0040] 131: Substrate

[0041] 133: Dielectric layer

[0042] 137: Passivation layer

[0043] 139: Electrical conductivity characteristics

[0044] 140: Surface element layer

[0045] 140BS: Dorsal side

[0046] 140FS: Front

[0047] 141: Substrate

[0048] 143: Dielectric layer

[0049] 147: Passivation layer

[0050] 149: Electrical conductivity characteristics

[0051] 210: Bottom substrate through-hole

[0052] 210BS: Bottom surface

[0053] 211: Conductive filling layer

[0054] 213: Seed layer

[0055] 215: Adhesive layer

[0056] 217: Barrier Layer

[0057] 219: Isolation Layer

[0058] 220: Through-hole in intermediate substrate

[0059] 220BS: Bottom surface

[0060] 230: Through-hole in intermediate substrate

[0061] 230BS: Bottom surface

[0062] 240: Surface mount through-hole

[0063] 240BS: Bottom surface

[0064] 310: Interlayer connection through hole

[0065] 320: Interlayer connection through hole

[0066] 330: Interlayer connection through hole

[0067] 410: First adhesive structure

[0068] 411: First adhesive layer

[0069] 413: First demolding layer

[0070] 415: First protective layer

[0071] 417: First stress compensation layer

[0072] 419: First reflective adhesive layer

[0073] 420: Second adhesive structure

[0074] 421: Second adhesive layer

[0075] 423: Second release layer

[0076] 425: Second protective layer

[0077] 427: Second stress compensation layer

[0078] 429: Second reflective adhesive layer

[0079] 510: The First Carrier

[0080] 520: The Second Carrier

[0081] 600: Functional Component Layer

[0082] 600FS: Front

[0083] 601: Conductivity characteristics

[0084] S11: Steps

[0085] S13: Steps

[0086] S15: Steps

[0087] S17: Steps

[0088] S19: Steps

[0089] T1: Thickness

[0090] T2: Thickness

[0091] T3: Thickness Detailed Implementation

[0092] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations described below are provided to simplify this disclosure. Of course, these are merely illustrative and not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature can include embodiments in which the first and second features are formed in direct contact, or embodiments in which an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and is not in itself a limitation on the relationship between the various embodiments and / or configurations discussed.

[0093] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," "upper part," or other similar terms may be used herein to describe the relative relationship between one element or feature depicted in the diagram and another. In addition to the orientations shown in the diagrams, spatially related terms are intended to cover different orientations of the element during use or operation. The element may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein can be interpreted accordingly.

[0094] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it may be directly connected to or coupled to the other component or layer, or there may be intermediate components or intermediate layers.

[0095] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one component from another. Thus, for example, the first component, first member, or first part discussed below may be referred to as the second component, second member, or second part without departing from the teachings of this disclosure.

[0096] Unless the context otherwise indicates, terms such as “identical,” “equal,” “plane,” or “coplanar” as used herein do not necessarily mean exactly identical orientations, layouts, locations, shapes, dimensions, quantities, or other measures of reference, but are intended to cover substantially identical orientations, layouts, locations, shapes, dimensions, quantities, or other measures of reference within an acceptable range of possible variations (e.g., due to manufacturing processes). The term “substantially” may be used herein to reflect this meaning. For example, articles described as “substantially identical,” “substantially equal,” or “substantially coplanar” may be exactly identical, equal, or coplanar, or may be substantially identical, equal, or coplanar within an acceptable range of possible variations (e.g., due to manufacturing processes).

[0097] In this disclosure, semiconductor element generally refers to an element that can operate using semiconductor properties, and electro-optic elements, light-emitting display elements, semiconductor circuits and electronic components are all included in the category of semiconductor element.

[0098] It should be noted that, in the description of this disclosure, "above" (or "up") corresponds to the direction of the arrow in the Z direction, and "below" (or "down") corresponds to the opposite direction of the arrow in the Z direction.

[0099] It should be noted that, in the description of this disclosure, the term "layer" refers to a portion of material comprising a region having a certain thickness. A layer may extend over the entire underlying or overlying structure, or its extent may be less than that of the underlying or overlying structure. Furthermore, a layer may be a region within a homogeneous or heterogeneous continuous structure having a thickness less than that of the continuous structure. For example, a layer may lie between any pair of horizontal planes, wherein the pair of horizontal planes are located between or between the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0100] Figure 1 This is a flowchart illustrating a method 10 for manufacturing a semiconductor element stack 1 according to an embodiment of the present disclosure. Figure 2 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor device stack 1 according to an embodiment of the present disclosure. Figure 3 This is a close-up view illustrating a substrate through-hole according to an embodiment of the present disclosure. Figures 4 to 8 This is a close-up view illustrating a first adhesive structure according to some embodiments of the present disclosure. Figure 9 and Figure 10 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor device stack 1 according to an embodiment of the present disclosure.

[0101] See Figures 1 to 9 In step S11, an intermediate stack 100 can be provided, the first carrier 510 can be bonded to the bottom element layer 110 of the intermediate stack 100, the wafer probing process can be performed through the opening OP1 of the surface element layer 140 of the intermediate stack 100, and the opening OP1 can be filled.

[0102] See Figure 2 The semiconductor device stack 1 may include a bottom device layer 110, at least one intermediate device layer, and a surface device layer 140. In this embodiment, two intermediate device layers 120 and 130 may be used as examples. The number of intermediate device layers may be more or less. In some embodiments, the bottom device layer 110, intermediate device layer 120, intermediate device layer 130, and surface device layer 140 may be stacked sequentially along the Z direction.

[0103] Specifically, the bottom component layer 110 may include a back side 110BS and a front side 110FS. The back side 110BS may face downwards, while the front side 110FS may be parallel to, opposite to, and facing upwards from the back side 110BS. The intermediate component layer 120 may include a back side 120BS and a front side 120FS, wherein the back side 120BS may be substantially coplanar with and in contact with the front side 110FS. The back side 120BS may face downwards and contact the front side 110FS. The front side 120FS may be parallel to, opposite to, and facing the same direction as the back side 120BS. Similarly, the intermediate component layer 130 may include a back side 130BS and a front side 130FS, wherein the back side 130BS may be substantially coplanar with and in contact with the front side 120FS. The front side 130FS may be parallel to, opposite to, and facing upwards from the back side 130BS. The surface element layer 140 may include a back side 140BS and a front side 140FS, wherein the back side 140BS may be substantially coplanar and in contact with the front side 140FS. The front side 140FS may be parallel to the back side 140BS, opposite to the back side 140BS, and facing away from the back side 140BS.

[0104] In some embodiments, the bottom component layer 110 may include a substrate 111, a plurality of component assemblies (not shown for clarity), a dielectric layer 113, a back cover layer 115, a passivation layer 117, and a plurality of conductive features 119.

[0105] In some embodiments, substrate 111 may include a main semiconductor substrate made entirely of at least one semiconductor material. The main semiconductor substrate may be formed of: for example, elemental semiconductors, such as silicon or germanium; compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, other group III-V compound semiconductors or group II-VI compound semiconductors; or combinations thereof.

[0106] In some embodiments, the thickness T1 of substrate 111 may be less than about 200 μm, less than about 50 μm, or less than about 10 μm. For example, the thickness T1 of substrate 111 may be about 3 μm. It should be noted that in the description of this disclosure, when the term "about" is used to modify the amount of a component, part, or reactant of this disclosure, it refers, for example, to numerical variations that may occur through typical measurement and liquid handling procedures used to prepare concentrates or solutions. Furthermore, variations may occur due to unintentional errors in the measurement procedure, differences in the manufacture, source, or purity of the components used to prepare the composition or to carry out the method, etc. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0107] In some embodiments, a plurality of component assemblies may be formed on a host semiconductor substrate. Some portions of the plurality of component assemblies may be formed in the host semiconductor substrate. The plurality of component assemblies may be transistors, such as complementary metal-oxide-semiconductor transistors, metal-oxide-semiconductor field-effect transistors, fin field-effect transistors, other similar transistors, or combinations thereof.

[0108] In some embodiments, dielectric layer 113 may be disposed on substrate 111. In some embodiments, dielectric layer 113 may be a stacked layer structure. Dielectric layer 113 may comprise a plurality of insulator layers. Each of the plurality of insulator layers may have a thickness between about 0.5 μm and about 3.0 μm. The plurality of insulator layers may be formed of materials such as silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, other similar materials, or combinations thereof. The plurality of insulator layers may be formed of different materials, but are not limited thereto. Low-k dielectric materials may have a dielectric constant of less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of the low-k dielectric material may be less than 2.0. The plurality of insulator layers may be formed by a deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other similar deposition processes. A planarization process may be performed after the deposition process to remove excess material and provide a substantially flat surface for subsequent process steps.

[0109] In some embodiments, a plurality of conductive features 119 may be disposed on dielectric layer 113. The plurality of conductive features 119 may include interconnect layers, conductive vias, and a plurality of conductive pads. The interconnect layers may be separated from each other and may be horizontally disposed among the plurality of dielectric layers arranged along the Z-direction. The topmost interconnect layer may be designated as a conductive pad. The top surface of the conductive pad may be substantially coplanar with the top surface of dielectric layer 113. Conductive vias may connect adjacent interconnect layers, adjacent component assemblies and interconnect layers, and adjacent conductive pads and interconnect layers along the Z-direction. In some embodiments, conductive vias may improve heat dissipation and provide structural support. In some embodiments, the plurality of conductive features may be formed of materials such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, or magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof. The plurality of conductive features 119 may be formed during the formation of dielectric layer 113.

[0110] In some embodiments, multiple component assemblies and multiple conductive features 119 may together constitute a functional unit of the bottom component layer 110. In the description of this disclosure, a functional unit generally refers to functionally related circuitry divided into different units for functional purposes. In some embodiments, a functional unit may typically be a highly complex circuit, such as a page buffer, decoder, sense amplifier, driver, charge pump, current or voltage reference, or any active or passive element of the circuitry, such as a transistor, diode, resistor, or capacitor. In some other embodiments, the complexity and functionality of the functional unit may be more or less complex. For example, a functional unit may be a string of memory intersecting with a conductor layer.

[0111] In some embodiments, a back-side cover layer 115 may be disposed beneath the substrate 111 to protect the back side of the substrate 111 during manufacturing. In some embodiments, the back-side cover layer 115 may be formed of silicon nitride, silicon carbonitride, or other suitable insulating materials. In this embodiment, the bottom surface of the back-side cover layer 115 may be referred to as the back side 110BS of the bottom element layer 110. In some embodiments, the back-side cover layer 115 may be optional. In this case, the bottom surface of the substrate 111 may be referred to as the back side 110BS of the bottom element layer 110.

[0112] In some embodiments, a passivation layer 117 may be disposed on the dielectric layer 113. In some embodiments, the passivation layer 117 may be formed of materials such as silicon oxide, silicon nitride, or other suitable dielectric materials. The passivation layer 117 may be formed by, for example, chemical vapor deposition or other suitable deposition processes. The passivation layer 117 may be used as a protective layer or buffer layer to prevent the topmost conductive feature 119 of the bottom element layer 110 from being exposed or damaged during subsequent semiconductor process steps.

[0113] In some embodiments, the intermediate element layer 120 may have the same or similar layout (or design) as the bottom element layer 110. Elements such as substrate 121, dielectric layer 123, passivation layer 127, and conductive features 129 may be formed of the same material as their corresponding elements in the bottom element layer 110 and arranged in the same manner; therefore, their description will not be repeated here.

[0114] In some embodiments, the intermediate element layer 130 may have the same or similar layout (or design) as the bottom element layer 110. Elements such as substrate 131, dielectric layer 133, passivation layer 137, and conductive features 139 may be formed of the same material as their corresponding elements in the bottom element layer 110 and arranged in the same manner; therefore, their description will not be repeated here.

[0115] In some embodiments, the surface element layer 140 may have the same or similar layout (or design) as the bottom element layer 110. Elements such as substrate 141, dielectric layer 143, passivation layer 147, and conductive features 149 may be formed of the same material as their corresponding elements in the bottom element layer 110 and arranged in the same manner; therefore, their description will not be repeated here.

[0116] See Figure 2 and Figure 3 A bottom substrate via 210 can be formed, penetrating the substrate 111 and the back cover layer 115, extending to the dielectric layer 113, and electrically connected to the corresponding topmost conductive feature 119. The bottom surface 210BS of the bottom substrate via 210 can be substantially coplanar with the back surface 110BS of the bottom element layer 110. In some embodiments, the bottom substrate via 210 may include a conductive fill layer 211, a seed layer 213, an adhesive layer 215, a barrier layer 217, and an isolation layer 219.

[0117] In some embodiments, the conductive filler layer 211 may be configured to penetrate the substrate 111 and the back cover layer 115, extend to the dielectric layer 113, and be electrically connected to the corresponding topmost conductive feature 119. The conductive filler layer 211 may be formed of materials such as polycrystalline silicon, tungsten, copper, carbon nanotubes, or solder alloys.

[0118] In some embodiments, a seed layer 213 may be disposed on the sidewall of the conductive fill layer 211. The thickness of the seed layer 213 may be between about 10 nm and about 40 nm. The seed layer 213 may be formed of, for example, copper. The seed layer 213 may reduce the resistivity of the opening during the formation of the conductive fill layer 211.

[0119] In some embodiments, an adhesive layer 215 may be disposed on the sidewall of the seed layer 213. The adhesive layer 215 may be formed of materials such as titanium, tantalum, titanium tungsten, or manganese nitride. The adhesive layer 215 may improve the adhesion between the seed layer 213 and the barrier layer 217.

[0120] In some embodiments, a barrier layer 217 may be disposed on the sidewall of the adhesive layer 215. The barrier layer 217 may be formed of materials such as tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or a tantalum nitride / tantalum bilayer. The barrier layer 217 may prevent the conductive material of the conductive fill layer 211 from diffusing into the adjacent dielectric layer or substrate (e.g., dielectric layer 113, back cover layer 115, and / or substrate 111).

[0121] In some embodiments, the isolation layer 219 may be formed on the sidewall of the barrier layer 217. The isolation layer 219 may electrically isolate the conductive fill layer 211 from the adjacent dielectric layer or substrate (e.g., dielectric layer 113, back cover layer 115 and / or substrate 111).

[0122] Intermediate substrate via 220 can be disposed in intermediate component layer 120. The bottom surface 220BS of intermediate substrate via 220 can be substantially coplanar with the back surface 120BS of intermediate component layer 120. Intermediate substrate via 230 can be disposed in intermediate component layer 130. The bottom surface 230BS of intermediate substrate via 230 can be substantially coplanar with the back surface 130BS of intermediate component layer 130. Surface substrate via 240 can be disposed in surface component layer 140. The bottom surface 240BS of surface substrate via 240 can be substantially coplanar with the back surface 140BS of surface component layer 140.

[0123] The intermediate substrate through-hole 220, intermediate substrate through-hole 230 and surface substrate through-hole 240 may have the same or similar structure and function as the bottom substrate through-hole 210; therefore, they will not be described in detail here.

[0124] See you again Figure 2 Interlayer connection vias 310 can be formed in passivation layer 117 to electrically connect the intermediate substrate via 220 and the corresponding conductive features 119 of the bottom element layer 110. Interlayer connection vias 320 can be formed in passivation layer 127 to electrically connect the intermediate substrate via 230 and the corresponding conductive features 129 of the intermediate element layer 120. Interlayer connection vias 330 can be formed in passivation layer 137 to electrically connect the surface substrate via 240 and the corresponding conductive features 139 of the intermediate element layer 130.

[0125] In some embodiments, the plurality of interlayer connection vias 310, 320, and 330 may be formed of the following materials: for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof.

[0126] See you again Figure 2The first carrier 510 may be bonded below the intermediate stack 100. In some embodiments, the first carrier 510 may be a dummy wafer. A dummy wafer is a wafer used to temporarily support a structure attached thereto and does not include any permanently integrated functional units. The dummy wafer may be formed of materials such as silicon, glass, polymer, sapphire, or other suitable substrates. In some embodiments, the first carrier 510 may also be a thick dielectric layer that can be removed by polishing in subsequent processes. This dielectric layer may include materials such as silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, silicon nitride, silicon oxynitride, silicon oxynitride, or other suitable dielectric materials. In some embodiments, the thickness of the dielectric layer may be greater than 500 μm.

[0127] In some embodiments, the first carrier 510 may be bonded to the back side 110BS of the bottom element layer 110 via a first adhesive structure 410 formed therebetween. In some embodiments, the first adhesive structure 410 may comprise an acid-, alkali-, and high-temperature-resistant material to ensure stability during back-side processes such as curing, polishing, etching, and metallization before the intermediate stack 100 is separated from the first carrier 510.

[0128] See Figure 2 and Figure 4 The first adhesive structure 410 may be disposed between the first carrier 510 and the bottom component layer 110. In some embodiments, the first adhesive structure 410 may include a first adhesive layer 411 and a first release layer 413. The first release layer 413 may directly contact the first carrier 510, meaning it is disposed on the first carrier 510. The first adhesive layer 411 may directly contact the back side 110BS of the bottom component layer 110 and is located between the first release layer 413 and the bottom component layer 110, meaning it is disposed below the bottom component layer 110.

[0129] In some embodiments, the first release layer 413 can be removed during subsequent processes by thermal slide debonding, chemical dissolution, mechanical peeling or laser ablation, thereby achieving debonding of the bottom element layer 110 from the first carrier 510.

[0130] In some embodiments where the bottom element layer 110 is debonded from the first carrier 510 by laser ablation, the first release layer 413 may be formed of a metallic material with properties such as reactive (i.e., non-inert), flexible, and relatively low melting point. For example, the first release layer 413 may be formed of a metallic material, such as aluminum, tin, or zinc. In some other embodiments, the first release layer 413 may be formed of a carbon material, such as carbon nanotubes and graphene. Depending on the material used for the first release layer 413, the thickness T2 of the first release layer 413 may be between about 5 nm and about 400 nm. For example, in an embodiment where the first release layer 413 is formed of a metallic material such as aluminum, the thickness of the first release layer 413 is between about 5 nm and about 200 nm. In another embodiment where the first release layer 413 is formed of a carbon material, the thickness of the first release layer 413 is less than about 400 nm.

[0131] See Figure 2 and Figure 4 In some embodiments where the bottom element layer 110 is decoupled from the first carrier 510 by laser ablation, the first adhesive layer 411 can be formed of any suitable adhesive material, which may or may not adequately absorb the laser energy. In some embodiments, the first adhesive layer 411 can be formed of materials such as polymeric adhesives, high-temperature thermoplastic polyimides, benzocyclobutene, acrylic resins, epoxy resins, or other suitable adhesives.

[0132] Regardless of the energy absorption capacity of the first adhesive layer 411, in some embodiments, the material composition and thickness of the first release layer 413 can be configured to strongly absorb laser energy and, as the primary release layer of the first adhesive structure 410, it is etched by laser energy. The first release layer 413 can improve laser ablation efficiency, thereby reducing the ablation threshold of the first adhesive structure 410 (compared to a bonding structure using an adhesive layer alone).

[0133] In some embodiments, the first adhesive structure 410 may be manufactured as follows. First, a first release layer 413 may be formed on the surface of the first carrier 510. For example, a layer of metallic material (e.g., aluminum) may be deposited using chemical vapor deposition, physical vapor deposition, or atomic layer deposition to form the first release layer 413. In some other embodiments, the first release layer 413 may be formed by growing or otherwise placing a layer of carbon material (e.g., carbon nanotubes, graphene layers, etc.) on the surface of the first carrier 510. The next step may include forming a first adhesive layer 411 on the first release layer 413. The first adhesive layer 411 may be formed using known materials and deposition techniques. For example, the first adhesive layer 411 may be formed from any suitable polymeric adhesive, high-temperature thermoplastic polyimide, benzocyclobutene, acrylic resin, epoxy resin, or other suitable adhesive. In some embodiments, the first adhesive layer 411 may be formed by spin-coating the adhesive material onto the first release layer 413 and heating and baking the adhesive material. Finally, a standard bonding process can be performed to bond the first carrier 510 (having a first adhesive structure 410) to the back side 110BS of the bottom element layer 110.

[0134] See Figure 2 and Figure 5 In some other embodiments, the first adhesive structure 410 may include a first adhesive layer 411, a first release layer 413, and a first protective layer 415. The first release layer 413 may directly contact the first carrier 510, meaning it is formed on the first carrier 510. The first adhesive layer 411 may be formed on the first release layer 413 and disposed between the first release layer 413 and the bottom component layer 110. The first protective layer 415 may directly contact the back side 110BS of the bottom component layer 110 and is disposed between the first adhesive layer 411 and the bottom component layer 110, meaning it is disposed below the bottom component layer 110.

[0135] In some embodiments, the first protective layer 415 can be used to protect the intermediate stack 100 from irradiation by energy emitted by the laser during laser ablation. Specifically, the configuration (material composition and thickness) of the first protective layer 415 can reflect incident laser energy from the intermediate stack 100 back to the first release layer 413. In some embodiments, the first protective layer 415 can be formed of an inert metallic material, such as titanium, chromium, gold, or copper, with a thickness sufficient to reflect energy. For example, the first protective layer 415 can be formed of a metallic material such as titanium, with a thickness ranging from about 50 nm to about 500 nm. In some embodiments, the additional radiation reflected back from the first protective layer 415 can further enhance the ablation efficiency of the irradiated portion of the first release layer 413 (and the adhesive material) in the laser ablation region.

[0136] In some embodiments, Figure 5 The first adhesive structure 410 in the above can be used as described above. Figure 4 It can be manufactured using a method similar to the one discussed above. Firstly, it can be manufactured using the same method described above. Figure 4 A similar method is used to form a first release layer 413 on the surface of the first carrier 510, and then a first adhesive layer 411 is formed on the first release layer 413. Next, a first protective layer 415 can be formed on the back side 110BS of the bottom element layer 110 using a suitable metallic material and known deposition techniques. Subsequently, a standard bonding process can be performed to bond the first carrier 510 (with the first adhesive structure 410) to the intermediate stack 100 (with the first protective layer 415) to construct the final stack structure.

[0137] See Figure 2 and Figure 6 In some other embodiments, the first adhesive structure 410 may include a first adhesive layer 411, a first release layer 413, and a first stress compensation layer 417. The first stress compensation layer 417 may directly contact the first carrier 510, meaning it is formed on the first carrier 510. The first release layer 413 may be formed on the first stress compensation layer 417 and disposed between the first stress compensation layer 417 and the bottom component layer 110. The first adhesive layer 411 may directly contact the back side 110BS of the bottom component layer 110 and is disposed between the first release layer 413 and the bottom component layer 110, meaning it is disposed below the bottom component layer 110. The first stress compensation layer 417 may be used to prevent warping of the intermediate stack 100, which may be caused by lateral stresses applied to the different layers of the intermediate stack 100 during semiconductor manufacturing processes.

[0138] In some embodiments, the configuration (material composition and thickness) of the first stress compensation layer 417 can counteract stresses that may be applied to the layers of the intermediate stack 100, which could cause the intermediate stack 100 to warp. Furthermore, the configuration (material composition and thickness) of the first stress compensation layer 417 can be transparent to the laser radiation wavelength used in the laser ablation process, allowing laser energy to penetrate the first stress compensation layer 417 and irradiate the first release layer 413. In some embodiments, the first stress compensation layer 417 can be formed of materials such as silicon oxide (e.g., SiO2) or silicon nitride (e.g., Si3N4). The thickness of the first stress compensation layer 417 can be formed in the range of about 100 nm to about 5000 nm, wherein this thickness depends on the material used and the magnitude of the stress-counteracting force required to prevent warping of the intermediate stack 100. In some embodiments, the same as described above can be used. Figure 4The first adhesive structure 410 is manufactured using a similar method to that discussed. First, a first stress compensation layer 417 can be formed on the surface of the first carrier 510, and then a first release layer 413 and a first adhesive layer 411 are sequentially formed on the first stress compensation layer 417. Afterward, a standard bonding process can be performed to bond the first carrier 510 (having the first adhesive structure 410, which includes the first stress compensation layer 417) to the intermediate stack 100 to construct the final stack structure.

[0139] See Figure 2 and Figure 7 In some other embodiments, the first adhesive structure 410 may include a first release layer 413 and a first reflective adhesive layer 419. The first release layer 413 may be in direct contact with the first carrier 510, meaning it is formed on the first carrier 510. The first reflective adhesive layer 419 may be in direct contact with the back side 110BS of the bottom element layer 110 and is disposed between the first release layer 413 and the bottom element layer 110, meaning it is located below the bottom element layer 110. In some embodiments, the first reflective adhesive layer 419 may be formed of, for example, a polymeric adhesive material premixed with laser energy reflective particles. The laser energy reflective particles may include metal particles (aluminum, copper, etc.), or ceramic spheres and / or other types of nanoparticles, such as alumina, boron nitride, silicon oxide, etc., which are used to block or reflect incident radiation. In some embodiments, the first reflective adhesive layer 419 may be used to protect the intermediate stack 100 from radiation. Furthermore, due to the additional radiation reflected back from the first reflective adhesive layer 419 to the first release layer 413, the first reflective adhesive layer 419 can be used to enhance the ablation efficiency of the first release layer 413 in the laser ablation region, thereby reducing the ablation threshold of the first release layer 413.

[0140] See Figure 2 and Figure 8 In some other embodiments, the first adhesive structure 410 may consist only of a first adhesive layer 411. The first adhesive layer 411 may be a laser energy-absorbing adhesive layer. In some embodiments, the first adhesive layer 411 may be formed of a polymeric adhesive material premixed with metal nanoparticles to improve laser energy absorption of the adhesive material. For example, the nanoparticles may be formed of tin (Sn), zinc (Zn), aluminum (Al), carbon nanotubes, or graphene, or combinations thereof. The first adhesive layer 411 may be formed by a deposition coating process, such as spin coating or spray coating, or other alternative forms of deposition coating known in the art (or any combination of deposition coating processes), wherein the premixed polymeric adhesive material with metal nanoparticles is deposited onto the surface of the first carrier 510 before being bonded to the intermediate stack 100. The first adhesive layer 411 may serve as a release layer for laser ablation.

[0141] In some embodiments, the first adhesive layer 411 may function as a release layer and may comprise a material with a low melting point or glass transition temperature, such that its viscosity decreases and it becomes fluid when heated to a specific temperature (e.g., its respective melting point or glass transition temperature). For example, the first adhesive layer 411 may comprise propylene carbonate, polyurethane, polypropylene carbonate, or HT series materials (available from Brewer Science).

[0142] In some embodiments, the first adhesive layer 411 may be formed of a solvent-soluble material. For example, the first adhesive layer 411 may comprise a thermosetting resin formed by the condensation polymerization of methyldiamine and aldehyde, polyisobutylene (PIB) rubber, or... (Available from BASF).

[0143] In some other embodiments, the first carrier 510 may directly contact the back side 110BS of the bottom element layer 110. That is, the first adhesive structure 410 may be omitted.

[0144] See you again Figure 2 An opening OP1 can be formed in the passivation layer 147. The topmost conductive feature 149 can be exposed through the opening OP1. The corresponding conductive feature 149 can be used to perform a wafer probing process through the opening OP1 to inspect the electrical characteristics of the intermediate stack 100.

[0145] See Figure 9 The opening OP1 can be filled after the wafer probing process. Planarization processes, such as chemical mechanical polishing, can be performed to remove excess material and provide a substantially flat surface for subsequent process steps.

[0146] In some other embodiments, the intermediate stack 100 may include only one intermediate element layer 120 (not shown). The intermediate element layer 120 may be disposed between the bottom element layer 110 and the surface element layer 140.

[0147] Figures 11 to 16 This is a close-up view illustrating a second adhesive structure according to some embodiments of the present disclosure. Figure 17 and Figure 19 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a semiconductor device stack 1 according to an embodiment of the present disclosure.

[0148] See Figure 1 and Figures 10 to 16 In step S13, the second carrier 520 can be attached to the intermediate stack 100.

[0149] See Figure 10The second carrier 520 can be bonded to the intermediate stack 100. In some embodiments, the second carrier 520 may be formed of the same material as the first carrier 510. In some embodiments, the second carrier 520 may be formed of a different material than the first carrier 510. The separation process for separating the intermediate stack 100 from the second carrier 520 may be different from the separation process for separating it from the first carrier 510. In some embodiments, the second carrier 520 may be a dummy wafer used to temporarily support structures attached thereto and does not include any permanently integrated functional units. In some embodiments, the second carrier 520 may be formed of silicon, glass, polymer, sapphire, or other suitable substrates. In some embodiments, the second carrier 520 may also be a thick dielectric layer that can be removed by polishing in subsequent processes. This dielectric layer may include materials such as silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, silicon nitride, silicon oxynitride, silicon oxynitride, or other suitable dielectric materials. In some embodiments, the thickness of the dielectric layer may be greater than 500 μm.

[0150] In some embodiments, the second carrier 520 may be bonded to the front side 140FS of the surface element layer 140 via a second adhesive structure 420 formed therebetween. In some embodiments, the second adhesive structure 420 may comprise an acid-, alkali-, and high-temperature-resistant material to ensure stability during back-side processes such as curing, polishing, etching, and metallization before the intermediate stack 100 is separated from the second carrier 520.

[0151] See Figure 10 and Figure 11 The second adhesive structure 420 may be disposed between the second carrier 520 and the surface element layer 140. In some embodiments, the second adhesive structure 420 may include a second adhesive layer 421 and a second release layer 423. The second release layer 423 may directly contact the second carrier 520, meaning it is disposed below the second carrier 520. The second adhesive layer 421 may directly contact the front side 140FS of the surface element layer 140 and is located between the second release layer 423 and the surface element layer 140, meaning it is disposed on the surface element layer 140.

[0152] In some embodiments, the second release layer 423 can be removed during subsequent processes by thermal sliding debonding, chemical dissolution, mechanical peeling or laser ablation, thereby achieving debonding of the surface element layer 140 from the second carrier 520.

[0153] In some embodiments where the surface element layer 140 is debonded from the second carrier 520 via laser ablation, the second release layer 423 may be formed of a metallic material with properties such as reactiveness (i.e., non-inertness), flexibility, and a relatively low melting point. For example, the second release layer 423 may be formed of a metallic material, such as aluminum, tin, or zinc. In some other embodiments, the second release layer 423 may be formed of a carbon material, such as carbon nanotubes and graphene. Depending on the material used for the second release layer 423, the thickness T3 of the second release layer 423 may be between about 5 nm and about 400 nm. For example, in an embodiment where the second release layer 423 is formed of a metallic material such as aluminum, the thickness of the second release layer 423 is between about 5 nm and about 200 nm. In another embodiment where the second release layer 423 is formed of a carbon material, the thickness of the second release layer 423 is less than about 400 nm.

[0154] See Figure 10 and Figure 11 In some embodiments where the surface element layer 140 is decoupled from the second carrier 520 by laser ablation, the second adhesive layer 421 can be formed of any suitable adhesive material, which may or may not adequately absorb the laser energy. In some embodiments, the second adhesive layer 421 can be formed of materials such as polymeric adhesives, high-temperature thermoplastic polyimides, benzocyclobutene, acrylic resins, epoxy resins, or other suitable adhesives.

[0155] Regardless of the energy absorption capacity of the second adhesive layer 421, in some embodiments, the material composition and thickness of the second release layer 423 can be configured to strongly absorb laser energy and, as the primary release layer of the second adhesive structure 420, it is etched by laser energy. The second release layer 423 can improve laser ablation efficiency, thereby reducing the ablation threshold of the second adhesive structure 420 (compared to a bonding structure using an adhesive layer alone).

[0156] In some embodiments, the second adhesive structure 420 may be manufactured as follows. First, a second release layer 423 may be formed on the surface of the second carrier 520. For example, a layer of metallic material (e.g., aluminum) may be deposited using chemical vapor deposition, physical vapor deposition, or atomic layer deposition to form the second release layer 423. In some other embodiments, the second release layer 423 may be formed by growing or otherwise placing a layer of carbon material (e.g., carbon nanotubes, graphene layers, etc.) on the surface of the second carrier 520. The next step may include forming a second adhesive layer 421 on the second release layer 423. The second adhesive layer 421 may be formed using known materials and deposition techniques. For example, the second adhesive layer 421 may be formed from any suitable polymeric adhesive, high-temperature thermoplastic polyimide, benzocyclobutene, acrylic resin, epoxy resin, or other suitable adhesive. In some embodiments, the second adhesive layer 421 may be formed by spin-coating the adhesive material onto the second release layer 423 and heating and baking the adhesive material. Finally, a standard bonding process can be performed to bond the second carrier 520 (having the second adhesive structure 420) to the front side 140FS of the surface element layer 140.

[0157] See Figure 10 and Figure 12 In some other embodiments, the second adhesive structure 420 may include a second adhesive layer 421, a second release layer 423, and a second protective layer 425. The second release layer 423 may directly contact the second carrier 520, meaning it is formed below the second carrier 520. The second adhesive layer 421 may be formed below the second release layer 423 and disposed between the second release layer 423 and the surface element layer 140. The second protective layer 425 may directly contact the front side 140FS of the surface element layer 140 and is disposed between the second adhesive layer 421 and the surface element layer 140, meaning it is disposed on the surface element layer 140.

[0158] In some embodiments, the second protective layer 425 can be used to protect the intermediate stack 100 from irradiation by energy emitted by the laser during laser ablation. Specifically, the configuration (material composition and thickness) of the second protective layer 425 can reflect incident laser energy from the intermediate stack 100 back to the second release layer 423. In some embodiments, the second protective layer 425 can be formed of an inert metallic material, such as titanium, chromium, gold, or copper, with a thickness sufficient to reflect energy. For example, the second protective layer 425 can be formed of a metallic material such as titanium, with a thickness ranging from about 50 nm to about 500 nm. In some embodiments, the additional radiation reflected back from the second protective layer 425 can further enhance the ablation efficiency of the irradiated portion of the second release layer 423 (and the adhesive material) in the laser ablation region.

[0159] In some embodiments, Figure 12 The second adhesive structure 420 in the above can be used as described above. Figure 11 It can be manufactured using a method similar to the one discussed above. Firstly, it can be manufactured using the same method described above. Figure 11 A similar method is used to form a second release layer 423 on the surface of the second carrier 520, and then a second adhesive layer 421 is formed on the second release layer 423. Next, a second protective layer 425 can be formed on the front side 140FS of the surface element layer 140 using a suitable metallic material and known deposition techniques. Subsequently, a standard bonding process can be performed to bond the second carrier 520 (with the second adhesive structure 420) to the intermediate stack 100 (with the second protective layer 425) to construct the final stack structure.

[0160] See Figure 10 and Figure 13 In some other embodiments, the second adhesive structure 420 may include a second adhesive layer 421, a second release layer 423, and a second stress compensation layer 427. The second stress compensation layer 427 may directly contact the second carrier 520, meaning it is formed below the second carrier 520. The second release layer 423 may be formed below the second stress compensation layer 427 and disposed between the second stress compensation layer 427 and the surface element layer 140. The second adhesive layer 421 may directly contact the front side 140FS of the surface element layer 140 and is disposed between the second release layer 423 and the surface element layer 140, meaning it is disposed on the surface element layer 140. The second stress compensation layer 427 may be used to prevent warping of the intermediate stack 100, which may be caused by lateral stresses applied to the different layers of the intermediate stack 100 during semiconductor manufacturing processes.

[0161] In some embodiments, the configuration (material composition and thickness) of the second stress compensation layer 427 can counteract stresses that may be applied to the layers of the intermediate stack 100, which could cause the intermediate stack 100 to warp. Furthermore, the configuration (material composition and thickness) of the second stress compensation layer 427 can be transparent to the laser radiation wavelength used in the laser ablation process, allowing laser energy to penetrate the second stress compensation layer 427 and irradiate the second release layer 423. In some embodiments, the second stress compensation layer 427 can be formed of materials such as silicon oxide (e.g., SiO2) or silicon nitride (e.g., Si3N4). The thickness of the second stress compensation layer 427 can be formed in the range of about 100 nm to about 5000 nm, wherein this thickness depends on the material used and the magnitude of the stress-counteracting force required to prevent warping of the intermediate stack 100. In some embodiments, the same as described above can be used. Figure 11The second adhesive structure 420 is manufactured using a similar method to that discussed. First, a second stress compensation layer 427 can be formed on the surface of the second carrier 520, and then a second release layer 423 and a second adhesive layer 421 are sequentially formed on the second stress compensation layer 427. Afterward, a standard bonding process can be performed to bond the second carrier 520 (having the second adhesive structure 420, which includes the second stress compensation layer 427) to the intermediate stack 100 to construct the final stack structure.

[0162] See Figure 10 and Figure 14 In some other embodiments, the second adhesive structure 420 may include a second release layer 423 and a second reflective adhesive layer 429. The second release layer 423 may directly contact the second carrier 520, meaning it is formed below the second carrier 520. The second reflective adhesive layer 429 may directly contact the front side 140FS of the surface element layer 140 and is disposed between the second release layer 423 and the surface element layer 140, meaning it is located below the surface element layer 140. In some embodiments, the second reflective adhesive layer 429 may be formed of, for example, a polymeric adhesive material premixed with laser energy reflective particles. The laser energy reflective particles may include metal particles (aluminum, copper, etc.), or ceramic spheres and / or other types of nanoparticles, such as alumina, boron nitride, silicon oxide, etc., which are used to block or reflect incident radiation. In some embodiments, the second reflective adhesive layer 429 may be used to protect the intermediate stack 100 from radiation. Furthermore, due to the additional radiation reflected back from the second reflective adhesive layer 429 to the second release layer 423, the second reflective adhesive layer 429 can be used to enhance the ablation efficiency of the second release layer 423 in the laser ablation region, thereby reducing the ablation threshold of the second release layer 423.

[0163] See Figure 10 and Figure 15 In some other embodiments, the second adhesive structure 420 may consist only of a second adhesive layer 421. The second adhesive layer 421 may be a laser energy absorbing adhesive layer. In some embodiments, the second adhesive layer 421 may be formed of a polymer adhesive material premixed with metal nanoparticles to improve laser energy absorption of the adhesive material. For example, the nanoparticles may be formed of tin (Sn), zinc (Zn), aluminum (Al), carbon nanotubes, or graphene, or combinations thereof. The second adhesive layer 421 may be formed by a deposition coating process, such as spin coating or spray coating, or other alternative forms of deposition coating known in the art (or any combination of deposition coating processes), wherein the premixed polymer adhesive material with metal nanoparticles is deposited onto the surface of the second carrier 520 before being bonded to the intermediate stack 100. The second adhesive layer 421 may serve as a release layer for laser ablation.

[0164] See Figure 10 and Figure 16 In some other embodiments, the second adhesive structure 420 may be omitted. That is, the second carrier 520 may directly contact the front side 140FS of the surface element layer 140. The second carrier 520 and the passivation layer 147 of the surface element layer 140 may be bonded by a melt bonding process. Before the melt bonding process, the second carrier 520 and the surface element layer 140 may be surface treated, for example, by plasma treatment. After the melt bonding process, an annealing process may be performed. The process temperature of the annealing process may be between approximately 800°C and approximately 1100°C.

[0165] See Figure 1 and Figure 17 In step S15, the first carrier 510 can be removed from the middle stack 100.

[0166] See Figure 17 In some embodiments, the first carrier 510 can be removed by a polishing process. In some embodiments, the polishing material used in the polishing process can be, for example, silicon carbide, diamond, or other suitable materials.

[0167] In some embodiments, a cleaning process may be performed after the polishing process to remove the first adhesive structure 410 (if present). In some embodiments, the cleaning process may be, for example, a wet etching process.

[0168] In some other embodiments, the first carrier 510 can be removed by a debonding process. The debonding process may include thermal sliding debonding, chemical dissolution, mechanical stripping, or laser ablation.

[0169] In some embodiments, thermal slide debonding may include heating the thermoplastic adhesive layer (e.g., the first adhesive structure 410) to reduce its viscosity, thereby causing the intermediate stack 100 to slide apart. The process temperature for thermal slide debonding may be between about 150°C and about 190°C, softening the polymer to enable separation with minimal mechanical stress.

[0170] In some embodiments, chemical dissolution can rely on a solvent to dissolve the temporary bonding adhesive (e.g., the first adhesive structure 410). In some embodiments, the solvent used for chemical dissolution may include sulfuric acid, hexane, or 1-dodecene.

[0171] In some embodiments, mechanical stripping can be used to separate the first carrier 510 from the intermediate stack 100 by applying controlled physical force. Separation can be initiated using blades or an air jet and then propagated by programmable rollers to complete the de-junction process.

[0172] In some embodiments, the laser ablation debonding process may employ ultraviolet (e.g., 308 nm, 355 nm) or mid-infrared laser (radiation) to selectively degrade the light-absorbing first release layer 413. The laser energy may evaporate the first release layer 413, causing the intermediate stack 100 to separate from the first carrier 510. In some embodiments, the wavelength of the mid-infrared laser may be between about 1.12 μm and about 5 μm, or between about 1.12 μm and about 3 μm. Laser ablation processes using mid-infrared radiation are compatible with carriers made of silicon or glass and are also suitable for use with stress-compensating layers.

[0173] In some embodiments, a cleaning process may be performed after the debonding process to remove any remaining first adhesive structure 410. In some embodiments, the cleaning process may be, for example, a wet etching process.

[0174] In some other embodiments, after the debonding process, the intermediate stack 100 may not immediately undergo any adhesive removal process, and the first adhesive layer 411 may remain on the back side 110BS of the bottom component layer 110. In this way, the residual first adhesive layer 411 protects the bonding interface on the back side 110BS from contamination during subsequent process steps. Specifically, it helps prevent metal regions at the bonding interface (e.g., the bottom surface 210BS of the bottom substrate via 210) from oxidation due to exposure to air. This protective effect of the residual first adhesive structure 410 also extends the allowable waiting time before bonding another component layer (e.g., the functional component layer 600, described later) to the intermediate stack 100.

[0175] See Figure 1 and Figure 18 In step S17, the intermediate stack 100 can be flipped, and the functional element layer 600 can be bonded to the bottom element layer 110 of the intermediate stack 100 to form a semiconductor element stack 1.

[0176] See Figure 18 The middle stack 100 and the second carrier 520 can be flipped so that the back side 110BS of the bottom component layer 110 faces upward.

[0177] The front side 600FS of the functional element layer 600 can be bonded to the back side 110BS of the bottom element layer 110 via a bonding process. In other words, the functional element layer 600 and the intermediate stack 100 can be bonded in a face-to-back configuration. The bonding process may include heat treatment to achieve hybrid bonding between the components of the functional element layer 600 and the bottom element layer 110. Hybrid bonding may include dielectric-to-dielectric bonding and metal-to-metal bonding. Dielectric-to-dielectric bonding may originate from the bonding between the dielectric layer (or passivation layer) of the functional element layer 600 and the passivation layer 147 of the bottom element layer 110. Metal-to-metal bonding may originate from the bonding between the conductive feature 601 of the functional element layer 600 and the via 210 of the bottom substrate. The temperature of the bonding process may be between approximately 300°C and approximately 450°C.

[0178] In some embodiments, functional element layer 600 may be an application-specific integrated circuit (ASIC). It may include circuitry for various functions, such as buffering, repair operations, global memory refresh management, mode register setting, power network optimization, memory built-in self-test (MBIST), training, trimming, fuse, or adjustment circuitry (for one-time programming), programmable registers, and / or feature selection or configuration functions. Element layers 110, 120, 130, and 140 of the intermediate stack 100 may include circuitry, such as memory arrays, decoders, multiplexers, buffers, and / or amplifiers. In some embodiments, functional element layer 600 and intermediate stack 100 may together constitute a high bandwidth memory (HBM) system.

[0179] See Figure 1 and Figure 19 In step S19, the second carrier 520 can be removed.

[0180] See Figure 19 In some embodiments, the second carrier 520 can be removed by a polishing process. In some embodiments, the polishing material used in the polishing process can be, for example, silicon carbide, diamond, or other suitable materials.

[0181] In some embodiments, a cleaning process may be performed after the polishing process to remove the second adhesive structure 420 (if present). In some embodiments, the cleaning process may be, for example, a wet etching process.

[0182] In some other embodiments, the second carrier 520 can be removed by a debonding process. The debonding process may include thermal sliding debonding, chemical dissolution, mechanical stripping, or laser ablation.

[0183] In some embodiments, thermal slide debonding may include heating the thermoplastic adhesive layer (e.g., the second adhesive structure 420) to reduce its viscosity, thereby causing the intermediate stack 100 to slide apart. The process temperature for thermal slide debonding may be between about 150°C and about 190°C, softening the polymer to enable separation with minimal mechanical stress.

[0184] In some embodiments, chemical dissolution can rely on a solvent to dissolve the temporary bonding adhesive (e.g., the second adhesive structure 420). In some embodiments, the solvent used for chemical dissolution may include sulfuric acid, hexane, or 1-dodecene.

[0185] In some embodiments, mechanical stripping can be used to separate the second carrier 520 from the intermediate stack 100 by applying controlled physical force. Separation can be initiated using blades or an air jet and then propagated by programmable rollers to complete the de-junction process.

[0186] In some embodiments, the laser ablation debonding process may employ ultraviolet (e.g., 308 nm, 355 nm) or mid-infrared laser (radiation) to selectively degrade the light-absorbing second release layer 423. The laser energy can evaporate the second release layer 423, causing the intermediate stack 100 to separate from the second carrier 520. In some embodiments, the wavelength of the mid-infrared laser may be between about 1.12 μm and about 5 μm, or between about 1.12 μm and about 3 μm. Laser ablation processes using mid-infrared radiation are compatible with carriers made of silicon or glass and are also suitable for use with stress-compensating layers.

[0187] In some embodiments, a cleaning process may be performed after the debonding process to remove any remaining second adhesive structure 420. In some embodiments, the cleaning process may be, for example, a wet etching process.

[0188] In some other embodiments, after the debonding process, the intermediate stack 100 may not immediately undergo any adhesive removal process, and the second adhesive structure 420 may remain on the front side 140FS of the surface element layer 140. In this way, the residual second adhesive layer 421 can protect the bonding interface on the front side 140FS from contamination during subsequent process steps. This protective effect of the residual second adhesive structure 420 can also extend the allowable waiting time before bonding another element layer to the intermediate stack 100.

[0189] One aspect of this disclosure provides a semiconductor device stack, comprising: a bottom device layer, at least one intermediate device layer, and a surface device layer stacked sequentially; a bottom substrate via located in the bottom device layer, wherein a bottom surface of the bottom substrate via is coplanar with a back side of the bottom device layer; at least one intermediate substrate via located in the at least one intermediate device layer, wherein a bottom surface of the at least one intermediate substrate via is coplanar with a back side of the at least one intermediate device layer that contacts the bottom device layer; a surface substrate via located in the surface device layer, wherein a bottom surface of the surface substrate via is coplanar with a back side of the surface device layer that contacts the at least one intermediate device layer; a plurality of interlayer interconnect vias electrically connecting the bottom substrate via and the at least one intermediate device layer, and electrically connecting the surface substrate via and the at least one intermediate device layer; a first carrier contacting the back side of the bottom device layer and covering the bottom substrate via; and a second carrier covering a front side of the surface device layer.

[0190] Another aspect of this disclosure provides a semiconductor device stack, comprising: a bottom device layer, at least one intermediate device layer, and a surface device layer stacked sequentially; a bottom substrate via located in the bottom device layer, wherein a bottom surface of the bottom substrate via is coplanar with a back side of the bottom device layer; at least one intermediate substrate via located in the at least one intermediate device layer, wherein a bottom surface of the at least one intermediate substrate via is coplanar with a back side of the at least one intermediate device layer that contacts the bottom device layer; a surface substrate via located in the surface device layer, wherein a bottom surface of the surface substrate via is coplanar with a back side of the surface device layer that contacts the at least one intermediate device layer; a plurality of interlayer connection vias electrically connecting the bottom substrate via and the at least one intermediate device layer, and electrically connecting the surface substrate via and the at least one intermediate device layer; a front side of a functional element layer located on the back side of the bottom device layer; and a second carrier covering the front side of the surface device layer.

[0191] Another aspect of this disclosure provides a method for manufacturing a semiconductor device stack, comprising: providing an intermediate stack including a bottom device layer, at least one intermediate device layer and a surface device layer stacked sequentially, and a bottom substrate via located in the bottom device layer, wherein a bottom surface of the bottom substrate via is coplanar with a back side of the bottom device layer; forming a first carrier covering the back side of the bottom device layer and the bottom surface of the bottom substrate via; performing a wafer probing process through an opening in the surface device layer and filling the opening; forming a second carrier covering a front side of the surface device layer; separating the intermediate stack from the first carrier; and flipping the intermediate stack and bonding a functional device layer to the back side of the bottom device layer.

[0192] Due to the design of the semiconductor device stack 1 disclosed herein, the functional element layer 600 can be bonded to the bottom substrate via 210 under the support of the second carrier 520, thereby avoiding the induced parasitic inductance caused by the suspended (or floating) bottom substrate via 210. In this way, the performance of the semiconductor device stack 1 can be improved.

[0193] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0194] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor device stack, comprising: A bottom component layer, at least one intermediate component layer, and a surface component layer are stacked in sequence; A bottom substrate through-hole is located in the bottom component layer, and a bottom surface of the bottom substrate through-hole is coplanar with a back side of the bottom component layer; At least one intermediate substrate through-hole is located in the at least one intermediate element layer, and a bottom surface of the at least one intermediate substrate through-hole is coplanar with a back side of the at least one intermediate element layer that contacts the bottom element layer; A surface substrate via is located in the surface element layer, and a bottom surface of the surface substrate via is coplanar with a back side of the surface element layer that contacts the at least one intermediate element layer; Multiple interlayer connecting vias electrically connect the bottom substrate vias to the at least one intermediate element layer, and electrically connect the surface substrate vias to the at least one intermediate element layer; A first carrier, contacting the back side of the bottom element layer and covering the through-hole of the bottom substrate; and A second carrier covers one front side of the surface element layer.

2. The semiconductor element stack as claimed in claim 1, wherein the first carrier and the second carrier comprise the same material.

3. The semiconductor device stack as claimed in claim 1, wherein the first carrier and the second carrier comprise different materials.

4. The semiconductor device stack as claimed in claim 1, further comprising a first adhesive structure located between the bottom device layer and the first carrier.

5. The semiconductor device stack of claim 1, wherein the first carrier comprises silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, silicon nitride, silicon oxynitride, or silicon oxynitride.

6. The semiconductor device stack of claim 1, wherein the first carrier comprises silicon, glass, polymer or sapphire.

7. The semiconductor device stack of claim 4, wherein the first adhesive structure comprises: A first release layer is located between the bottom component layer and the first carrier; as well as A first adhesive layer is located between the first release layer and the bottom component layer.

8. The semiconductor device stack of claim 7, wherein the first release layer comprises aluminum, tin, or zinc.

9. The semiconductor device stack of claim 7, wherein the first release layer comprises carbon nanotubes and graphene.

10. The semiconductor device stack of claim 7, wherein the first adhesive layer comprises a polymeric adhesive material, a high-temperature thermoplastic polyimide, benzocyclobutene, an acrylic resin, or an epoxy resin.

11. The semiconductor device stack of claim 4, wherein the first adhesive structure comprises: A first release layer is located between the bottom component layer and the first carrier; A first adhesive layer is located between the first release layer and the bottom component layer; as well as A first stress compensation layer is located between the first release layer and the first carrier.

12. The semiconductor device stack of claim 11, wherein the first stress compensation layer comprises silicon oxide, silicon nitride, or a combination thereof.

13. The semiconductor device stack of claim 4, wherein the first adhesive structure comprises: A first release layer is located between the bottom component layer and the first carrier; A first adhesive layer is located between the first release layer and the bottom component layer; as well as A first protective layer is located between the first adhesive layer and the bottom component layer.

14. The semiconductor device stack of claim 13, wherein the first protective layer comprises titanium, chromium, gold or copper.

15. The semiconductor device stack of claim 4, wherein the first adhesive structure includes a first adhesive layer located in the bottom device layer between the first carriers, and the first adhesive layer includes a polymer adhesive material premixed with metal nanoparticles.

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