Wafer level packaging structure and method of manufacture

Abstract

The application provides a wafer-level packaging structure and a preparation method, which can solve the problems of low heat dissipation efficiency, significant electromagnetic crosstalk, high parasitic parameters, obvious wafer warping and insufficient yield in mass production of traditional packaging, and realize the combination of high integration, excellent heat dissipation performance and wafer-level mass production capacity. It comprises: a high-thermal-conductivity copper plate layer; a high-power chip set comprising at least one high-power chip; a silicon-based packaging layer comprising a silicon wafer, a silicon groove, a thick glue layer, a TSV silicon through hole and a TSV conductive interconnection column; a first redistribution layer; and N groups of upper packaging units, N being a natural number greater than or equal to 1, the N groups of adjacent upper packaging units being arranged in a stacked manner in the height direction, and each upper packaging unit comprising a plastic packaging layer, at least one small-power chip and a redistribution layer, the redistribution layer of the upper packaging unit located on the top layer being a top redistribution layer, and a plurality of tin balls being arranged on the top redistribution layer.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor device packaging, specifically to a wafer-level packaging structure. The invention also provides a method for fabricating the wafer-level system-level packaging structure. Background Technology

[0002] With the large-scale deployment of third-generation power semiconductor devices such as SiC and GaN in new energy vehicles, photovoltaic inverters, and industrial power supplies, system-in-package (SiP) technology continues to evolve towards higher frequencies, higher power densities, and miniaturization. However, current highly integrated multilayer SiP technologies still face numerous technical bottlenecks in practical applications, making it difficult to meet the performance and mass production requirements of third-generation semiconductors. These bottlenecks are specifically manifested in the following aspects: 1. Limited heat dissipation capacity. In traditional system-in-package (SoC) structures, the power chip is entirely encapsulated in epoxy molding compound. The heat generated by the chip must be conducted outward through the molding compound layer, which is more than 200μm thick. The steady-state thermal resistance of the junction is generally 2-3℃ / W, which is insufficient to meet the heat dissipation requirements of high-power devices. Currently, the industry often optimizes heat dissipation by increasing the chip spacing and adding external heat dissipation structures. However, such solutions directly increase the package size, which contradicts the trend of high integration. 2. Poor signal integrity and electromagnetic compatibility (EMC) performance. Traditional power SiPs often employ a coplanar layout of power chips and small-signal control chips, with no physical isolation between the two types of chips. High-frequency switching noise generated during the operation of the power chip can easily couple to the small-signal control chip through electromagnetic radiation and the common ground plane, causing control signal distortion. In addition, the electrical interconnection between chips relies on the planar redistribution layer (RDL), with interconnection path lengths typically ranging from hundreds of micrometers to several millimeters. This results in high parasitic inductance of the lines, leading to high-frequency switching losses and failing to fully unleash the high-frequency operating potential of third-generation power semiconductors. 3. Significant wafer warpage, high complexity of multilayer integration processes, and low mass production yield. Traditional multilayer packaging often employs a one-time thick-layer injection molding process, resulting in wafer warpage exceeding 1mm after processing. This easily induces subsequent photolithography misalignment, solder ball cracking, and other failures, leading to a significant drop in product yield. Existing vertical stacking solutions largely rely on complex TSV (Through Silicon Via) processes, which suffer from long process chains and high equipment investment costs. Furthermore, the overall rigidity of pure plastic packaging architecture is insufficient, further exacerbating wafer warpage and making it difficult to support large-scale wafer-level mass production. Summary of the Invention

[0003] To address the aforementioned problems, this invention provides a wafer-level packaging structure that can solve the issues of low heat dissipation efficiency, significant electromagnetic crosstalk, high parasitic parameters, obvious wafer warpage, and insufficient mass production yield in traditional packaging, achieving a balance between high integration, excellent heat dissipation performance, and wafer-level mass production capabilities.

[0004] A wafer-level packaging structure, characterized in that it comprises: High thermal conductivity copper plate layer; A high-power chipset, which includes at least one high-power chip; A silicon-based encapsulation layer, comprising a silicon wafer, a silicon trench, a thick adhesive layer, a TSV through-silicon via, and a TSV conductive interconnect pillar; First wiring layer; And N groups of upper packaging units, where N is a natural number greater than or equal to 1. The N groups of adjacent upper packaging units are stacked in the height direction, and each upper packaging unit includes a molding layer, at least one low-power chip and a redistribution layer. The redistribution layer of the upper packaging unit located at the top is the top redistribution layer, and a number of solder balls are provided on the top redistribution layer. The high thermal conductivity copper plate layer, silicon-based packaging layer, first redistribution layer, and N sets of upper packaging units are stacked sequentially from bottom to top. The lower surface of the silicon wafer is etched with silicon grooves extending upwards. The number and shape of the silicon grooves correspond to the number and shape of the high-power chips in the high-power chipset. Each high-power chip is embedded in the corresponding silicon groove. The active surface of each high-power chip is attached to the bottom of the corresponding silicon groove through an adhesive layer. The non-active surface of each high-power chip faces outwards and is connected to the high thermal conductivity copper plate layer. A thick adhesive layer formed by polymer dry film curing is pressed onto the lower surface of the silicon wafer. The thick adhesive layer fills the gap between the chip sidewall and the silicon groove. A through-hole TSV silicon via is opened in the silicon-based packaging layer. The via is filled with TSV conductive interconnect pillars. The lower end of the TSV conductive interconnect pillar is electrically connected to the pad of the active surface of the high-power chip, and the upper end of the TSV conductive interconnect pillar is electrically connected to the first redistribution layer.

[0005] Its further features are: When the thickness of the high-power chips is inconsistent, the thickness of the silicon wafer is higher than the thickness of the highest high-power chip. The lower surface of the silicon wafer is provided with corresponding silicon grooves of different heights and depths. The silicon wafer is also provided with corresponding TSV through-silicon vias. The upper region of the silicon wafer corresponding to each group of high-power chips is provided with corresponding TSV through-silicon vias. The TSV through-silicon vias are filled to form corresponding TSV conductive interconnect pillars. The high-power chip is a power or radio frequency semiconductor chip that performs the functions of power transmission and power conversion. It is suitable for high voltage, high current and high frequency operating conditions. The high-power chip includes power semiconductor chips such as SiC and GaN transistors and radio frequency semiconductor chips. The first wiring layer consists of multiple layers of alternately stacked metal circuit layers and insulating passivation layers, used to realize the lateral transmission of electrical signals and power of the power chip and the vertical conduction between layers; The non-active surface of the small signal chip in each upper packaging unit is bonded to the lower redistribution layer, and the active surface of the small signal chip is arranged facing upwards. The small signal chip is a digital or analog semiconductor chip that performs signal acquisition, logic operation, and data storage functions; Each upper-layer encapsulation unit also has a TMV conductive interconnect pillar on its plastic encapsulation layer. The TMV conductive interconnect pillar transmits the electrical signals from the high-power chip to the first redistribution layer layer by layer to the upper redistribution layer until they reach the top redistribution layer.

[0006] A method for fabricating a wafer-level packaging structure is characterized by: after fabricating a high thermal conductivity copper plate layer that completely covers the fan-out structure, encapsulating the corresponding high-power chip in the silicon recess of the silicon-based packaging layer, then mounting the non-active side of the high-power chip onto the high thermal conductivity copper plate layer, then obtaining TSV through-silicon vias from top to bottom on the surface of the silicon wafer, then obtaining corresponding TSV conductive interconnects within the TSV through-silicon vias, then fabricating a first redistribution layer on the top surface of the silicon-based packaging layer to complete the signal fan-out of the high-power chip, and sequentially completing the mounting of low-power chips, molding of the molding layer, processing of the corresponding TSV conductive interconnects in each of the N groups of upper packaging units, and processing of the redistribution layer, then performing the back-end packaging process on the top redistribution layer, processing to obtain solder balls, and then performing wafer-level dicing to obtain a single independent finished packaged device.

[0007] Its further features are: It includes the following steps: S1 substrate preparation: A glass wafer is selected as a temporary carrier, and a high thermal conductivity copper plate layer is laid on the entire surface of the temporary carrier through a temporary bonding adhesive layer. S2 silicon wafer patterning: A whole silicon wafer 300 is taken, which has an upper surface and a lower surface arranged opposite to each other. On the lower surface of the silicon wafer, a photolithography + deep silicon etching process is used to form a corresponding number and shape of silicon grooves extending towards the upper surface of the silicon wafer; The S3 high-power chip is fixed by mounting each high-power chip individually inside the corresponding silicon groove, so that the active side of the chip is tightly attached to the bottom of the groove, and the non-active side of the chip is facing the lower surface. A filling gap is reserved between the sidewall of the chip and the sidewall of the silicon groove. The overall structure is then subjected to high-temperature curing to complete the fixing of the high-power chip. S4 gap filling uses a vacuum dry film lamination process to laminate a polymer dry film 502 onto the entire lower surface of a silicon wafer. After curing, a thick adhesive layer is formed. The thick adhesive layer fully fills the gap between the chip sidewall and the silicon recess and covers the four sides of the high-power chip. S5 Silicon wafer alignment and bonding: The silicon wafer that has completed the above process is flipped over as a whole, and the silicon wafer with high power chip is aligned and permanently bonded to a temporary carrier plate with a high thermal conductivity copper plate layer 210 through a high thermal conductivity permanent bonding adhesive layer 301. S6 TSV fabrication involves thinning the silicon wafer to a suitable thickness using a grinding and polishing process; then, using laser drilling or deep reactive ion etching, processing is performed from the top surface of the silicon wafer towards the silicon groove to fabricate through-hole TSVs at the locations of the active surface pads corresponding to the high-power chip; an insulating layer is deposited on the inner wall of the TSVs, followed by physical vapor deposition, electroplating, and etching to complete the metal filling of the TSVs, forming TSV conductive interconnect pillars. The lower end of the TSV conductive interconnect pillars is electrically connected to the active surface pads of the corresponding high-power chip, and the upper end of the TSV conductive interconnect pillars extends to the top surface of the silicon wafer, where it is electrically connected to the subsequently fabricated first interconnect layer 600. S7 First interconnect layer fabrication: The first interconnect layer 600 is fabricated on the upper surface of the silicon wafer and the upper end surface of the TSV conductive interconnect pillar using a wafer-level whole-wafer processing technology. The S8 small signal chip mounting process uses a high-precision surface mount technology to mount the small signal chip of the first upper packaging unit to a preset position on the top surface of the first rewiring layer, with the active side of each small signal chip facing upwards. S9 molding layer preparation and planarization adopts wafer-level molding process, using wafer-level epoxy molding compound to encapsulate all small signal chips. The molding compound fully fills the gaps around the chips and forms a molding layer after high temperature curing. S10 TMV molding via fabrication: At the preset conductive points corresponding to the first redistribution layer in the molding layer, TMV molding vias are formed by ultraviolet laser drilling. An insulating layer and a seed layer are deposited sequentially on the inner wall of the via. The via is then filled with metal by electroplating to form a TMV conductive interconnect pillar. The lower end of the TMV conductive interconnect pillar is electrically connected to the first redistribution layer, and the upper end is exposed on the top surface of the molding layer. The S11 redistribution layer is fabricated using a wafer-level whole-wafer process on the flattened top surface of the molding layer and the TMV conductive interconnect pillars. The redistribution layer completes the system-level signal interconnection and power distribution of all high-power chips and small-signal chips. As needed, prepare the corresponding upper-layer packaging units layer by layer, repeat steps S8 to S11 until the preparation of all upper-layer packaging units is completed. The redistribution layer of the topmost upper-layer packaging unit is the top redistribution layer. The S12 back-end packaging process completes the fabrication of the insulating passivation layer of the top redistribution layer and the metal layer under the bumps; then the entire wafer is flipped over, the bottom temporary carrier is peeled off, and the residual temporary bonding adhesive layer on the surface is removed; a wafer-level ball-planting process is performed in the metal layer area under the bumps to form conductive solder balls; finally, a wafer dicing process is used to dice the wafers to obtain individual finished packaged devices.

[0008] Its further characteristic is: In step S1, the thickness of the high thermal conductivity copper plate layer is 100μm to 250μm, and the material is oxygen-free copper or copper-molybdenum alloy. In step S2, the size of the silicon groove is slightly larger than the corresponding chip. Relative to the chip outline, the silicon groove expands outward by 20-50 μm on one side in the horizontal direction and by 5-15 μm on one side in the depth direction. In step S3, the thickness of the high-power chip is preferably 150μm to 350μm, and the thickness difference between different high-power chips is no greater than 80μm. In step S5, the thickness of the high thermal conductivity permanent bonding adhesive layer is 1μm to 5μm, and the material is silver sintered adhesive or high thermal conductivity epoxy adhesive. In step S8, the functional types of the small signal chips can be different, and the thickness difference between the chips is no greater than 10 μm; When multi-layer stacked packaging is used, the overall total thickness is controlled within 2.0mm, and the cumulative total thickness of all molding layers is controlled within 1.5mm; this thickness is combined with the rigid support of the bottom high thermal conductivity copper plate.

[0009] This invention effectively solves a series of technical problems in traditional system-in-package, such as insufficient heat dissipation, significant electromagnetic crosstalk between power and small signal chips, high parasitic parameters of interconnect lines, obvious wafer warpage, complex multilayer integration process, and low mass production yield. This invention optimizes the heat dissipation path by directly attaching a high thermal conductivity copper plate to the back of the chip, which can reduce the steady-state thermal resistance of the package junction to 0.8-1.2℃ / W and significantly reduce the chip's operating temperature rise, thus meeting the application requirements of 200V / 10A level third-generation semiconductor devices. The vertical layered layout achieves physical isolation between power circuits and signal circuits. Combined with the TSV and TMV combined vertical interconnect structure, the interconnect distance between chips can be shortened to 100-200μm, parasitic inductance and high-frequency switching losses are significantly reduced, and signal integrity and EMC performance are greatly improved. The high thermal conductivity copper plate and silicon-based packaging layer form a dual rigid support system, which can effectively control the warpage of the entire wafer. Combined with mature silicon-based embedded technology, TSV technology, and wafer-level molding technology, the wafer-level mass production yield can reach over 99%. The overall architecture can be expanded upwards to a multi-layer chip stacking structure, reducing the package footprint while improving system integration. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a specific embodiment of the present invention, and also a schematic diagram of step S12 of the preparation method; Figure 2 This is a schematic diagram of step S1 of the preparation method of the present invention; Figure 3 This is a schematic diagram of step S2 in the preparation method of the present invention: Figure 4 This is a schematic diagram of step S3 in the preparation method of the present invention; Figure 5 This is a schematic diagram of step S4 in the preparation method of the present invention; Figure 6 This is a schematic diagram of step S5 in the preparation method of the present invention; Figure 7 This is a schematic diagram of step S6 in the preparation method of the present invention; Figure 8 This is a schematic diagram of step S7 in the preparation method of the present invention; Figure 9 This is a schematic diagram of step S8 in the preparation method of the present invention; Figure 10 This is a schematic diagram of step S9 in the preparation method of the present invention; Figure 11 This is a schematic diagram of step S10 of the preparation method of the present invention; Figure 12 This is a schematic diagram of step S11 of the preparation method of the present invention; Figure 13 This is a schematic diagram of the three-layer stacked extended structure of the present invention. Detailed Implementation

[0011] A wafer-level packaging structure, see Figure 1 and Figure 13 It includes a high thermal conductivity copper plate layer 210, a high-power chipset, a silicon-based packaging layer, a first redistribution layer 600, and N upper packaging units (N is a natural number greater than or equal to 1). A high-power chipset includes at least one high-power chip; The silicon-based encapsulation layer includes a silicon wafer 300, a silicon recess 310, a thick adhesive layer 502, a TSV through-silicon via, and a TSV conductive interconnect pillar 510. N groups of adjacent upper packaging units are stacked in the height direction, and each upper packaging unit includes a molding layer, at least one low-power chip and a redistribution layer. The redistribution layer of the upper packaging unit located at the top is the top redistribution layer, and a number of solder balls 1000 are provided on the top redistribution layer. A high thermal conductivity copper plate layer 210, a silicon-based encapsulation layer, a first redistribution layer 600, and N sets of upper-layer encapsulation units are stacked sequentially from bottom to top. The lower surface of the silicon wafer 300 is etched with silicon grooves 310 extending upwards. The number and shape of the silicon grooves 310 correspond to the number and shape of the high-power chips in the high-power chipset. Each high-power chip is embedded inside its corresponding silicon groove 310. The active surface of each high-power chip is bonded to the bottom of its corresponding silicon groove 310 via an adhesive layer. The non-active side is positioned outward and docked with the high thermal conductivity copper plate layer 210; a thick adhesive layer formed by polymer dry film curing is pressed onto the lower surface of the silicon wafer 300, and the thick adhesive layer also fills the gap between the chip sidewall and the silicon groove; a through-type TSV silicon via is opened in the silicon-based packaging layer, and the via is filled with TSV conductive interconnect pillars 510. The lower end of the TSV conductive interconnect pillar 510 is electrically connected to the pad of the active side of the high-power chip, and the upper end of the TSV conductive interconnect pillar 510 is electrically connected to the first redistribution layer 600.

[0012] In practice, high-power chips are power or radio frequency semiconductor chips that perform power transmission and power conversion functions and are suitable for high voltage, high current and high frequency operating conditions. High-power chips include power semiconductor chips such as SiC and GaN transistors and radio frequency semiconductor chips.

[0013] The first wiring layer 600 consists of multiple layers of alternately stacked metal circuit layers and insulating passivation layers, used to realize the lateral transmission of electrical signals and power of the power chip as well as the vertical conduction between layers. The non-active surface of the small signal chip in each upper packaging unit is bonded to the lower redistribution layer, and the active surface of the small signal chip is set upwards. Small signal chips are digital or analog semiconductor chips that perform signal acquisition, logic operations, and data storage functions.

[0014] Each upper-layer encapsulation unit also has a TMV conductive interconnect post 810. The TMV conductive interconnect post 810 transmits the electrical signals from the high-power chip to the first rewiring layer 600 layer by layer to the upper rewiring layer until they reach the top rewiring layer.

[0015] In a specific embodiment, N is set to 1, meaning that the wafer-level packaging structure includes only one upper packaging unit. This upper packaging unit includes two small signal chips, a second molding layer 800, and a top redistribution layer 900. The two small signal chips are specifically small signal chip a710 and small signal chip b720. The high-power chipset includes two high-power chips, namely high-power chip a410 and high-power chip b420.

[0016] The specific implementation method for fabricating the wafer-level system-in-package structure is as follows: see Figures 1-12 : S1 substrate preparation: a glass wafer is selected as a temporary carrier 100, and a high-temperature resistant temporary bonding adhesive layer 110 is coated on the surface of the temporary carrier 100; a high thermal conductivity copper plate layer 210 is laid on the entire surface of the temporary bonding adhesive layer; the thickness of the high thermal conductivity copper plate layer 210 is 100μm~250μm, and the material is oxygen-free copper or copper-molybdenum alloy. S2 silicon wafer patterning: A whole silicon wafer 300 is taken, which has a lower surface and an upper surface that are positioned opposite each other. On the lower surface of the silicon wafer, a silicon groove A 310 and a silicon groove B 320 extending towards the upper surface of the silicon wafer are formed by photolithography and deep silicon etching processes. The shapes of silicon groove A 310 and silicon groove B 320 are adapted to the shapes of high-power chip a 410 and high-power chip b 420, respectively. The size of the silicon groove is slightly larger than the corresponding chip. Relative to the chip shape, the silicon groove expands outward by 20 to 50 μm on one side in the horizontal direction and 5 to 15 μm on one side in the depth direction. The S3 high-power chip is fixed using a polymer adhesive film 501. Individual high-power chips a 410 and b 420 are individually mounted inside their corresponding silicon recesses, ensuring the active surfaces of the chips are tightly fitted to the bottom of the recess, with the non-active surfaces facing upwards. A pre-filled gap is left between the chip sidewalls and the silicon recess sidewalls. The entire structure undergoes high-temperature curing to fully cure the polymer adhesive film 501, thus completing the fixation of the high-power chips. The thickness of the high-power chip is 150μm to 350μm, and the thickness difference between different high-power chips is no more than 80μm; the polymer adhesive film 501 adopts DAF film, NCF film, or other non-conductive high-temperature resistant adhesive film with similar properties. S4 gap filling employs a vacuum dry film lamination process, where a polymer dry film 502 is fully laminated onto the lower surface of silicon wafer 300. After curing, a thick adhesive layer is formed. This thick adhesive layer fully fills the gaps between the chip sidewalls and silicon recesses A310 and B320, and covers the four sides of the high-power chip. During operation, the dry film lamination thickness is controlled to ensure that only a small amount of adhesive overflows from the silicon recesses after filling. After the thick adhesive layer is cured in segments at high temperature, a chemical mechanical polishing (CMP) process is used to grind and flatten the excess thick adhesive layer on the lower surface of the silicon wafer. This ensures that the non-active surfaces of the high-power chip are exposed, while also maintaining the flatness of the lower surface of the silicon wafer to meet the processing requirements of subsequent processes. S5 silicon wafer alignment and bonding involves flipping the silicon wafer that has completed the aforementioned process, and then using a high thermal conductivity permanent bonding adhesive layer 301 to align and permanently bond the silicon wafer with the high power chip to a temporary carrier plate with a high thermal conductivity copper plate layer 210. The thickness of the high thermal conductivity permanent bonding adhesive layer 301 is 1μm to 5μm, and the material is silver sintered adhesive or high thermal conductivity epoxy adhesive. S6 TSV fabrication involves thinning the silicon wafer to a suitable thickness using a grinding and polishing process. Then, laser drilling or deep reactive ion etching (DRIE) is used to process the silicon wafer 300 from its upper surface towards the silicon groove, creating through-hole TSVs at the locations of the active surface pads of the high-power chip on the silicon wafer 300. An insulating layer of silicon dioxide with a thickness of 0.5 μm to 2 μm is deposited on the inner wall of the TSV. Subsequently, physical vapor deposition (PVD), electroplating, and etching processes are used to complete the metal filling of the TSV, forming the TSV conductive interconnect pillars 510. The lower end of the TSV conductive interconnect pillar 510 is electrically connected to the active surface pads of high-power chip a 410 and high-power chip b 420, and the upper end extends to the upper surface of silicon wafer 300 and is electrically connected to the first redistribution layer 600 subsequently prepared; if there are local protrusions on the surface, a fine grinding process can be used to complete the surface flattening of the silicon-based encapsulation layer. The S7 first wiring layer is fabricated on the upper surface of the silicon wafer and the upper end surface of the TSV conductive interconnect pillars using a wafer-level whole-wafer processing technology to obtain the first wiring layer 600; the first wiring layer 600 is used to realize the lateral signal interconnection of high-power chips as well as the interlayer power and signal conduction. The first redistribution layer 600 includes at least one alternating layer of metal circuitry and an insulating passivation layer. The metal circuitry layer is made of copper and has a single layer thickness of 1 μm to 5 μm. S8 small signal chip mounting uses a high-precision surface mount technology to mount small signal chip a 710 and small signal chip b720 at preset positions on the top surface of the first wiring layer 600, with the active side of the chip facing upwards. The functional types of small signal chip a 710 and small signal chip b 720 may be different, and the thickness difference between each chip shall not exceed 10μm; The S9 molding layer is prepared and planarized using a wafer-level molding process. Wafer-level epoxy molding compound is used to encapsulate all small signal chips. The molding compound fully fills the gaps around the chips. After high-temperature curing, molding layer 800 is formed. After curing, chemical mechanical polishing is used to planarize the top surface of molding layer 800. The vertical distance between the top surface of molding layer 800 and the active surface pads of the small signal chips is controlled to be 10μm to 20μm to avoid damage to the active area of ​​the chip during polishing. S10 TMV molding via fabrication: At the preset conductive points corresponding to the first redistribution layer 600 in the molding layer 800, TMV molding vias are formed using ultraviolet laser drilling. An insulating layer and a seed layer are sequentially deposited on the inner wall of the via. The via is then filled with metal by electroplating to form a TMV conductive interconnect pillar 810. The lower end of the TMV conductive interconnect pillar 810 is electrically connected to the first redistribution layer 600, and the upper end is exposed on the top surface of the molding layer. If there is overflow or unevenness on the surface, fine chemical mechanical polishing can be added to level it, ensuring that the overall flatness of the top surface is ≤2μm. S11 Top redistribution layer fabrication: On the flattened top surface of the molding layer 800 and the TMV conductive interconnect pillar 810, the top redistribution layer 900 is fabricated using a wafer-level whole-wafer process. The top redistribution layer 900 completes the system-level signal interconnection and power distribution of all high-power chips and small-signal chips, while realizing the external signal lead-out and pad fan-out of the package structure. The top redistribution layer 900 includes at least one alternating layer of metal circuitry and insulating passivation layer. The metal layer is made of copper and has a single layer thickness of 2μm to 10μm. The insulating passivation layer is made of polyimide (PI) or benzocyclobutene (BCB). In the S12 back-end process, after preparing the under-bump metal layer (UBM) at the preset pad position of the top redistribution layer 900, the entire wafer is flipped over, and the temporary substrate 100 at the bottom is peeled off by mechanical debonding or laser debonding process. The temporary bonding adhesive layer 110 remaining on the surface is removed by cleaning with organic solvent, and the back side of the high thermal conductivity copper plate layer 210 is fully exposed.

[0017] A wafer-level ball-planting process is performed in the metal layer area under the bumps to form 1000 conductive solder balls. The solder balls are made of SAC305 lead-free solder and have a diameter of 150μm to 250μm. Finally, a wafer dicing process is used to dic the balls to obtain individual finished packaged devices.

[0018] This invention is not limited to the above-mentioned two-layer chip packaging structure. It can be extended to a three-layer or higher multi-layer stacked structure according to system integration requirements to achieve higher-density system-level integration. The specific fabrication process is as follows: After completing the fabrication of the current top-layer redistribution layer, the mounting, molding, via, and redistribution processes of steps S8 to S11 are repeated to sequentially stack multiple sets of small-signal chip packaging units; after all stacked units are processed, step S12 is then uniformly executed to complete the downstream packaging process.

[0019] The overall thickness of the multi-layer stacked structure is controlled within 2.0mm, and the cumulative total thickness of all molding layers does not exceed 1.5mm. Relying on the composite rigid support structure formed by the bottom high thermal conductivity copper plate layer and the silicon-based encapsulation layer, the process warpage of the entire wafer can be controlled within 150μm, effectively ensuring the processing accuracy and product yield of subsequent precision processes such as wafer-level photolithography, alignment, and ball placement.

[0020] The innovative aspects of this invention are as follows: 1. Vertical Layered Isolation Architecture: High-power chips are placed in the bottom silicon-based embedded area, while small-signal chips are vertically stacked in the upper plastic-encapsulated area. Physical isolation between the two types of chips is achieved through the silicon wafer and the plastic encapsulation layer, effectively suppressing electromagnetic crosstalk from high-frequency noise of the power chips to the small-signal chips. Simultaneously, a combination of TSV and TMV vertical vias is used for inter-layer interconnection, significantly shortening the interconnection path length between chips, reducing parasitic inductance, and improving signal integrity and EMC performance under high-frequency operating conditions.

[0021] 2. High-efficiency composite heat dissipation structure: The non-active surfaces of high-power chips have no additional dielectric barrier; a high thermal conductivity copper plate layer is directly bonded to the entire surface, constructing a short-path, low-resistance heat dissipation channel, significantly improving the overall heat dissipation capacity of the package. The silicon wafer adopts an embedded structure with slotted placement and top dry film filling, which reduces the difficulty of deep etching of the silicon wafer and simplifies the production process.

[0022] 3. Dual rigidity anti-warping structure: The bottom high thermal conductivity copper plate and the middle silicon wafer form a composite support structure with two layers of inorganic rigid materials, which greatly improves the overall rigidity of the package. It can effectively suppress the warping deformation of the whole wafer in the whole process, ensure the processing accuracy of wafer-level photolithography, ball placement, alignment and other precision processes, and improve the mass production yield.

[0023] 4. Combined vertical interconnect process: The bottom silicon wafer uses the mature TSV (Through Silicon Via) process to achieve high-density vertical wiring, while the upper plastic encapsulation area uses TMV (Through Silicon Motion) molding vias to achieve interlayer interconnection. The two processes complement each other, combining high wiring density with excellent process compatibility.

[0024] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0025] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A wafer-level packaging structure, characterized in that, It includes: High thermal conductivity copper plate layer; A high-power chipset, which includes at least one high-power chip; A silicon-based encapsulation layer, comprising a silicon wafer, a silicon trench, a thick adhesive layer, a TSV through-silicon via, and a TSV conductive interconnect pillar; First wiring layer; And N groups of upper packaging units, where N is a natural number greater than or equal to 1. The N groups of adjacent upper packaging units are stacked in the height direction, and each upper packaging unit includes a molding layer, at least one low-power chip and a redistribution layer. The redistribution layer of the upper packaging unit located at the top is the top redistribution layer, and a number of solder balls are provided on the top redistribution layer. The high thermal conductivity copper plate layer, silicon-based packaging layer, first redistribution layer, and N sets of upper packaging units are stacked sequentially from bottom to top. The lower surface of the silicon wafer is etched with silicon grooves extending upwards. The number and shape of the silicon grooves correspond to the number and shape of the high-power chips in the high-power chipset. Each high-power chip is embedded in the corresponding silicon groove. The active surface of each high-power chip is attached to the bottom of the corresponding silicon groove through an adhesive layer. The non-active surface of each high-power chip faces outwards and is connected to the high thermal conductivity copper plate layer. A thick adhesive layer formed by polymer dry film curing is pressed onto the lower surface of the silicon wafer. The thick adhesive layer fills the gap between the chip sidewall and the silicon groove. A through-hole TSV silicon via is opened in the silicon-based packaging layer. The via is filled with TSV conductive interconnect pillars. The lower end of the TSV conductive interconnect pillar is electrically connected to the pad of the active surface of the high-power chip, and the upper end of the TSV conductive interconnect pillar is electrically connected to the first redistribution layer.

2. The wafer-level packaging structure according to claim 1, characterized in that: When the thickness of the high-power chips is inconsistent, the thickness of the silicon wafer is higher than that of the highest high-power chip. The lower surface of the silicon wafer has corresponding silicon grooves with different heights and depths. The silicon wafer also has corresponding TSV vias. The upper region of the silicon wafer corresponding to each group of high-power chips has corresponding TSV vias. The TSV vias are filled to form corresponding TSV conductive interconnect pillars.

3. The wafer-level packaging structure according to claim 1, characterized in that: The high-power chip is a power or radio frequency semiconductor chip that performs power transmission and power conversion functions and is suitable for high voltage, high current and high frequency operating conditions. The high-power chip includes power semiconductor chips such as SiC and GaN transistors and radio frequency semiconductor chips.

4. The wafer-level packaging structure according to claim 1, characterized in that: The first wiring layer consists of multiple layers of alternately stacked metal circuit layers and insulating passivation layers, used to realize the lateral transmission of electrical signals and power of the power chip as well as the vertical conduction between layers.

5. The wafer-level packaging structure according to claim 1, characterized in that: The non-active surface of the small signal chip in each upper packaging unit is bonded to the lower redistribution layer, and the active surface of the small signal chip is arranged facing upwards. The small signal chip is a digital or analog semiconductor chip that performs signal acquisition, logic operation, and data storage functions.

6. The wafer-level packaging structure according to claim 1, characterized in that: Each upper-layer encapsulation unit also has a TMV conductive interconnect pillar on its plastic encapsulation layer. The TMV conductive interconnect pillar transmits the electrical signals from the high-power chip to the first redistribution layer layer by layer to the upper redistribution layer until they reach the top redistribution layer.

7. A method for fabricating a wafer-level packaging structure, used to fabricate a wafer-level packaging structure as described in any one of claims 1 to 6, characterized in that: After fabricating a high thermal conductivity copper plate layer that completely covers the fan-out structure, the corresponding high-power chip is packaged in the silicon recess of the silicon-based packaging layer. Then, the non-active side of the high-power chip is mounted onto the high thermal conductivity copper plate layer. Next, TSV through-silicon vias are obtained from top to bottom on the surface of the silicon wafer. Then, corresponding TSV conductive interconnects are obtained in the TSV through-silicon vias. Then, the first redistribution layer is fabricated on the top surface of the silicon-based packaging layer to complete the signal fan-out of the high-power chip. The low-power chip mounting, molding, corresponding TMV conductive interconnects and redistribution layer processing are completed in each of the N upper packaging units in sequence. After that, the top redistribution layer undergoes the back-end packaging process, and after obtaining solder balls, wafer-level dicing is performed to obtain a single independent finished packaged device.

8. The method for fabricating a wafer-level packaging structure according to claim 7, characterized in that, It includes the following steps: S1 substrate preparation: A glass wafer is selected as a temporary carrier, and a high thermal conductivity copper plate layer is laid on the entire surface of the temporary carrier through a temporary bonding adhesive layer. S2 silicon wafer patterning: A whole silicon wafer 300 is taken, which has an upper surface and a lower surface arranged opposite to each other. On the lower surface of the silicon wafer, a photolithography + deep silicon etching process is used to form a corresponding number and shape of silicon grooves extending towards the upper surface of the silicon wafer; The S3 high-power chip is fixed by mounting each high-power chip individually inside the corresponding silicon groove, so that the active side of the chip is tightly attached to the bottom of the groove, and the non-active side of the chip is facing the lower surface. A filling gap is reserved between the sidewall of the chip and the sidewall of the silicon groove. The overall structure is then subjected to high-temperature curing to complete the fixing of the high-power chip. S4 gap filling uses a vacuum dry film lamination process to laminate a polymer dry film 502 onto the entire lower surface of a silicon wafer, which is then cured to form a thick adhesive layer. The thick adhesive layer fully fills the gap between the chip sidewall and the silicon recess, and covers the four sides of the high-power chip; S5 Silicon wafer alignment and bonding: The silicon wafer that has completed the above process is flipped over as a whole, and the silicon wafer with high power chip is aligned and permanently bonded to a temporary carrier plate with a high thermal conductivity copper plate layer 210 through a high thermal conductivity permanent bonding adhesive layer 301. S6 TSV fabrication involves thinning the silicon wafer to a suitable thickness using a grinding and polishing process; then, using laser drilling or deep reactive ion etching, processing is performed from the top surface of the silicon wafer towards the silicon groove to fabricate through-hole TSVs at the locations of the active surface pads corresponding to the high-power chip; an insulating layer is deposited on the inner wall of the TSVs, followed by physical vapor deposition, electroplating, and etching to complete the metal filling of the TSVs, forming TSV conductive interconnect pillars. The lower end of the TSV conductive interconnect pillars is electrically connected to the active surface pads of the corresponding high-power chip, and the upper end of the TSV conductive interconnect pillars extends to the top surface of the silicon wafer, where it is electrically connected to the subsequently fabricated first interconnect layer 600. S7 First interconnect layer fabrication: The first interconnect layer 600 is fabricated on the upper surface of the silicon wafer and the upper end surface of the TSV conductive interconnect pillar using a wafer-level whole-wafer processing technology. The S8 small signal chip mounting process uses a high-precision surface mount technology to mount the small signal chip of the first upper packaging unit to a preset position on the top surface of the first rewiring layer, with the active side of each small signal chip facing upwards. S9 molding layer preparation and planarization adopts wafer-level molding process, using wafer-level epoxy molding compound to encapsulate all small signal chips. The molding compound fully fills the gaps around the chips and forms a molding layer after high temperature curing. S10 TMV molding via fabrication: At the preset conductive points corresponding to the first redistribution layer in the molding layer, TMV molding vias are formed by ultraviolet laser drilling. An insulating layer and a seed layer are deposited sequentially on the inner wall of the via. The via is then filled with metal by electroplating to form a TMV conductive interconnect pillar. The lower end of the TMV conductive interconnect pillar is electrically connected to the first redistribution layer, and the upper end is exposed on the top surface of the molding layer. The S11 redistribution layer is fabricated using a wafer-level whole-wafer process on the flattened top surface of the molding layer and the TMV conductive interconnect pillars. The redistribution layer completes the system-level signal interconnection and power distribution of all high-power chips and small-signal chips. As needed, prepare the corresponding upper-layer packaging units layer by layer, repeat steps S8 to S11 until the preparation of all upper-layer packaging units is completed. The redistribution layer of the topmost upper-layer packaging unit is the top redistribution layer. The S12 back-end packaging process completes the fabrication of the insulating passivation layer of the top redistribution layer and the metal layer under the bumps; then the entire wafer is flipped over, the bottom temporary carrier is peeled off, and the residual temporary bonding adhesive layer on the surface is removed. A wafer-level ball-forming process is performed in the metal layer region under the bumps to form conductive solder balls; finally, a wafer dicing process is used to dic the wafers to obtain individual finished packaged devices.

9. The method for fabricating a wafer-level packaging structure according to claim 8, characterized in that: In step S1, the thickness of the high thermal conductivity copper plate layer is 100μm to 250μm, and the material is oxygen-free copper or copper-molybdenum alloy.

10. The method for fabricating a wafer-level packaging structure according to claim 8, characterized in that: When multi-layer stacked packaging is used, the overall total thickness is controlled within 2.0mm, and the cumulative total thickness of all molding layers is controlled within 1.5mm; this thickness is combined with the rigid support of the bottom high thermal conductivity copper plate.

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