Reinforcement components and semiconductor packages including reinforcement components

Abstract

A reinforcement and a semiconductor package including the reinforcement. The semiconductor package includes: a substrate including a plurality of pads; a semiconductor chip structure attached to the substrate via a plurality of interconnect structures and electrically connected to the plurality of pads; and a reinforcement attached to the substrate and including a plurality of capacitors, the plurality of capacitors including first electrodes and second electrodes connected to a plurality of bonding wires. The height of the reinforcement is equal to the height of the semiconductor chip structure.

Description

Technical Field

[0001] This disclosure relates to a reinforcement and a semiconductor package including the reinforcement. Background Technology

[0002] As semiconductor chips become more high-performance, their frequencies may increase, generating more noise. Furthermore, with increased noise, the power loss within the semiconductor chip may also increase.

[0003] In addition, semiconductor packages, including semiconductor chips, are manufactured with a very thin thickness, making them very fragile to external physical stresses, such as warping. Summary of the Invention

[0004] This disclosure relates to a reinforcement and a semiconductor package including said reinforcement.

[0005] Some implementations involve reinforcements including capacitors and semiconductor packages including said reinforcements.

[0006] Some implementations relate to reinforcements for optimizing semiconductor package dimensions and semiconductor packages including said reinforcements.

[0007] In some embodiments, a semiconductor package includes: a substrate including a plurality of pads; a semiconductor chip structure attached to the substrate via a plurality of interconnect structures and electrically connected to the plurality of pads; and a reinforcement attached to the substrate and including a plurality of capacitors, the plurality of capacitors including a first electrode and a second electrode connected to a plurality of bonding wires, wherein the height of the reinforcement is equal to the height of the semiconductor chip structure.

[0008] In some embodiments, a semiconductor package includes: a substrate; a semiconductor chip structure attached to the substrate via a plurality of first interconnect structures; and a reinforcement attached to the substrate and configured to mechanically support the substrate, the reinforcement including a first layer and a second layer on the first layer, the first layer including a material having the same coefficient of thermal expansion as the substrate, and the reinforcement including a plurality of capacitors in the first layer and the second layer.

[0009] In some embodiments, a reinforcement includes: a first layer comprising a silicon wafer; a second layer situated on the first layer, wherein the reinforcement defines a trench extending into at least a portion of the first layer and at least a portion of the second layer; and a silicon capacitor including a first electrode in the trench, a dielectric layer on the first electrode, and a second electrode on the dielectric layer. Attached Figure Description

[0010] Figure 1 This is a perspective view of a semiconductor package according to some implementation methods.

[0011] Figure 2 It is along Figure 1 A sectional view taken by line A-A'.

[0012] Figure 3 It is along Figure 1 The sectional view taken by line B-B'.

[0013] Figure 4 This is a cross-sectional view showing the upper surface of the reinforcement according to some embodiments.

[0014] Figure 5 This is a cross-sectional view showing the upper surface of the reinforcement according to some embodiments.

[0015] Figure 6 This is a perspective view of a semiconductor package according to some implementation methods.

[0016] Figure 7 It is along Figure 6 A sectional view taken by line C-C'.

[0017] Figure 8 This is a perspective view of a semiconductor package according to some implementation methods.

[0018] Figure 9 It is along Figure 8 A sectional view taken by line D-D'.

[0019] Figure 10 This is a perspective view of a semiconductor package according to some implementation methods.

[0020] Figure 11 It is along Figure 10 A sectional view taken from line E-E'.

[0021] Figure 12 This is a perspective view of a semiconductor package according to some implementation methods.

[0022] Figure 13 This is a perspective view of a semiconductor package according to some implementation methods. Detailed Implementation

[0023] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement this disclosure. However, this disclosure can be implemented in various different forms and is not limited to the embodiments described herein.

[0024] Furthermore, to clearly illustrate this disclosure in the accompanying drawings, parts unrelated to the description have been omitted, and similar reference numerals have been given to similar parts throughout the specification. In the flowcharts described with reference to the accompanying drawings, the order of operations can be changed, several operations can be combined, some operations can be split, and some operations can be omitted.

[0025] Furthermore, terms expressed in the singular can be interpreted as either singular or plural unless explicitly stated as "a" or "singular." Terms including ordinal numbers such as first, second, etc., can be used to describe various components, but components are not limited by these terms. These terms can be used to distinguish one component from another.

[0026] As described above, as semiconductor chips become more high-performance, their frequencies may increase, generating more noise. Furthermore, with increased noise, the power loss within the semiconductor chip may also increase. This problem can be addressed by forming capacitors around the semiconductor chip. Additionally, semiconductor packages containing semiconductor chips are manufactured with very thin thicknesses, making them highly susceptible to external physical stresses, such as warping. This problem can be solved by using reinforcements located around the semiconductor chip.

[0027] However, when capacitors and reinforcements are placed around a semiconductor chip to address its physical and electrical problems, the overall size of the semiconductor package may increase due to the area occupied by the capacitors and reinforcements.

[0028] This disclosure addresses various aspects of the relevant art discussed above. Figure 1 This is a perspective view of a semiconductor package according to some embodiments, and Figure 2 It is along Figure 1 A sectional view taken by line A-A'.

[0029] refer to Figure 1 and Figure 2 The semiconductor package 100 may include a substrate 110, a semiconductor chip structure 120, and reinforcement components 130.

[0030] Semiconductor chip structure 120 can be placed on substrate 110. Semiconductor chip structure 120 can be attached to substrate 110 via interconnect structure 121 (e.g., microbumps or solder bumps). Semiconductor chip structure 120 can be physically and electrically connected to substrate 110 via interconnect structure 121. Semiconductor chip structure 120 can be electrically connected to wires inside substrate 110 via interconnect structure 121. Figure 2 (111). The semiconductor chip structure 120 can receive electrical signals from or output electrical signals to the outside through the interconnect structure 121 and the wires 111 inside the substrate 110. The wires 111 may include at least one metal selected from copper Cu, aluminum Al, nickel Ni, silver Ag, gold Au, platinum Pt, tin Sn, lead Pb, titanium Ti, chromium Cr, palladium Pd, indium In, zinc Zn and carbon C, or an alloy including two or more of these metals.

[0031] Semiconductor chip structure 120 can be an IC chip in which multiple integrated circuit ICs are formed on a wafer. Semiconductor chip structure 120 may include, for example, logic chips such as central processing units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs), digital signal processors, cryptographic processors, microprocessors, microcontrollers, analog-to-digital converters (ADCs), and application-specific integrated circuits (ASICs); or memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), or flash memory. Semiconductor package 100 may also include an underfill (…). Figure 2 The bottom filler 123 fills the space between the substrate 110 and the semiconductor chip structure 120 and surrounds the interconnect structure 121. The bottom filler 123 can be formed using, for example, epoxy resin, benzocyclobutene resin or polyimide resin.

[0032] In some embodiments, the substrate 110 may include a plurality of pads 150. The plurality of pads 150 may be spaced apart from each other on the substrate 110 at predetermined intervals. Here, the plurality of pads 150 are illustrated as being spaced apart from the semiconductor chip structure 120 in a first direction and a second direction opposite to the first direction, but are not limited thereto. In some embodiments, the number of the plurality of pads 150 may be varied.

[0033] refer to Figure 2In some embodiments, each of the plurality of pads 150 is electrically connected to an interconnect structure 121 via wires 111 within the substrate 110. Each of the plurality of pads 150 is electrically connected to a semiconductor chip structure 120 via wires 111 within the substrate 110 and the interconnect structure 121. The semiconductor chip structure 120 receives a voltage of a first polarity (e.g., a power supply voltage) and a voltage of a second polarity (e.g., a ground voltage) from the outside via the interconnect structure 121. The semiconductor chip structure 120 may receive both a first polarity voltage and a second polarity voltage from the outside via some interconnect structures 121. Each of the plurality of pads 150 is electrically connected to the interconnect structure 121 providing the first polarity voltage and the second polarity voltage via wires 111 within the substrate 110.

[0034] refer to Figure 1 The reinforcement 130 can be placed on the substrate 110. The reinforcement 130 can be arranged on the substrate 110 to surround the side of the semiconductor chip structure 120. The upper surface of the reinforcement 130 can be at a horizontal height substantially the same as or lower than the upper surface of the semiconductor chip structure 120. The height of the reinforcement 130 can be substantially the same as or lower than the height of the semiconductor chip structure 120. In some embodiments, the reinforcement 130 can surround at least a portion of the semiconductor chip structure 120. For example, the reinforcement 130 can surround the semiconductor chip structure 120 along a first direction (d1) and a third direction (d3) perpendicular to the first direction (d1). Here, the reinforcement 130 is illustrated as having a square ring shape surrounding the semiconductor chip structure 120, but the shape of the reinforcement 130 is not limited to this. For example, the reinforcement 130 may have any other suitable shape surrounding the semiconductor chip structure 120 (e.g., circular, rectangular, elliptical, pentagonal, hexagonal, octagonal). The reinforcement 130 may improve the thermal properties of the substrate 110, such as the warpage properties of the substrate 110, by mechanically supporting the substrate 110.

[0035] In some embodiments, the reinforcement 130 may be formed of silicon. The reinforcement 130 may be formed of a silicon wafer. The reinforcement 130 may be formed by dicing a silicon wafer. The reinforcement 130 may be formed of a material substantially the same as the substrate 110. For example, the reinforcement 130 may be formed of a silicon wafer having a coefficient of thermal expansion (CTE) substantially the same as the substrate 110 and high thermal conductivity. Reference Figure 2The reinforcement 130 may include a silicon layer 133 formed from a silicon wafer. The reinforcement 130 may be mechanically bonded to or attached to the substrate 110 using an adhesive 131. The reinforcement 130 may include a passivation layer 135 formed on the silicon layer 133. The passivation layer 135 may be formed of an insulator. For example, the passivation layer 135 may be formed of silicon nitride, silicon oxynitride, silicon carbonitride, a polymer, other materials, or combinations thereof.

[0036] In some embodiments, the reinforcement 130 may include a plurality of capacitors 140 housed in trenches formed by etching a silicon wafer. The reinforcement 130 may include a plurality of capacitors 140 located in trenches penetrating at least a portion of the passivation layer 135 and at least a portion of the silicon layer 133. The plurality of capacitors 140 included in the trenches formed by etching the passivation layer 135 and the silicon layer 133 of the reinforcement 130 may be silicon capacitors.

[0037] refer to Figure 1 In some embodiments, a plurality of capacitors 140 may extend within a reinforcement 130. The plurality of capacitors 140 may extend within the reinforcement 130 in a square ring shape surrounding the semiconductor chip structure 120. The plurality of capacitors 140 may be electrically connected to a plurality of pads 150 via bonding wires 160. For example, a first capacitor 140a of the plurality of capacitors may be electrically connected to a plurality of pads via bonding wires 160, and a second capacitor 140b of the plurality of capacitors may be electrically connected to a plurality of pads via bonding wires 160. The plurality of capacitors 140 may function as capacitors when voltages of different polarities are applied to each capacitor.

[0038] In some embodiments, the plurality of capacitors 140 may each be applied with a voltage of different polarity via bonding wires 160 and a plurality of pads 150. For example, a first capacitor 140a may receive a voltage of a first polarity via bonding wire 160 and a first pad 150b, and a voltage of a second polarity via bonding wire 160 and a second pad 150d. Alternatively, a second capacitor 140b may receive a voltage of the first polarity via bonding wire 160 and a third pad 150a, and a voltage of the second polarity via bonding wire 160 and a fourth pad 150c.

[0039] In some embodiments, a plurality of capacitors 140 may be electrically connected to an interconnect structure 121 electrically connected to the semiconductor chip structure 120 via bonding wires 160 and a plurality of pads 150. Specifically, the plurality of capacitors 140 may be electrically connected to the interconnect structure 121 that provides a voltage of a first polarity and a voltage of a second polarity to the semiconductor chip structure 120 via bonding wires 160 and a plurality of pads 150. For example, a first capacitor 140a may be electrically connected to the interconnect structure 121 that provides a voltage of a first polarity and a voltage of a second polarity to the semiconductor chip structure 120 via bonding wires 160 and a plurality of pads 150. In some embodiments, a second capacitor 140b may be electrically connected to the interconnect structure 121 that provides a voltage of a first polarity and a voltage of a second polarity to the semiconductor chip structure 120 via bonding wires 160 and a plurality of pads 150.

[0040] According to the comparative example, the semiconductor package includes multiple die-side capacitors disposed around the semiconductor chip structure. The semiconductor package according to the comparative example ensures the power integrity (PI) characteristics of the semiconductor chip structure through the die-side capacitors.

[0041] According to some embodiments, a semiconductor package 100 includes a reinforcement 130 having a plurality of capacitors 140. The semiconductor package 100 according to some embodiments can enhance the physical properties of the semiconductor package 100 through the reinforcement 130, while ensuring the power integrity characteristics of the semiconductor chip structure 120 through the capacitors 140 formed within the reinforcement 130. In some embodiments, there is an advantage that the size of the semiconductor package 100 can be reduced by eliminating the die-side capacitors. A detailed description of the capacitors 140 formed in the reinforcement 130 will be referred to... Figure 3 The following will explain.

[0042] Figure 3 It is along Figure 1 A cross-sectional view taken by line B-B'. Specifically, Figure 3 This is a diagram illustrating a capacitor within a reinforcement according to some embodiments.

[0043] In some embodiments, the reinforcement 300 may include a silicon layer 333 formed from a silicon wafer, and may include a passivation layer 335 formed on the silicon layer 333. In some embodiments, the reinforcement 300 may include a plurality of capacitors 340. The reinforcement 300 may include a plurality of capacitors 340, which are included in trenches formed by etching the silicon layer 333 and the passivation layer 335.

[0044] In some embodiments, capacitor 340 may include a first electrode 341, a dielectric layer 343, and a second electrode 345. The first electrode 341, dielectric layer 343, and second electrode 345 may be sequentially stacked in a trench formed by etching silicon layer 333 and passivation layer 335. Specifically, the first electrode 341 may be located on the trench formed by etching silicon layer 333 and passivation layer 335, the dielectric layer 343 may be located on the first electrode 341, and the second electrode 345 may be located on the dielectric layer 343. Therefore, dielectric layer 343 may be placed between the first electrode 341 and the second electrode 345. The first electrode 341 and the second electrode 345 are arranged facing each other with dielectric layer 343 located between them, such that they can function as capacitors when voltages of different polarities are applied to the first electrode 341 and the second electrode 345. The first electrode 341, dielectric layer 343, and second electrode 345 may be exposed on the upper side of the reinforcement 300.

[0045] In some embodiments, capacitor 340 can be applied with voltages of different polarities. For example, the first electrode 341 of the first capacitor 340a can be applied with a voltage of the first polarity, and the second electrode 345 can be applied with a voltage of the second polarity. Similarly, the second capacitor 340b can also be applied with a voltage of the first polarity and a voltage of the second polarity. Capacitor 340 can receive the first polarity voltage and the second polarity voltage from the outside via bonding wire 360.

[0046] Figure 4 This is a cross-sectional view showing the upper surface of the reinforcement according to some embodiments.

[0047] refer to Figure 4 According to some embodiments, the reinforcement 400 may include a passivation layer 435 and a capacitor 440 formed by etching a silicon layer beneath the passivation layer. The capacitor 440 may include a first electrode 441, a dielectric layer 443, and a second electrode 445. The first electrode 441 and the second electrode 445 are arranged facing each other with the dielectric layer 443 located between them, such that they can function as capacitors when voltages of different polarities are applied to the first electrode 441 and the second electrode 445.

[0048] In some embodiments, the first electrode 441, the dielectric layer 443, and the second electrode 445 may extend in the same direction, and the first electrode 441, the dielectric layer 443, and the second electrode 445 may be formed uniformly in all cross-sections. These capacitors 440 have the advantages of simple shape and therefore ease of manufacture.

[0049] Figure 5 This is a cross-sectional view showing the upper surface of the reinforcement according to some embodiments.

[0050] refer to Figure 5 According to some embodiments, the reinforcement 500 may include a passivation layer 535 and a capacitor 540 formed by etching a silicon layer beneath the passivation layer. The capacitor 540 may include a first electrode 541, a dielectric layer 543, and a second electrode 545. The first electrode 541 and the second electrode 545 are arranged facing each other with the dielectric layer 443 located between them, such that they can function as capacitors when voltages of different polarities are applied to the first electrode 541 and the second electrode 545.

[0051] In some embodiments, the first electrode 541, dielectric layer 543, and second electrode 545 can be formed in a trench shape on the reinforcement 500. Therefore, the surface area of ​​the first electrode 541, dielectric layer 543, and second electrode 545 can be increased. These capacitors 540 have the advantage of large electrostatic capacitance.

[0052] Figure 6 This is a perspective view of a semiconductor package according to some embodiments, and Figure 7 It is along Figure 6 The sectional view taken along line C-C'. For clarity, details related to the section are omitted here. Figure 1 The semiconductor package 100 is described in the same or similar way.

[0053] refer to Figure 6 The semiconductor package 600 may include a substrate 610, a semiconductor chip structure 620, and reinforcement 630. The semiconductor chip structure 620 may be placed on the substrate 610 and physically and electrically connected to the substrate 610 through an interconnect structure 621.

[0054] In some embodiments, the reinforcement 630 may be disposed on the substrate 610. In some embodiments, the reinforcement 630 may surround at least a portion of the semiconductor chip structure 620. For example, the reinforcement 630 may surround the semiconductor chip structure 620 along a first direction (d1) and a third direction (d3) perpendicular to the first direction (d1). Here, the reinforcement 630 is illustrated as having a square ring shape surrounding the semiconductor chip structure 620, but the shape of the reinforcement 630 is not limited thereto. In some embodiments, the reinforcement 630 may be attached to the substrate 610 via an interconnect structure 680. The interconnect structure 680 may include, but is not limited to, bumps (e.g., microbumps or solder bumps) or hybrid copper bonding. The interconnect structure 680 may be formed of a conductive material, such as copper, aluminum, etc. The reinforcement 630 may be physically connected to the substrate 610 via the interconnect structure 680.

[0055] In some embodiments, the reinforcement 630 may include a plurality of capacitors 640 housed in trenches formed by etching a silicon layer within the reinforcement 630. The plurality of capacitors 640 may include a plurality of electrodes and may function as capacitors when voltages of different polarities are applied to the plurality of electrodes. Reference Figure 7 The reinforcement 630 may include a silicon layer 633 and a passivation layer 635, and may include a plurality of capacitors 640 formed in trenches formed by etching the lower portion of the reinforcement 630. Each capacitor 640 may include a first electrode 641 located on the trenches formed by etching the lower portion of the reinforcement 630, a dielectric layer 643 located on the first electrode 641, and a second electrode 645 located on the dielectric layer 643. The capacitor 640 may include a first electrode 641 and a second electrode 645 arranged opposite to each other, with the dielectric layer 643 located between them. The first electrode 641, the dielectric layer 643, and the second electrode 645 may be exposed at the bottom of the reinforcement 630. Here, the capacitor 640 is illustrated as being formed by etching only the silicon layer 633, but is not limited thereto. For example, the capacitor 640 may extend to the passivation layer 635, and the second electrode 645 of the capacitor 640 may be exposed at the top of the reinforcement 630. In some embodiments, the internal structure of the capacitor 640 may be consistent with... Figure 3 The capacitor 340 described herein has the same or similar construction.

[0056] In some embodiments, multiple capacitors 640 may be connected to multiple interconnect structures 680. The multiple capacitors 640 may be electrically connected to the substrate 610 through the multiple interconnect structures 680. The multiple capacitors 640 may be applied with different polarities through the interconnect structures 680. The interconnect structures 680 may apply voltages of different polarities to the multiple capacitors 640. (Reference) Figure 7 Interconnect structure 680 can be attached to pad 650 on substrate 610 and electrically connects the first electrode 641 and second electrode 645 within reinforcement 630 to wires 611 within substrate 610. Multiple capacitors 640 can be applied with voltages of different polarities through interconnect structure 680. For example, multiple capacitors 640 can be electrically connected to interconnect structure 621, which provides voltages of first and second polarities to semiconductor chip structure 620, through interconnect structure 680 and wires 611 within substrate 610. Therefore, the first electrode 641 of capacitor 640 can be applied with a voltage of the first polarity, and the second electrode 645 can be applied with a voltage of the second polarity.

[0057] Figure 8 This is a perspective view of a semiconductor package according to some embodiments, and Figure 9 It is along Figure 8The cross-sectional view taken by line D-D'. For ease of explanation, details related to... Figure 1 and Figure 6 The same or similar description of semiconductor packages.

[0058] refer to Figure 8 The semiconductor package 800 may include a substrate 810, a semiconductor chip structure 820, and reinforcement 830. The semiconductor chip structure 820 may be placed on the substrate 810 and physically and electrically connected to the substrate 810 through an interconnect structure 821.

[0059] In some embodiments, the substrate 810 may include a plurality of pads 850. The plurality of pads 850 may be spaced apart from each other on the substrate 810 at predetermined intervals. Here, the plurality of pads 850 are illustrated as being arranged spaced apart from the semiconductor chip structure 820 in a first direction and a second direction opposite to the first direction, but are not limited thereto. In some embodiments, the number of the plurality of pads 850 may be varied.

[0060] In some embodiments, the reinforcement 830 may be disposed on the substrate 810. In some embodiments, the reinforcement 830 may surround at least a portion of the semiconductor chip structure 820. For example, the reinforcement 830 may surround the semiconductor chip structure 820 along a first direction (d1) and a third direction (d3) perpendicular to the first direction (d1). Here, the reinforcement 830 is illustrated as having a square ring shape surrounding the semiconductor chip structure 820, but the shape of the reinforcement 830 is not limited thereto. Reference Figure 9 In some embodiments, the reinforcement member 830 can be attached to the substrate 810 via the interconnect structure 880. The reinforcement member 830 can be physically connected to the substrate 810 via the interconnect structure 880.

[0061] In some embodiments, the reinforcement 830 may include a plurality of capacitors 840 housed in trenches formed by etching a silicon layer within the reinforcement 830. The reinforcement 830 may also include a plurality of capacitors 840 housed in trenches formed by etching an upper portion of the reinforcement 830. In some embodiments, the reinforcement 830 may further include a plurality of capacitors housed in trenches formed by etching a lower portion of the reinforcement 830. (See reference...) Figure 9 According to some embodiments, the reinforcement 830 may include an upper capacitor 840 and a lower capacitor 841. The upper capacitor 840 is included in a trench formed by etching the upper portion of the reinforcement 830, and the lower capacitor 841 is included in a trench formed by etching the lower portion of the reinforcement 830. The internal structure of the capacitors 840 and 841 may be consistent with... Figure 3 The capacitor 340 described herein has the same or similar construction.

[0062] In some embodiments, the upper capacitor 840 can be electrically connected to a pad 850a on the substrate 810 via a bonding wire 860. Specifically, the upper capacitor 840 can receive voltages of different polarities via a wire 811 inside the substrate 810, a pad 850a on the substrate 810, and a bonding wire 860. In some embodiments, the lower capacitor 841 can be electrically connected to a pad 850b on the substrate 810 via an interconnect structure 880. Specifically, the lower capacitor 841 can be applied voltages of different polarities via a wire 811 inside the substrate 810, a pad 850b on the substrate 810, and an interconnect structure 880. The upper capacitor 840 and the lower capacitor 841 are each provided with voltages of different polarities and can function as capacitors.

[0063] Figure 10 This is a perspective view of a semiconductor package according to some embodiments, and Figure 11 It is along Figure 10 The sectional view taken by line E-E'. For ease of explanation, details related to... Figure 1 , Figure 6 and Figure 8 The same or similar description of semiconductor packages.

[0064] refer to Figure 10 The semiconductor package 1000 may include a substrate 1010, a semiconductor chip structure 1020, and reinforcement 1030. The semiconductor chip structure 1020 may be placed on the substrate 1010 and may be physically and electrically connected to the substrate 1010 via an interconnect structure 1021.

[0065] In some embodiments, the substrate 1010 may include a plurality of pads 1050. The plurality of pads 1050 may be spaced apart from each other on the substrate 1010 at predetermined intervals. Here, the plurality of pads 1050 are illustrated as being spaced apart in a direction surrounding the semiconductor chip structure 1020, but are not limited thereto. In some embodiments, the number of the plurality of pads 1050 may be varied.

[0066] In some embodiments, the reinforcement 1030 may be disposed on the substrate 1010. In some embodiments, the reinforcement 1030 may surround at least a portion of the semiconductor chip structure 1020. For example, the reinforcement 1030 may surround the semiconductor chip structure 1020 along a first direction (d1) and a third direction (d3) perpendicular to the first direction (d1). Here, the reinforcement 1030 is illustrated as having a square ring shape surrounding the semiconductor chip structure 1020, but the shape of the reinforcement 1030 is not limited thereto. Reference Figure 11 The reinforcement 1030 may include an adhesive 1031, a silicon layer 1033, and a passivation layer 1035, and may be attached to the substrate 1010 via the adhesive 1031. The reinforcement 1030 may be physically attached to the substrate 1010 via the adhesive 1031.

[0067] In some embodiments, the reinforcement 1030 may include a plurality of capacitors 1040 housed in trenches formed by etching a silicon wafer within the reinforcement 1030. The reinforcement 1030 may also include a plurality of capacitors 1040 housed in trenches formed by etching an upper portion of the reinforcement 1030. In some embodiments, the reinforcement 1030 may include a plurality of capacitors 1040 spaced apart from each other. The plurality of capacitors 1040 may be electrically connected to a plurality of pads 1050 on the substrate 1010 via bonding wires. For example, see reference... Figure 10 The capacitor 1040 can be electrically connected to the first pad 1050a via the first bonding wire 1060a, and can be electrically connected to the second pad 1050b via the second bonding wire 1060b. The capacitor 1040 can receive voltages of different polarities via the first bonding wire 1060a and the second bonding wire 1060b.

[0068] refer to Figure 11 Each capacitor 1040 may include a first electrode 1041, a dielectric layer 1043, and a second electrode 1045. The multiple electrodes 1041 and 1045 can be electrically connected to multiple pads 1050 via bonding wires 1060. The multiple electrodes 1041 and 1045 can receive voltages of different polarities via the bonding wires 1060 and the multiple pads 1050. For example, the first electrode 1041 may be applied with a voltage of a first polarity, and the second electrode 1045 may be applied with a voltage of a second polarity.

[0069] Figure 12 This is a perspective view of a semiconductor package according to some embodiments. For ease of explanation, details related to... Figure 1 , Figure 6 , Figure 8 and Figure 10The same or similar description of semiconductor packages.

[0070] In some embodiments, the semiconductor package 1200 may include a substrate 1210, a semiconductor chip structure 1220, and a plurality of reinforcement members 1230a, 1230b. The semiconductor chip structure 1220 may be physically and electrically connected to the substrate 1210 via an interconnect structure 1221.

[0071] In some embodiments, multiple reinforcement members 1230a, 1230b may be disposed on the substrate 1210. (See reference...) Figure 12 Each of the plurality of reinforcement members 1230a and 1230b may be spaced apart from the semiconductor chip structure 1220 in a first direction (d1) and a second direction opposite to the first direction (d1). The plurality of reinforcement members 1230a and 1230b may extend on the substrate 1210 along a third direction (d3) perpendicular to the first direction (d1). However, this is not a limitation. For example, each of the plurality of reinforcement members 1230a and 1230b may be spaced apart from the semiconductor chip structure 1220 in a third direction (d3) and a fourth direction opposite to the third direction (d3), and may extend on the substrate 1210 along the first direction (d1). The upper surfaces of the plurality of reinforcement members 1230a and 1230b may be at substantially the same horizontal level as or below the upper surface of the semiconductor chip structure 1220. The height of multiple reinforcement components 1230a and 1230b can be substantially the same as or lower than the height of the semiconductor chip structure 1220.

[0072] In some embodiments, each of the plurality of reinforcements 1230a, 1230b may include a plurality of capacitors 1240. The plurality of capacitors 1240 are electrically connected to the substrate 1210 via bonding wires 1260 and pads 1250. The plurality of capacitors 1240 are electrically connected to the interconnect structure 1221 via bonding wires 1260 and pads 1250. The plurality of capacitors 1240 can receive voltages of different polarities via bonding wires 1260 and pads 1250. The internal structure and connection structure of the plurality of capacitors 1240 may be adapted to... Figures 1 to 11 The internal structure and connection structure of the capacitor are the same or similar.

[0073] Figure 13 This is a perspective view of a semiconductor package according to some embodiments. For ease of explanation, details related to... Figure 1 , Figure 6 , Figure 8 and Figure 10 The same or similar description of semiconductor packages.

[0074] In some embodiments, the semiconductor package 1300 may include a substrate 1310, a semiconductor chip structure 1320, and a plurality of reinforcement components 1330a, 1330b, 1330c, and 1330d. The semiconductor chip structure 1320 may be physically and electrically connected to the substrate 1310 via an interconnect structure 1321.

[0075] In some embodiments, multiple reinforcement members 1330a, 1330b, 1330c, and 1330d may be disposed on the substrate 1310. (See reference...) Figure 13 Each of the multiple reinforcements 1330a, 1330b, 1330c, and 1330d can be spaced apart from the semiconductor chip structure 1320 in the edge direction of the semiconductor chip structure 1320.

[0076] In some embodiments, each of the plurality of reinforcements 1330a, 1330b, 1330c, and 1330d may include a plurality of capacitors 1340. The plurality of capacitors 1340 may be electrically connected to the substrate 1310 via bonding wires 1360 and pads 1350. The plurality of capacitors 1340 may be electrically connected to the interconnect structure 1321 via bonding wires 1360 and pads 1350. The plurality of capacitors 1340 may receive voltages of different polarities via bonding wires 1360 and pads 1350. For example, a capacitor 1340 may be applied with a voltage of a first polarity via a first bonding wire 1360a and a first pad 1350a, and a capacitor 1340 may be applied with a voltage of a second polarity via a second bonding wire 1360b and a second pad 1350b. The internal structure and connection structure of the plurality of capacitors 1340 may be adapted to [the specific configuration / details]. Figures 1 to 11 The internal structure and connection structure of the capacitor are the same or similar.

[0077] As used herein, “about,” “approximately,” “generally,” and “substantially” are understood to mean a number within, for example, a range of -10% to +10% of a reference value, preferably -5% to +5% of the reference value, more preferably -1% to +1% of the reference value, and most preferably -0.1% to +0.1% of the reference value. Furthermore, any numerical range disclosed herein should be interpreted as supporting any particular value or subrange within that range. For example, the disclosure of a range from 1 to 10 supports subranges such as 1 to 5, 3 to 6, 1 to 9, 2.5 to 4.7, 2.2 to 9.9, etc.

[0078] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope that can be claimed, but rather as descriptions of features specific to particular implementations of a particular invention. Some features described in the context of individual implementations in this specification may also be implemented in combinations of individual implementations. Conversely, various features described in the context of individual implementations may also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in certain combinations, in some cases, one or more features from a combination may be removed from the combination, and a combination may refer to a sub-combination or a variation of a sub-combination.

[0079] Although the embodiments of this disclosure have been described in detail above, the scope of this disclosure is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concepts of this disclosure as defined in the appended claims are also within the scope of this disclosure.

Claims

1. A semiconductor package, the semiconductor package comprising: Substrate, the substrate including multiple pads, A semiconductor chip structure, wherein the semiconductor chip structure is attached to the substrate via a plurality of interconnect structures, and the semiconductor chip structure is electrically connected to the plurality of pads, and A reinforcement member is attached to the substrate and includes a plurality of capacitors, the plurality of capacitors including a first electrode and a second electrode connected to a plurality of bonding wires, wherein the height of the reinforcement member is equal to the height of the semiconductor chip structure, and the plurality of capacitors are electrically connected to the plurality of pads via the plurality of bonding wires.

2. The semiconductor package according to claim 1, wherein, The reinforcement components include: An adhesive configured to attach the reinforcement to the substrate. A silicon layer, the silicon layer being situated on the adhesive and comprising a silicon wafer, and A passivation layer, the passivation layer being located on the silicon layer and comprising an insulator.

3. The semiconductor package according to claim 2, wherein, The reinforcement defines a trench that extends into at least a portion of the silicon layer and at least a portion of the passivation layer, wherein the plurality of capacitors are located in the trench.

4. The semiconductor package according to claim 3, wherein: The plurality of capacitors include a dielectric layer, and The first electrode is located in the trench, the dielectric layer is located on the first electrode, and the second electrode is located on the dielectric layer.

5. The semiconductor package according to claim 1, wherein: The first electrode is electrically connected to a first interconnect structure among the plurality of interconnect structures via the plurality of bonding wires and the plurality of pads, wherein the first interconnect structure is configured to provide a first voltage to the semiconductor chip structure, and The second electrode is electrically connected to a second interconnect structure among the plurality of interconnect structures via the plurality of bonding wires and the plurality of pads, wherein the second interconnect structure is configured to provide a second voltage to the semiconductor chip structure that is different from the first voltage.

6. The semiconductor package according to claim 5, wherein, The first voltage is the power supply voltage provided to the semiconductor chip structure, and the second voltage is the ground voltage provided to the semiconductor chip structure.

7. The semiconductor package according to claim 1, wherein, The reinforcement is located on the outside of at least a portion of the semiconductor chip structure.

8. The semiconductor package according to claim 1, in, The reinforcement includes a first reinforcement and a second reinforcement. The first reinforcement member is spaced apart from the semiconductor chip structure in a first direction and extends along a second direction perpendicular to the first direction. The second reinforcement member is spaced apart from the semiconductor chip structure in a third direction opposite to the first direction and extends along the second direction.

9. The semiconductor package according to claim 1, wherein, The capacitors mentioned are silicon capacitors.

10. A semiconductor package, the semiconductor package comprising: Substrate, A semiconductor chip structure, wherein the semiconductor chip structure is attached to the substrate via a plurality of first interconnect structures, and A reinforcement member is attached to the substrate and configured to mechanically support the substrate. The reinforcement member includes a first layer and a second layer located on the first layer. The first layer includes a material having the same coefficient of thermal expansion as the substrate. The reinforcement member includes a plurality of capacitors in the first layer and the second layer.

11. The semiconductor package according to claim 10, in, The reinforcement defines grooves in the first and second layers. At least one of the plurality of capacitors includes: A first electrode is located on the trench in the first and second layers. A first dielectric layer, the first dielectric layer being located on the first electrode, and The second electrode is located on the first dielectric layer. The first electrode, the first dielectric layer, and the second electrode are exposed on the upper side of the reinforcement.

12. The semiconductor package of claim 11, wherein the semiconductor package comprises: A first bonding wire is electrically connected to the first electrode. A first pad, attached to the substrate and configured to electrically connect the first bonding line to a first-to-first interconnect structure among the plurality of first interconnect structures. The second bonding wire is electrically connected to the second electrode, and The second pad is attached to the substrate and configured to electrically connect the second bonding line to a second-first interconnect structure among the plurality of first interconnect structures.

13. The semiconductor package of claim 12, wherein: The first electrode is configured to receive a first voltage through the first bonding wire and the first pad, and The second electrode is configured to receive a second voltage, different from the first voltage, through the second bonding wire and the second pad.

14. The semiconductor package of claim 10, wherein, The reinforcement defines a trench in the first layer, wherein at least one of the plurality of capacitors includes: The third electrode is located on the trench in the first layer. A second dielectric layer, which is located on the third electrode, and The fourth electrode is located on the second dielectric layer. The third electrode, the second dielectric layer, and the fourth electrode are exposed on the lower side of the reinforcement.

15. The semiconductor package of claim 14, further comprising: Multiple second interconnect structures, Wherein, a first-second interconnect structure among the plurality of second interconnect structures is configured to attach the reinforcement to the substrate, the first-second interconnect structure is electrically connected to the third electrode, and is configured to apply a first voltage to the third electrode, and The second-to-second interconnect structure of the plurality of second interconnect structures is configured to attach the reinforcement to the substrate, the second-to-second interconnect structure is electrically connected to the fourth electrode, and is configured to apply a second voltage different from the first voltage to the fourth electrode.

16. The semiconductor package of claim 15, wherein, The plurality of second interconnect structures are microbumps.

17. The semiconductor package of claim 10, wherein, The reinforcement is located on the outside of at least a portion of the semiconductor chip structure.

18. The semiconductor package of claim 10, wherein, The first layer comprises a silicon wafer.

19. A reinforcement component, the reinforcement component comprising: The first layer comprises a silicon wafer. A second layer, situated on top of the first layer, wherein the reinforcement defines a trench extending into at least a portion of the first layer and at least a portion of the second layer. as well as A silicon capacitor, the silicon capacitor including a first electrode in the trench, a dielectric layer on the first electrode, and a second electrode on the dielectric layer.

20. The reinforcement component according to claim 19, further comprising: A first bonding wire is connected to the first electrode; as well as The second bonding wire is connected to the second electrode.

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