Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a first semiconductor structure and a second semiconductor structure bonded over the first semiconductor structure. The device also includes a first chain including a plurality of first bond pad pairs, each first bond pad pair having a first bond pad in the first semiconductor structure and a second bond pad in the second semiconductor structure bonded together. A second bond pad pair not belonging to the first chain and adjacent to at least one first bond pad pair in the first chain includes a third bond pad in the first semiconductor structure and a fourth bond pad in the second semiconductor structure. A first misalignment distance between the first bond pad and the second bond pad is greater than a second misalignment distance between the third bond pad and the fourth bond pad.

Description

Technical Field

[0001] This disclosure relates generally to semiconductor technology, and more specifically to semiconductor devices including bonding pad structures embedded in a chip. Background Technology

[0002] With the increasing demand for storage capacity and performance, three-dimensional (3D) storage devices, such as 3D NAND flash memory, 3D dynamic random access memory (DRAM), and high bandwidth memory (HBM), have become widely used. To optimize the performance of 3D storage devices and other types of semiconductor devices, semiconductor bonding techniques have also been developed. In this example, two chips are formed separately and then bonded together using wafer bonding technology.

[0003] However, chips may not be properly aligned during bonding. Various factors can cause alignment deviations during bonding. These factors include, but are not limited to, wafer deformation, alignment mark and equipment accuracy, vacuum and pressure control, and differences in thermal expansion and contraction. These alignment deviations can lead to alignment misalignment at the bonding interface, and the alignment quality of the bond directly affects production reliability and device yield. Summary of the Invention

[0004] Various aspects of this disclosure provide a semiconductor device and a method for manufacturing the same, to improve alignment deviation detection and reliability of the semiconductor device.

[0005] In a first aspect of this disclosure, an exemplary embodiment provides a semiconductor device comprising: a first semiconductor structure and a second semiconductor structure bonded to the first semiconductor structure; a first chain including a plurality of first bonding pad pairs, each first bonding pad pair including a first bonding pad in the first semiconductor structure and a second bonding pad in the second semiconductor structure bonded together; and a second bonding pad pair not belonging to the first chain and adjacent to at least one of the first bonding pad pairs in the first chain, the second bonding pad pair including a third bonding pad in the first semiconductor structure and a fourth bonding pad in the second semiconductor structure, wherein a first alignment deviation distance between the first bonding pad and the second bonding pad is greater than a second alignment deviation distance between the third bonding pad and the fourth bonding pad.

[0006] In some examples, the semiconductor device further includes a third pair of bonding pads that is not part of the first chain and is adjacent to the second pair of bonding pads. The third pair of bonding pads includes a fifth bonding pad in the first semiconductor structure and a sixth bonding pad in the second semiconductor structure. A first difference between a first alignment deviation distance and a second alignment deviation distance is greater than a second difference between a third alignment deviation distance and a second alignment deviation distance. The third alignment deviation distance is the alignment deviation distance between the fifth bonding pad and the sixth bonding pad.

[0007] In some examples, each of the first and second bonding pad pairs has substantially the same diameter, and the difference between the first alignment deviation distance and the second alignment deviation distance is greater than one-tenth of that diameter.

[0008] In some examples, the first alignment deviation distance is greater than or equal to 60 percent of the diameter, and the second alignment deviation distance is less than 60 percent of the diameter.

[0009] In some examples, the first semiconductor structure and the second semiconductor structure each further include a dielectric bonding region in which the dielectric material comprises carbon-doped silicon nitride.

[0010] In some examples, the first bonding pad pair is located between the sealing ring and the second bonding pad pair.

[0011] In some examples, adjacent first bonding pad pairs in the first chain are connected via conductive paths within either the first semiconductor structure or the second semiconductor structure, such that the first bonding pad pairs in the first chain are connected in series.

[0012] In some examples, adjacent first bonding pads in the first chain are connected via a first interconnect layer in the first semiconductor structure that connects the first bonding pads and a second interconnect layer in the second semiconductor structure that connects the second bonding pads.

[0013] In some examples, the first semiconductor structure includes a first semiconductor component, and the second semiconductor structure includes a second semiconductor component, and the first semiconductor component is connected to the second semiconductor component via a second bonding pad pair.

[0014] In some examples, the semiconductor device also includes a second chain comprising a plurality of first bonding pad pairs, each of the first and second chains comprising first bonding pad pairs having alignment deviations in the same direction, the first bonding pad pairs within each chain being connected in series, and the first and second chains being isolated from each other.

[0015] In some examples, the first alignment deviation distance is along the plane where the first and second bonding pads are bonded together.

[0016] In some examples, the first semiconductor structure and the second semiconductor structure are of the same type.

[0017] In a second aspect of this disclosure, an exemplary embodiment provides a semiconductor device comprising: a first semiconductor structure and a second semiconductor structure bonded to the first semiconductor structure; a chain including a plurality of first bonding pad pairs, each bonding pad pair including a first bonding pad in the first semiconductor structure and a second bonding pad in the second semiconductor structure bonded together; and a second bonding pad pair not belonging to the chain and adjacent to bonding pad pairs in the chain, wherein the first bonding pad pairs have a first alignment deviation vector indicating a first alignment deviation between the first bonding pad and the second bonding pad, the second bonding pad pair has a second alignment deviation vector indicating a second alignment deviation between a third bonding pad and a fourth bonding pad, and the vector difference between the first alignment deviation vector and the second alignment deviation vector is not zero.

[0018] In some examples, the first semiconductor structure includes a fifth bonding pad, and the second semiconductor structure includes a sixth bonding pad, the fifth and sixth bonding pads being bonded together to form a third bonding pad pair that does not belong to the chain and is adjacent to the second bonding pad pair, wherein, in terms of vector length, the vector difference between the first alignment deviation vector and the second alignment deviation vector is greater than the vector difference between the third alignment deviation vector and the second alignment deviation vector.

[0019] In some examples, the first semiconductor structure and the second semiconductor structure each further include a dielectric bonding region in which the dielectric material comprises carbon-doped silicon nitride.

[0020] In some examples, the first bonding pad pair is located between the sealing ring and the second bonding pad pair.

[0021] In some examples, each bonding pad in the first bonding pad pair and the second bonding pad pair has substantially the same diameter, and the vector difference between the first alignment deviation vector and the second alignment deviation vector is greater than one-tenth of that diameter.

[0022] In some examples, the length of the first alignment deviation vector is greater than or equal to 60 percent of the diameter, and the length of the second alignment deviation vector is less than 60 percent of the diameter.

[0023] In some examples, the first semiconductor structure includes a memory cell array, and the second semiconductor structure includes peripheral circuitry for the memory cell array.

[0024] In a third aspect of this disclosure, an exemplary embodiment provides a method for manufacturing a semiconductor device, the method comprising: forming a first semiconductor structure including a first bonding pad and a second bonding pad; forming a second semiconductor structure including a third bonding pad and a fourth bonding pad; and bonding the first semiconductor structure onto the second semiconductor structure, wherein the first bonding pad and the third bonding pad are respectively bonded together to form a first bonding pad pair, the first bonding pad pairs are connected to form a chain, at least two of the first bonding pad pairs in the chain are connected via a conductive path within either the first semiconductor structure or the second semiconductor structure, and the second bonding pad and the fourth bonding pad are bonded together to form a second bonding pad pair not belonging to the chain, wherein a first alignment deviation distance between the first bonding pad and the third bonding pad is greater than a second alignment deviation distance between the second bonding pad and the fourth bonding pad.

[0025] In some examples, the first semiconductor structure includes a fifth bonding pad, and the second semiconductor structure includes a sixth bonding pad. The fifth and sixth bonding pads are bonded together to form a third bonding pad pair that is not part of the chain and is adjacent to the second bonding pad pair. The third bonding pad pair has a third alignment offset distance, wherein the difference between the first and second alignment offset distances is greater than the difference between the third and second alignment offset distances.

[0026] In some examples, the first semiconductor structure and the second semiconductor structure each further include a dielectric bonding region in which the dielectric material comprises carbon-doped silicon nitride.

[0027] In some examples, the first bonding pad pair is located between the sealing ring and the second bonding pad pair.

[0028] In some examples, each of the first and second bonding pad pairs has substantially the same diameter, and the difference between the first alignment deviation distance and the second alignment deviation distance is greater than one-tenth of that diameter.

[0029] In some examples, the first alignment deviation distance is greater than or equal to 60 percent of the diameter, and the second alignment deviation distance is less than 60 percent of the diameter. Attached Figure Description

[0030] Various embodiments of this disclosure presented as examples will be described in detail with reference to the following accompanying drawings, wherein similar reference numerals denote similar elements, and wherein: Figure 1 A block diagram of an exemplary system having storage devices according to some aspects of this disclosure is shown.

[0031] Figure 2An illustration of an exemplary memory card having storage devices according to some aspects of this disclosure is shown.

[0032] Figure 3 An illustration of an exemplary solid-state drive (SSD) with storage devices is shown, according to some aspects of this disclosure.

[0033] Figure 4 A schematic diagram of an exemplary storage device including peripheral circuitry is shown, according to some aspects of this disclosure.

[0034] Figure 5 A schematic cross-sectional view of a storage device according to some aspects of this disclosure is shown.

[0035] Figure 6 A schematic cross-sectional view of another storage device according to some aspects of this disclosure is shown.

[0036] Figure 7 A block diagram is shown of a first semiconductor structure and a second semiconductor structure after they are bonded together in a face-to-face orientation to form a semiconductor device, according to some aspects of this disclosure.

[0037] Figure 8 It shows in Figure 7 A schematic cross-sectional view of a portion of a semiconductor device having bonding pad pairs in a hybrid bonding layer, showing the alignment deviation Dd of the design.

[0038] Figure 9 A schematic top view of a bonding pad pair as an example according to this disclosure is shown.

[0039] Figure 10 A schematic cross-sectional view of a portion of a semiconductor device with two adjacent bonding pad pairs is shown, illustrating different alignment misalignment distances D1 and D2.

[0040] Figure 11A A schematic top view of two adjacent bonding pad pairs is shown, illustrating different alignment misalignment distances D1 and D2.

[0041] Figure 11B A schematic top view of two adjacent bonding pad pairs is shown, illustrating the different alignment deviation vectors V1 and V2, as well as the vector difference VD.

[0042] Figures 12A to 12E A schematic top view of five example arrangements of bonding pad pairs according to other examples of this disclosure is shown.

[0043] Figure 13A simplified schematic cross-sectional view of a first semiconductor structure and a second semiconductor structure bonded together in a face-to-face orientation to form a chain in a semiconductor device is shown, wherein adjacent bonding pad pairs are interconnected through a substrate.

[0044] Figure 14 A simplified schematic cross-sectional view of a first semiconductor structure and a second semiconductor structure bonded together in a face-to-face orientation to form a chain in a semiconductor device is shown, wherein adjacent bonding pad pairs are interconnected through an interconnect layer.

[0045] Figure 15 A flowchart of a method for manufacturing semiconductor devices is shown. Detailed Implementation

[0046] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0047] It should be noted that references to "an embodiment," "embodiment," "example embodiment," "some embodiments," "example," etc., in the specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same example. Moreover, when describing a specific feature, structure, or characteristic in conjunction with examples, the implementation of such feature, structure, or characteristic in conjunction with other examples, whether explicitly described or not, is within the knowledge of those skilled in the art.

[0048] The terminology used in this disclosure is generally understood, at least in part, based on its use in the context. For example, depending at least in part on the context, the term “one or more” as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a,” “an,” or “the” may also be understood to convey either singular or plural use, depending at least in part on the context. Furthermore, the term “based on” may be understood to not necessarily be intended to convey an exclusive set of factors, and alternatively may allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0049] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also includes “on” with intermediate features or layers in between. Furthermore, “above” or “on top of” means not only “above” or “on top of” but also “above” or “on top of” without any intermediate features or layers (i.e., directly on).

[0050] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or feature shown in the figures and another element(s) or feature(s). These spatial relative terms are intended to cover different orientations of the device in use or process steps other than the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein will be interpreted accordingly.

[0051] As used herein, the term "layer" refers to a portion of material comprising an area of ​​thickness. A layer may extend over the entire underlying or overlying structure, or may have a extent smaller than the underlying or overlying structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where pads, interconnects, and / or vertical interconnect pathways (VIAs) are formed), and one or more dielectric layers.

[0052] In this disclosure, the term "horizontal / horizontally / lateral" refers to a lateral surface that is nominally parallel to the substrate. In this disclosure, the term "each" does not necessarily mean "each of all" but may also mean "each of a subset".

[0053] As used in this article, a “wafer” is a piece of semiconductor material into which semiconductor devices are built and / or on which semiconductor materials may undergo various processes before being diced into dies.

[0054] Although terms such as first, second, third, etc., may be used to describe different constituent elements, such constituent elements are not limited by these terms. These terms are only used to distinguish one constituent element from other constituent elements in the specification. These terms are not intended to order the constituent elements or / or the order of their manufacturing processes.

[0055] In the accompanying drawings, for ease of description, an XYZ orthogonal coordinate system is used, where the Z direction defines the stacking direction along which the first and second semiconductor structures are stacked. The X and Y directions are orthogonal to the Z direction and are also referred to as lateral directions.

[0056] Figure 1 A block diagram of an exemplary system with storage devices according to some aspects of this disclosure is shown. System 10 can represent a wide variety of electronic devices, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle control units, game consoles, printers, navigation systems, wearable electronic devices, smart sensors, virtual reality (VR) headsets, augmented reality (AR) devices, or other suitable devices with integrated storage devices. Figure 1 As shown, system 10 includes a host 20 and a memory system 30, which consists of one or more memory devices 34 and a memory controller 32. The host 20 can be any processor within an electronic device, including a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP), which communicates with the memory system 30 to send or retrieve data.

[0057] The storage device 34 may include various types of memory, such as NAND flash memory, vertical NAND flash memory, DRAM, ferroelectric RAM (FRAM), magnetoresistive RAM (MRAM), phase-change RAM (PCRAM), resistive RAM (RRAM), and nanoRAM (NRAM).

[0058] The memory controller 32 connects the storage device 34 to the host 20 and is responsible for managing memory operations. It controls data read, erase, and write operations and performs tasks such as bad block management, garbage collection, logical-to-physical address mapping, and wear leveling. In some embodiments, the memory controller 32 is designed to operate in low-duty-cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 32 is designed to operate in high-duty-cycle environments, such as SSDs or embedded multi-media cards (eMMCs) used as data storage devices in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. The memory controller 32 can be configured to control the operation of the storage device 34, such as read, erase, and program operations. The memory controller 32 can also be configured to manage various functions related to data stored or to be stored in the storage device 34, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0059] In some implementations, the memory controller 32 is further configured to process error correction codes (ECCs) for data read from or written to the storage device 34. The memory controller 32 may also perform any other suitable function, such as formatting the storage device 34. The memory controller 32 may communicate with external devices (e.g., host 20) according to specific communication protocols. For example, the memory controller 32 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnection (PCI), PCI-Express (PCI-express, PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0060] Figure 2 An illustration of an exemplary memory card having a storage device according to some aspects of this disclosure is shown. Figure 2 As shown, the memory controller 32 and storage devices 34 can be packaged together in a single memory card 40, which can be a PCMCIA card, CF card, smart media card, Memory Stick, MMC, SD card, UFS card, etc. The memory card 40 includes a connector 42 for interfacing with a host device. The memory controller 32 and one or more storage devices 34 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 30 can be implemented and packaged into different types of end electronic products. Figure 2 In one example shown, the memory controller 32 and a single storage device 34 may be integrated into the memory card 40. The memory card 40 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 40 may also include a connection between the memory card 40 and a host computer (e.g., Figure 1 The memory card connector 42 is coupled to the host 20.

[0061] Figure 3 An illustration of an exemplary solid-state drive (SSD) with storage devices according to some aspects of this disclosure is shown. Figure 3 In another configuration shown, the memory controller 32 and multiple storage devices 34 may be integrated into a solid-state drive (SSD) 50, which includes an SSD connector 52 for connection to a host interface. Compared to memory cards, SSDs typically offer higher capacity and faster data transfer speeds.

[0062] Figure 4 A schematic diagram of an exemplary storage device including peripheral circuitry is shown, according to some aspects of this disclosure. Storage device 60 may be... Figure 1 An example of memory device 34 is shown. Memory device 60 may include a memory cell array 62 and peripheral circuitry 64 coupled to the memory cell array 62. The memory cell array 62 may be a NAND flash memory cell array, wherein the memory cells are provided in the form of an array of NAND memory strings 66, each memory string extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 66 includes a plurality of memory cells coupled in series and stacked vertically. Each memory cell may hold a continuous analog value, such as voltage or charge, which depends on the number of electrons trapped in the region of the memory cell. Each memory cell may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trap type memory cell including a charge-trap transistor.

[0063] In some implementations, each memory cell is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each memory cell is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell, three bits per cell (also called a triple-level cell (TLC)), or four bits per cell (also called a quad-level cell (QLC)). Each MLC can be programmed to present a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erase state to present one of the three possible programming levels by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used in the erase state.

[0064] like Figure 4 As shown, peripheral circuitry 64 can be coupled to the memory cell array via bit lines (BL), word lines (WL), source select gates (SSG), and drain select gates (DSG). The peripheral circuitry can include any suitable analog, digital, and mixed-signal circuitry for facilitating associated operation of the memory cell array by applying voltage and / or current signals to each target memory cell via bit lines, word lines, sources, SSGs, or DSGs, and by sensing voltage and / or current signals from each target memory cell. Furthermore, the peripheral circuitry can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. Peripheral circuitry 64 can include components such as page buffers, row and column decoders, sense amplifiers, word line drivers, input / output (I / O) circuitry, voltage generators or regulators, charge pumps, control logic, registers, interfaces, data buses, and various active or passive components, including transistors, resistors, diodes, capacitors, or sub-circuits thereof.

[0065] Figure 5 A schematic cross-sectional view of a semiconductor device 100 according to some aspects of this disclosure is shown. Figure 6A schematic cross-sectional view of another semiconductor device 101 according to some aspects of this disclosure is shown. Semiconductor devices 100 or 101 may each include a first semiconductor structure 102 and a second semiconductor structure 104 stacked together. The first semiconductor structure 102 and the second semiconductor structure 104 may be fabricated on separate substrates and then bonded to form an integrated device.

[0066] For example, the first semiconductor structure 102 is a memory cell array, and the second semiconductor structure 104 is peripheral circuitry. This peripheral circuitry is configured to support memory operations and may include digital, analog, or mixed-signal circuitry. In some embodiments, the peripheral circuitry is formed using CMOS technology with advanced logic process nodes (e.g., from 90nm to 2nm). The memory cell array may consist of memory cells implemented using switching and selection transistors. While a DRAM cell array is used as a representative example for illustrative purposes, other memory technologies may be used in other embodiments. In some embodiments, when hybrid bonding is applied to the memory array and peripheral circuitry, the memory array may also include a NAND flash memory array or other types of non-volatile memory arrays. These non-volatile memory arrays include phase-change memory (PCM), static random-access memory (SRAM), ferroelectric RAM (FRAM), resistive RAM (RRAM), magnetic RAM (MRAM), spin-transfer torque (STT) memory arrays, or combinations thereof. A common architecture is the one-transistor-one-capacitor (1T1C) cell. Depending on the specific DRAM architecture, other cell structures may also be used, such as one-transistor-zero-capacitor (1T0C), one-transistor-multiple-capacitor (1TnC), or two-transistor-multiple-capacitor (2TnC) configurations. In some embodiments, hybrid bonding can be applied to multi-chip stacking scenarios, such as high-bandwidth memory (HBM) or hybrid bonding flash memory (HBF). In this case, multiple chips can be stacked, each including both a memory array and associated peripheral circuitry, forming a hybrid bond between the stacked chips. In some embodiments, a hybrid bond can be formed between memory chips and logic control chips, thereby achieving efficient integration of memory and logic functions within a single package. This disclosure is not limited to the specific examples described herein, but is broadly applicable to various hybrid bonding applications involving memory arrays, peripheral circuitry, and chip stacking technologies.

[0067] Furthermore, the spatial orientation of the first semiconductor structure 102 and the second semiconductor structure 104 is defined relative to the X-axis, Y-axis, and Z-axis, such as... Figure 5 and Figure 6 As shown. For each of semiconductor structures 102 and 104, semiconductor device 100 or 101 has two lateral surfaces in the XY plane: a top surface on the substrate where the device is formed, and a bottom surface on the back side of the substrate. The Z-axis extends perpendicular to the XY plane. In this context, terms such as “above,” “below,” or “up” refer to the position along the Z-axis relative to the substrate located at the bottommost layer of the device. This directional terminology is used consistently throughout the disclosure.

[0068] like Figure 5 As shown, a first semiconductor structure 102 and a second semiconductor structure 104 are bonded at a bonding interface 106. The bonding interface 106 is located between the first structure 102 and the second structure 104. This vertical stacking method allows the two structures to be fabricated independently, enabling parallel manufacturing. The bonding interface 106 includes a number of interconnects (e.g., bonding pads) to enable short-distance, high-speed communication between the two structures. In contrast, traditional chip-to-chip connections on a circuit board are typically longer and slower. The vertical integration of these layers not only minimizes data path latency and power consumption but also enables more compact chip sizes and higher memory densities. In some embodiments, the interconnects at the bonding interface facilitate signal transmission between the memory array and peripheral circuitry.

[0069] The vertical arrangement of the two semiconductor structures 102 and 104 can be flexible. For example, Figure 6 Semiconductor device 101 is an alternative configuration of semiconductor device 100. In semiconductor device 101, a second semiconductor structure 104, including peripheral circuitry, is positioned on top of a second semiconductor structure 102. This semiconductor structure includes an array of memory cells of the first semiconductor structure 102. Although the stacking order is reversed, the two layers are still vertically bonded through a bonding interface 106. This interface is established using a hybrid bonding technique. Hybrid bonding allows for direct dielectric-to-dielectric and metal-to-metal contacts and is often referred to as metal / dielectric hybrid bonding. This method avoids intermediate materials such as solder or adhesives and supports copper-to-copper and silicon oxide-to-silicon oxide bonding.

[0070] exist Figures 5 to 6 In both configurations, data or control communication between the storage cell array and the peripheral circuitry occurs through the bonding interface 106.

[0071] Figure 7A block diagram is shown of a first semiconductor structure 102 (e.g., a memory cell array) and a second semiconductor structure 104 (e.g., peripheral circuitry) according to some aspects of this disclosure, after being bonded together in a face-to-face orientation to form a semiconductor device 101. The first semiconductor structure 102 includes a first substrate 105, a memory array 107, a first interconnect layer 108, and a first hybrid bonding layer 112 (or first bonding layer 112). The semiconductor structure 104 includes a second substrate 116, peripheral circuitry 118, a second interconnect layer 120, and a second hybrid bonding layer 122 (or second bonding layer 122). These layers are as follows... Figure 7 The semiconductor structures are stacked together as shown. The first semiconductor structure 102 includes a first bonding pad (not shown), and the second semiconductor structure 104 includes a second bonding pad (not shown). Figure 7 In this bonding configuration, one or more first bonding pads of the hybrid bonding layer 112 are electrically contacted, for example, via hybrid bonding, one or more corresponding second bonding pads of the second hybrid bonding layer 122. Additional details of the first and second bonding pads are described below.

[0072] Hybrid bonding typically refers to wafer-level or die-level bonding techniques that combine dielectric-to-dielectric bonding and metal-to-metal bonding within the same interface. In this process, interlayer dielectrics (e.g., oxides) can be contacted and bonded, and direct metal connections (e.g., copper-to-copper) can be formed across the bonding interface. Compared to conventional bonding methods such as thermoforming or solder-based bonding, this method enables fine-pitch interconnects, reduces parasitics, and improves electrical and mechanical properties.

[0073] Bonding layers 112 or 122 may include multiple bonding contact structures embedded in the dielectric layer. The bonding contact structures include metal lines, vias, and bonding pads. The dielectric layer may include one or more layers of dielectric material.

[0074] It should be noted that Figures 6 to 7 The orientation of the semiconductor device 101 shown (i.e., the first semiconductor structure at the bottom and the second semiconductor structure at the top) is illustrative and not limiting. That is, the semiconductor device 101 can be oriented such that the second semiconductor structure 104 is at the bottom with bonding layer 122 as its top layer, and the first semiconductor structure 102 is at the top with bonding layer 112 as its bottom layer. In this alternative orientation, a memory array is located in the top portion of the semiconductor device 101. In various manufacturing processes, after the first and second semiconductor structures are bonded together, the substrate can be partially or completely removed from at least one of the two semiconductor structures, and a new semiconductor layer can be formed on that structure.

[0075] Figure 8 It shows a feature embedded in Figure 7A schematic cross-sectional view of a portion of a semiconductor device 100 or 101, showing bonding pad pairs in hybrid bonding layers 112 and 122. Semiconductor device 100 or 101 includes a first semiconductor structure 102 and a second semiconductor structure 104. In some embodiments, the first semiconductor structure 102 includes a first interconnect layer 108 and a first bonding layer 112. The first bonding layer 112 includes a first dielectric bonding region 112a. A first bonding pad 124 is formed in the first bonding layer 112. In some embodiments, the second semiconductor structure 104 includes a second interconnect layer 120 and a second bonding layer 122. The second bonding layer 122 includes a second dielectric bonding region 122a. A second bonding pad 126 is formed in the second bonding layer 122. Bonding pads 124 and 126 may have various shapes at the bonding interface 106.

[0076] In some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 are bonded, and the first bonding pad 124 and the second bonding pad 126 are electrically connected via direct contact. Bonding can occur in a face-to-face configuration, where the active layers or metallization layers of the two structures are aligned and bonded. In such a configuration, the first bonding pad 124 and the corresponding second bonding pad 126 together form a bonding pad pair. In some embodiments, the first bonding pad 124 and the second bonding pad 126 may form an aligned bonding pad pair (not shown), i.e., the first bonding pad 124 and the second bonding pad 126 completely overlap.

[0077] In some embodiments, such as Figure 8 As shown, the first bonding pad 124 and the second bonding pad 126 can form an misaligned bonding pad pair. The misaligned bonding pad pair has a designed alignment deviation Dd between the first bonding pad 124 and the second bonding pad 126. Because the first bonding pad 124 and the second bonding pad 126 are in direct electrical contact, the resistance of the bonding pad pair varies with the contact area between the pads. As the alignment deviation increases, the overlapping contact area decreases, which leads to an increase in the resistance of the bonding pad pair. Conversely, as the overlapping area increases, the resistance decreases. This correlation between contact area and resistance allows the measurement of the designed alignment deviation Dd, and the resistance thus detected reflects the alignment deviation between the first semiconductor structure 102 and the second semiconductor structure 104.

[0078] The designed alignment deviation Dd can be intentionally designed to be larger than conventional bonding tolerances, enabling effective detection of alignment deviations in the bonded pad pair. For example, the designed alignment deviation Dd can be greater than one-tenth of the critical dimension of the first bonded pad 124 or the second bonded pad 126, or greater than one-tenth of the diameter of the first bonded pad 124 or the second bonded pad 126 when the first bonded pad 124 or the second bonded pad 126 is circular. In some examples, the designed alignment deviation Dd can be from one-tenth to eight-tenths of the critical dimension of the first bonded pad 124 or the second bonded pad 126. This alignment deviation in the bonded pad pair 114 is intentionally designed to enhance the detection of potential misalignments during the bonding process, because the predetermined alignment deviation amplifies any alignment deviations that may occur during bonding.

[0079] In some embodiments, the alignment deviation Dd of the design may exceed the alignment tolerance. For example, the alignment tolerance may be defined as 60% of the diameter of a bonding pad having a circular shape. In this case, misaligned bonding pad pairs may not form sufficient electrical connections, also reflecting the alignment deviation between the first semiconductor structure 102 and the second semiconductor structure 104.

[0080] In some embodiments, the alignment deviation of bonding pads 124 and 126 may alternatively be detected by measuring capacitance. The capacitance between the first bonding pad 124 and the second bonding pad 126 is determined by the overlap contact area and the spacing between the first bonding pad 124 and the second bonding pad 126. As the alignment deviation Dd of the design increases, the overlap area decreases, which results in a decrease in capacitance. Conversely, as the overlap area increases, the capacitance increases accordingly. Therefore, the change in capacitance provides another way to determine the alignment deviation Dd of the design and thus the relative alignment between the first semiconductor structure 102 and the second semiconductor structure 104.

[0081] The designed alignment deviation Dd can be the distance from the center of the first bonding pad 124 to the center of the second bonding pad 126. The center can be the geometric center of the respective bonding pad 124 or 126. For example, for a bonding pad with a rectangular or square shape at the bonding interface 106, the center is the intersection of the diagonals. For a bonding pad with a circular shape, the center is the center of the circle. The designed alignment deviation Dd can extend in any direction along the XY plane of the bonding interface 106.

[0082] In an alternative embodiment, the bonding pads form an alignment deviation vector that indicates the alignment deviation between the first bonding pad 124 and the corresponding second bonding pad 126, for example from the center of the first bonding pad 124 to the center of the second bonding pad 126, or from the edge of the first bonding pad 124 to the corresponding edge of the second bonding pad 126.

[0083] In some embodiments, a first bonding layer 112 of the first semiconductor structure 102 includes first bonding pads 124 disposed therein. A first interconnect layer 108 including interconnects is also shown. In this exemplary embodiment, one or more first bonding pads 124 may be electrically contacted with interconnects of the first interconnect layer 108. Interconnects from the first interconnect layer 108 provide electrical pathways from, for example, a memory array of the first semiconductor structure 102 to one or more first bonding pads 124. Similarly, a second bonding layer 122 of the second semiconductor structure 104 may include second bonding pads 126 disposed therein. The second semiconductor structure 104 also includes a second interconnect layer 120 including interconnects. In this exemplary embodiment, one or more second bonding pads 126 may be electrically contacted with interconnects of the second interconnect layer 120. Interconnects from the second interconnect layer 120 provide electrical pathways from, for example, peripheral circuitry of the second semiconductor structure 104 to one or more second bonding pads 126.

[0084] In some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 may each include a dielectric bonding region 112a or 122a. In some embodiments, the dielectric bonding regions 112a and 122a are located in the first bonding layer 112 and the second bonding layer 122, respectively. In some embodiments, the dielectric material in the dielectric bonding regions may include carbon-doped silicon nitride (SiCN). For example, the dielectric bonding regions 112a or 122a may each have a multilayer structure. The multilayer structure may include a SiCN layer at the bonding interface 106. In some embodiments, the first semiconductor structure 102 and the second semiconductor structure 104 may be connected (bonded) via the dielectric bonding regions 112a and 122a.

[0085] In some embodiments, semiconductor device 100 includes, for example, a first semiconductor structure 102 and a second semiconductor structure 104 bonded at a bonding interface 106 via a hybrid bonding process. In some examples, the first semiconductor structure 102 and the second semiconductor structure 104 are of the same type. In some examples, semiconductor device 101 includes a NAND stack, i.e., a stack of NAND flash memory. In some examples, both the first semiconductor structure 102 and the second semiconductor structure 104 include NAND flash memory. In some examples, the first semiconductor structure 102 and the second semiconductor structure 104 are of different types. In one example, one of the first semiconductor structure 102 and the second semiconductor structure 104 may include NAND flash memory, and the other may be a substrate die. In yet another example, the first semiconductor structure 102 includes peripheral circuitry, and the second semiconductor structure 104 includes a memory array structure (such as a memory array chip), or vice versa.

[0086] Figure 9 A schematic top view of an example bonding pad pair according to this disclosure is shown. Semiconductor device 100 or 101 may include multiple functional blocks in a main chip, multiple main chip test pads, and a sealing ring 660. (As...) Figure 9 As shown, in some embodiments, semiconductor device 100 or 101 further includes a first chain 111a including a first bonding pad pair and a second chain 111b including a first bonding pad pair. In some examples, each bonding pad pair in the first bonding pad pair 114 is formed by a first bonding pad 124 disposed in a first semiconductor structure and a corresponding second bonding pad 126 disposed in a second semiconductor structure. Adjacent first bonding pad pairs 114 in the first chain 111a or the second chain 111b may be electrically coupled via conductive paths within the first and second semiconductor structures. The first bonding pad 124 and the second bonding pad 126 may form misaligned pad pairs, such as... Figure 9 As shown. Figure 8 As shown, the alignment deviation between the first bonding pad 124 and the second bonding pad 126 is intentionally designed as a designed alignment deviation Dd, and... Figures 8 to 9 No bonding alignment deviation is shown in the data.

[0087] In some embodiments, a second bonding pad pair is provided at a location adjacent to the first bonding pad pair 114 in the first chain 111a. This second pad pair is not part of the first chain 111a, but is located nearby. The second bonding pad pair includes a third bonding pad formed in the first semiconductor structure 102 and a fourth bonding pad formed in the second semiconductor structure 104. The third and fourth bonding pads are bonded together.

[0088] In some embodiments and Figure 10 and Figure 11A The diagram further illustrates that the first alignment deviation distance between the first bonding pad 124 and the second bonding pad 126 is greater than the second alignment deviation distance between the third bonding pad and the fourth bonding pad. This relative difference in alignment deviation between adjacent pad pairs after the bonding process can further facilitate the identification of non-uniform displacement across the bonding interface. This enables the detection of tilting or rotational alignment deviation trends that may not be apparent from individual pad pairs, thereby improving the accuracy of characterizing overall alignment.

[0089] In some examples, semiconductor device 100 or 101 may include multiple segments that are not connected to each other. Each segment includes a separate chain. For example, a first chain 111a includes multiple first bonding pad pairs 114, and a second chain 111b includes multiple first bonding pad pairs 114, such as... Figure 9As shown. In other examples, a plurality of first bonding pad pairs 114 in the first chain 111a may be aligned along a predetermined wiring path and connected in series to form a chain-like test or signal path. In some embodiments, a group of adjacent first bonding pad pairs 114 in the first chain 111a may be connected in parallel. In some embodiments, multiple groups of such parallel-connected first bonding pad pairs 114 may be connected in series.

[0090] In some examples, a second chain 111b is presented, and multiple pairs of first bonding pads are part of the second chain 111b. Each of the first chain 111a or the second chain 111b includes the same direction along the XY plane (e.g., approximately along...). Figure 9 The first bond pad pairs (within the Y direction of the chain) have alignment misalignment. The first bond pad pairs within each chain 111a or 111b are connected in series, and the first chain 111a and the second chain 111b are electrically isolated from each other. In some examples, the alignment misalignment direction of the first chain 111a is perpendicular to the alignment misalignment direction of the second chain 111b. In some examples, the alignment misalignment direction of the first chain 111a is opposite to the alignment misalignment direction of the second chain 111b. In some examples, the electrical connection between the bond pad pairs in the first chain 111a or the second chain 111b can be connected in series (e.g., for resistance measurement), can be connected in parallel, or can be arranged using alternative connection schemes, provided that the measured electrical parameter exhibits a correlation with the bond alignment accuracy. Therefore, the configuration of the bond pad chains can be adapted to different test methods, such as resistance, capacitance, or signal integrity measurements, depending on design requirements and the sensitivity to detection of alignment misalignment.

[0091] In some embodiments, all first bonding pad pairs 114 may be connected in series to form a single continuous test chain. In some embodiments, the bonding pad pairs 114 may be divided into multiple segments of the test chain. Each segment of the test chain includes bonding pad pairs having the same alignment misalignment direction, and the pad pairs within a segment are connected in series while different segments remain electrically isolated. During alignment misalignment testing, if the resistance of any segment exceeds a predetermined threshold, it can be determined that the chip is misaligned.

[0092] In some examples, adjacent first bonding pad pairs 114 in the first chain 111a are electrically connected. In some examples, this connection is achieved through a first interconnect layer 108 and a second interconnect layer 120. In some examples, the first interconnect layer 108 in the first semiconductor structure 102 connects to the first bonding pad 124, and the second interconnect layer 120 in the second semiconductor structure 104 connects to the second bonding pad 126. Similarly, adjacent second bonding pad pairs can be electrically connected through the first interconnect layer 108 in the first semiconductor structure 102 that connects to the third bonding pad and the second interconnect layer 120 in the second semiconductor structure 104 that connects to the fourth bonding pad, or adjacent third bonding pad pairs can be electrically connected through the first interconnect layer 108 in the first semiconductor structure 102 that connects to the fifth bonding pad and the second interconnect layer 120 in the second semiconductor structure 104 that connects to the sixth bonding pad.

[0093] In some examples, either of bonding pads 124 and 126 may be located in the peripheral portion. While the first bonding pad 124 and the second bonding pad 126 located in the peripheral portion may be misaligned, e.g., aligned pad pairs, other sets of bonding pads located in the inner portion may be adequately aligned to form reliable electrical contacts, e.g., aligned pad pairs. It should be understood that the inner portion shown herein may be closer to the geometric center of semiconductor device 100 or 101 (and / or the geometric center of first semiconductor structure 102 and second semiconductor structure 104) than the peripheral portion. The peripheral portion may be closer to the outer edge of semiconductor device 100 or 101 (and / or the geometric center of first semiconductor structure 102 and second semiconductor structure 104) than the inner portion. In some examples, the first bonding pad pair may be located between the sealing ring 660 and the second bonding pad pair. In some examples, the second bonding pad pair may be located between the first bonding pad pair and the third bonding pad pair.

[0094] As described above, the first semiconductor structure 102 may include a first semiconductor component (e.g., memory array 107), and the second semiconductor structure 104 may include a second semiconductor component (e.g., peripheral circuitry 118), with the first semiconductor component connected to the second semiconductor component via a second bonding pad pair. The multiple functional blocks in the main chip may be transistors such as complementary metal-oxide-semiconductor transistors, metal-oxide-semiconductor field-effect transistors, fin field-effect transistors, or combinations thereof. These multiple functional blocks can work together to provide various functions, such as logic, I / O, memory, analog circuitry, etc.

[0095] Figure 10 A schematic cross-sectional view of a portion of a semiconductor device 100 or 101 with two adjacent bonding pad pairs is shown, illustrating different alignment misalignment distances D1 and D2. Figure 11AA schematic top view of two adjacent bonding pad pairs is shown, illustrating different alignment misalignment distances D1 and D2. Figures 10 to 11A The alignment misalignment relationship between two adjacent bonding pad pairs caused by alignment misalignment between the first semiconductor structure 102 and the second semiconductor structure 104 is further illustrated. In some embodiments, bonding pads 124 and 126 in the first and second bonding pad pairs have comparable physical dimensions (e.g., similar diameters in the XY plane), but these bonding pad pairs exhibit different levels of alignment misalignment. In some examples, a first alignment misalignment distance D1 and a second alignment misalignment distance D2 can be detected after the bonding process. In some examples, the first alignment misalignment distance D1 between the first bonding pad 124 and the second bonding pad 126 of the first bonding pad pair is greater than the second alignment misalignment distance D2 between adjacent first bonding pads 124 and adjacent second bonding pads 126 of the second bonding pad pair. The detected different levels of alignment misalignment provide a benchmark for comparison, which improves detection accuracy by distinguishing between systematic offsets and random variations. This comparative measurement enables calibration of alignment across a wider bonding interface, improves yield by identifying local alignment misalignment defects, and facilitates process optimization by mapping alignment uniformity across multiple bonding pad pairs. Therefore, the reliability of semiconductor devices 100 or 101 is improved.

[0096] Figure 11B A schematic top view of two adjacent bond pad pairs is shown, illustrating the different alignment deviation vectors V1 and V2, and the vector difference VD. In some examples, such as in... Figure 11BIn this configuration, a first pair of bonded pads forms a first alignment deviation vector V1, which indicates a first alignment deviation between the first bonded pad and its corresponding second bonded pad. A second pair of bonded pads forms a second alignment deviation vector V2, which indicates a second alignment deviation between the third and fourth bonded pads. The vector difference VD between the first alignment deviation vector V1 and the second alignment deviation vector V2 is not zero. In some examples, the vector length of the vector difference VD between the first alignment deviation vector V1 and the second alignment deviation vector V2 is greater than zero. Such a first alignment deviation vector V1 or second alignment deviation vector V2 may, for example, be formed from the center of the first or third bonded pad to the center of the second or fourth bonded pad, or from the edge of the first or third bonded pad to the corresponding edge of the second or fourth bonded pad. The use of alignment deviation vectors provides another two-dimensional analysis of displacement, thereby allowing the identification of both the magnitude and direction components of the alignment deviation. This vector approach improves alignment characterization, facilitates the detection of rotational or angular alignment deviations, and provides more comprehensive data for process control and yield optimization. The first alignment deviation distance D1, or the first alignment deviation vector, extends in the XY plane corresponding to the bonding interface where the first bonding pad 124 and the second bonding pad 126 are bonded together.

[0097] In some embodiments, the first difference may be defined as the difference between a first alignment deviation distance D1 (between the first and second bonding pads) and a second alignment deviation distance D2 (between the third and fourth bonding pads). In some examples, the first difference between the first alignment deviation distance D1 and the second alignment deviation distance D2 is greater than 5%-15% of the diameter of either bonding pads 124 and 126 in the XY plane, or the first difference is greater than 10% of the diameter of either bonding pads 124 and 126 in the XY plane. In some examples, the first alignment deviation distance D1 is greater than or equal to 60% of the diameter of either bonding pads 124 and 126 in the XY plane, and the second alignment deviation distance D2 is less than 60% of the diameter of either bonding pads 124 and 126 in the XY plane. In some examples, a first alignment misalignment distance D1 is greater than or equal to 50% of the diameter of either bonding pads 124 and 126 in the XY plane, and a second alignment misalignment distance D2 is less than 50% of the diameter of either bonding pads 124 and 126 in the XY plane. In some examples, a first alignment misalignment distance D1 is greater than or equal to 70% of the diameter of either bonding pads 124 and 126 in the XY plane, and a second alignment misalignment distance D2 is less than 70% of the diameter of either bonding pads 124 and 126 in the XY plane. In some examples, the first difference, the first alignment misalignment distance D1, or the second alignment misalignment distance D2 may be compared with the average diameter of either bonding pads 124 and 126, the maximum size of either bonding pads 124 and 126, the minimum size of either bonding pads 124 and 126, or a combination thereof.

[0098] In some embodiments, the device further includes a third pair of bonding pads that is not part of the first chain and is positioned adjacent to the second pair of bonding pads. The third pair of bonding pads includes a fifth bonding pad disposed in the first semiconductor structure 102 and a sixth bonding pad disposed in the second semiconductor structure 104. The fifth and sixth bonding pads may be bonded together across a bonding interface. A third alignment deviation distance D3 is defined as the lateral offset between the center points of the fifth and sixth bonding pads. Similar to the first and second pad pairs, the third pair of bonding pads may have comparable physical pad geometries (e.g., shape and size) to facilitate controlled comparison of alignments across multiple pairs.

[0099] In some embodiments, the third bonding pad pair has a third alignment deviation vector, and the vector difference between the first alignment deviation vector and the second alignment deviation vector is greater than the vector difference between the third alignment deviation vector and the second alignment deviation vector in terms of vector length. Here, the vector difference can be defined as the length of the vector between the corresponding alignment deviation vectors.

[0100] In some embodiments, the first difference is defined as the difference between a first alignment misalignment distance D1 and a second alignment misalignment distance D2. The second difference is defined as the difference between a third alignment misalignment distance D3 and a second alignment misalignment distance D2. The first difference may be greater than the second difference. For example, this configuration helps diagnose alignment or deformation modes across the bonding interface under edge loading or thermal expansion effects during hybrid bonding processes.

[0101] Figures 12A to 12E A schematic top view shows five example arrangements of bond pad pairs according to other examples of this disclosure. In some exemplary embodiments, such as Figure 9 As shown, multiple first bonding pad pairs 114 can follow a consistent pattern in terms of area, shape, and positioning. For example, the pad pairs can be symmetrically distributed along the periphery of the semiconductor structure, wherein each bonding pad pair has uniform geometry (such as diameter), a consistent shape (e.g., circular or square), and uniform spacing.

[0102] However, this disclosure is not limited to such a uniform configuration. In other embodiments, such as Figures 12A to 12E As shown, variations in the number, arrangement, size, or shape of bonding pad pairs can be achieved. In one example, such as Figure 12A As shown, the number of pad pairs is reduced to suit devices with simplified testing or limited surface area. Figure 12B The diagram shows a configuration in which bonding pad pairs are arranged in an alternating pattern between internal and external locations, which allows for improved sensitivity to the detection of alignment deviations across different chip regions. Figure 12C Pad pairs with inconsistent sizes are shown to evaluate alignment behavior at different feature scales. In another example, Figure 12D A structure is shown in which the circular arrangement of bonding pad pairs is divided into multiple shorter chains, enabling local or partition alignment evaluation. Figure 12E Pairs of pads with different geometries are shown, such as combinations of circular and square pads, which allows for multidimensional alignment testing within the same structure.

[0103] Figures 12A to 12E These variations offer flexibility in chip layout and bonding interface design while still supporting the alignment characterization techniques disclosed herein. The architecture remains applicable regardless of the specific number or layout of pad pairs, as long as a measurable correlation exists between test parameters and bonding alignment accuracy.

[0104] Figures 13 to 14A schematic cross-sectional view of an example of a first chain 111a is shown. In these embodiments, each chain 111a or 111b may include any combination of the following: a first bonding pad pair 114, a first substrate 105 of the first semiconductor structure 102 and a second substrate 116 of the second semiconductor structure 104, a first interconnect layer 108 of the first semiconductor structure 102 and a second interconnect layer 120 of the second semiconductor structure 104, and an element connecting any two of the foregoing. Adjacent first bonding pad pairs 114 in the first chain 111a may be electrically coupled via an interconnect layer near the bonding interface or via a conductive path within either the first or second semiconductor structure, such that the bonding pad pairs in the first chain can be connected in series. In some examples, the first chain 111a of bonding pad pairs may be formed by physically non-adjacent bonding pad pairs. For example, the bonding pad pairs in chain 111a are not necessarily connected in a manner of direct physical proximity; one or more pad pairs may be intentionally skipped between connected pad pairs. In some embodiments, the bonding pad pairs in the first chain 111a may be connected in parallel, or the bonding pad pairs in the first chain 111a may be partially disconnected. Alignment misalignment between the bonding pad pairs is not... Figures 13 to 14 This is shown in detail in the text.

[0105] Figure 13 A simplified schematic cross-sectional view is shown of a chain 111a or 111b formed in semiconductor device 100 or 101 by bonding a first semiconductor structure 102 and a second semiconductor structure 104 in a face-to-face orientation. In this example, adjacent first bonding pad pairs 114 are interconnected via a first substrate 105 of the first semiconductor structure 102 and / or a second substrate 116 of the second semiconductor structure 104. Such substrate-level interconnect paths can be used to transmit electrical signals between bonding pad pairs or to form continuous conductive chains for testing or alignment verification purposes.

[0106] Figure 14 Another simplified schematic cross-sectional view of another chain 111a or 111b in semiconductor device 100 or 101 is shown. In this embodiment, adjacent first bonding pad pairs 114 are interconnected via a first interconnect layer 108 and a second interconnect layer 120 within a first semiconductor structure 102 or a second semiconductor structure 104. This configuration allows electrical signals to be transmitted via predefined metal paths formed in the interconnect stack, thereby supporting more flexible signal linking and compatibility with complex multilayer metallization architectures.

[0107] refer to Figure 15According to some embodiments of this disclosure, a method 200 for manufacturing a semiconductor device 100 or 101 is provided. Method 200 includes operation 210, which involves forming a first semiconductor structure 102 including a plurality of first bonding pads 124 and at least one second bonding pad 126. The method further includes operation 220, which involves forming a second semiconductor structure 104 including a plurality of third bonding pads corresponding to the first bonding pads 124 and a fourth bonding pad corresponding to the second bonding pads 126. The method further includes operation 230, which involves bonding the first semiconductor structure 102 onto the second semiconductor structure 104, such as through a hybrid bonding process, wherein the exposed metallized surfaces of the corresponding bonding pads are aligned and joined to form conductive vias across bonding interfaces 106. In some embodiments, the first bonding pads 124 and the second bonding pads 126 are aligned and bonded together to form a pair of first bonding pads 114. Then, the first bonding pad pair 114 are connected to each other through internal conductive paths within the first semiconductor structure 102 or the second semiconductor structure 104, thereby forming a first chain 111a. This chain can be used as a test path or signal transmission path for evaluating bonding alignment or electrical continuity.

[0108] In some embodiments, the third bonding pad in the first semiconductor structure 102 and the fourth bonding pad in the second semiconductor structure 104 may be aligned and bonded together to form a second bonding pad pair. The second bonding pad pair may not belong to the first chain 111a, but may be positioned adjacent to at least one first bonding pad pair in the first chain 111a. In some embodiments, the second bonding pad pair belongs to the second chain 111b. In some embodiments, a first alignment deviation distance D1, which may be defined between the first bonding pad 124 and its corresponding second bonding pad 126, is greater than a second alignment deviation distance D2, which may be defined between the third and fourth bonding pads.

[0109] While several examples have been described and illustrated herein, those skilled in the art will readily conceive of various other ways and / or structures for performing these functions and / or obtaining these results and / or one or more advantages described herein, and each of such variations and / or modifications is considered to be within the scope of the examples described herein. More generally, those skilled in the art will readily understand that all parameters, dimensions, materials, and configurations described herein are intended as examples, and actual parameters, dimensions, materials, and / or configurations will depend on one or more specific applications using the teachings. Those skilled in the art will recognize, or can determine, many equivalents of the specific examples described herein simply by conducting routine experiments. Therefore, it should be understood that the foregoing examples are presented by way of example only, and that the examples may be practiced in ways different from the specific descriptions and claims within the scope of the appended claims and their equivalents. The examples of this disclosure relate to each individual feature, system, article of manufacture, material, kit, and / or method described herein. Furthermore, any combination of two or more such features, systems, articles of manufacture, materials, kits, and / or methods is included within the scope of this disclosure if such features, systems, articles of manufacture, materials, kits, and / or methods do not contradict each other.

Claims

1. A semiconductor device, the semiconductor device comprising: First semiconductor structure; A second semiconductor structure bonded to the first semiconductor structure; A first chain comprising a plurality of first bonding pad pairs, each first bonding pad pair comprising a first bonding pad in the first semiconductor structure and a second bonding pad in the second semiconductor structure bonded together; as well as A second bonding pad pair that does not belong to the first chain and is adjacent to at least one of the first bonding pad pairs in the first chain, the second bonding pad pair including a third bonding pad in the first semiconductor structure and a fourth bonding pad in the second semiconductor structure. Wherein, the first alignment deviation distance between the first bonding pad and the second bonding pad is greater than the second alignment deviation distance between the third bonding pad and the fourth bonding pad.

2. The semiconductor device of claim 1, further comprising a third pair of bonding pads not belonging to the first chain and adjacent to the second pair of bonding pads, the third pair of bonding pads comprising a fifth bonding pad in the first semiconductor structure and a sixth bonding pad in the second semiconductor structure, wherein, The first difference is the difference between the first alignment deviation distance and the second alignment deviation distance, the second difference is the difference between the third alignment deviation distance and the second alignment deviation distance, the third alignment deviation distance is the distance between the fifth bonding pad and the sixth bonding pad, and the first difference is greater than the second difference.

3. The semiconductor device according to claim 1, wherein, Each of the first and second bonding pad pairs has substantially the same diameter, and the difference between the first alignment deviation distance and the second alignment deviation distance is greater than one-tenth of the diameter.

4. The semiconductor device according to claim 3, wherein, The first alignment deviation distance is greater than or equal to 60 percent of the diameter, and the second alignment deviation distance is less than 60 percent of the diameter.

5. The semiconductor device according to claim 1, wherein, The first semiconductor structure and the second semiconductor structure each further include a dielectric bonding region, wherein the dielectric material in the dielectric bonding region includes carbon-doped silicon nitride.

6. The semiconductor device according to claim 1, wherein, The first bonding pad pair is located between the sealing ring and the second bonding pad pair.

7. The semiconductor device of claim 1, wherein adjacent first bonding pad pairs in the first chain are connected via a conductive path within either the first semiconductor structure or the second semiconductor structure, such that the first bonding pad pairs in the first chain are connected in series.

8. The semiconductor device according to claim 1, wherein, The adjacent first bonding pads in the first chain are connected through a first interconnect layer in the first semiconductor structure that connects the first bonding pads and a second interconnect layer in the second semiconductor structure that connects the second bonding pads.

9. The semiconductor device according to claim 1, wherein, The first semiconductor structure includes a first semiconductor component, and the second semiconductor structure includes a second semiconductor component, and the first semiconductor component is connected to the second semiconductor component via the second bonding pad pair.

10. The semiconductor device of claim 1, further comprising a second chain including a plurality of first bonding pad pairs, each of the first chain and the second chain including first bonding pad pairs having alignment deviations in the same direction, the first bonding pad pairs in each chain being connected in series, and the first chain and the second chain being isolated from each other.

11. The semiconductor device according to claim 1, wherein, The first alignment deviation distance is along the plane where the first bonding pad and the second bonding pad are bonded together.

12. The semiconductor device according to claim 1, wherein, The first semiconductor structure and the second semiconductor structure are of the same type.

13. A semiconductor device, said semiconductor device comprising: First semiconductor structure; A second semiconductor structure bonded to the first semiconductor structure; A chain comprising a plurality of first bonding pad pairs, each first bonding pad pair comprising a first bonding pad in the first semiconductor structure and a second bonding pad in the second semiconductor structure bonded together; as well as A second bonding pad pair that is not part of the chain and is adjacent to the first bonding pad pair in the chain, the second bonding pad pair including the third bonding pad in the first semiconductor structure and the fourth bonding pad in the second semiconductor structure. The first bonding pad pair has a first alignment deviation vector indicating a first alignment deviation between the first bonding pad and the second bonding pad, the second bonding pad pair has a second alignment deviation vector indicating a second alignment deviation between the third bonding pad and the fourth bonding pad, and the vector difference between the first alignment deviation vector and the second alignment deviation vector is not zero.

14. The semiconductor device according to claim 13, wherein, The first semiconductor structure includes a fifth bonding pad, and the second semiconductor structure includes a sixth bonding pad. The fifth and sixth bonding pads are bonded together to form a third bonding pad pair that is not part of the chain and is adjacent to the second bonding pad pair. The third bonding pad pair has a third alignment deviation vector, wherein, in terms of vector length, the vector difference between the first and second alignment deviation vectors is greater than the vector difference between the third and second alignment deviation vectors.

15. The semiconductor device according to claim 13, wherein, The first semiconductor structure and the second semiconductor structure each further include a dielectric bonding region, wherein the dielectric material in the dielectric bonding region includes carbon-doped silicon nitride.

16. The semiconductor device according to claim 13, wherein, The first bonding pad pair is located between the sealing ring and the second bonding pad pair.

17. The semiconductor device according to claim 13, wherein, Each of the first and second bonding pad pairs has substantially the same diameter, and the vector difference between the first alignment deviation vector and the second alignment deviation vector is greater than one-tenth of the diameter.

18. The semiconductor device according to claim 17, wherein, The length of the first alignment deviation vector is greater than or equal to 60 percent of the diameter, and the length of the second alignment deviation vector is less than 60 percent of the diameter.

19. The semiconductor device according to claim 13, wherein, The first semiconductor structure includes a memory cell array, and the second semiconductor structure includes peripheral circuitry for the memory cell array.

20. A method for manufacturing a semiconductor device, the method comprising: A first semiconductor structure including a first bonding pad and a second bonding pad is formed; A second semiconductor structure including a third bonding pad and a fourth bonding pad is formed; as well as The first semiconductor structure is bonded onto the second semiconductor structure. The first bonding pad and the third bonding pad are bonded together to form a first bonding pad pair. The first bonding pad pairs are connected to form a chain. At least two first bonding pad pairs in the chain are connected via a conductive path within either the first semiconductor structure or the second semiconductor structure. Wherein, the second bonding pad and the fourth bonding pad are bonded together to form a second bonding pad pair that does not belong to the chain, and Wherein, the first alignment deviation distance between the first bonding pad and the third bonding pad is greater than the second alignment deviation distance between the second bonding pad and the fourth bonding pad.

21. The method according to claim 20, wherein, The first semiconductor structure includes a fifth bonding pad, and the second semiconductor structure includes a sixth bonding pad. The fifth and sixth bonding pads are bonded together to form a third bonding pad pair that is not part of the chain and is adjacent to the second bonding pad pair. The third bonding pad pair has a third alignment deviation distance, wherein the difference between the first and second alignment deviation distances is greater than the difference between the third and second alignment deviation distances.

22. The method according to claim 20, wherein, The first semiconductor structure and the second semiconductor structure each further include a dielectric bonding region, wherein the dielectric material in the dielectric bonding region includes carbon-doped silicon nitride.

23. The method of claim 20, wherein, The first bonding pad pair is located between the sealing ring and the second bonding pad pair.

24. The method of claim 20, wherein, Each of the first and second bonding pad pairs has substantially the same diameter, and the difference between the first alignment deviation distance and the second alignment deviation distance is greater than one-tenth of the diameter.

25. The method according to claim 24, wherein, The first alignment deviation distance is greater than or equal to 60 percent of the diameter, and the second alignment deviation distance is less than 60 percent of the diameter.

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