Semiconductor structure and method of manufacturing the same

Abstract

In joining two workpieces, a high thermal conductivity film is used to reduce thermal resistance between the two joined workpieces. The high thermal conductivity joining film enhances heat dissipation during processing and / or handling. The high thermal conductivity joining film can be applied to one or both workpieces to be joined. In some embodiments, the high thermal conductivity joining film can be used in conjunction with a lower thermal conductivity joining film, such as an oxide joining film or a nitride joining film. Embodiments of the present disclosure provide for forming semiconductor structures and methods of manufacturing the same.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor structures and methods of manufacturing the same. Background Technology

[0002] The electronics industry has a growing demand for smaller, faster electronic devices capable of supporting a greater number of increasingly complex and sophisticated functions. To meet these demands, the integrated circuit (IC) industry continues to trend towards manufacturing low-cost, high-performance, and low-power ICs. To date, these goals have been primarily achieved by reducing IC size (e.g., by reducing the size of the smallest IC component), thereby improving production efficiency and reducing associated costs. However, this scaling also increases the complexity of IC manufacturing processes. Therefore, continued advancements in IC manufacturing processes and technologies are needed to achieve sustained progress in IC devices and their performance. Summary of the Invention

[0003] Some embodiments of this disclosure provide a method for manufacturing a semiconductor structure, the method comprising: providing a first structure; forming a first bonding film stack on a first side of the first structure, wherein the first bonding film stack includes a dielectric film having a thermal conductivity greater than that of silicon oxide; performing a pre-bonding surface treatment to form an activation portion in the dielectric film; bonding a second structure to the activation portion of the first structure, wherein the second structure includes a second bonding film stack, and the activation portion of the first structure is pressed onto the second bonding film stack; and performing an annealing process to form a bonding interface between the first structure and the second structure.

[0004] Other embodiments of this disclosure provide a method for manufacturing a semiconductor structure, the method comprising: providing a first substrate having a device layer and a first interconnect structure formed on a first side of the first substrate; depositing a dielectric layer over the first interconnect structure; forming a first bonding film over the dielectric layer, wherein the first bonding film includes a nitride-containing layer; processing the first bonding film to generate dangling bonds on a top surface of the first bonding film; bonding a carrier substrate to the first bonding film on the first substrate, wherein the carrier substrate includes a second bonding film and forming a bonding interface between the first bonding film and the second bonding film; processing the first substrate from a second side to remove at least a portion of the first substrate; and forming a second interconnect structure on the device layer.

[0005] Further embodiments of this disclosure provide a semiconductor structure comprising: a first structure; a second structure stacked on the first structure; a first bonding film formed on the first structure, wherein the first bonding film includes a thermally conductive dielectric layer; a second bonding film formed on the second structure; and a bonding interface located between the first bonding film and the second bonding film, wherein the bonding interface includes Al-O bonds. Attached Figure Description

[0006] The aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a flowchart of a method for back-side processing including bonding technology according to an embodiment of the present disclosure.

[0008] Figure 2A This is a schematic three-dimensional diagram of the first structure.

[0009] Figure 2B This is a schematic cross-sectional view of the first structure.

[0010] Figure 3A This is a schematic three-dimensional diagram of the first structure.

[0011] Figure 3B This is a schematic cross-sectional view of the first structure.

[0012] Figure 3C This is a schematic three-dimensional diagram of the first structure.

[0013] Figure 4A This is a schematic three-dimensional diagram of the first structure.

[0014] Figure 4B This is a schematic cross-sectional view of the first structure.

[0015] Figure 4C This is a schematic diagram of the top surface after pre-bonding treatment.

[0016] Figure 4D and Figure 4E These are energy-dispersive X-ray spectral data of an exemplary aluminum nitride film before and after pre-bonding treatment with an oxidant.

[0017] Figure 4F This includes X-ray crystallography of an exemplary aluminum nitride film before and after pre-bonding treatment with an oxidant.

[0018] Figure 5 This is a schematic diagram of the top surface after the hydration process.

[0019] Figure 6A This is a schematic three-dimensional diagram of the second structure.

[0020] Figure 6B This is a schematic cross-sectional view of the second structure.

[0021] Figure 7A It is a schematic three-dimensional diagram of the first and second structures.

[0022] Figure 7B The surface reaction between the activated portions during bonding is schematically shown.

[0023] Figure 7C This is a schematic cross-sectional view of the first structure joined to the second structure.

[0024] Figure 8A The surface reaction between the activated portions during annealing is schematically shown.

[0025] Figure 8B This is a schematic cross-sectional view of the first structure joined to the second structure.

[0026] Figure 9A It is a schematic three-dimensional diagram of the first and second structures.

[0027] Figure 9B This is a schematic cross-sectional view of the first structure joined to the second structure.

[0028] Figure 10A It is a schematic three-dimensional diagram of the first and second structures.

[0029] Figure 10B This is a schematic cross-sectional view of the first structure joined to the second structure.

[0030] Figure 11A It is a schematic three-dimensional diagram of the first and second structures.

[0031] Figure 11B This is a schematic cross-sectional view of the first structure joined to the second structure.

[0032] Figure 12A The normalized thermal reflectance obtained by SSTR (steady-state thermal reflectance) measurement is shown.

[0033] Figure 12B The normalized system thermal resistance of the three bonding films is schematically shown.

[0034] Figure 13A and Figure 13B The bonding structure between a first structure having a bonding film with high thermal conductivity and a second structure having a bonding film based on oxide is schematically shown.

[0035] Figure 14A and Figure 14B The bonding structure between a first structure having a bonding film with high thermal conductivity and a second structure having a bonding film based on nitride is schematically shown.

[0036] Figure 15AThe schematic diagram illustrates the bonding structure between a first structure of a bonding stack having a high thermal conductivity bonding film and an oxide-based film and a second structure having a high thermal conductivity bonding film.

[0037] Figure 15B The joining structure between the first structure and the second structure is schematically shown.

[0038] Figure 15C The joining structure between the first structure and the second structure is schematically shown.

[0039] Figure 15D The schematic diagram illustrates the bonding structure between a first structure of a bonding stack having a high thermal conductivity bonding film and a nitride-based film and a second structure having a high thermal conductivity bonding film.

[0040] Figure 15E The joining structure between the first structure and the second structure is schematically shown.

[0041] Figure 15F The joining structure between the first structure and the second structure is schematically shown.

[0042] Figure 15G The bonding structure between a first structure having an oxide-based bonding film and a second structure having a bonding film with high thermal conductivity is schematically shown.

[0043] Figure 15H The bonding structure between a first structure having a nitride-based bonding film and a second structure having a high thermal conductivity bonding film is schematically shown. Detailed Implementation

[0044] The following disclosure provides numerous different embodiments or instances of various components for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify this description. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Additionally, reference numerals and / or characters may be repeated in various instances of this disclosure. This repetition is for clarity and simplicity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0045] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” “above,” “top,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0046] Embodiments of this disclosure include methods and structures involving bonding techniques using semiconductor manufacturing processes, such as during carrier wafer bonding in back-side processes. The bonding techniques according to this disclosure can also be used in other processes, such as 3DIC packaging. In some embodiments, when bonding two workpieces (such as two wafers), at least one workpiece includes a high thermal conductivity film located in a bonding film stack. By incorporating a high thermal conductivity film into the bonding interface, embodiments of this disclosure reduce the thermal resistance between the two bonded workpieces, thus enhancing heat dissipation during processing and / or operation. The high thermal conductivity bonding film can be applied to one or both bonded workpieces. In some embodiments, the high thermal conductivity bonding film can be used to bond with bonding films of lower thermal conductivity, such as oxide bonding films or nitride bonding films.

[0047] In some embodiments, the high thermal conductivity film is a dielectric film with high thermal conductivity. In some embodiments, the high thermal conductivity film may include one or more metal compounds, such as aluminum compounds. In some embodiments, the high thermal conductivity film may include one or more nitrogen-containing films. In some embodiments, the high thermal conductivity film is a nitride film, such as aluminum nitride, aluminum boron nitride (AlBN), titanium aluminum nitride (TiAlN), etc. In some embodiments, a pre-bonding treatment is performed on the high thermal conductivity film prior to bonding. The pre-bonding treatment may be used to activate the surface of the high thermal conductivity film within a few nanometers. In some embodiments, the pre-bonding treatment may oxidize the surface of the high thermal conductivity film and generate dangling bonds to facilitate the bonding process. The pre-bonding treatment may be a plasma treatment, a wet process, or a chemical mechanical polishing (CMP) process. In some embodiments, a hydration operation is performed after plasma treatment and before bonding. In some embodiments, the bonding process may be performed by applying pressure between the two components. In some embodiments, an annealing process is performed to remove moisture and reduce the thickness of the bonding interface.

[0048] Figure 1 This is a flowchart of a back-side processing method 100 including bonding technology according to an embodiment of the present disclosure. Figures 2A to 2B , Figures 3A to 3C , Figures 4A to 4F , Figure 5 , Figures 6A to 6B , Figures 7A to 7C , Figures 8A to 8B , Figures 9A to 9B , Figures 10A to 10B and Figures 11A to 11B The semiconductor structure of each manufacturing stage using method 100 is illustrated schematically.

[0049] In operation 102 of method 100, a first structure 200 to be joined is provided. In some embodiments, such as Figure 2A and Figure 2B As shown, the first structure 200 is the device substrate after the front-side processing. Figure 2A This is a schematic three-dimensional view of the first structure 200. Figure 2B This is a schematic cross-sectional view of the first structure 200. The first structure 200 may include a substrate 202, a device layer 204 formed on the front side 202f of the substrate 202, and a front interconnect structure 206 formed above the device layer 204.

[0050] Substrate 202 can be formed of any material suitable for forming components of a semiconductor device. In some embodiments, substrate 202 is a semiconductor wafer, which can be formed of any semiconductor material. In some embodiments, substrate 202 can be a single-crystal silicon (Si) wafer, an amorphous silicon wafer, a gallium arsenide (GaAs) wafer, or any other semiconductor wafer. In some embodiments, an oxide layer can be formed on substrate 202, and in some embodiments, the formation of the oxide layer can include as part of the process described herein. The oxide layer can be referred to as a buried oxide layer and is disposed on at least one surface of substrate 202. The oxide layer can be formed of any suitable oxide, and in some embodiments, the oxide layer can be a silicon dioxide (SiO2) layer. In some embodiments, substrate 202 and the oxide layer can be collectively referred to as a silicon-on-insulator (SOI) wafer. The oxide layer can be formed by any suitable process, including, for example, by deposition, thermal oxidation, or any other suitable technique. In some embodiments, substrate 202 can include implanted ions.

[0051] Device layer 204 and front-side interconnect structure 206 are formed on substrate 202 using various processes, such as front-end online (FEOL), mid-end online (MEOL), and / or back-end online (BEOL) processes. Device layer 204 may include any semiconductor device structure. For example, in some embodiments, device layer 204 may include one or more transistors, capacitors, resistors, or any other semiconductor device structure or component that may be patterned or otherwise formed in a semiconductor device. Figure 2BIn this example, device layer 204 may include a plurality of transistors 242. Transistor 242 may include an active region and a gate structure. Transistor 242 may be a planar transistor, a FinFET transistor, a gate all-around (GAA) transistor, or other multi-channel transistor. Figure 2B A GAA transistor is shown. Transistor 242 may include a source / drain region 246 and a channel region 244 located between the source / drain regions 246. A gate structure 248 is disposed above the channel region. Various dielectric materials are formed around and between the source / drain regions 246 and the gate structure 248 to complete device layer 204. Device layer 204 may also include conductive components electrically connected to the source / drain regions 246 and the gate structure 248. Device layer 204 may be formed during FEOL and MEOL processes.

[0052] The front interconnect structure 206 includes conductive lines or wiring structures that can be electrically coupled or connected to one or more components (such as transistors) in device layer 204. In some embodiments, the front interconnect structure 206 may include one or more metallization layers, dielectric or insulating layers, metal layers, bonding elements, bonding sites, etc. For example, the front interconnect structure 206 may include conductive components 264, such as wires and conductive vias, formed in a layer of dielectric material 262. The front interconnect structure 206 can be formed by any suitable BEOL process, including conventional BEOL processes for forming BEOL structures.

[0053] In some embodiments, a second wafer (such as a carrier wafer) is bonded to the first structure 200 over the front interconnect structure 206, thereby enabling processing to be performed on the back side 202b of the substrate 202.

[0054] In operation 104 of method 100, such as Figure 3A and Figure 3B As shown, a pre-bonded stack 216 containing a thermally conductive film is formed above the first structure 200. Figure 3A This is a schematic three-dimensional view of the first structure 200. Figure 3B This is a schematic cross-sectional view of the first structure 200. The pre-bonded stack 216 includes one or more dielectric layers configured to ensure bonding between the first structure 200 and a second structure, such as a carrier wafer. In some embodiments, the pre-bonded stack 216 includes a thermally conductive film. Figure 3B In one example, the pre-bonded stack 216 includes a first dielectric layer 210 and a second dielectric layer 214 deposited sequentially over the front interconnect structure 206.

[0055] In some embodiments, the first dielectric layer 210 may be an etch stop layer configured to allow for additional processing over the front-side interconnect structure 206 in subsequent processes, such as forming an RDL (redistribution layer) and / or bonding pads. For example, the dielectric layer 210 may serve as an etch stop layer during the formation of contact pad openings in the pre-bonded stack 216. In some embodiments, the first dielectric layer 210 may include or be silicon nitride, silicon carbonitride, silicon carbide, carbonitride, or combinations thereof. The first dielectric layer 210 may be deposited by CVD, PECVD, ALD, or another deposition technique. In some embodiments, the first dielectric layer 210 is deposited in a temperature range between room temperature and about 500°C. Process temperatures below room temperature may result in lower deposition rates and increased production costs. Process temperatures above about 500°C may adversely affect the conductive component 264, such as undesirable diffusion. The thickness of the first dielectric layer 210 may range from about 3 nm to about 10 nm.

[0056] In some embodiments, the second dielectric layer 214 comprises one or more material layers with high thermal conductivity. For example, the second dielectric layer 214 may include a material layer having a thermal conductivity significantly greater than that of the silicon oxide film. For example, the thermal conductivity of the second dielectric layer 214 is between about 50 times and about 200 times that of the silicon oxide film. In some embodiments, the second dielectric layer 214 comprises a dielectric material having a thermal conductivity greater than 50 W / m*K.

[0057] The second dielectric layer 214 can be any dielectric film having high thermal conductivity. In some embodiments, the second dielectric layer 214 may include a nitrogen-containing film, such as a nitride. In some embodiments, the second dielectric layer 214 may include a metal nitride, such as aluminum nitride. In other embodiments, the second dielectric layer 214 may include silicon nitride.

[0058] In some embodiments, the second dielectric layer 214 has a thickness T1 ranging from about 100 Å to about 50 kÅ. A thickness less than about 100 Å may be difficult to fabricate. A thickness greater than about 50 kÅ may cause wafer warping or difficulty in topology control.

[0059] The second dielectric layer 214 can be deposited using PECVD, PEALD, PVD, or another deposition technique. In some embodiments, the second dielectric layer 214 is deposited in a temperature range between room temperature and approximately 500°C. Process temperatures below room temperature may result in lower deposition rates and increased production costs. Process temperatures above approximately 500°C may adversely affect the conductive component 264, such as causing undesirable diffusion. In some embodiments, a CMP process can be used after the deposition process to achieve desired surface topography features or a desired thickness.

[0060] The top surface 216t of the pre-jointed stack 216 can be referred to as the joining surface of the first structure 200. For example... Figure 3A and Figure 3B As shown, after operation 104, the top surface 216t includes a second dielectric layer 214, which is a dielectric material with high thermal conductivity.

[0061] In operation 106 of method 100, an edge trimming process is performed to remove a portion of the first structure 200, such as... Figure 3C As shown. Figure 3C This is a schematic perspective view of the first structure 200. A pre-bonding edge trimming process can be performed to trim the front peripheral region of the first structure 200. Edge trimming typically refers to the process of removing the edge portion of the substrate along its entire circumference. The pre-bonding edge trimming process can remove an annular peripheral portion of the first structure 200, which is located within an edge trimming width tw from the outermost periphery of the first structure 200 and within an edge trimming depth td from the horizontal plane including the front side 202f of the substrate 202. A commercially available wafer edge trimming tool can be used to perform the pre-bonding edge trimming process. The pre-bonding edge trimming process forms an annular horizontal edge trimming surface in a horizontal plane located at an edge trimming depth td from the front surface of the first structure 200. The pre-bonding edge trimming process forms a first cylindrical sidewall on the first structure 200, the position of which is laterally offset relative to the outermost periphery of the first structure 200 by the first edge trimming width tw. In one embodiment, the edge trimming width tw can be in the range of 0.1 mm to 5.0 mm, but smaller and larger first edge trimming widths can also be used. In one embodiment, the edge trimming depth td is in the range of 10 micrometers to 50 micrometers, but smaller and larger edge trimming depths can also be used.

[0062] In operation 108 of method 100, such as Figure 4A and Figure 4B As shown, a pre-bonding surface treatment is performed to activate the top surface of the bonded stack. Figure 4A This is a schematic three-dimensional view of the first structure 200. Figure 4B This is a schematic cross-sectional view of the first structure 200. The pre-bonding surface treatment can be referred to as an activation process. In some embodiments, the pre-bonding surface treatment transforms a portion of the second dielectric layer 214 to generate dangling bonds on the top surface 216t (the top surface 216t is the bonding surface) to facilitate bonding.

[0063] Figure 4C This is a schematic diagram of the top surface 216t after pre-bonding treatment. Figure 4CIn this process, the second dielectric layer 214 comprises aluminum nitride. After pre-bonding, some Al-N bonds on the top surface 216t are replaced by Al-OH bonds. Some -OH bonds can be dangling on the top surface 216t to facilitate subsequent bonding with the second workpiece. Similarly, when the second dielectric layer 214 comprises a material other than aluminum nitride (such as silicon nitride), some Si-N bonds on the top surface 216t can be replaced by Si-OH bonds.

[0064] In some embodiments, the pre-bonding process is an oxidation process that oxidizes a portion of the second dielectric layer 214 from the top surface 216t. For example... Figure 4B As shown, the pre-bonding process can transform a portion of the second dielectric layer 214 into an activation portion 218. In some embodiments, after the pre-bonding process, the top surface 216t of the pre-bonded stack 216 is composed of the activation portion 218. When the second dielectric layer 214 comprises aluminum nitride, the activation portion 218 may comprise aluminum oxide. When the second dielectric layer 214 comprises silicon nitride, the activation portion 218 may comprise silicon oxide. The activation portion 218 has a thickness T2. In some embodiments, the thickness T2 is less than about 5 nm. In some embodiments, the thickness T2 is in the range of about 1 nm to about 5 nm. If the thickness T2 is less than 1 nm, there may not be enough -OH bonds on the top surface 216t to facilitate effective bonding. If the thickness T2 is greater than about 5 nm, the oxide material may increase the thermal conductivity in the subsequent bonding interface without providing additional benefits to the bonding strength.

[0065] like Figure 4B As shown, after the pre-bonding operation, the second dielectric layer 214 has a reduced thickness T3. In some embodiments, the combination of thickness T2 and thickness T3 is substantially equal to thickness T1, which is formed in operation 104. In other words, after the pre-bonding surface treatment, the second dielectric layer 214 has a reduced thickness T3. The activation portion 218 is thinner than the second dielectric layer 214.

[0066] In some embodiments, the pre-bonded surface treatment may be a plasma activation process. For example, the plasma activation process can be performed by exposing the top surface 216t to plasma containing an oxidant. In some embodiments, the plasma treatment may be an oxygen plasma treatment, an oxygen-hydrogen plasma treatment, or other suitable plasma treatment. In some embodiments, the plasma source may be a plasma of O2, N2O, O3, Ar, or N2. In some embodiments, the plasma activation process may be performed at a temperature range between room temperature and approximately 500°C. Process temperatures below room temperature may result in lower deposition rates and increased production costs. Process temperatures above approximately 500°C may adversely affect the conductive component 264, such as causing undesirable diffusion.

[0067] In other embodiments, the pre-bonded surface treatment can be a wet process. For example, the top surface 216t can be exposed to a treatment solution containing O3 and H2O2. In some embodiments, the wet process can be performed at a temperature below 500°C, for example, in the temperature range from room temperature to about 100°C.

[0068] In other embodiments, pre-bonding surface treatment can be performed using a CMP process. For example, the top surface 216t can be exposed to a polishing slurry containing H2O2. In some embodiments, pre-bonding surface treatment can be performed during a planarization process (such as operation 104) when forming the second dielectric layer 214.

[0069] It has been observed that the pre-bonding surface treatment in operation 108 only affects the surface portion of the second dielectric layer 214, while the composition of the body portion of the second dielectric layer 214 is not affected by the pre-bonding surface treatment. Figure 4D and Figure 4E These are energy-dispersive X-ray spectral data of an exemplary aluminum nitride film before and after pre-bonding treatment with an oxidant. Figure 4D The deposited aluminum nitride film has a composition of Al: 52.9%, O: 23.5%, and N: 23.5%. Figure 4E In the O2-treated aluminum nitride film, the composition is Al: 50%, O: 33%, and N: 16.6%. However, the compositional variation occurs in the portion between 50 nm and 60 nm in the x-direction. In the bulk aluminum nitride film (the film exceeding 60 nm in the x-direction), the composition remains essentially the same.

[0070] It has also been observed that the pre-bonding surface treatment in operation 108 does not affect the bulk portion of the second dielectric layer 214 or the crystal structure of the bonding film. Figure 4F This includes X-ray crystallography of an exemplary aluminum nitride film before and after pre-bonding treatment with an oxidant. Figure 4F The study included crystallographic analysis of an aluminum nitride film with a thickness of 2 kÅ before and after oxygen pre-bonding. The grain orientation of the aluminum nitride film was (0002) phase. The crystallinity after deposition was 94.38%, and the crystallinity after pre-bonding was 95.29%. No structural changes were observed in the bulk aluminum nitride film after pre-bonding.

[0071] In operation 110 of method 100, a hydration process is performed to create terminations of dangling bonds on the bonding surface. In some embodiments, when the dangling bonds on the bonding surface (i.e., the top surface 216t) are -OH bonds, a rinsing process may be performed to provide terminations of the -OH bonds. When the pre-bonding surface treatment in operation 108 is performed by plasma treatment, a separate rinsing process using water may be performed. When the pre-bonding surface treatment in operation 108 is performed by a wet process or a CMP process, the hydration process may be performed during rinsing and cleaning following the wet process or CMP process.

[0072] Figure 5 This is a schematic diagram of the 216t top surface after the hydration process. Figure 5 In this process, the second dielectric layer 214 comprises aluminum nitride and creates -OH dangling bonds after a pre-bonding surface treatment. Upon hydration, the dangling -OH bonds on the top surface 216t are terminated by H₂O. Termination of the dangling bonds provides stability to the bonding surface. The hydration process also generates a liquid film above the top surface 216t. This liquid film enhances capillary forces at the interface, helping to bring the two bonding sheets close together.

[0073] In operation 112 of method 100, the second structure 300 is bonded to the bonding surface of the first structure 200. In some embodiments, the second structure 300 may be a carrier wafer, such as... Figure 6A and Figure 6B As shown. Figure 6A This is a schematic three-dimensional view of the second structure 300. Figure 6B This is a schematic cross-sectional view of the second structure 300. The second structure 300 may include a carrier substrate 302 and a bonding film 314 formed on the carrier substrate 302. In some embodiments, an optional release layer 312 is formed between the carrier substrate 302 and the bonding film 314. The release layer 312 allows the second structure 300 to be removed from the first structure 200 after back-side processing.

[0074] The carrier substrate 302 can be any wafer or substrate suitable for bonding to a semiconductor device structure attached to or otherwise supported by the first structure 200. For example, it can be suitable for bonding to a pre-bonded stack 216 formed on the front-side interconnect structure 206. In some embodiments, the carrier substrate 302 can be a semiconductor wafer, such as a single-crystal silicon (Si) wafer, an amorphous silicon wafer, a gallium arsenide (GaAs) wafer, or any other semiconductor wafer. In some embodiments, the carrier substrate 302 can be a glass wafer or any other substrate material suitable for supporting a semiconductor device structure during processing. In some embodiments, the carrier substrate 302 can have a thickness in the range of 500 μm to 100 μm. In some embodiments, the carrier substrate 302 can have a thickness of about 775 μm or equal to 775 μm.

[0075] In some embodiments, the bonding film 314 includes a highly thermally conductive dielectric layer. In some embodiments, the bonding film 314 may be similar to the second dielectric layer 214. In some embodiments, the second structure 300 may be treated by a pre-bonding surface treatment (similar to the pre-bonding surface treatment described in operation 108) and a hydration process (similar to the hydration process described in operation 110).

[0076] In some embodiments, the bonding film 314 comprises one or more material layers with high thermal conductivity. For example, the bonding film 314 may include a dielectric material layer having a thermal conductivity significantly greater than that of the silicon oxide film. For example, the thermal conductivity of the bonding film 314 is between about 50 times and about 200 times that of the silicon oxide film. In some embodiments, the bonding film 314 comprises a dielectric material having a thermal conductivity greater than 50 W / m·K. The bonding film 314 can be any dielectric film with high thermal conductivity. In some embodiments, the bonding film 314 may include a nitrogen-containing film, such as a nitride. In some embodiments, the bonding film 314 may include a metal nitride, such as aluminum nitride. In other embodiments, the bonding film 314 may include silicon nitride. In some embodiments, the bonding film 314 may first be formed with a thickness T4 in the range of about 100 Å to about 50 kÅ. Thicknesses less than about 100 Å may be difficult to manufacture. Thicknesses greater than about 50 kÅ may cause wafer warpage or difficulty in topology control. The bonding film 314 can be deposited using PECVD, PEALD, PVD, or another deposition technique.

[0077] A pre-bonding surface treatment is performed to activate the top surface of the bonding film 314 to form the activation portion 318. In some embodiments, when the bonding film 314 comprises aluminum nitride, some Al-N bonds in the activation portion 318 are replaced by Al-OH bonds after the pre-bonding treatment. Some -OH bonds may be dangling on the top surface of the activation portion 318 to facilitate subsequent bonding with the first structure 200. Similarly, when the bonding film 314 comprises a material other than aluminum nitride, such as silicon nitride, some Si-N bonds on the top surface of the activation portion 318 may be replaced by Si-OH bonds.

[0078] In some embodiments, the pre-bonding process is an oxidation process. When the bonding film 314 comprises aluminum nitride, the activation portion 318 may comprise aluminum oxide. When the bonding film 314 comprises silicon nitride, the activation portion 318 may comprise silicon oxide. The activation portion 318 has a thickness T5. In some embodiments, the thickness T5 is less than about 5 nm. In some embodiments, the thickness T5 is in the range of about 1 nm to about 5 nm. If the thickness T5 is less than 1 nm, there may not be enough -OH bonds on the top surface to facilitate effective bonding. If the thickness T5 is greater than about 5 nm, the oxide material may increase the thermal conductivity in the subsequent bonding interface without providing additional benefits to the bonding strength.

[0079] like Figure 6B As shown, after the pre-bonding operation, the bonding film 314 has a reduced thickness T6. In some embodiments, the combination of thickness T5 and thickness T6 is substantially equal to thickness T4, which is the original deposition thickness of the bonding film 314. In other words, after the pre-bonding surface treatment, the bonding film 314 has a reduced thickness T6. The activation portion 318 is thinner than the bonding film 314.

[0080] In some embodiments, the pre-bonding surface treatment may be a plasma activation process. For example, the plasma activation process can be performed by exposing the top surface of the bonding film 314 to a plasma containing an oxidant. In some embodiments, the plasma treatment may be an oxygen plasma treatment, an oxygen-hydrogen plasma treatment, or other suitable plasma treatment. In some embodiments, the plasma source may be a plasma of O2, N2O, O3, Ar, or N2. In other embodiments, the pre-bonding surface treatment may be a wet process. For example, the top surface 216t may be exposed to a treatment solution containing O3 and H2O2. In still other embodiments, the pre-bonding surface treatment may be performed by a CMP process. For example, the top surface may be exposed to a polishing slurry containing H2O2. In some embodiments, the pre-bonding surface treatment may be performed during the planarization process when forming the bonding film 314.

[0081] In some embodiments, a hydration process is performed to create dangling bond terminations on the bonding surface of the activation portion 318. In some embodiments, when the dangling bond on the bonding surface (i.e., the top surface) is a -OH bond, a rinsing process may be performed to provide -OH bond terminations. When the pre-bonding surface treatment is performed by plasma treatment, a separate rinsing process using water may be performed. When the pre-bonding surface treatment is performed by a wet process or a CMP process, the hydration process may be performed during rinsing and cleaning following the wet process or CMP process. After the hydration process, the top surface of the activation portion 318 may include aluminum nitride, and -OH dangling bonds are created after the pre-bonding surface treatment. After hydration, the dangling -OH bonds on the top surface are terminated by H2O. Terminating the dangling bonds provides stability to the bonding surface.

[0082] The debonding layer 312 can be formed of any material suitable for bonding the front-side interconnect structure 206 to the carrier substrate 302, or suitable for bonding the bonding film 314 to the carrier substrate 302. Furthermore, the debonding layer 312 can be formed of any material suitable for easy removal, thereby releasing the carrier substrate 302 from the first structure 200 after the debonding layer 312 is removed. In some embodiments, the debonding layer 312 may include SiCN, SiOCN, SiN, SiO2, HfO2, ZrO2, or HfAlO. x HfSiO x It may be one or more of TiN, organic materials, or any other suitable release layer material. In some embodiments, the release layer 312 may be an adhesive layer.

[0083] In some embodiments, an optional dielectric layer (not shown) may be formed between the release layer 312 and the surface of the carrier substrate 302. The optional dielectric layer may be an oxide layer or a nitride layer. The release layer 312 may be selected to separate the optional dielectric layer and the bonding film 314.

[0084] In some embodiments, such as Figure 7A , Figure 7B and Figure 7C As shown, the bonding process can be performed by flipping the second structure 300 over the first structure 200 so that the activation portion 318 of the second structure 300 is aligned with the activation portion 218 of the first structure 200, and by applying external pressure between the first structure 200 and the second structure 300. Figure 7A It is a schematic three-dimensional view of the first structure 200 and the second structure 300. Figure 7B The surface reaction between activation portion 318 and activation portion 218 during bonding is schematically shown. Figure 7C It is a schematic cross-sectional view of the first structure 200 that is joined to the second structure 300.

[0085] like Figure 7BAs shown, the hydration process on the first structure 200 and the second structure 300 forms a liquid film above the top surface 216t of the first structure 200 and the top surface of the second structure 300. The liquid film enhances the capillary forces at the interface between the first structure 200 and the second structure 300, thereby facilitating closer proximity of the first structure 200 and the second structure 300 and improving the contact area. During bonding, an external force is applied to bring the first structure 200 and the second structure 300 close enough to form hydrogen bonds 220 at the bonding interface, such as... Figure 7B As shown. H2O was also removed during the bonding process.

[0086] In operation 114 of method 100, such as Figure 8A and Figure 8B As shown, an annealing process is performed to bond the activated portion 218 and the activated portion 318. Figure 8A The surface reaction between the activated portion 318 and the activated portion 218 during annealing is schematically shown. Figure 8B It is a schematic cross-sectional view of the first structure 200 that is joined to the second structure 300.

[0087] In some cases, annealing can also be used to initiate dehydration and remove H2O. For example... Figure 8A As shown, a bonding interface 222 is formed between the first structure 200 and the second structure 300. The bonding interface 222 may include an activation portion 218 and an activation portion 318 following the reaction during bonding and annealing.

[0088] In some instances, when active portions 218 and 318 comprise a single dielectric layer, the bonds between the active surfaces may include XOY bonds, where X is an element in active portion 218 and Y is an element in active portion 318. Figure 8A In the example, elements X and Y are both aluminum, and the bonding interface 222 includes Al-O-Al bonds.

[0089] In operation 116 of method 100, the joining structure of the first structure 200 and the second structure 300 is flipped for back-side processing, such as... Figures 9A to 9B , Figures 10A to 10B and Figures 11A to 11B As shown.

[0090] Figure 9A It is a schematic three-dimensional view of the first structure 200 and the second structure 300. Figure 9B This is a schematic cross-sectional view of the first structure 200, which is joined to the second structure 300. (See diagram below.) Figure 9A and Figure 9BAs shown, the bonding structure is flipped so that the back side 202b of the substrate 202 faces upward. The carrier substrate 302 supports the bonding structure, thereby enabling processing to be performed on the back side 202b of the substrate 202.

[0091] Figure 10A It is a schematic three-dimensional view of the first structure 200 and the second structure 300. Figure 10B This is a schematic cross-sectional view of the first structure 200, which is joined to the second structure 300. (See diagram below.) Figure 10A and Figure 10B As shown, at least a portion of the substrate 202 is removed for back-side processing.

[0092] Figure 11A It is a schematic three-dimensional view of the first structure 200 and the second structure 300. Figure 11B This is a schematic cross-sectional view of the first structure 200, which is joined to the second structure 300. (See diagram below.) Figure 11A and Figure 11B As shown, a back-side interconnect structure 208 is formed above device layer 204. Similar to the front-side interconnect structure 206, the back-side interconnect structure 208 includes conductors or wiring structures that can be electrically coupled or connected to one or more components (such as transistors) in device layer 204. In some embodiments, the back-side interconnect structure 208 may include one or more metallization layers, dielectric or insulating layers, metal layers, bonding elements, bonding sites, etc. For example, the back-side interconnect structure 208 may include conductive components formed in a layer of dielectric material, such as conductors and conductive vias. The back-side interconnect structure 208 can be formed by any suitable BEOL process, including conventional BEOL processes for forming BEOL structures.

[0093] It has been observed that using bonding films with high thermal conductivity can achieve a thermal resistance reduction of approximately 24%. Figure 12A The normalized thermal reflectance obtained by SSTR (steady-state thermal reflectance) measurement is shown. Figure 12A The image shows the thermal resistance variations of silicon oxide bonding films, aluminum nitride bonding films, and activated aluminum nitride bonding films of the same thickness at different power levels. Figure 12A As shown, the silicon oxide bonding film exhibits the highest thermal resistance, while the aluminum nitride bonding film exhibits the lowest thermal resistance. The surface-activated aluminum nitride bonding film shows a slight increase in thermal resistance compared to the unactivated aluminum nitride film. Figure 12B The normalized system thermal resistance of the three bonding films is schematically shown. Compared with silicon oxide bonding films and aluminum nitride bonding films of the same thickness, the aluminum nitride film exhibits a thermal resistance that is approximately 24% lower than that of silicon oxide bonding films.

[0094] In the above examples, a high thermal conductivity bonding film is formed on the bonding surfaces of the two workpieces to be joined. In some embodiments, one workpiece to be joined includes a high thermal conductivity bonding film, while the other workpiece may include an oxide-based bonding film. In some embodiments, the two workpieces may include high thermal conductivity bonding films with different compositions.

[0095] Figure 13A and Figure 13B The schematic diagram illustrates the bonding structure between a first structure having a bonding film with high thermal conductivity and a second structure having a bonding film based on an oxide. Specifically, in Figure 13A and Figure 13B In one embodiment, a first structure 200 having a second dielectric layer 214 (which is a highly thermally conductive film) is bonded to a second structure 300a having an oxide-based bonding film. Figure 13A A cross-section of the second structure 300a is schematically shown. The second structure 300a includes a carrier substrate 302 and a bonding film 315. In some embodiments, a release layer 312 may be formed between the carrier substrate 302 and the bonding film 315. In some embodiments, the bonding film 315 includes an oxide layer, such as a SiO2 layer. Figure 13B As shown, when the second structure 300a is bonded to the first structure 200, a bonding interface 222a is formed between the bonding film 315 on the second structure 300a and the second dielectric layer 214 on the first structure 200. The bonding interface 222a may include an activation portion 218 formed from the surface portion of the second dielectric layer 214. The bonding interface 222a includes Si-O-Al bonds.

[0096] Figure 14A and Figure 14B The schematic diagram illustrates the bonding structure between a first structure having a bonding film with high thermal conductivity and a second structure having a nitride-based bonding film. Specifically, in Figure 14A and Figure 14B In one embodiment, a first structure 200 having a second dielectric layer 214 (which is a highly thermally conductive film) is bonded to a second structure 300b having a nitride-based bonding film. Figure 14A A cross-section of the second structure 300b is schematically shown. The second structure 300b includes a carrier substrate 302 and a bonding film 317. In some embodiments, a release layer 312 may be formed between the carrier substrate 302 and the bonding film 317. In some embodiments, the bonding film 317 includes a nitride layer, such as SiN, SiON, SiCN, TiN, BN, or a film. In some embodiments, the bonding film 317 may be activated by a pre-bonding surface treatment, similar to the process described in operation 108 of method 100. The pre-bonding surface treatment results in an activation portion 319 on the top portion of the bonding film 317.

[0097] like Figure 14B As shown, when the second structure 300b is bonded to the first structure 200, a bonding interface 222b is formed between the bonding film 317 on the second structure 300b and the second dielectric layer 214 on the first structure 200. The bonding interface 222b may include an activation portion 218 formed from a surface portion of the second dielectric layer 214 and an activation portion 319 formed from the nitride-based bonding film 317. Depending on the composition of the bonding film 317, the bonding interface 222b may include Si-O-Al bonds, Si-C-Al bonds, Ti-O-Al bonds, or B0-Al bonds. In some embodiments, when the bonding film 317 comprises silicon nitride, the bonding interface 222b comprises Si-O-Al bonds.

[0098] Figures 15A to 15H Various embodiments of the joining scheme according to embodiments of the present disclosure are illustrated schematically.

[0099] Figure 15A The schematic diagram illustrates the bonding structure between a first structure 200a and a second structure. The first structure 200a has a high thermal conductivity bonding film and a bonding stack of oxide-based films, while the second structure has a high thermal conductivity bonding film. Specifically, in Figure 15A In one embodiment, the first structure 200a includes an oxide-based bonding film 212 disposed between a second dielectric layer 214, which serves as a high thermal conductivity film, and a first dielectric layer 210, which serves as an etch stop layer. In some embodiments, the oxide-based bonding film 212 may include silicon oxide. The second dielectric layer 214 on the first structure 200a is processed using a pre-bonding activation process and has an activation portion 218 thereon. The second structure 300 includes the activation portion 318. When the second structure 300 is bonded to the first structure 200a, a bonding interface 222 is formed between the activation portion 318 on the second structure 300 and the activation portion 218 on the second dielectric layer 214 on the first structure 200a. The bonding interface 222 includes the activation portion 218 and the activation portion 318 formed from the surface portion of the second dielectric layer 214. The bonding interface 222 includes Al-O-Al bonds.

[0100] Figure 15B The joining structure between the first structure 200a and the second structure 300a is schematically shown. A joining interface 222a is formed between the two.

[0101] Figure 15C The joining structure between the first structure 200a and the second structure 300b is schematically shown. A joining interface 222b is formed between the two.

[0102] Figure 15DThe schematic diagram illustrates the bonding structure between a first structure 200b and a second structure. The first structure 200b has a bonding stack of a high thermal conductivity bonding film and a nitride-based film, and the second structure has a high thermal conductivity bonding film. Specifically, in Figure 15D In one embodiment, the first structure 200b includes a nitride-based bonding film 213 disposed between a second dielectric layer 214, which serves as a high thermal conductivity film, and a first dielectric layer 210, which serves as an etch stop layer. In some embodiments, the nitride-based bonding film 213 may include a nitride layer, such as SiN, SiON, SiCN, TiN, BN, or a film. The second dielectric layer 214 on the first structure 200b is processed using a pre-bonding activation process and has an activation portion 218 thereon. The second structure 300 includes the activation portion 318. When the second structure 300 is bonded to the first structure 200b, a bonding interface 222 is formed between the activation portion 318 on the second structure 300 and the activation portion 218 on the second dielectric layer 214 on the first structure 200b. The bonding interface 222 includes the activation portion 218 and the activation portion 318 formed from the surface portion of the second dielectric layer 214. The bonding interface 222 includes Al-O-Al bonds.

[0103] Figure 15E The joining structure between the first structure 200b and the second structure 300a is schematically shown. A joining interface 222a is formed between the two.

[0104] Figure 15F The joining structure between the first structure 200b and the second structure 300b is schematically shown. A joining interface 222b is formed between the two.

[0105] Figure 15G The schematic diagram illustrates the bonding structure between a first structure 200c and a second structure. The first structure 200c has an oxide-based bonding film, and the second structure has a high thermal conductivity bonding film. The first structure 200c is a device substrate. Specifically, in Figure 15G In one embodiment, the first structure 200c includes an oxide-based bonding film 224 formed on a first dielectric layer 210 (which is an etch stop layer). In some embodiments, the oxide-based bonding film 224 includes silicon oxide. The second structure 300 is a carrier substrate and includes an activation portion 318 from the bonding film 314, which is a high thermal conductivity bonding film. When the second structure 300 is bonded to the first structure 200c, a bonding interface 222c is formed between the activation portion 318 on the second structure 300 and the oxide-based bonding film 224. The bonding interface 222c includes the activation portion 318. The bonding interface 222c contains Si-O-Al bonds.

[0106] Figure 15HThe bonding structure between a first structure 200d and a second structure is schematically shown. The first structure 200d has a nitride-based bonding film, and the second structure has a high thermal conductivity bonding film. The first structure 200d is a device substrate. Specifically, in Figure 15H In one embodiment, the first structure 200d includes a nitride-based bonding film 226 formed on a first dielectric layer 210, which serves as an etch stop layer. In some embodiments, the nitride-based bonding film 226 may include a nitride layer, such as SiN, SiON, SiCN, TiN, BN, or a film. The nitride-based bonding film 226 on the first structure 200d is processed using a pre-bonding activation process and has an activation portion 228 thereon. The second structure 300 is a carrier substrate and includes an activation portion 318 from a bonding film 314, which is a high thermal conductivity bonding film. When the second structure 300 is bonded to the first structure 200d, a bonding interface 222d is formed between the activation portion 318 on the second structure 300 and the activation portion 228 on the nitride-based bonding film 226. Depending on the composition of the bonding film 226, the bonding interface 222d may include Si-O-Al bonds, Si-C-Al bonds, Ti-O-Al bonds, or B0-Al bonds. In some embodiments, when the bonding film 226 comprises silicon nitride, the bonding interface 222d comprises Si-O-Al bonds.

[0107] Although embodiments of the present disclosure have been described above in the context of bonding between a device substrate and a carrier substrate, these embodiments can be used in any bonding situation. For example, bonding techniques with high thermal conductivity films can be used in packaging processes such as three-dimensional integrated circuit (3DIC) processes. In some embodiments, the first structure 200 and the second structure 300 can be a top die and a bottom die to be bonded together. Similar to the second dielectric layer 214 and / or the bonding film 314, a high thermal conductivity bonding film can be retained in the 3DIC package between the top die and the bottom die. Similar to the bonding interface 222 described above, a bonding interface can be retained in the 3DIC package between the top die and the bottom die. In other embodiments, both the first structure 200 and the second structure 300 are device substrates and are bonded together to form a 3DIC, and the bonding interface 222, the second dielectric layer 214, and / or the bonding film 314 can be retained in the subsequently formed 3DIC package.

[0108] The various embodiments or examples described herein offer several advantages over the prior art. By incorporating a high thermal conductivity film into the bonding interface, embodiments of this disclosure reduce the thermal resistance between two bonded workpieces, thereby enhancing heat dissipation during handling and / or operation.

[0109] It should be understood that this document does not need to discuss all advantages, not all embodiments or examples must have specific advantages, and other embodiments or examples may offer different advantages.

[0110] In some aspects, the technology described herein relates to a method comprising: providing a first structure; forming a first bonding film stack on a first side of the first structure, wherein the first bonding film stack includes a high thermal conductivity dielectric film having a thermal conductivity greater than that of silicon oxide; performing a pre-bonding surface treatment to form an activation portion in the high thermal conductivity dielectric film; bonding a second structure to the activation portion of the first structure, wherein the second structure includes a second bonding film stack, and the activation portion of the first structure is pressed onto the second bonding film stack; and performing an annealing process to form a bonding interface between the first structure and the second structure.

[0111] In some aspects, the technology described herein relates to a method comprising: providing a first substrate having a device layer and a first interconnect structure formed on a first side of the first substrate; depositing a dielectric layer over the first interconnect structure; forming a first bonding film over the dielectric layer, wherein the first bonding film includes a nitride-containing layer; processing the first bonding film to generate dangling bonds on a top surface of the first bonding film; bonding a carrier substrate to the first bonding film on the first substrate, wherein the carrier substrate includes a second bonding film, and forming a bonding interface between the first bonding film and the second bonding film; processing the first substrate from a second side to remove at least a portion of the first substrate; and forming a second interconnect structure on the device layer.

[0112] In some aspects, the techniques described herein relate to a semiconductor structure comprising: a first structure; a second structure stacked on the first structure; a first bonding film formed on the first structure, wherein the first bonding film includes a dielectric layer with high thermal conductivity; a second bonding film formed on the second structure; and a bonding interface located between the first bonding film and the second bonding film, wherein the bonding interface includes Al-O bonds.

[0113] According to one aspect of this disclosure, a method of manufacturing a semiconductor structure is disclosed, the method comprising: providing a first structure; forming a first bonding film stack on a first side of the first structure, wherein the first bonding film stack includes a dielectric film having a thermal conductivity greater than that of silicon oxide; performing a pre-bonding surface treatment to form an activation portion in the dielectric film; bonding a second structure to the activation portion of the first structure, wherein the second structure includes a second bonding film stack, and the activation portion of the first structure is pressed to the second bonding film stack; and performing an annealing process to form a bonding interface between the first structure and the second structure. In some embodiments, the dielectric film includes a nitride. In some embodiments, the dielectric film includes aluminum nitride. In some embodiments, the pre-bonding surface treatment replaces nitrogen bonds in the activation portion with oxygen bonds. In some embodiments, the pre-bonding surface treatment is one of plasma treatment, wet processing, and chemical mechanical polishing. In some embodiments, the method of manufacturing the semiconductor structure further includes hydrating the activation portion prior to bonding the second structure. In some embodiments, the second bonding film stack includes a second dielectric film having a second activation portion. In some embodiments, the second bonding film stack includes an oxide-based bonding film. In some embodiments, the second bonding film stack includes a nitride-based bonding film. In some embodiments, the first bonding film stack includes an oxide-based bonding film disposed on a first side of the first structure, and a dielectric film disposed on the oxide-based bonding film. In some embodiments, the first bonding film stack includes a nitride-based bonding film disposed on a first side of the first structure, and a dielectric film disposed on the nitride-based bonding film.

[0114] According to another aspect of this disclosure, a method for manufacturing a semiconductor structure is disclosed, the method comprising: providing a first substrate having a device layer and a first interconnect structure formed on a first side of the first substrate; depositing a dielectric layer over the first interconnect structure; forming a first bonding film over the dielectric layer, wherein the first bonding film includes a nitride-containing layer; processing the first bonding film to generate dangling bonds on a top surface of the first bonding film; bonding a carrier substrate to the first bonding film on the first substrate, wherein the carrier substrate includes a second bonding film and a bonding interface is formed between the first bonding film and the second bonding film; processing the first substrate from a second side to remove at least a portion of the first substrate; and forming a second interconnect structure on the device layer. In some embodiments, bonding the carrier substrate to the first substrate comprises: hydrating the first bonding film to form a liquid film on the first bonding film; placing the carrier substrate close to the first substrate; and applying an external force to press the carrier substrate to the first substrate. In some embodiments, processing the first bonding film comprises performing a plasma treatment to oxidize a portion of the first bonding film. In some embodiments, an activation portion is formed on the first bonding film, and the activation portion has a thickness of less than about 5 nm. In some embodiments, the method of manufacturing a semiconductor structure further includes forming a third bonding film between an etch stop layer and a first bonding film, wherein the third bonding film comprises an oxide or a nitride. In some embodiments, the second bonding film comprises aluminum nitride, silicon oxide, or silicon nitride.

[0115] According to another aspect of this disclosure, a semiconductor structure is disclosed, comprising: a first structure; a second structure stacked on the first structure; a first bonding film formed on the first structure, wherein the first bonding film includes a thermally conductive dielectric layer; a second bonding film formed on the second structure; and a bonding interface located between the first bonding film and the second bonding film, wherein the bonding interface includes Al-O bonds. In some embodiments, the thermal conductivity of the first bonding film is greater than that of silicon oxide. In some embodiments, the thermally conductive dielectric layer includes aluminum nitride.

[0116] As used herein, the terms “about” and “approximately” generally refer to a given amount that can vary based on a specific process node associated with the subject semiconductor device. Based on a specific process node, the term “about” can refer to a given amount that varies within, for example, 10% to 30% of that value (e.g., ±10%, ±20%, or ±30% of that value).

[0117] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, comprising: Provide the first structure; A first bonding film stack is formed on a first side of the first structure, wherein the first bonding film stack includes a dielectric film having a thermal conductivity greater than that of silicon oxide. Perform a pre-bonding surface treatment to form an activation portion in the dielectric film; A second structure is bonded to the activation portion of the first structure, wherein the second structure includes a second bonding film stack, and the activation portion of the first structure is pressed onto the second bonding film stack; and An annealing process is performed to form a bonding interface between the first structure and the second structure.

2. The method according to claim 1, wherein, The dielectric film comprises nitrides.

3. The method according to claim 2, wherein, The dielectric film comprises aluminum nitride.

4. The method according to claim 2, wherein, The pre-bonded surface treatment replaces nitrogen bonds in the activated portion with oxygen bonds.

5. The method according to claim 4, wherein, The pre-bonded surface treatment is one of plasma treatment, wet process, and chemical mechanical polishing process.

6. The method of claim 4, further comprising hydrating the activation portion prior to joining the second structure.

7. The method according to claim 1, wherein, The second bonding film stack includes: The second dielectric film has a second activation portion.

8. The method according to claim 1, wherein, The second bonding film stack comprises an oxide-based bonding film.

9. A method for manufacturing a semiconductor structure, comprising: A first substrate is provided, the first substrate having a device layer and a first interconnect structure formed on a first side of the first substrate; A dielectric layer is deposited over the first interconnect structure; A first bonding film is formed over the dielectric layer, wherein the first bonding film includes a nitride-containing layer; The first bonding membrane is processed to generate dangling bonds on the top surface of the first bonding membrane; A carrier substrate is bonded to the first bonding film on the first substrate, wherein the carrier substrate includes a second bonding film, and a bonding interface is formed between the first bonding film and the second bonding film; The first substrate is processed from the second side to remove at least a portion of the first substrate; and A second interconnect structure is formed on the device layer.

10. A semiconductor structure, comprising: First structure; The second structure is stacked on top of the first structure; A first bonding film is formed on the first structure, wherein the first bonding film includes a thermally conductive dielectric layer; A second bonding film is formed on the second structure; and A bonding interface is located between the first bonding film and the second bonding film, wherein the bonding interface includes Al-O bonds.

Images