A method of forming a semiconductor structure, a semiconductor structure, and a memory

Abstract

The present disclosure provides a semiconductor structure forming method, a semiconductor structure and a memory. The forming method comprises: providing a wafer; determining a virtual bonding mapping pattern and a chip bonding mapping pattern of the wafer; wherein the virtual bonding mapping pattern and the chip bonding mapping pattern are in a complementary configuration relative to the wafer, and the virtual bonding mapping pattern corresponds to an edge region of the wafer; exposing and etching the wafer based on the chip bonding mapping pattern to form a chip bonding region, and the edge region of the wafer corresponding to the virtual bonding mapping pattern forms an edge layer; and bonding a plurality of chips in the chip bonding region to form a semiconductor structure; wherein each chip in the plurality of chips is a complete chip. In the present disclosure, the chip bonding region and the edge layer can uniformly bear stress, thereby avoiding the generation of bubbles, balancing the stress distribution in subsequent processes, and reducing the risk of wafer warping, thereby effectively improving the yield and process reliability of the chip bonding process of the wafer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a method for forming a semiconductor structure, a semiconductor structure, and a memory. Background Technology

[0002] Die-to-wafer (D2W) bonding is a process in which individual, pre-cut and selected dies are precisely aligned and bonded onto a whole wafer. Hybrid bonding is typically used in D2W. Due to wafer topography limitations, placing dies at wafer edges can cause issues such as edge lifting and bubbles. Therefore, dummy dies are bonded to these areas to improve the surface flatness of the entire wafer after D2W bonding.

[0003] Currently, small-sized bare silicon (Bare Si) is typically used as virtual chips at the edge of the wafer. However, bare silicon and functional chips differ in materials and coefficients of thermal expansion, which can easily lead to defects such as warping and bonding interface delamination in subsequent high-temperature processes. Furthermore, bonding virtual chips consumes lithography machine time, affecting the efficiency of the D2W process. Summary of the Invention

[0004] This disclosure provides a method for forming a semiconductor structure, a semiconductor structure, and a memory.

[0005] In a first aspect, embodiments of this disclosure provide a method for forming a semiconductor structure, including: Provide wafers; The virtual bonding mapping pattern and the chip bonding mapping pattern of the wafer are determined; wherein the virtual bonding mapping pattern and the chip bonding mapping pattern are complementary to the wafer, and the virtual bonding mapping pattern corresponds to the edge region of the wafer; The wafer is exposed and photolithographically ... Multiple chips are bonded within the chip bonding region to form a semiconductor structure; wherein each of the multiple chips is a complete chip.

[0006] In some embodiments, determining the virtual bonding mapping pattern of the wafer and the chip bonding mapping pattern specifically includes: Based on the size of the chip, determine the corresponding exposure field size of the chip; The effective bonding region on the wafer is calculated based on the exposure field size, and an initial mapping pattern is obtained based on the effective bonding region. Based on the effective bonding region, a virtual exposure field is determined, and the virtual bonding mapping pattern is obtained based on the virtual exposure field; Based on the virtual exposure field and the initial mapping pattern, the target exposure field that the lithography machine needs to execute is calculated, and the chip bonding mapping pattern is obtained based on the target exposure field.

[0007] In some embodiments, calculating the effective bonding region on the wafer based on the exposure field size specifically includes: According to the exposure field size, the chip exposure field corresponding to the chip is arranged in an array on the wafer according to a preset arrangement rule, excluding the part involving the edge of the wafer, to obtain the effective bonding area.

[0008] In some embodiments, the preset arrangement rule includes at least a rectangular array arrangement or a hexagonal array arrangement, and the chip retains preset cutting channels around its perimeter; The chip bonding area also includes a gap; the gap is adjacent to the edge layer; metal interconnects are arranged in the gap, and the metal interconnects are electrically connected to the chip bonded in the chip bonding area.

[0009] In some embodiments, calculating the target exposure field that the lithography machine needs to perform based on the virtual exposure field and the initial mapping pattern, and obtaining the chip bonding mapping pattern based on the target exposure field, specifically includes: By filtering out the exposure fields in the initial mapping pattern where the pre-bonded chip intersects with the edge of the wafer and the boundary of the virtual exposure field, candidate target exposure fields are obtained. The intersection area of ​​the candidate target exposure field with the outline of the wafer and the boundary of the virtual exposure field is detected, and the candidate target exposure field is skipped according to preset conditions; The candidate target exposure fields that have not been skipped are identified as the target exposure fields, and the initial mapping pattern is updated based on the target exposure fields to obtain the chip bonding mapping pattern.

[0010] In some embodiments, the step of performing photolithography on the wafer based on the chip bonding mapping pattern to form a chip bonding region specifically includes: A protective layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer are sequentially deposited on the wafer along a first direction, wherein the first direction is perpendicular to the surface of the wafer; A photoresist layer is formed on the surface of the third sacrificial layer along the first direction; Using the chip bonding mapping pattern as a mask, the photoresist layer is exposed and developed to form a patterned photoresist layer; Using the patterned photoresist layer as a mask, the third sacrificial layer is etched until the surface of the second sacrificial layer is exposed; Using the etched third sacrificial layer as a mask, the second sacrificial layer is etched until the surface of the first sacrificial layer is exposed; Using the etched second sacrificial layer as a mask, the first sacrificial layer is etched until the surface of the protective layer is exposed; Using the etched first sacrificial layer as a mask, the protective layer is etched until the bonding surface of the wafer surface is exposed, forming the chip bonding region.

[0011] In some embodiments, bonding multiple chips within the chip bonding region to form a semiconductor structure specifically includes: The surface of the wafer is subjected to surface activation treatment; The pre-bonded chip is aligned and bonded to the chip bonding area; After the chip and the wafer are bonded, the dicing channel between the chip and the wafer is filled with a dielectric material to form the semiconductor structure.

[0012] Secondly, embodiments of this disclosure provide a semiconductor structure, including a wafer, a perimeter, and multiple chips; The wafer includes a chip bonding region, and the edge layer is disposed in the edge region of the wafer. The chip bonding region and the edge layer are complementary in configuration to the wafer. Each chip bonded in the chip bonding region is a complete chip.

[0013] In some embodiments, the edge layer is further disposed along a first direction at the edge of the chip bonding region.

[0014] Thirdly, embodiments of this disclosure provide a memory comprising a semiconductor structure manufactured according to the semiconductor structure formation method described in any one of the first aspects or a semiconductor structure as described in any one of the second aspects.

[0015] Fourthly, embodiments of this disclosure provide an electronic device, the electronic device including a memory as described in the third aspect.

[0016] This disclosure provides a method for forming a semiconductor structure, a semiconductor structure, and a memory. The method involves determining a virtual bonding mapping pattern and a chip bonding mapping pattern for a wafer. The virtual bonding mapping pattern and the chip bonding mapping pattern are complementary to the wafer, with the virtual bonding mapping pattern corresponding to the edge region of the wafer. Photolithography is performed on the wafer based on the chip bonding mapping pattern to form a chip bonding region, and the edge region of the wafer corresponding to the virtual bonding mapping pattern forms a side layer. Multiple chips are bonded within the chip bonding region to form a semiconductor structure, where each of the multiple chips is a complete chip. In this disclosure, both the chip bonding region and the side layer of the wafer can be uniformly stressed, thereby avoiding bubbles caused by uneven stress at the bonding interface and balancing the stress distribution in subsequent high-temperature processes. This reduces the risk of wafer warpage and bonding interface delamination, effectively improving the yield and process reliability of the chip bonding process. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a preset wafer plane provided in an embodiment of the present disclosure; Figure 2 A schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this disclosure; Figure 3 A schematic diagram of the structure obtained during the formation process of a semiconductor structure provided in this disclosure embodiment. Figure 1 ; Figure 4 A schematic diagram of the structure obtained during the formation process of a semiconductor structure provided in this disclosure embodiment. Figure 2 ; Figure 5 A schematic diagram of the structure obtained during the formation process of a semiconductor structure provided in this disclosure embodiment. Figure 3 ; Figure 6 A schematic diagram of the structure obtained during the formation process of a semiconductor structure provided in this disclosure embodiment. Figure 4 ; Figure 7 A schematic diagram of the structure obtained during the formation process of a semiconductor structure provided in this disclosure embodiment. Figure 5 ; Figure 8 A schematic diagram of the structure obtained during the formation process of a semiconductor structure provided in this disclosure embodiment. Figure 6 ; Figure 9 A schematic diagram of the structure obtained during the formation process of a semiconductor structure provided in this disclosure embodiment. Figure 7 ; Figure 10A schematic diagram of the structure obtained during the formation process of a semiconductor structure provided in this disclosure embodiment. Figure 8 ; Figure 11 A schematic diagram of the structure obtained during the formation process of a semiconductor structure provided in this disclosure embodiment. Figure 9 ; Figure 12 A schematic diagram of the structure obtained during the formation process of a semiconductor structure provided in this disclosure embodiment. Figure 10 ; Figure 13 A schematic diagram of the structure obtained during the formation process of a semiconductor structure provided in this disclosure embodiment. Figure 10 one; Figure 14 A schematic diagram of the structure obtained during the formation process of a semiconductor structure provided in this disclosure embodiment. Figure 10 two; Figure 15 A schematic diagram of the structure obtained during the formation process of a semiconductor structure provided in this disclosure embodiment. Figure 10 three; Figure 16 A schematic diagram of a semiconductor structure provided in this embodiment of the disclosure. Figure 1 ; Figure 17 A schematic diagram of a semiconductor structure provided in this embodiment of the disclosure. Figure 2 ; Figure 18 A schematic diagram of a semiconductor structure provided in this embodiment of the disclosure. Figure 3 ; Figure 19 A schematic diagram of a semiconductor structure obtained during the formation process provided in this embodiment of the disclosure. Figure 10 Four; Figure 20 This is a schematic diagram of a memory structure provided in an embodiment of the present disclosure; Figure 21 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0018] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining the relevant applications and are not intended to limit the scope of this disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0020] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0021] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0022] In an exemplary embodiment of this disclosure, reference is made to Figure 1 It provides a preset wafer 01 and a corresponding virtual chip 02, wherein the virtual chip 02 is configured to fill the edge region of the wafer in the wafer bonding process to achieve stress equalization. Here, Figure 1 The square grid filled with a mesh pattern represents the chips bonded during the chip-to-wafer bonding process.

[0023] Understandably, due to the inherent shape limitations of the pre-set wafer 01, the edge region of the pre-set wafer 01 cannot be completely covered with chips of the same specifications as the central region (i.e., the square grid filled with a mesh pattern in the figure). If the edge region of the pre-set wafer 01 is in a blank state without chip filling, the stress and heat conditions of the edge and central regions of the pre-set wafer 01 will be uneven during bonding pressure and subsequent high-temperature processes. This can easily lead to chip warping and bubbles forming at the bonding interface, resulting in a decrease in the surface flatness of the entire pre-set wafer 01, which in turn affects the processing effect and accuracy of subsequent photolithography, chemical mechanical polishing, etc. Therefore, a virtual chip 02 is bonded to the blank edge region of the pre-set wafer 01. By filling the edge region with the virtual chip 02 to balance the stress, the overall in-plane flatness of the pre-set wafer 01 after bonding can be improved.

[0024] However, the virtual chip 02 differs significantly from the chip bonded to the central region in terms of material composition, device structure, and coefficient of thermal expansion. In subsequent processes such as high-temperature annealing and dielectric layer deposition after bonding, thermal deformation will introduce additional thermal stress, which can easily lead to reliability issues such as pre-set wafer warpage and bonding interface delamination. At the same time, the virtual chip 02 requires bonding equipment to perform pick-up, alignment, and bonding processes separately, which adds extra process steps and restricts the overall production efficiency of the chip for wafer bonding process.

[0025] Based on this, the present disclosure provides a method for forming a semiconductor structure; wherein the method requires determining a virtual bonding mapping pattern and a chip bonding mapping pattern of a wafer; the virtual bonding mapping pattern and the chip bonding mapping pattern are complementary configurations relative to the wafer, and the virtual bonding mapping pattern corresponds to the edge region of the wafer; the wafer is exposed and photolithographically ...

[0026] In this embodiment of the disclosure, a method for forming a semiconductor structure is provided, the process flow diagram of which can be found in [reference needed]. Figure 2 It can include: S1, Provide wafers.

[0027] S2. Determine the virtual bonding mapping pattern of the wafer and the chip bonding mapping pattern; wherein the virtual bonding mapping pattern and the chip bonding mapping pattern are complementary to the wafer, and the virtual bonding mapping pattern corresponds to the edge region of the wafer.

[0028] Here, the chip bonding mapping pattern, or bond mapping, is a layout pattern that defines the bonding positions of chips on the wafer surface. It can be determined through calculations such as bonding process simulation.

[0029] In some embodiments, the present disclosure arranges the chip bonding mapping pattern to the central region of the wafer and the virtual bonding mapping pattern to the edge region of the wafer, with the two being complementary relative to the wafer. Here, the complementary configuration means that within the planar projection range of the wafer, the arrangement areas of the chip bonding mapping pattern and the virtual bonding mapping pattern do not overlap, and the adjacent boundaries of the two types of patterns are closely connected, and the union of their areas completely covers the surface of the wafer.

[0030] Here, the edge region can be a ring-shaped area surrounding the central region of the wafer. Due to the boundary of the wafer's own topography, a complete chip cannot be arranged in this region.

[0031] S3. Based on the chip bonding mapping pattern, the wafer is exposed and photolithographically lithographically formed to form the chip bonding area, and the edge area of ​​the wafer corresponding to the virtual bonding mapping pattern forms the edge layer.

[0032] It is understandable that the edge layer here is a structure formed by not performing an exposure process on the corresponding area of ​​the wafer, based on a virtual bonding mapping pattern.

[0033] In the semiconductor structure fabrication process, this disclosure only performs exposure, development and subsequent etching processes on the central region corresponding to the chip bonding mapping pattern, and does not perform exposure operations on the edge region corresponding to the virtual bonding mapping pattern, thereby forming an edge layer that is integrally formed with the wafer structure; here, forming an edge layer without exposure means that the photoresist in the edge region has not undergone exposure and development steps, and no functional bonding pads and interconnection lines are fabricated in this region.

[0034] Since the edge layer is formed based on the virtual bonding mapping pattern and the chip bonding region is formed based on the chip bonding mapping pattern, and the virtual bonding mapping pattern and the chip bonding mapping pattern are complementary in configuration to the wafer, the edge layer and the chip bonding region are complementary in configuration to the wafer. Here, complementary configuration means that within the planar projection range of the wafer, the edge layer and the chip bonding region do not overlap, and the adjacent boundaries of the edge layer and the chip bonding region are closely connected, and the union of their regions completely covers the surface of the wafer.

[0035] S4. Multiple chips are bonded in the chip bonding area to form a semiconductor structure; each of the multiple chips is a complete chip.

[0036] Here, a complete chip can be a chip with a complete physical structure, no cutting defects, and complete circuit functions.

[0037] Here, after the chip and wafer are bonded, the top surface of all chips and the top surface of the edge layer are on the same horizontal plane, closely adjacent and without height difference. "Without height difference" means that there are no obvious step differences or abrupt changes in morphology after bonding. This ensures the surface flatness of the entire wafer after bonding, thus avoiding bubbles caused by uneven stress at the bonding interface. It also balances the stress distribution in subsequent high-temperature processes, reducing the risk of wafer warpage and bonding interface delamination, effectively improving the yield and process reliability of the chip-to-wafer bonding process. Furthermore, this disclosure eliminates the need for additional virtual chip picking and bonding, saving lithography machine time and improving the production efficiency of the lithography equipment.

[0038] In this embodiment of the disclosure, step S2, determining the virtual bonding mapping pattern of the wafer and the chip bonding mapping pattern, may specifically include: S21. Determine the exposure field size corresponding to the chip based on the chip size.

[0039] It is understandable that the exposure field size (shot size) refers to the physical size of the pattern area formed on the wafer by a single exposure of a lithography machine, usually in millimeters. The exposure field corresponding to a single exposure can contain one or more complete chip patterns. The upper limit of the exposure field size is determined by the field of view hardware parameters of the projection system of the lithography machine. The specific size actually used is within the range of this upper limit, and the optimal solution is determined by the chip parameters with the goal of maximizing production efficiency.

[0040] Here, the maximum field of view defined by the lithography machine is a hard constraint on the size of the exposure field. The actual size of the exposure field must always be limited within the maximum field of view of the lithography machine. The planar size and area of ​​the chip are the core factors that determine the final size of the exposure field. Specifically, with the goal of maximizing the utilization rate of the lithography field of view, based on the chip size parameters, within the constraint range of the maximum field of view of the lithography machine, the size of the exposure field that is closest to the boundary of the maximum field of view and can just accommodate an integer number of complete chips is calculated. This maximizes the effective chip output of a single exposure, reduces the total number of exposures in the whole wafer processing, and improves the overall capacity of wafer manufacturing.

[0041] In some embodiments, the exposure field size corresponding to the chip can be 4×4mm to 52×66mm.

[0042] In some embodiments, the exposure field size corresponding to the chip can be 26×33mm.

[0043] S22. Calculate the effective bonding area on the wafer based on the exposure field size, and obtain the initial mapping pattern based on the effective bonding area.

[0044] refer to Figure 3 and Figure 4 The effective bonding region 111 refers to the central region on the surface of wafer 110 after removing the edge portions, where standard processes can be stably supported and chips can be completely deployed. It can be understood that the effective bonding region 111 is a continuous region formed by stitching together exposure fields that conform to the exposure field size. The initial mapping pattern 112 and the projection of the effective bonding region 111 along the first direction completely overlap, where the first direction is perpendicular to the wafer surface. Figure 4 The overlapping portion of the outline of the initial mapping pattern 112 shown indicates the portion of the initial mapping pattern 112 that overlaps with the subsequently determined virtual bonding mapping pattern 121.

[0045] S23. Determine the virtual exposure field based on the effective bonding region, and obtain the virtual bonding mapping pattern based on the virtual exposure field.

[0046] refer to Figure 3 and Figure 4Based on the effective bonding area 111 of the chip, in the area between the outer boundary of the effective bonding area 111 and the outline boundary of the wafer 110, virtual exposure fields 120 (dummy shots) with the same size specifications as the exposure fields corresponding to the aforementioned chips are arranged. Then, according to the arrangement position of all virtual exposure fields 120, the set of bonding point coordinates of all virtual chips is generated, and the virtual bonding mapping pattern 121 can be obtained.

[0047] Here, the process can be understood as calculating the virtual exposure field 120 that needs to be laid out at the edge of wafer 110 based on the area already covered with chips, and finally generating the corresponding virtual bonding mapping pattern 121 (see below). Figure 5 As shown); the virtual exposure field 120 adopts the same size standard as the exposure field corresponding to the aforementioned chip, which can ensure that the exposure field array of the entire wafer 110 is continuous and regular, avoiding the problem of uneven bonding force caused by specification differences.

[0048] S24. Based on the virtual exposure field and the initial mapping pattern, calculate the target exposure field that the lithography machine needs to execute, and obtain the chip bonding mapping pattern based on the target exposure field.

[0049] refer to Figure 4 and Figure 5 Based on the exposure fields corresponding to all chips covered by the initial mapping pattern 112, the parts intersecting with the virtual exposure field 120 are excluded to obtain the total target exposure field 130 for which the lithography machine needs to perform exposure operations. Then, according to the preset chip arrangement rules in the target exposure field 130, the bonding coordinate information of all complete chips is extracted to generate the chip bonding mapping pattern 131. It can be understood that the chip bonding mapping pattern 131 and the projection of the target exposure field 130 along the first direction completely overlap.

[0050] Here, the process can be understood as calculating the set of exposure fields that the lithography machine actually needs to perform exposures based on the virtual exposure field 120 that needs to be set up at the edge of the wafer 110.

[0051] In some embodiments, reference Figure 6 It shows a schematic diagram of the wafer 110 structure after exposure is performed by the lithography machine according to the dummy-shot setup recipe 120. Figure 6 As can be seen, by exposing and photolithography on the wafer 110 based on the chip bonding mapping pattern 131 obtained from the target exposure field 130, a chip bonding region 132 can be formed; it can be understood that the chip bonding region 132 and the chip bonding mapping pattern 131 are completely overlapped by projection along the first direction.

[0052] In this embodiment of the disclosure, calculating the effective bonding region on the wafer based on the exposure field size may specifically include: Based on the exposure field size, the chip exposure field corresponding to the chip is arranged in an array on the wafer according to a preset arrangement rule, excluding the part involving the wafer edge, to obtain the effective bonding area.

[0053] In some embodiments, reference Figures 2-6 It can be seen that: the effective bonding region 111 on wafer 110 is calculated based on the exposure field size. Specifically, according to the determined exposure field size, the chip exposure field carrying the corresponding chip pattern is used as the basic arrangement unit and laid out within the plane of wafer 110 according to a preset arrangement rule; the positional relationship between each chip exposure field and the edge contour of wafer 110 is checked one by one, and chip exposure fields involving the edge of wafer 110 and unable to completely carry the chip pattern are excluded. The continuous area covered by the remaining chip exposure fields is the effective bonding region 111 of wafer 110. Here, the chip exposure field is the exposure field corresponding to the exposure field size of the chip in the aforementioned embodiment.

[0054] In the embodiments disclosed herein, the preset arrangement rules include at least a rectangular array arrangement or a hexagonal array arrangement, and preset cutting channels are reserved around the perimeter of the chip.

[0055] Here, rectangular array arrangement refers to all chip exposure fields being aligned along the row and column directions; hexagonal array arrangement refers to adjacent rows of chip exposure fields being staggered; in this embodiment, the preset arrangement rule can also be other types of rules, which can be determined according to the actual situation, and no specific limitation is made.

[0056] In some embodiments, the chip bonding region further includes a gap; the gap is adjacent to the edge layer; and metal interconnects are arranged in the gap, the metal interconnects being electrically connected to a plurality of chips bonded in the chip bonding region.

[0057] The gap serves as an outer component of the chip bonding area, adjacent to the edge layer, and allows chip signals to be led out through internally arranged metal interconnects.

[0058] In some embodiments, the gap is in a closed loop around the circumference of the chip bonding area, with its outer edge adjacent to the inner edge of the edge layer, and the inner edge enclosing the core bonding area of ​​the chip bonding area; the multiple chips are all bonded within this core bonding area, and multiple sets of mutually insulated metal interconnects are arranged in the gap, each set of metal interconnects being electrically connected to the chip to lead the input and output signals of each chip to the peripheral functional circuit.

[0059] In some embodiments, the gap may be annular in shape.

[0060] In this embodiment of the disclosure, the width of the gap ranges from 2μm to 20μm.

[0061] It is understood that different ways can be used to define the gap: it can be included within the chip bonding area as described in the embodiments of this disclosure, as a peripheral component of the chip bonding area; or it can be defined as an independent region located between the chip bonding area and the edge layer, i.e., one side of the gap is adjacent to the edge layer, and the other side is adjacent to the chip bonding area, with the projections of all three along the first direction completely covering the surface area of ​​the wafer. Any technical solution possessing the corresponding structural features and achieving the same technical effect falls within the protection scope of this disclosure, and this disclosure does not impose any additional limitations on it.

[0062] In addition, the dicing channels reserved between chips are used to provide space for subsequent wafer dicing processes, avoiding damage to the functional structure of the chips during the dicing process.

[0063] In this embodiment of the disclosure, step S24, calculating the target exposure field that the lithography machine needs to perform based on the virtual exposure field and the initial mapping pattern, and obtaining the chip bonding mapping pattern based on the target exposure field, may specifically include: S241. Screen out the exposure fields in the initial mapping pattern where the pre-bonded chip intersects with the edge of the wafer and the boundary of the virtual exposure field to obtain the candidate target exposure fields.

[0064] Here, the process equipment can automatically calculate the global coordinates of all exposure fields based on the exposure field size, wafer diameter, virtual mask field size, etc. After screening is enabled, the system automatically skips all exposure fields that intersect with the wafer edge contour or with the virtual exposure field boundary.

[0065] It is understandable that the exposure field is the smallest unit for performing photolithography and bonding processes, and a single chip is a functional unit within the exposure field. Within the rectangular area of ​​an exposure field, the chip will not be completely filled: process redundancy areas such as scribe lines, alignment marks, and test patterns will be reserved around the chip array, and there will be a preset safety margin between the chip edge and the boundary of the exposure field.

[0066] Here, the criterion is whether the chip intersects with the boundary. As long as the chip is intact, the exposure field is determined to be a candidate target exposure field.

[0067] S242. Detect the intersection area of ​​the candidate target exposure field with the outline of the wafer and the boundary of the virtual exposure field, and skip the candidate target exposure field according to preset conditions.

[0068] In some embodiments, it is determined whether the effective intersection area ratio is lower than the determination threshold. In this case, the preset conditions may include: if the effective intersection area ratio is less than the determination threshold, it is determined that the exposure field does not meet the photolithography process requirements and is marked as a skipped state where exposure is not performed; specifically: the system calculates the actual intersection area of ​​each candidate target exposure field with the wafer outline and the virtual exposure field boundary one by one, and presets the lower limit of the effective area (actual intersection area) ratio of the exposure field as the determination threshold.

[0069] In some embodiments, the determination threshold can be 100%.

[0070] S243. The candidate target exposure fields that have not been skipped are determined as the target exposure fields. The initial mapping pattern is updated based on the target exposure fields to obtain the chip bonding mapping pattern.

[0071] In some embodiments, if the intersection area of ​​candidate target exposure fields is less than the product of the minimum coverage ratio and the exposure field size, or falls within the edge exclusion region, the candidate target exposure field is marked as skipped; wherein the edge exclusion region is the area within a preset safety margin from the wafer edge and the mask field edge, and exposure fields within this range will be forcibly excluded.

[0072] In some embodiments, the preset safety margin can be 50~200μm.

[0073] In some embodiments, the target exposure field is marked as the exposure state for which an exposure is performed.

[0074] Here, the minimum coverage ratio is a pre-configured process judgment ratio parameter used to limit the minimum area ratio of the exposure field falling within the effective range of the wafer. When it is required that the exposure field completely falls within the effective outline of the wafer, the minimum coverage ratio can be set to 1 (corresponding to 100% ratio).

[0075] The product of the minimum coverage ratio and the exposure field size represents the minimum effective area threshold for a single exposure field to meet process compliance requirements. Multiplying the minimum coverage ratio (in proportional form) by the total area of ​​the exposure field yields the judgment threshold in absolute area. This threshold represents the minimum effective coverage area of ​​the exposure field that must fall within the legal range of the wafer outline and the virtual exposure field boundary to be feasible for performing photolithography and bonding pressurization processes. If the actual intersection area is less than this threshold, it indicates that the effective coverage area of ​​the exposure field does not meet the minimum process requirements, and defects such as photolithography defocusing and bubbles are likely to occur. Therefore, this exposure field is marked as skipped and is not considered a target exposure field.

[0076] Understandably, lithography machines operate according to a preset program. During the actual execution phase of the lithography process, only the target exposure fields marked as being in the exposure state undergo optical valve / mask alignment and exposure operations. Here, after the aforementioned intersection area determination and edge exclusion area verification, the system marks each exposure field in the wafer with an exposure state or a skip state. It only retrieves the coordinates of the target exposure fields marked as being in the exposure state, skipping all exposure fields marked as being in the skip state. This eliminates the need for alignment and exposure operations, reducing invalid process actions and improving the operating efficiency of the lithography equipment.

[0077] In one embodiment, a strict exposure mode can be enabled, in which the system automatically sets the minimum coverage ratio to 100%. In this mode, only complete exposure fields are marked as exposed and exposure is performed.

[0078] In this embodiment of the disclosure, step S3, performing photolithography on the wafer based on the chip bonding mapping pattern to form the chip bonding area, may specifically include: refer to Figure 7 A protective layer 140, a first sacrificial layer 141, a second sacrificial layer 142 and a third sacrificial layer 143 are sequentially deposited above the wafer 110 along a first direction, the first direction being perpendicular to the surface of the wafer 110. In some embodiments, reference Figure 8 The wafer 110 may include a substrate 113, and a tetraethyl orthosilicate layer 114 and an isolation layer 115 sequentially formed on the substrate along a first direction. The tetraethyl orthosilicate layer 114 is made of tetraethyl orthosilicate (TEOS), which is a liquid precursor for depositing silicon dioxide thin films. After undergoing a decomposition reaction on the substrate through a chemical vapor deposition process, it forms a silicon dioxide (SiO2) insulating dielectric film. The wafer 110 may also include metal interconnects 116, which penetrate the tetraethyl orthosilicate layer 114 and the isolation layer 115, for signal transmission with the chip to be bonded (or pre-bonded).

[0079] Here, combined Figure 7 and Figure 8 As shown, a protective layer 140, a first sacrificial layer 141, a second sacrificial layer 142 and a third sacrificial layer 143 are sequentially deposited above the isolation layer 115 of the wafer 110 along a first direction.

[0080] In some embodiments, the material of the protective layer 140 includes, but is not limited to, a stacked structure formed by any one or more of the following materials: titanium nitride, tantalum nitride, titanium-tantalum alloy, silicon nitride, and silicon oxynitride; the protective layer 140 is used to block electrical failure problems caused by the diffusion of metal atoms at the bonding interface.

[0081] In some embodiments, the first sacrificial layer 141 and the third sacrificial layer 143 are made of the same material.

[0082] In some embodiments, the first sacrificial layer 141 and the third sacrificial layer 143 may be made of oxide.

[0083] In some embodiments, the material of the second sacrificial layer 142 is the same as the material of the surface dielectric layer of the chip.

[0084] refer to Figure 9 A photoresist layer 144 is formed on the surface of the third sacrificial layer 143 along the first direction.

[0085] Understandably, the third sacrificial layer 143 has better interfacial adhesion to the photoresist. Forming a photoresist layer 144 on the surface of the third sacrificial layer 143 can strengthen the adhesion between the photoresist and the underlying medium, reducing the risk of photoresist detachment and pattern drift during photolithography development and pattern transfer.

[0086] refer to Figure 10 Using the chip bonding mapping pattern as a mask, the photoresist layer 144 is exposed and developed to form a patterned photoresist layer 144. refer to Figure 11 Using the patterned photoresist layer 144 as a mask, the third sacrificial layer 143 is etched until the surface of the second sacrificial layer 142 is exposed.

[0087] In some embodiments, after the surface of the second sacrificial layer 142 is exposed, the residual photoresist layer 144 is removed.

[0088] refer to Figure 12 Using the etched third sacrificial layer 143 as a mask, the second sacrificial layer 142 is etched until the surface of the first sacrificial layer 141 is exposed.

[0089] In some embodiments, after the surface of the first sacrificial layer 141 is exposed, the remaining third sacrificial layer 143 is removed.

[0090] refer to Figure 13 Using the etched second sacrificial layer 142 as a mask, the first sacrificial layer 141 is etched until the surface of the protective layer 140 is exposed. See Figure 14 Using the etched first sacrificial layer 141 as a mask, the protective layer 140 is etched until the bonding surface of the wafer 110 is exposed, forming the chip bonding region 132.

[0091] Here, the remaining first sacrificial layer 141 and protective layer 140 are the formed edge layer 122.

[0092] It is understood that the removal of the residual photoresist layer 144, the third sacrificial layer 143, and the second sacrificial layer 142 can be achieved by wet cleaning, or by dry ashing, dry stripping, or a combination of wet and dry cleaning processes. These removal processes are merely examples and do not constitute a limitation of this disclosure. In this disclosure, the first sacrificial layer 141, the second sacrificial layer 142, and the third sacrificial layer 143 can be either single-layer structures or multi-layer stacked composite dielectric structures. Furthermore, this disclosure employs a sequential etching method with two oxide layers, which can improve the thickness distribution deviation of the wafer 110, enhance the overall uniformity of the dielectric layer, and ensure the flatness of the subsequent bonding interface.

[0093] In this embodiment of the disclosure, step S4, bonding multiple chips within the chip bonding region 132 to form a semiconductor structure 100, may specifically include: refer to Figure 15 Surface activation treatment is performed on the surface of wafer 110; Here, surface activation treatment refers to using plasma to bombard the bonding surface of wafer 110 in an inert gas atmosphere. The plasma bombardment will generate hydrophilic hydroxyl groups on the bonding surface of wafer 110, thereby improving the bonding force between the chip and the bonding interface of wafer 110, strengthening the bonding strength of the hybrid bonding interface, and reducing process defects such as bonding delamination and interface bubbles.

[0094] refer to Figure 16 The pre-bonded chip is aligned and bonded to the chip bonding area 132; In some embodiments, the alignment and bonding operation is performed by the bonding equipment: the bonding head 03 of the bonding equipment picks up the chip 04, completes the position alignment and calibration of the chip and the wafer 110, and then bonds the chip 04 to the chip bonding area 132.

[0095] refer to Figure 17 After the chip and wafer 110 are bonded, dielectric material 150 is filled in the dicing channel (not shown in the figure) between chip 04 and wafer 110 to form semiconductor structure 100.

[0096] The dielectric material 150 is an insulating dielectric material; in some embodiments, the dielectric material 150 may be a silicon dioxide dielectric deposited using tetraethyl orthosilicate as a precursor. It should be understood that the specific material of the dielectric material 150 described above is merely illustrative and does not constitute a limitation of this disclosure. Depending on actual process requirements and device design requirements, insulating materials with gap-filling capabilities, such as silicon nitride, silicon oxynitride, and photosensitive insulating polymers, may also be selected, and this disclosure does not impose any restrictions on this.

[0097] Understandably, after chip 04 is bonded to wafer 110, since the virtual exposure field at the edge of wafer 110 does not need to be fitted with a virtual chip, a high-temperature annealing process can be directly performed, thereby improving the bonding strength and interface stability of the bonding interface. The use of a deposition process to fill the dicing channel with dielectric material can effectively avoid bubble defects caused by uneven dielectric deposition in the edge area of ​​wafer 110. At the same time, it can form a stress buffer for chip 04 in the edge area, reducing the risk of chip 04 near the edge area breaking under stress during the subsequent wafer 110 thinning process.

[0098] In other embodiments of this disclosure, a semiconductor structure 100 is also provided, with reference to... Figure 18 The semiconductor structure 100 may include a wafer 110, a side layer 122, and multiple chips 04; The wafer 110 includes a chip bonding region 132 and an edge layer 122 disposed in the edge region of the wafer 110. The chip bonding region 132 and the edge layer 122 are complementary in configuration to the wafer 110. Each chip 04 bonded in the chip bonding region 132 is a complete chip.

[0099] Here, the edge layer 122 is disposed in the edge region of the wafer 110 and is formed corresponding to the virtual bonding mapping pattern in the aforementioned embodiment. The chip bonding region 132 is formed corresponding to the chip bonding mapping pattern in the aforementioned embodiment. The virtual bonding mapping pattern and the chip bonding mapping pattern are complementary in configuration to the wafer 110. Therefore, the edge layer 122 and the chip bonding region 132 are complementary in configuration to the wafer 110. Here, complementary configuration means that within the planar projection range of the wafer 110, the edge layer 122 and the chip bonding region 132 do not overlap, and the adjacent boundaries of the edge layer 122 and the chip bonding region 132 are closely connected. The union of their regions completely covers the surface of the wafer 110.

[0100] In the chip bonding region 132, the top surface of each chip 04 bonded therein is at the same level as the upper surface of the edge layer 122. The two are closely adjacent and have no height difference. Here, "no height difference" means that there is no obvious step difference or abrupt change in morphology after bonding. This ensures the surface flatness of the entire wafer 110 after bonding. This avoids the generation of bubbles due to uneven stress at the bonding interface and can also balance the stress distribution in subsequent high-temperature processes, thereby reducing the risk of wafer warpage and bonding interface delamination, and effectively improving the yield and process reliability of chip bonding to wafer bonding. At the same time, this disclosure eliminates the need for additional picking and bonding of virtual chips, saving the bonding process of virtual chips, saving lithography machine time, and improving the production efficiency of lithography equipment.

[0101] In summary, for reference Figure 19 ,in Figure 19Figure (A) shows the positional distribution of the virtual exposure field 120 and the target exposure field 130 relative to the wafer 110. Each rectangular grid in the figure corresponds to a chip bonding space, and each bonding space within the coverage area of ​​the target exposure field corresponds to a complete chip. The virtual exposure field 120 is located in the edge region of the wafer 110. Due to the spatial constraints of the circular outline of the wafer 110, the bonding space inside it corresponds to an incomplete virtual chip structure and does not have the process conditions to support a complete chip.

[0102] refer to Figure 19 In (B), during the lithography exposure stage, the target exposure field 130 is included in the exposure operation range (i.e., the dot-filled part) to complete the exposure of the bonding pattern; the virtual exposure field 120 corresponding to the edge region of the wafer 110 is set to the skip state and the exposure process is not performed.

[0103] After exposure is completed, the wafer undergoes etching, wet cleaning, surface activation and other process steps in sequence to form a hybrid bonding interface in the region corresponding to the target exposure field, which is the corresponding chip bonding area for chip mounting; a side layer structure is formed in the region corresponding to the virtual exposure field. The side layer and the chip bonding area are closely connected to each other on the wafer surface without overlapping, and the overall arrangement is complementary.

[0104] refer to Figure 19 In the (C) stage of chip bonding to wafer, chip alignment and bonding are completed only in the chip bonding area 132 corresponding to the target exposure field 130; the edge layer 122 area corresponding to the virtual exposure field 120 does not need to be chip mounted, and can directly enter the subsequent high-temperature annealing, dielectric filling and other processes. This can not only balance the stress distribution and process uniformity of the wafer through the edge layer 122, but also avoid the yield loss caused by mounting defective chips in the edge area.

[0105] In embodiments of this disclosure, the edge layer may also be disposed along the first direction at the edge of the chip bonding area.

[0106] Here, the edge layer is arranged around the periphery of the chip bonding area on the plane where the wafer is located, and extends along the first direction of the bonding surface. Its size along the first direction can be flexibly configured according to the process requirements.

[0107] In other embodiments of this disclosure, reference is made to Figure 20 A memory 200 is provided, including a semiconductor structure manufactured according to the semiconductor structure formation method of any of the foregoing embodiments or a semiconductor structure 100 as described in any of the foregoing embodiments.

[0108] Here, the term "memory" refers to any physical device or module used to store data, including but not limited to: memory chips, memory dies, multi-chip packages, ball grid array packaged memory, single in-line memory modules, dual in-line memory modules, small outline dual in-line memory modules, micro dual in-line memory modules, registered memory, low-load memory, high-bandwidth memory, solid-state drives, embedded multimedia cards, general-purpose flash memory, memory cards, and on-board packaged or integrated memory units.

[0109] In yet another embodiment of this disclosure, reference is made to Figure 21 An electronic device 300 is provided, which includes a memory 200 as described in the foregoing embodiments. The electronic device 300 may be a user equipment (UE), mobile device, handheld device, computing device, vehicle-mounted device, wearable device, etc.

[0110] Examples include: personal computers (PCs), mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), enterprise digital assistants (EDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, server computers, data centers, workstations, mobile phones, smartphones, and tablets.

[0111] For details not disclosed in the embodiments of this disclosure, please refer to the description of the foregoing embodiments for understanding.

[0112] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0113] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0114] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0115] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0116] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0117] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0118] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide wafers; The virtual bonding mapping pattern and the chip bonding mapping pattern of the wafer are determined; wherein the virtual bonding mapping pattern and the chip bonding mapping pattern are complementary to the wafer, and the virtual bonding mapping pattern corresponds to the edge region of the wafer; The wafer is exposed and photolithographically ... Multiple chips are bonded within the chip bonding region to form a semiconductor structure; wherein each of the multiple chips is a complete chip.

2. The forming method according to claim 1, characterized in that, The determination of the virtual bonding mapping pattern of the wafer and the chip bonding mapping pattern specifically includes: Based on the size of the chip, determine the corresponding exposure field size of the chip; The effective bonding region on the wafer is calculated based on the exposure field size, and an initial mapping pattern is obtained based on the effective bonding region. Based on the effective bonding region, a virtual exposure field is determined, and the virtual bonding mapping pattern is obtained based on the virtual exposure field; Based on the virtual exposure field and the initial mapping pattern, the target exposure field that the lithography machine needs to execute is calculated, and the chip bonding mapping pattern is obtained based on the target exposure field.

3. The forming method according to claim 2, characterized in that, The step of calculating the effective bonding region on the wafer based on the exposure field size specifically includes: According to the exposure field size, the chip exposure field corresponding to the chip is arranged in an array on the wafer according to a preset arrangement rule, excluding the part involving the edge of the wafer, to obtain the effective bonding area.

4. The forming method according to claim 3, characterized in that, The preset arrangement rules include at least a rectangular array arrangement or a hexagonal array arrangement, and the chip retains preset cutting channels around its perimeter; The chip bonding area also includes a gap; the gap is adjacent to the edge layer; metal interconnects are arranged in the gap, and the metal interconnects are electrically connected to the chip bonded in the chip bonding area.

5. The forming method according to claim 2, characterized in that, The step of calculating the target exposure field that the lithography machine needs to perform based on the virtual exposure field and the initial mapping pattern, and obtaining the chip bonding mapping pattern based on the target exposure field, specifically includes: By filtering out the exposure fields in the initial mapping pattern where the pre-bonded chip intersects with the edge of the wafer and the boundary of the virtual exposure field, candidate target exposure fields are obtained. The intersection area of ​​the candidate target exposure field with the outline of the wafer and the boundary of the virtual exposure field is detected, and the candidate target exposure field is skipped according to preset conditions; The candidate target exposure fields that have not been skipped are identified as the target exposure fields, and the initial mapping pattern is updated based on the target exposure fields to obtain the chip bonding mapping pattern.

6. The forming method according to claim 1, characterized in that, The step of performing photolithography on the wafer based on the chip bonding mapping pattern to form the chip bonding region specifically includes: A protective layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer are sequentially deposited on the wafer along a first direction, wherein the first direction is perpendicular to the wafer surface; A photoresist layer is formed on the surface of the third sacrificial layer along the first direction; Using the chip bonding mapping pattern as a mask, the photoresist layer is exposed and developed to form a patterned photoresist layer; Using the patterned photoresist layer as a mask, the third sacrificial layer is etched until the surface of the second sacrificial layer is exposed; Using the etched third sacrificial layer as a mask, the second sacrificial layer is etched until the surface of the first sacrificial layer is exposed; Using the etched second sacrificial layer as a mask, the first sacrificial layer is etched until the surface of the protective layer is exposed; Using the etched first sacrificial layer as a mask, the protective layer is etched until the bonding surface of the wafer surface is exposed, forming the chip bonding region.

7. The forming method according to claim 4, characterized in that, The bonding of multiple chips within the chip bonding region to form a semiconductor structure specifically includes: The surface of the wafer is subjected to surface activation treatment; The pre-bonded chip is aligned and bonded to the chip bonding area; After the chip and the wafer are bonded, the dicing channel between the chip and the wafer is filled with a dielectric material to form the semiconductor structure.

8. A semiconductor structure, characterized in that, Includes wafers, edge layers, and multiple chips; The wafer includes a chip bonding region, and the edge layer is disposed in the edge region of the wafer. The chip bonding region and the edge layer are complementary in configuration to the wafer. Each chip bonded in the chip bonding region is a complete chip.

9. The semiconductor structure according to claim 8, characterized in that, The edge layer is also disposed along the first direction at the edge of the chip bonding area.

10. A memory, characterized in that, The memory includes a semiconductor structure manufactured by the method for forming a semiconductor structure according to any one of claims 1 to 7, or a semiconductor structure according to any one of claims 8 to 9.

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