Silicon-based capacitor stack structure and method of making the same

Abstract

The application provides a silicon-based capacitor stack structure and a preparation method thereof. The silicon-based capacitor stack structure integrates a deep trench capacitor structure and a silicon interposer, and the two are interconnected through a coplanar hybrid bonding interface. First, a deep trench capacitor is formed on a first silicon substrate, an interconnection metal layer and a first conductive column are constructed, a planarized first bonding layer is prepared on the back surface, and finally the first bonding layer is bonded with a silicon interposer having a coplanar second bonding surface. Through the hybrid bonding process, the interconnection distance is reduced to the micron level, the interconnection density per unit area is increased by more than 10 times, and the capacitor layer does not occupy the wiring resources; the micro-bump is eliminated to reduce the vertical interconnection height and optimize the high-frequency signal integrity; in addition, the structure adopts a full-silicon structure to realize thermal expansion matching and improve the interface reliability; the preparation process is compatible with 300mm wafer manufacturing, and the steps of bumping and underfilling are omitted, so that the packaging cost can be reduced by 10-15%.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology and relates to a silicon-based capacitor stacking structure and its preparation method. Background Technology

[0002] Driven by artificial intelligence training and data center computing, the bandwidth demand between processors and memory is growing exponentially, while the instantaneous current demand faced by chip power supply networks is approaching physical limits. Current 3D integration technology faces four core challenges: the density and electrical performance of traditional micro-bump interconnects have reached their bottlenecks, unable to support next-generation TB / s-level data exchange; system noise margins approach critical values ​​when the supply voltage drops below 0.8V, and parasitic parameters of existing packaging architectures severely restrict power integrity; thermomechanical stress caused by direct stacking of heterogeneous materials leads to interface delamination risks, becoming a major constraint on yield and reliability; and there is a lack of effective architectures for co-integrating special process devices such as deep trench capacitors with logic chips in a low-loss, high-density manner.

[0003] In recent years, advanced packaging has solved the interconnect density bottleneck through silicon interposers (Si-Interposers). However, as chips enter the GHz era, power supply noise has become a new performance constraint. Traditional discrete capacitors have reached their limits in high-frequency decoupling capabilities due to excessive parasitic inductance. While silicon capacitors (Si-Cap / NDC) provide an ultra-low inductance solution at the device level, their effectiveness can only be fully realized when achieving the ultimate interconnection with the load at the "shortest distance and lowest impedance". Therefore, deep integration of Si-Cap and Si-Interposers is an inevitable technical direction for solving the system-level bottleneck of power integrity, with the goal of building an "ideal chip base" that combines ultra-high bandwidth and ultimate power quality.

[0004] However, existing technologies have failed to achieve this ideal integration. The three main approaches all have fundamental flaws: 1) Mounting via micro-bump process results in low interconnect density and long paths, which degrades the high-frequency performance of Si-Cap; 2) Embedding capacitor structures within Si-Interposer, but integration is limited by interconnect process, making it impossible to achieve independent optimization of capacitor performance; 3) Direct stacking results in a tradeoff between yield and performance due to unreconcilable thermal stress between heterogeneous materials, conflicting process thermal budgets, and interface reliability issues.

[0005] Therefore, it is particularly important to achieve high-performance and high-reliability integration at the wafer level and effectively solve the problems of power integrity, heat dissipation bottlenecks and mechanical stress concentration caused by high-density integration.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a silicon-based capacitor stack structure and its fabrication method, which can achieve high-performance and high-reliability heterogeneous integration at the wafer level, and effectively solve the problems of power integrity, heat dissipation bottleneck and mechanical stress concentration caused by high-density integration.

[0008] To achieve the above and other related objectives, the present invention provides a method for fabricating a silicon-based capacitor stack structure, comprising the following steps:

[0009] S1, a first silicon substrate is provided, and a deep trench capacitor structure is formed in the first silicon substrate; the first silicon substrate has a front side and a back side disposed opposite to each other; the deep trench capacitor structure includes a polycrystalline silicon electrode and a capacitor dielectric layer located between the polycrystalline silicon electrode and the first silicon substrate.

[0010] S2, An interconnect structure electrically connected to the deep trench capacitor structure is formed on the front side of the first silicon substrate. The interconnect structure includes blind via pillars and an interconnect metal layer. The back side of the first silicon substrate is thinned to form a through first conductive pillar. The first conductive pillars are staggered with the deep trench capacitor structure in a planar layout. The interconnect metal layer is electrically connected to the deep trench capacitor structure.

[0011] S3, a first bonding layer is formed on the back side of the first silicon substrate. The first bonding layer includes a coplanar first conductive block and a double dielectric layer surrounding the first conductive block. The first conductive block is electrically connected to the interconnect metal layer through the first conductive post.

[0012] S4, a silicon interposer is provided, the silicon interposer comprising a second silicon substrate, a second conductive pillar penetrating the second silicon substrate, and a second bonding layer located on the front side of the second silicon substrate; the second bonding layer is electrically connected to the second conductive pillar; wherein, the second bonding layer has a second bonding surface composed of a second dielectric layer and a second conductive block embedded in the second dielectric layer, and the top surface of the second conductive block is flush with the top surface of the second dielectric layer;

[0013] S5, the first bonding layer on the back side of the first silicon substrate is mixed and bonded with the second bonding surface on the front side of the silicon interposer.

[0014] Optionally, the step of forming the first bonding layer in step S3 includes:

[0015] S3-1, A temporary substrate is provided, and the front side of the first silicon substrate is bonded to the temporary substrate through a temporary bonding layer;

[0016] S3-2, Planarize the back side of the first silicon substrate to expose the first conductive pillar;

[0017] S3-3, a double dielectric layer is formed on the back side of the first silicon substrate; the double dielectric layer includes a SiCN layer at the bottom and a first silicon oxide layer above the SiCN layer;

[0018] S3-4, A first conductive block is formed in the double-layer dielectric layer using a damascus process, and the first conductive block is electrically connected to the first conductive post.

[0019] S3-5, Planarize the first silicon oxide layer and the first conductive block so that their top surfaces are flush, forming the first bonding layer;

[0020] S3-6, Remove the temporary substrate.

[0021] Optionally, the SiCN layer is formed using a PECVD process at a temperature range of 300~500℃.

[0022] Optionally, the interconnect structure is formed using a double damask process in step S2, including:

[0023] S2-1, deposit an interlayer dielectric layer on the front side of the first silicon substrate, and sequentially etch to form a first blind hole electrically connected to the deep trench capacitor structure, and a first trench located above the first blind hole;

[0024] S2-2, after filling the first blind hole and the first trench through a single electroplating process, the thickness is reduced to form the interconnect metal layer and the first conductive pillar.

[0025] Optionally, the temperature range of the hybrid bonding process is 300~400℃.

[0026] Optionally, the capacitor dielectric layer includes one of hafnium oxide and zirconium oxide.

[0027] Optionally, the SiCN double dielectric layer is formed using a PECVD process at a temperature range of 300~500℃.

[0028] Optionally, the deep trench capacitor structure formed in the first silicon substrate includes multiple functional regions with different capacitance densities; and the interconnect metal layer is configured as multiple conductive structures corresponding to the functional regions and electrically isolated from each other.

[0029] This application also proposes a silicon-based capacitor stack structure, including:

[0030] A silicon capacitor structure includes a first silicon substrate having a front side and a back side disposed opposite to each other; the silicon capacitor structure includes a deep trench capacitor structure; the deep trench capacitor structure includes a polycrystalline silicon electrode and a capacitor dielectric layer located between the polycrystalline silicon electrode and the first silicon substrate.

[0031] An interconnect structure is provided, comprising an interconnect metal layer and a first conductive pillar. The interconnect metal layer is located on the front side of the first silicon substrate and is electrically connected to the polysilicon electrode. The first conductive pillar penetrates the first silicon substrate, and a first barrier layer is provided between the sidewall of the first conductive pillar and the first silicon substrate. The first conductive pillar is staggered with the deep trench capacitor structure in a planar layout, and the front end of the first conductive pillar is electrically connected to the interconnect metal layer.

[0032] The first bonding layer is located on the back side of the first silicon substrate and includes a coplanar first conductive block and a double dielectric layer surrounding the first conductive block; the first conductive block is electrically connected to the back end of the first conductive post.

[0033] A silicon interposer, the silicon interposer comprising a second silicon substrate, a second conductive pillar penetrating the second silicon substrate, and a second bonding layer located on the front side of the second silicon substrate; the second bonding layer is electrically connected to the second conductive pillar.

[0034] The second bonding layer has a second bonding surface consisting of a second dielectric layer and a second conductive block embedded in the second dielectric layer, wherein the top surface of the second conductive block is flush with the top surface of the second dielectric layer.

[0035] Optionally, the dual dielectric layer includes a SiCN layer at the bottom and a silicon oxide layer above the SiCN layer.

[0036] Optionally, the deep trench capacitor structure within the first silicon substrate includes multiple functional regions with different capacitance densities; and the interconnect metal layer is configured as multiple conductive bilayer dielectric layers corresponding to the functional regions and electrically isolated from each other.

[0037] As described above, this invention proposes a silicon-based capacitor stack structure and its fabrication method. The structure includes a silicon capacitor structure integrating deep trench capacitors and a silicon interposer, which are directly connected through a coplanar hybrid bonding interface. First, a deep trench capacitor is formed on a first silicon substrate, and after constructing a front interconnect metal layer and a first conductive pillar, a planarized back bonding layer is prepared, which is then hybrid-bonded with a silicon interposer having a coplanar second bonding surface. This technology, through a hybrid bonding process, enables interconnect spacing to break through to the micrometer level, increasing the interconnect density per unit area by more than 10 times, and the capacitor layer does not occupy wiring resources; at the same time, it eliminates microbumps, reduces the vertical interconnect height, and improves the high-frequency performance of the structure; in addition, this structure uses an all-silicon structure to achieve thermal expansion matching, enhancing interface reliability. Furthermore, the capacitor layer also serves as an auxiliary heat dissipation path to reduce lateral thermal resistance; this fabrication process is compatible with 300mm wafer manufacturing, eliminating the steps of bumping and bottom filling, and reducing packaging costs by 10-15%. Attached Figure Description

[0038] Figure 1 The diagram shows a schematic flow chart of the fabrication process of the silicon-based capacitor stack structure in an embodiment of the present invention.

[0039] Figure 2 The diagram shown is a schematic representation of the structure of a first silicon substrate after forming a deep trench and a capacitor dielectric layer in an embodiment of the present invention.

[0040] Figure 3 The diagram shown is a schematic representation of the structure after forming a deep trench capacitor in an embodiment of the present invention.

[0041] Figure 4 The diagram shown is a schematic representation of the structure after the formation of the interlayer dielectric layer in an embodiment of the present invention.

[0042] Figure 5 The diagram shows the structure after the first trench and the first blind hole are formed in an embodiment of the present invention.

[0043] Figure 6 The diagram shown is a schematic representation of the structure after the interconnect metal layer and the first conductive pillar are formed in an embodiment of the present invention.

[0044] Figure 7 The diagram shows a schematic of the structure after the silicon capacitor structure is bonded to a temporary substrate in an embodiment of the present invention.

[0045] Figure 8 The diagram shown is a schematic representation of the structure after the formation of the first bonding layer in an embodiment of the present invention.

[0046] Figure 9 The diagram shown is a schematic representation of the structure after the temporary substrate has been removed in an embodiment of the present invention.

[0047] Figure 10The diagram shows the structure after the formation of the second blind via and the second barrier layer in the silicon interposer in an embodiment of the present invention.

[0048] Figure 11 The diagram shows the structure after the formation of the second conductive pillar and the second bonding layer in an embodiment of the present invention.

[0049] Figure 12 The diagram shows the structure after the silicon capacitor structure and the silicon interposer are bonded together in an embodiment of the present invention.

[0050] Figure 13 The diagram shown is a schematic representation of the structure after the bumps are formed in an embodiment of the present invention.

[0051] Explanation of reference numerals in the attached figures

[0052] 100 First silicon substrate 101 Silicon capacitor structure 110 capacitor dielectric layer 111 Interlayer dielectric layer 130 polycrystalline silicon electrode 140 Interconnect metal layer 141 First trench 142 First blind hole 150 First conductive post 151 First barrier layer 160 First bonding layer 161 Double dielectric layer 162 First conductive block 163 First silicon oxide layer 164 SiCN layer 170 temporary substrate 171 Temporary bonding layer 200 Second silicon substrate 201 Silicon interposer 210 Second bonding layer 211 Second dielectric layer 212 Second conductive block 220 Second conductive post 230 Second barrier layer 242 Second blind hole 310 First bonding bump 320 Second bonding bump Detailed Implementation

[0053] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0055] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0056] It should be noted that the illustrations provided in this embodiment are only intended to illustrate the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0057] Example 1

[0058] like Figures 1-13 This embodiment provides a method for fabricating a silicon-based capacitor stack structure. A deep trench capacitor is formed on a first silicon substrate, and front-side interconnects and through-silicon vias are simultaneously constructed to form through-conductive pillars. A planarized back-side bonding layer is then fabricated, and finally, it is mixed-bonded with a silicon interposer having a coplanar second bonding surface. The following is in conjunction with the appendix... Figures 1-13 Further details are provided regarding the fabrication of silicon-based capacitor stack structures.

[0059] First, refer to Figures 1-3 Step S1 is executed, a first silicon substrate 100 is provided, and a deep trench capacitor structure is formed in the first silicon substrate 100; the first silicon substrate 100 has a front side and a back side disposed opposite to each other; the deep trench capacitor structure includes a polysilicon electrode 130 and a capacitor dielectric layer 110 located between the polysilicon electrode 130 and the first silicon substrate 100.

[0060] Specifically, in this embodiment, a first silicon substrate 100 with a front and a back side disposed opposite to each other is provided. Deep trenches are formed in the first silicon substrate 100 by a deep silicon etching process. Subsequently, a capacitor dielectric layer 110 and a polysilicon electrode 130 are formed sequentially on the inner wall of the deep trenches. The capacitor dielectric layer 110 covers the sidewalls and bottom of the deep trenches, and the polysilicon electrode 130 fills the remaining space of the deep trenches, thereby forming a three-dimensional integrated deep trench capacitor structure inside the first silicon substrate 100.

[0061] Furthermore, the capacitor dielectric layer 110 employs a high-quality, high-k dielectric material compatible with silicon processes. As an example, the capacitor dielectric layer includes one of hafnium oxide and zirconium oxide. The large surface area provided by the deep trench three-dimensional structure significantly increases capacitance density per unit area. By optimizing the aspect ratio and array arrangement, the deep trench capacitor structure forms a distributed decoupling network within the chip, effectively suppressing power supply noise and improving signal integrity. This structure integrates passive devices within the first silicon substrate 100, avoiding the surface wiring space occupied by traditional discrete capacitors and freeing up critical layout resources for subsequent three-dimensional stacked interconnects.

[0062] Next, refer to Figure 1 , Figures 4-6In step S2, an interconnect structure electrically connected to the deep trench capacitor structure is formed on the front side of the first silicon substrate 100. The interconnect structure includes blind via pillars and an interconnect metal layer 140. The back side of the first silicon substrate 100 is thinned to form a through first conductive pillar 150. The first conductive pillars 150 are staggered with the deep trench capacitor structure in a planar layout, and a first barrier layer 151 is provided between the sidewall of the first conductive pillar 150 and the first silicon substrate 100. The interconnect metal layer 140 is electrically connected to the deep trench capacitor structure.

[0063] Specifically, on the front side of the first silicon substrate 100, an interlayer dielectric layer 111 is deposited. Through photolithography and etching, patterns for first trenches 141 and first blind vias 142 are simultaneously formed in the dielectric layer to construct interconnect structures. The first blind vias 142, used to form first conductive pillars 150, are staggered with the deep trench capacitor array in a planar layout. This staggered distribution allows the first conductive pillars to serve as both vertical power supply paths and heat dissipation channels for the deep trench capacitor structure. Subsequently, copper metal is electroplated into the first trenches 141 and the first blind vias 142 in a single pass. After chemical mechanical polishing, interconnect metal layers 140 embedded in the interlayer dielectric layer 111 and blind via pillars serving as prototypes of through-silicon vias (TSVs) are simultaneously formed. A first barrier layer 151 is formed between the sidewalls of the blind via pillars and the silicon substrate through thermal oxidation or deposition. Preferably, the first barrier layer 151 is made of TaN / Ta. Next, the back side of the first silicon substrate 100 is thinned by mechanical grinding or chemical mechanical polishing until the bottom of the blind via pillar is exposed, thereby forming the first conductive pillar 150 penetrating the first silicon substrate 100. The interconnect metal layer 140 and the polysilicon electrode 130 are connected with low resistance to complete the integration of the capacitance signal and power path.

[0064] See Figures 4-6 The diagram illustrates a detailed process for forming an interconnect structure according to an embodiment of the present invention, specifically corresponding to the steps defined above, including: S2-1, depositing an interlayer dielectric layer 111 on the front side of the first silicon substrate 100, and sequentially etching to form a first blind via 142 electrically connected to the deep trench capacitor structure, and a first trench 141 located above the first blind via 142; S2-2, filling the first blind via 142 and the first trench 141 through a single electroplating process, and then thinning to form an interconnect metal layer 140 and a first conductive pillar 150.

[0065] This embodiment utilizes a dual damascene process to simultaneously form the interconnect metal layer 140 and the first conductive pillar 150 in a single operation, achieving a high-density, low-parasitic-capacitance structure and providing a structural foundation for vertical interconnects. The staggered layout of the first conductive pillar 150 and the deep trench capacitor structure maximizes the use of chip area. Simultaneously, the process employs a sequence of first forming the front blind via pillars and then thinning and connecting them to the back side, ensuring precise alignment and high-quality connection between the TSV and the front interconnect. The first barrier layer 151 formed on its sidewalls ensures reliable electrical isolation between the first conductive pillar 150 and the first silicon substrate 100. The interconnect metal layer 140 is directly connected to the polysilicon electrode 130 of the deep trench capacitor via the first conductive pillar 150, forming a low-loss electrical path from the capacitor structure to the first conductive pillar 150 and then to the subsequent back first bonding layer 160, which is beneficial for improving power integrity and high-frequency signal transmission.

[0066] In some other specific embodiments, the interconnect metal layer 140 and the first conductive pillar 150 can be formed in steps. First, through-holes are formed in the first silicon substrate 100 by photolithography and etching on the surface of the first silicon substrate 100. Then, a first barrier layer 151 and a seed layer are deposited, the through-holes are filled by electroplating, and the substrate is planarized to form the first conductive pillar 150. Next, an interlayer dielectric layer 111 is deposited on the planarized surface, and a second photolithography and etching are performed to etch a first trench 141 in the interlayer dielectric layer 111, exposing the top surface of the first conductive pillar 150. Then, a barrier layer and a seed layer are deposited, the trench is filled by electroplating, and the substrate is planarized to form the interconnect metal layer 140. The interconnect metal layer 140 electrically connects the first conductive pillar 150 and the polysilicon electrode 130. The above-mentioned step-by-step formation process is mature in production and has a higher yield. The interconnect structure formed in one step using the double martensitic process mentioned above has higher production efficiency. The specific choice depends on the actual situation and is not limited here.

[0067] In this embodiment, the first conductive post 150 and the deep trench capacitor structure are arranged in a planar staggered distribution, so that the first conductive post 150 is embedded in the first silicon substrate 100. This design can effectively alleviate the thermomechanical stress caused by the mismatch of the thermal expansion coefficients of the materials in the first conductive post 150 and the deep trench capacitor structure, and avoid the shear stress that would cause cracking or delamination in the capacitor dielectric layer 110 during subsequent bonding annealing, thereby significantly improving the reliability and manufacturing yield of the silicon-based capacitor stack structure. At the same time, the first conductive post 150 serves as both a vertical power supply path and a heat dissipation channel for the deep trench capacitor structure.

[0068] As an example, the deep trench capacitor structure formed in the first silicon substrate 100 includes multiple functional regions with different capacitance densities; and the interconnect metal layer 140 is configured as multiple conductive structures corresponding to the functional regions and electrically isolated from each other.

[0069] Specifically, the deep trench capacitor structure formed within the first silicon substrate 100 is not uniformly distributed, but rather designed to include multiple functional regions with different capacitance densities. For example, a high-density capacitor region with a first capacitance density is provided for the integrated processor core region; and a medium-density capacitor region with a second capacitance density is provided for the high-speed memory interface region. Correspondingly, the interconnect metal layer 140 formed on the front side of the first silicon substrate 100 is also configured as multiple electrically isolated conductive structures. These conductive structures correspond to the aforementioned functional regions in vertical projection and are electrically connected to them, thereby constructing independent and dedicated power supply and decoupling paths for different load blocks. This collaborative design of "partitioned capacitors - independent interconnects" allows decoupling capacitors to be placed closest to the target circuit, achieving distributed optimization of the power supply network.

[0070] Next, refer to Figure 1 and Figures 7-9 In step S3, a first bonding layer 160 is formed on the back side of the first silicon substrate 100. The first bonding layer 160 includes a coplanar first conductive block 162 and a double-layer dielectric layer 161 surrounding the first conductive block 162. The first conductive block 162 is electrically connected to the interconnect metal layer 140 through a first conductive post 150.

[0071] Specifically, the first bonding layer 160 is fabricated on the back side of the integrated first conductive pillar 150 and silicon capacitor structure 101, creating an atomically flat interface that can be directly used for hybrid bonding. The key is to form first conductive blocks 162 aligned with the first conductive pillars 150 on the exposed array of first conductive pillars 150, ensuring the entire surface achieves nanometer-level flatness to meet the stringent requirements of subsequent chip-level hybrid bonding.

[0072] As a specific embodiment, the steps of forming the first bonding layer 160 include:

[0073] First, step S3-1 is performed to provide a temporary substrate 170, and the front side of the first silicon substrate 100 is bonded to the temporary substrate 170 through a temporary bonding layer 171.

[0074] The temporary substrate 170 includes a glass or silicon carrier. This step provides the necessary mechanical support for subsequent back-side processing and prevents the thinner silicon capacitor structure 101 from cracking or warping during processing.

[0075] Next, step S3-2 is performed to planarize the back side of the first silicon substrate 100 and expose the first conductive pillar 150.

[0076] Specifically, the back side of the first silicon substrate 100 is mechanically ground and chemically mechanically polished to achieve global thinning and planarization. This process requires precise control of the endpoint until the end face of the first conductive pillar 150 is fully exposed and a completely flat surface is formed.

[0077] Next, step S3-3 is performed to form a double dielectric layer 161 on the back side of the first silicon substrate 100; the double dielectric layer includes a SiCN layer 164 at the bottom and a first silicon oxide layer 163 above the SiCN layer.

[0078] Specifically, electrical isolation between the subsequent first conductive blocks 162 is achieved by forming a double dielectric layer 161, which also serves as a carrier for subsequent siding processes. Surface treatment is required after deposition to ensure good adhesion and flatness. The SiCN layer 164 acts as a copper diffusion barrier layer; the SiCN layer has extremely high bulk resistivity and breakdown field strength, providing reliable electrical isolation for the high-density integrated first conductive blocks 162, ensuring signal integrity and suppressing leakage. The first silicon oxide layer 163 is crucial for achieving atomic-level coplanarity and flatness of the bonding surface. The material selection of the double dielectric layer 161 is primarily based on its excellent thermal stability and near-perfect matching of its thermal expansion coefficient with the silicon substrate. In subsequent hybrid bonding and annealing processes, it effectively suppresses copper atom diffusion and alleviates interfacial stress caused by the difference in thermal expansion coefficients between the first silicon substrate 100 and the bonding layer, thereby improving the long-term reliability and electrical stability of the bonding interface.

[0079] As an example, the SiCN layer is formed using a PECVD process at a temperature range of 300~500℃.

[0080] Specifically, plasma-enhanced chemical vapor deposition (PECVD) is performed within a relatively low-temperature window, specifically between 300 and 500°C, such as any value within this range (e.g., 300°C, 350°C, 400°C, 450°C, 500°C). This temperature range is significantly lower than that of traditional thermal oxidation processes, effectively preventing thermal damage to the formed interconnect structures. Furthermore, this temperature is sufficient to drive a full reaction of the precursor gases, resulting in a high-quality silicon oxide film with low hydrogen content, high density, and excellent step coverage. By precisely controlling the reactant gas ratio, RF power, and chamber pressure, a uniformly thick insulating dielectric layer with low defect density and controllable stress state can be obtained on the wafer surface, providing a structural basis for subsequent planarization processes and hybrid bonding interfaces.

[0081] Next, step S3-4 is performed to form a first conductive block 162 in the double dielectric layer 161 using a damascus process. The first conductive block 162 is electrically connected to the first conductive post 150.

[0082] Specifically, the pattern of the first conductive block 162 is defined by photolithography; a groove is formed in the double dielectric layer 161 by dry etching; the bottom of the groove will expose the end face of the first conductive pillar 150 below; then a diffusion barrier layer (such as Ta / TaN) and a copper seed layer are deposited, and copper is filled by electroplating to form a bump structure directly connected to the TSV.

[0083] S3-5, planarize the double-layer dielectric layer 161 and the first conductive block 162 to form the first bonding layer 160.

[0084] Specifically, excess copper and barrier layers are removed from the surface through chemical mechanical polishing or other grinding processes until the top surface of the first conductive block 162 and the top surface of the double dielectric layer 161 are atomically coplanar. This step is crucial for forming a high-quality hybrid bonding interface, and its flatness directly determines the bonding success rate and interconnect resistance.

[0085] S3-6, Remove the temporary substrate 170 to obtain a silicon capacitor structure 101 with a complete and coplanar first bonding layer 160 on the back side, which facilitates subsequent alignment and hybrid bonding operations.

[0086] Next, refer to Figure 1 , Figures 10-11 Step S4 is executed to provide a silicon interposer 201. The silicon interposer 201 includes a second silicon substrate 200, a second conductive post 220 penetrating the second silicon substrate 200, and a second bonding layer 210 located on the front side of the second silicon substrate 200. The second bonding layer 210 is electrically connected to the second conductive post 220. The second bonding layer 210 has a second bonding surface composed of a second dielectric layer 211 and a second conductive block 212 embedded in the second dielectric layer 211, and the top surface of the second conductive block 212 is flush with the top surface of the second dielectric layer 211.

[0087] Specifically, the flush design of the second bonding surface ensures uniform contact and reliable connection when bonding with the corresponding silicon capacitor structure 101. The second conductive blocks 212 are arrayed on the top layer of the second bonding layer 210, and their size and spacing are optimized according to signal transmission and power distribution requirements. This structure not only improves the density and performance of vertical interconnects, but also enables efficient integration of multi-chip systems through the redistribution function of the silicon interposer 201.

[0088] In this embodiment, a second blind via is formed in the second silicon substrate within the silicon interposer and electroplated to fill it, forming a second blind via pillar. A second bonding layer is then formed on the surface of the second silicon substrate. This second bonding layer is formed using a damascus process, i.e., a second dielectric layer is formed on the surface of the second silicon substrate, and a second trench is formed to expose the second blind via pillar. Preferably, the second dielectric layer is silicon oxide. A second conductive block 212 is formed using an electroplating process, and then the back side of the second silicon substrate is thinned to form a second conductive pillar. A second barrier layer 230 is also disposed between the second conductive pillar 220 and the second silicon substrate 200. Preferably, the second barrier layer is TaN / Ta. Of course, other preparation methods can also be used, and this is not a limitation.

[0089] Next, refer to Figure 1 and Figure 12 Step S5 is executed to mix and bond the first bonding layer 160 on the back side of the first silicon substrate 100 with the second bonding surface on the front side of the silicon interposer 201.

[0090] The first bonding layer 160 and the second bonding surface are aligned and brought into direct contact under a preset bonding temperature and pressure, resulting in a metallic bond between the first conductive block 162 and the second conductive block 212. Simultaneously, a covalent bond is formed between the first silicon oxide layer 163 and the second dielectric layer 211 in the bilayer dielectric layer, thereby completing the electrical interconnection and mechanical integration between the silicon capacitor structure 101 and the silicon interposer 201. By employing hybrid bonding, the size and parasitic parameter limitations of microbumps are directly circumvented, enabling the achievement of ultra-high density.

[0091] As an example, the temperature range of the hybrid bonding process is 300~400℃, such as any value within this range like 320℃, 340℃, 350℃, 360℃, 380℃, and 400℃. This temperature range is set based on a comprehensive optimization of material properties, process compatibility, and bonding quality. First, 300~400℃ is sufficient to drive significant solid-state diffusion of copper atoms at the bonding interface, thereby achieving metallurgical bonding and low-resistance ohmic contact between copper bumps. Simultaneously, this temperature effectively activates dangling bonds on the dielectric layer surface, promoting covalent bond formation to enhance interface strength. Second, this temperature range avoids thermal damage to the capacitor dielectric layer 110 and interconnect metal layer 140 in the deep trench capacitor structure, ensuring that the electrical performance and reliability of the preceding processes are not degraded by the bonding process. Furthermore, the hybrid bonding of the silicon capacitor structure 101 and the silicon interposer 201 forms the shortest vertical interconnect path, significantly reducing parasitic inductance and resistance. Ultimately, hybrid bonding performed at this optimized temperature enables ultra-high alignment accuracy (submicron level) interconnection while achieving high bonding strength, low interface void ratio, and excellent electrothermal reliability. This fundamentally avoids the thermal stress disaster of high-temperature heterogeneous stacking, thereby fully leveraging the comprehensive advantages of three-dimensional stacked structures in terms of density, performance, and power consumption.

[0092] In other embodiments, see Figure 13 After forming the above-mentioned silicon-based capacitor stack structure, a first metal bump 310 is formed on the back side of the silicon interposer 201 for electrical connection with an external packaging substrate or circuit board, and a second metal bump 320 is formed on the front side of the silicon capacitor structure 101 for integration with another functional chip. These details will not be elaborated here.

[0093] The silicon-based capacitor stack structure and its fabrication method provided by this invention achieve ultra-high-density electrical interconnection between heterogeneous chips by employing a silicon interposer 201 with through-silicon vias and a high-density second bonding layer, and hybrid bonding it with a silicon capacitor structure 101 integrated with deep trench capacitors. This significantly improves the integration density and signal transmission bandwidth of system-in-package (SiP), while also effectively shortening the interconnection path and reducing parasitic effects and power consumption. This structure fully leverages the high-precision interconnection advantages of the silicon interposer 201 and the high capacitance density characteristics of the deep trench capacitors, providing an innovative three-dimensional integration solution for advanced microelectronic systems requiring high bandwidth, low latency, and high reliability, such as high-performance computing and artificial intelligence accelerators.

[0094] Example 2

[0095] This embodiment provides a silicon-based capacitor stack structure. The silicon-based capacitor stack structure is obtained by further extending the fabrication method of Embodiment 1 or by other suitable similar methods. Please refer to [link to previous document]. Figure 12 or Figure 13The image shows a cross-sectional schematic diagram of a silicon-based capacitor stack structure, which includes:

[0096] The silicon capacitor structure 101 includes a first silicon substrate 100, which has a front side and a back side disposed opposite to each other; the silicon capacitor structure 101 includes a deep trench capacitor structure; the deep trench capacitor structure includes a polysilicon electrode 130 and a capacitor dielectric layer 110 located between the polysilicon electrode 130 and the first silicon substrate 100.

[0097] The interconnect structure includes an interconnect metal layer 140 and a first conductive pillar 150. The interconnect metal layer 140 is located on the front side of the first silicon substrate 100 and is electrically connected to the polysilicon electrode 130. The first conductive pillar 150 penetrates the first silicon substrate 100, and a first barrier layer 151 is provided between the sidewall of the first conductive pillar 150 and the first silicon substrate 100. The first conductive pillar 150 is staggered with the deep trench capacitor structure in a planar layout, and the front end of the first conductive pillar 150 is electrically connected to the interconnect metal layer 140.

[0098] The first bonding layer 160 is located on the back side of the first silicon substrate 100 and includes a coplanar first conductive block 162 and a double dielectric layer 161 surrounding the first conductive block 162; the first conductive block 162 is electrically connected to the back end of the first conductive post 150.

[0099] The silicon interposer 201 includes a second silicon substrate 200, a second conductive pillar 220 penetrating the second silicon substrate 200, and a second bonding layer 210 located on the front side of the second silicon substrate 200; the second bonding layer 210 is electrically connected to the second conductive pillar 220.

[0100] The second bonding layer 210 has a second bonding surface formed by the second dielectric layer 211 and the second conductive block 212 embedded in the second dielectric layer 211, and the top surface of the second conductive block 212 is flush with the top surface of the dielectric layer.

[0101] As an example, the dual dielectric layer includes a SiCN layer 164 at the bottom and a first silicon oxide layer 163 above the SiCN layer 164.

[0102] Specifically, a double dielectric layer 161 is formed to achieve electrical isolation between the subsequent first conductive blocks 162 and serves as a carrier for subsequent siding processes. Surface treatment is required after deposition to ensure good adhesion and flatness. The SiCN layer 164 serves as a copper diffusion barrier layer; simultaneously, the SiCN layer 164 has extremely high bulk resistivity and breakdown field strength, providing reliable electrical isolation for the high-density integrated first conductive blocks 162, ensuring signal integrity and suppressing leakage. The first silicon oxide layer 163 serves as the bonding dielectric layer for hybrid bonding and is crucial for achieving atomic-level coplanarity and flatness of the bonding surface. The material selection of the double dielectric layer 161 is primarily based on its excellent thermal stability and near-perfect thermal expansion coefficient matching with the silicon substrate. This effectively avoids interface delamination or cracking caused by stress mismatch during subsequent hybrid bonding. Furthermore, during subsequent hybrid bonding and annealing processes, it effectively suppresses copper atom diffusion and alleviates interface stress caused by the difference in thermal expansion coefficients between the first silicon substrate 100 and the bonding layer, thereby improving the long-term reliability and electrical stability of the bonding interface.

[0103] As an example, the deep trench capacitor structure formed in the first silicon substrate 100 includes multiple functional regions with different capacitance densities; and the interconnect metal layer 140 is configured as multiple conductive structures corresponding to the functional regions and electrically isolated from each other.

[0104] Specifically, the deep trench capacitor structure formed within the first silicon substrate 100 is not uniformly distributed, but rather designed to include multiple functional regions with different capacitance densities. For example, a high-density capacitor region with a first capacitance density is provided for the integrated processor core region; and a medium-density capacitor region with a second capacitance density is provided for the high-speed memory interface region. Correspondingly, the interconnect metal layer 140 formed on the front side of the first silicon substrate 100 is also configured as multiple electrically isolated conductive structures. These conductive structures correspond to the aforementioned functional regions in vertical projection and are electrically connected to them, thereby constructing independent and dedicated power supply and decoupling paths for different load blocks. This collaborative design of "partitioned capacitors - independent interconnects" allows decoupling capacitors to be placed closest to the target circuit, achieving distributed optimization of the power supply network.

[0105] The specific structure and related materials in this example are similar to those in Example 1, and will not be described in detail here.

[0106] In summary, this patent provides a silicon-based capacitor stack structure and its fabrication method, aiming to achieve high-density, high-performance three-dimensional system integration. The structure includes an integrated deep trench capacitor and a silicon interposer. The silicon capacitor structure is directly hybrid-bonded to the second bonding surface on the front side of the silicon interposer via a first bonding layer on its back side. The core of this method lies in the "capacitor-first" integration process: firstly, a deep trench capacitor is formed within a first silicon substrate, and an interconnect metal layer and a first conductive pillar are constructed on its front side, along with a planarized first bonding layer. Finally, the deep trench capacitor structure is hybrid-bonded to a pre-prepared silicon interposer with a coplanar second bonding surface. The technical effects of this invention achieve breakthroughs in multiple dimensions: in terms of integration density, hybrid bonding reduces the interconnect spacing to the micrometer level, increasing the interconnect density per unit area by more than 10 times, and the capacitor layer does not occupy the wiring resources of the silicon interposer. In terms of electrical performance, eliminating microbumps significantly shortens the vertical interconnect distance and optimizes high-frequency signal integrity. In terms of reliability, the all-silicon structure achieves thermal expansion matching, significantly enhancing thermo-mechanical reliability and effectively reducing hotspot temperatures. In terms of manufacturing, this process is compatible with 300mm wafer fabrication, eliminating the need for bump fabrication and underfill steps, and is expected to reduce packaging costs by 10-15%. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0107] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a silicon-based capacitor stack structure, characterized in that, Includes the following steps: S1, a first silicon substrate is provided, and a deep trench capacitor structure is formed in the first silicon substrate; the first silicon substrate has a front side and a back side disposed opposite to each other; the deep trench capacitor structure includes a polycrystalline silicon electrode and a capacitor dielectric layer located between the polycrystalline silicon electrode and the first silicon substrate. S2, An interconnect structure electrically connected to the deep trench capacitor structure is formed on the front side of the first silicon substrate. The interconnect structure includes blind via pillars and an interconnect metal layer. The back side of the first silicon substrate is thinned to form a through first conductive pillar. The first conductive pillars are staggered with the deep trench capacitor structure in a planar layout. The interconnect metal layer is electrically connected to the deep trench capacitor structure. S3, a first bonding layer is formed on the back side of the first silicon substrate. The first bonding layer includes a coplanar first conductive block and a double dielectric layer surrounding the first conductive block. The first conductive block is electrically connected to the interconnect metal layer through the first conductive post. S4, a silicon interposer is provided, the silicon interposer comprising a second silicon substrate, a second conductive pillar penetrating the second silicon substrate, and a second bonding layer located on the front side of the second silicon substrate; the second bonding layer is electrically connected to the second conductive pillar; wherein, the second bonding layer has a second bonding surface composed of a second dielectric layer and a second conductive block embedded in the second dielectric layer, and the top surface of the second conductive block is flush with the top surface of the second dielectric layer; S5, the first bonding layer on the back side of the first silicon substrate is mixed and bonded with the second bonding surface on the front side of the silicon interposer.

2. The method for fabricating the silicon-based capacitor stack structure according to claim 1, characterized in that, The step of forming the first bonding layer in step S3 includes: S3-1, A temporary substrate is provided, and the front side of the first silicon substrate is bonded to the temporary substrate through a temporary bonding layer; S3-2, Planarize the back side of the first silicon substrate to expose the first conductive pillar; S3-3, a double dielectric layer is formed on the back side of the first silicon substrate; the double dielectric layer includes a SiCN layer at the bottom and a first silicon oxide layer above the SiCN layer; S3-4, A first conductive block is formed in the double-layer dielectric layer using a damascus process, and the first conductive block is electrically connected to the first conductive post. S3-5, Planarize the first silicon oxide layer and the first conductive block so that their top surfaces are flush, forming the first bonding layer; S3-6, Remove the temporary substrate.

3. The method for fabricating the silicon-based capacitor stack structure according to claim 2, characterized in that: The SiCN layer is formed using a PECVD process at a temperature range of 300~500℃.

4. The method for fabricating the silicon-based capacitor stack structure according to claim 1, characterized in that, The interconnect structure is formed using a double damask process in step S2, including: S2-1, deposit an interlayer dielectric layer on the front side of the first silicon substrate, and sequentially etch to form a first blind hole electrically connected to the deep trench capacitor structure, and a first trench located above the first blind hole; S2-2, after filling the first blind hole and the first trench through a single electroplating process, the thickness is reduced to form the interconnect metal layer and the first conductive pillar.

5. The method for fabricating the silicon-based capacitor stack structure according to claim 1, characterized in that: The temperature range of the hybrid bonding process is 300~400℃.

6. The method for fabricating the silicon-based capacitor stack structure according to claim 1, characterized in that: The capacitor dielectric layer includes one of hafnium oxide and zirconium oxide.

7. The method for fabricating the silicon-based capacitor stack structure according to claim 1, characterized in that: The deep trench capacitor structure formed within the first silicon substrate includes multiple functional regions with different capacitance densities; and the interconnect metal layer is configured as multiple conductive structures corresponding to the functional regions and electrically isolated from each other.

8. A silicon-based capacitor stacking structure, characterized in that, include: A silicon capacitor structure, the silicon capacitor structure including a first silicon substrate, the first silicon substrate having a front side and a back side disposed opposite to each other; The silicon capacitor structure includes a deep trench capacitor structure; the deep trench capacitor structure includes a polycrystalline silicon electrode and a capacitor dielectric layer located between the polycrystalline silicon electrode and the first silicon substrate; An interconnect structure is provided, comprising an interconnect metal layer and a first conductive pillar. The interconnect metal layer is located on the front side of the first silicon substrate and is electrically connected to the polysilicon electrode. The first conductive pillar penetrates the first silicon substrate, and a first barrier layer is provided between the sidewall of the first conductive pillar and the first silicon substrate. The first conductive pillar is staggered with the deep trench capacitor structure in a planar layout, and the front end of the first conductive pillar is electrically connected to the interconnect metal layer. The first bonding layer is located on the back side of the first silicon substrate and includes a coplanar first conductive block and a double dielectric layer surrounding the first conductive block. The first conductive block is electrically connected to the back end of the first conductive post; A silicon interposer, the silicon interposer comprising a second silicon substrate, a second conductive pillar penetrating the second silicon substrate, and a second bonding layer located on the front side of the second silicon substrate; the second bonding layer is electrically connected to the second conductive pillar. The second bonding layer has a second bonding surface consisting of a second dielectric layer and a second conductive block embedded in the second dielectric layer, wherein the top surface of the second conductive block is flush with the top surface of the second dielectric layer.

9. The silicon-based capacitor stacking structure according to claim 8, characterized in that: The bilayer dielectric layer includes a SiCN layer at the bottom and a silicon oxide layer above the SiCN layer.

10. The silicon-based capacitor stack structure according to claim 8, characterized in that: The deep trench capacitor structure within the first silicon substrate includes multiple functional regions with different capacitance densities; and the interconnect metal layer is configured as multiple conductive structures corresponding to the functional regions and electrically isolated from each other.

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