A semiconductor device, a chip package structure, and an electronic device

Abstract

The application provides a semiconductor device, a chip packaging structure and an electronic device, and relates to the technical field of semiconductors. The application is used to solve the problem that the layout of electronic devices is affected due to the continuous thinning of electronic devices, the continuous reduction of internal space, and the continuous increase in the number of electronic devices inside the electronic devices. The semiconductor device comprises a first chip and a second chip. The first chip has two opposite surfaces, at least part of one of the two surfaces forms a first active surface, at least part of the other of the two surfaces forms a second active surface, and the first active surface is electrically connected to the second active surface. The second chip is fixed to the surface where the first active surface is located, and the second chip is electrically connected to the first active surface.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device, chip packaging structure, and electronic device. Background Technology

[0002] The trend towards thinner and lighter electronic devices has led to a continuous reduction in internal space. Furthermore, as users' functional demands for electronic devices increase, the number of internal electronic components continues to rise. Therefore, the decreasing internal space coupled with the increasing number of components is impacting their layout. Summary of the Invention

[0003] This application provides a semiconductor device, a chip packaging structure, and an electronic device to address the problem that as electronic devices become increasingly thinner, their internal space decreases while the number of electronic devices inside them increases, affecting the layout of these devices.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] In a first aspect, a semiconductor device is provided, comprising a first chip and a second chip. The first chip has two opposing surfaces, at least a portion of one of the surfaces forming a first active surface, and at least a portion of the other surface forming a second active surface, wherein the first active surface and the second active surface are electrically connected. The second chip is fixed to the surface containing the first active surface and is electrically connected to the first active surface.

[0006] The semiconductor device provided in the first aspect of this application has a second chip disposed on the surface where the first active surface of the first chip is located, and electrically connected to the first active surface. For example, the second chip can be soldered to the first active surface, thereby enabling the second chip to be electrically connected to the first active surface. When the semiconductor device is soldered onto a substrate, the second chip can achieve electrical connection with the substrate through the first chip. Therefore, no leads are needed between the second chip and the substrate, which can save dimensions along the thickness direction, thereby ensuring chip integration while also facilitating chip thinning.

[0007] In one possible implementation of the first aspect of this application, the first chip includes a doped layer and a first metal wiring layer, the first metal wiring layer being electrically connected to the doped layer, and a first active surface being formed on the surface of the first metal wiring layer away from the doped layer. In this structure, the transistor formed by the doped layer and the first metal wiring layer can form an integrated circuit, and the second chip is electrically connected to the first metal wiring layer, thereby making the second chip electrically connected in the integrated circuit.

[0008] In one possible implementation of the first aspect of this application, the first chip further includes a second metal wiring layer, which is disposed on the side of the doped layer away from the doped layer and is electrically connected to the doped layer. In this structure, the first and second metal wiring layers share a single doped layer, which helps to reduce the distance between the first and second metal wiring layers, i.e., reduces the thickness of the first chip, thereby facilitating overall chip thinning.

[0009] In one possible implementation of the first aspect of this application, a first groove is formed on the surface where the first active surface is located, and the bottom surface of the first groove forms the first active surface. In this structure, the second chip can be fixed within the first groove, thereby improving the connection strength between the first chip and the second chip and enhancing the overall structural reliability of the semiconductor device. Furthermore, it facilitates the thinning of the entire semiconductor device.

[0010] In one possible implementation of the first aspect of this application, the first chip includes a first region and a second region distributed along the thickness direction. A first groove is disposed in the first region, and a doped layer and a first metal wiring layer are both disposed in the second region. In this structure, the first region forms the substrate portion of the first chip. By placing the first groove in the first region, the first groove can be prevented from affecting the doped layer, the first metal wiring layer, and the second metal wiring layer disposed in the second region, thereby further improving the reliability of the overall structure.

[0011] In one possible implementation of the first aspect of this application, the first groove extends into the second region. With this structure, the bottom surface of the first groove exposes the first metal wiring layer, thereby forming a first active surface on the bottom surface of the first groove. Therefore, it is not necessary to establish an electrical connection between the bottom surface of the first groove and the first metal wiring layer through vias or similar means, which helps to reduce manufacturing complexity.

[0012] In one possible implementation of the first aspect of this application, a first metal wiring layer of the first chip is disposed on the bottom surface of a first groove. In this structure, the first metal wiring layer is disposed on the bottom surface of the first groove, meaning the first groove extends to the aforementioned doped layer, thereby electrically connecting the first metal wiring layer and the doped layer, which helps to reduce processing difficulty.

[0013] In one possible implementation of the first aspect of this application, a plurality of first grooves are formed on the surface of the first chip, and a second chip is disposed in each first groove. With this structure, by providing multiple second chips, the integration density of the semiconductor device can be further improved without increasing the thickness of the semiconductor device, thus saving internal space when the semiconductor device is applied in an electronic device.

[0014] In one possible implementation of the first aspect of this application, a plurality of second chips are disposed within the first groove. With this structure, only one first groove can be formed on the first chip, thereby saving processing steps and reducing production costs.

[0015] In one possible implementation of the first aspect of this application, an adhesive material is used to fill the gap between the second chip and the inner wall of the first groove. In this structure, the adhesive material can fill the gap between the second chip and the inner wall of the first groove, and the two are bonded and fixed together, which can improve the connection strength between them, thereby improving the reliability of the overall structure.

[0016] In one possible implementation of the first aspect of this application, the semiconductor device includes a third chip, a second groove is formed on the surface of the second chip, the third chip is disposed in the second groove and electrically connected to the second chip. For example, the second groove is formed on the surface of the second chip facing the bottom surface of the first groove, and the third chip is electrically connected to the first chip. Alternatively, the second groove is formed on the surface of the second chip facing the outside of the first groove, and the third chip is electrically connected to the second chip.

[0017] This allows for further improvement in the integration of semiconductor devices and a reduction in their thickness, which in turn saves internal space in electronic devices and makes them thinner and lighter.

[0018] In one possible implementation of the first aspect of this application, multiple second chips are provided, and all the multiple second chips are fixed on the surface where the first active surface is located and electrically connected to the first active surface. With this structure, multiple second chips can be provided on the first active surface, thereby improving the integration density of the semiconductor device while also reducing the thickness of the semiconductor device.

[0019] In one possible implementation of the first aspect of this application, both the first chip and the second chip are bare chips. In this structure, multiple bare chips are electrically connected via the aforementioned structure before packaging, thereby improving the integration density of the semiconductor device. Furthermore, the semiconductor device formed after packaging multiple bare chips has a smaller overall thickness. When used in electronic devices, this facilitates space saving, i.e., it promotes the thinning of electronic devices.

[0020] Secondly, a chip packaging structure is provided, which includes a packaging substrate, a molding compound, and a first semiconductor device. The first semiconductor device is a semiconductor device as described in any of the above technical solutions. The first semiconductor device is packaged in the molding compound, and the first chip of the first semiconductor device is connected to the packaging substrate.

[0021] The chip packaging structure provided in the second aspect of this application, since it includes the semiconductor device described in any of the above technical solutions, can solve the same technical problem and achieve the same technical effect.

[0022] In one possible implementation of the second aspect of this application, multiple first semiconductor devices are provided, all of which are encapsulated within a molding compound. Exemplarily, the number of second chips included in each first semiconductor device may be exactly the same or different. The number of first recesses formed in the first chips of each first semiconductor device may be exactly the same or different. Furthermore, the number of second chips disposed within the first recesses of each first semiconductor device may be exactly the same or different.

[0023] In one possible implementation of the second aspect of this application, the chip package structure further includes a second semiconductor device encapsulated within a molding compound. Exemplarily, the second semiconductor device may include only one chip or multiple chips. When the second semiconductor device includes multiple chips, the structure of the second semiconductor device may be the same as or different from the first semiconductor device. Furthermore, the chip package structure may include one or more second semiconductor devices.

[0024] Thirdly, an electronic device is provided, comprising a housing, a circuit board, and a chip packaging structure. The circuit board is disposed within the housing, and the chip packaging structure is as described in any of the above technical solutions. The packaging substrate of the chip packaging structure is fixed on the circuit board and electrically connected to the circuit board.

[0025] The electronic device provided in the third aspect of this application, by including the packaging structure described in any of the above technical solutions, is able to solve the same technical problem and achieve the same technical effect. Attached Figure Description

[0026] Figure 1 A structural diagram of an electronic device provided in an embodiment of this application;

[0027] Figure 2 A front view of an electronic device provided in an embodiment of this application;

[0028] Figure 3 This is a front view of an electronic device in a folded state, as provided in an embodiment of this application.

[0029] Figure 4 An exploded view of an electronic device provided in an embodiment of this application;

[0030] Figure 5 This is a structural diagram of a chip packaging structure provided in an embodiment of this application;

[0031] Figure 6 This is a structural diagram of another chip packaging structure provided in an embodiment of this application;

[0032] Figure 7 A structural diagram of a semiconductor device provided in an embodiment of this application;

[0033] Figure 8 A schematic diagram of the structure of the first chip provided in the embodiments of this application, including the doped layer, the first metal wiring layer, and the second metal wiring layer;

[0034] Figure 9 This is a structural diagram of yet another chip packaging structure provided in an embodiment of this application;

[0035] Figure 10 This is a structural diagram of another semiconductor device provided in an embodiment of this application;

[0036] Figure 11 for Figure 10 A structural diagram of the first chip of the provided semiconductor device;

[0037] Figure 12 A cross-sectional structural diagram of a semiconductor device provided in an embodiment of this application;

[0038] Figure 13 This is a structural diagram of another chip packaging structure provided in the embodiments of this application;

[0039] Figure 14 A structural diagram of another second chip included in the chip packaging structure provided in the embodiments of this application;

[0040] Figure 15 A chip packaging structure including multiple second chips is provided in an embodiment of this application;

[0041] Figure 16 A structural diagram of another chip packaging structure provided in this application embodiment, including multiple second chips and multiple third chips;

[0042] Figure 17 A structural diagram of another chip packaging structure provided in this application embodiment, including multiple second chips and multiple third chips;

[0043] Figure 18 A top view of a wafer provided in an embodiment of this application;

[0044] Figure 19 This is a structural diagram of the first chip provided in an embodiment of this application;

[0045] Figure 20 Exploded views of the first chip and the second chip provided in the embodiments of this application;

[0046] Figure 21 for Figure 20 A structural diagram of the semiconductor device formed by the first chip and the second chip is provided.

[0047] Figure 22 for Figure 21 A structural diagram of the provided semiconductor device after the first groove is filled with adhesive material;

[0048] Figure 23 for Figure 22 A structural diagram showing the semiconductor device fixed on the substrate;

[0049] Figure 24 for Figure 23 A structural diagram of the chip formed after the provided semiconductor device is packaged.

[0050] Figure 25 This is a structural diagram of a chip packaging structure including multiple semiconductor devices, provided as an embodiment of this application.

[0051] Reference numerals: 01-Electronic device; 10-Folding screen; 11-First part; 12-Second part; 20-Support device; 21-Housing; 22-Hinge mechanism; 30-Outer screen; 40-Circuit board; 50-Electronic device; 51-Chip packaging structure; 100-Packaging substrate; 200-Molding layer; 300-Semiconductor device; 310-First chip; 311-First active surface; 312-Second active surface; 313-Doped layer; 314-First metal wiring layer; 315-Second metal wiring layer; 316-First groove; 317-First region; 318-Second region; 320-Second chip; 321-Second groove; 330-Third chip; 400-Bump; 500-Lead; 600-Adhesive film; 700-Adhesive material; 02-Wafer; 03-Metal wiring area. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0053] In the following text, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature.

[0054] Furthermore, in this application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0055] In this application, unless otherwise expressly specified and limited, the term "connection" shall be interpreted broadly. For example, "connection" may be a fixed connection, a detachable connection, or an integral part; it may be a direct connection or an indirect connection through an intermediate medium.

[0056] This application provides an electronic device. Specifically, the electronic device can be a portable electronic device or other types of electronic devices. For example, the electronic device can be a mobile phone, tablet personal computer, laptop computer, personal digital assistant (PDA), monitor, camera, personal computer, laptop computer, wearable device, etc.

[0057] Furthermore, the aforementioned electronic devices can also be terminal devices with foldable screens, such as foldable screen phones. For ease of explanation, the following examples all use foldable screen phones as an example.

[0058] Specifically, please refer to Figure 1 and Figure 2 , Figure 1 This is a structural diagram of an electronic device 01 provided in an embodiment of this application. Figure 2 This is a front view of an electronic device 01 provided in an embodiment of this application. The electronic device 01 may include a foldable screen 10 and a support device 20. The foldable screen 10 is supported and attached to the support device 20, and the support device 20 is capable of driving the foldable screen 10 to rotate between an unfolded state and a folded state. It is understood that... Figure 1 and Figure 2 Only some components of electronic device 01 are shown schematically; the actual shape, size, location, and construction of these components are not subject to change. Figure 1 and Figure 2 The limitations of the structure shown.

[0059] For ease of description in the following embodiments, an XYZ coordinate system is established. When the electronic device 01 is in an unfolded or folded state, the width direction of the electronic device 01 is defined as the X-axis, the length direction as the Y-axis, and the thickness direction as the Z-axis. It should be noted that this XYZ coordinate system can be flexibly transformed according to actual needs. The embodiments in this application only provide one possible example and should not be considered as a special limitation of this application.

[0060] The aforementioned foldable screen 10 is used to display images, videos, etc. The foldable screen 10 may include multiple first portions 11 and at least one second portion 12, with the second portion 12 disposed between two adjacent first portions 11. When the electronic device 01 is in a folded state, the second portion 12 of the foldable screen 10 is bent, and the multiple first portions 11 are stacked. At least the second portion 12 of the foldable screen 10 is a flexible screen. The first portions 11 of the foldable screen 10 may be flexible screens, non-flexible screens, or a combination of both. Therefore, this application does not impose specific limitations in this regard.

[0061] Among them, the aforementioned foldable screen 10 can be an organic light-emitting diode (OLED) display, an active-matrix organic light-emitting diode (AMOLED) display, a mini organic light-emitting diode (MLED) display, a micro organic light-emitting diode (MOLED) display, a quantum dot light-emitting diode (QLED) display, a liquid crystal display (LCD), etc.

[0062] The aforementioned support device 20 is used to support the folding screen 10. The support device 20 may include multiple housings 21 and at least one pivot mechanism 22, with the pivot mechanism 22 connecting two adjacent housings 21. A first portion 11 of the folding screen 10 is supported and attached to a corresponding housing 21, and a second portion 12 of the folding screen 10 is supported and attached to a corresponding pivot mechanism 22. Adjacent housings 21 are rotatably connected via a rotating mechanism, allowing the electronic device 01 to rotate between the unfolded and folded states. In the following embodiment, the support device 20 includes two housings 21 and one pivot mechanism 22, and the folding screen 10 includes two first portions 11 and one second portion 12 as an example for illustration.

[0063] With electronic device 01 in the unfolded state, please continue reading. Figure 1 and Figure 2 , Figure 1 and Figure 2 The diagram shows the structure of electronic device 01 in its unfolded state. In this state, the folding screen 10 can be fully unfolded, meaning the first part 11 and the second part 12 of the folding screen 10 are on the same plane, ensuring the flatness of the folding screen 10. In this state, a large-screen display is achieved by electronic device 01, providing a better user experience. For example, when watching a movie, a large screen can enhance the viewing experience.

[0064] When electronic device 01 is in a folded state, please refer to Figure 3 , Figure 3 This is a front view of an electronic device 01 in a folded state, as provided in an embodiment of this application. In this state, the two first portions 11 of the folded screen 10 are opposite each other, the second portion 12 is bent, and the support device 20 protects the folded screen 10 from external impact, meaning the folded screen 10 is positioned between the two housings 21 of the support device 20. In this state, the folded screen 10 is invisible to the user, preventing scratches or damage and thus providing effective protection for the folded screen 10. For example, when the phone is not needed, the electronic device 01 can be folded to avoid screen damage.

[0065] In some embodiments, please continue reading Figure 3 The electronic device 01 may also include an external screen 30 (also referred to as a secondary screen), which is located on the side of any of the housings 21 away from the folding screen 10. When the electronic device 01 is in the folded state, the external screen 30 can be used to display images, allowing users to operate it with one hand, thus making the use scenarios of the electronic device 01 more diverse. For example, when a user is riding public transportation, one hand needs to hold the handrail. At this time, the external screen 30 can be used to display images for one-handed operation, which helps to further improve the user experience.

[0066] Based on this, please refer to Figure 4 , Figure 4 This is an exploded view of an electronic device 01 provided in an embodiment of this application. The electronic device 01 also includes a circuit board 40 and electronic components 50. The circuit board 40 is used to house the electronic components 50 inside the electronic device 01 and to realize electrical connections between the electronic components 50. The circuit board 40 can be fixed to the middle plate by means of adhesive bonding, threaded connection, welding, snap-fit, etc. Therefore, this application does not impose any special limitations on the fixing method of the circuit board 40.

[0067] The aforementioned electronic device 50 is used to implement various functions of the electronic device 01. For example, the electronic device 50 can be a control chip (e.g., a system-on-chip, SOC), a graphics processing unit (GPU), universal flash storage (UFS), a camera module, a flash module, and capacitors, resistors, inductors, etc.

[0068] Furthermore, the aforementioned control chips and graphics control chips are used to realize high-speed data computation, logic processing, and data storage functions, serving as the "brain" of electronic device 01. Hereinafter referred to as chip package structure 51. Please refer to... Figure 5 , Figure 5 This is a structural diagram of a chip packaging structure 51 provided in an embodiment of this application. The chip packaging structure 51 includes a packaging substrate 100, a molding compound 200, and a semiconductor device 300. The semiconductor device 300 may include at least one chip, and the semiconductor device 300 is disposed on the packaging substrate 100 and encapsulated within the molding compound 200.

[0069] It should be noted that the chip included in the aforementioned semiconductor device 300 can also be called a bare chip or bare die, which refers to a single die formed by cutting after integrated circuits are laid out on a wafer. In other words, the chip included in the semiconductor device 300 refers to a bare die that has not undergone packaging process.

[0070] As the electronic device 01 becomes increasingly thinner, its internal space is continuously compressed, resulting in a decrease in the usable area on the circuit board 40 for mounting the electronic device 50. Therefore, there is a growing demand for a smaller chip package structure 51 with higher integration. For example, the chip package structure 51 may include multiple chips stacked together, with adjacent chips fixed together by an adhesive film 600, thus forming the semiconductor device 300 from the multiple chips.

[0071] For example, the semiconductor device 300 may include a first chip 310 and a second chip 320. The first chip 310 is disposed on the packaging substrate 100, and the first chip 310 and the packaging substrate 100 are electrically connected by bumps 400. The second chip 320 is disposed on the side of the first chip 310 away from the packaging substrate 100, and the second chip 320 and the first chip 310 are connected by an adhesive film 600, and the second chip 320 and the packaging substrate 100 are electrically connected by wire bonding.

[0072] Please continue reading for more details. Figure 5 In the aforementioned chip packaging structure 51, along the Z-axis direction, the thickness of the packaging substrate 100 is approximately 150 μm, the height of the bump 400 is approximately 50 μm, the thickness of the first chip 310 is approximately 150 μm, the thickness of the adhesive film 600 is approximately 20 μm, the thickness of the second chip 320 is approximately 100 μm, the arc height of the lead 500 is approximately 80 μm, the molding die gap is approximately 100 μm (the overall thickness of the molding layer 200 is approximately 400 μm), and the solder ball height for soldering the packaging substrate 100 to the circuit board 40 is approximately 150 μm. Therefore, when this chip packaging structure 51 is soldered onto the circuit board 40, its total dimension along the Z-axis direction is approximately 0.8 mm.

[0073] It can be seen that the thickness of the chip packaging structure 51 is still relatively large, and the more chips integrated in the chip packaging structure 51, the larger the thickness will be. Therefore, it is not conducive to the overall thinning of the electronic device 01.

[0074] To address the aforementioned problems, this application provides a semiconductor device 300, which can be applied to the aforementioned electronic device 01. Please refer to... Figure 6 , Figure 6 This is a structural diagram of another chip packaging structure 51 provided in an embodiment of this application.

[0075] Specifically, the semiconductor device 300 may include a first chip 310 and a second chip 320, wherein the first chip 310 has a first surface and a second surface facing away from each other. Figure 6 In the indicated direction, the surface of the first chip 310 facing the second chip 320 is the first surface, and the surface of the first chip 310 facing the substrate 100 is the second surface. At least a portion of the first surface forms a first active surface 311, and at least a portion of the second surface forms a second active surface 312. The first active surface 311 and the second active surface 312 are electrically connected.

[0076] The second chip 320 is fixed to the first surface of the first chip 310, and the second chip 320 is electrically connected to the first active surface 311. For example, the second chip 320 can be soldered to the first active surface 311. The second active surface 312 is used to solder to the packaging substrate 100.

[0077] It is understood that the aforementioned active surfaces (including the first active surface 311 and the second active surface 312) refer to the surfaces used to connect the electronic device 50, so that the first chip 310 can transmit signals with the electronic device 50. That is, active surfaces are formed on both sides of the first chip 310, so that the electronic device 50 can be disposed on both sides of the first chip 310. Furthermore, both sides of the first chip 310 can be entirely formed as active surfaces, or only a portion of the surface can be formed as active surfaces; therefore, this application does not impose any special limitations on this.

[0078] For example, the aforementioned second chip 320 may be provided as a single unit or in multiple units. All multiple second chips 320 are fixed to the first surface of the first chip 310 and are electrically connected to the first active surface 311, thereby improving the integration of the semiconductor device 300 and saving space occupied inside the electronic device 01. Therefore, the embodiments of this application do not limit the number of second chips 320 provided.

[0079] In this way, after the semiconductor device 300 is packaged, the second chip 320 is electrically connected to the packaging substrate 100 through the first chip 310, so that the second chip 320 and the packaging substrate 100 do not need to be electrically connected by wire bonding, thereby saving the arc height dimension of the lead 500 (i.e. saving 80μm), so as to reduce the thickness dimension of the chip packaging structure 51 formed after the semiconductor device 300 is packaged.

[0080] And please see Figure 7 , Figure 7 This is a structural diagram of a semiconductor device 300 provided in an embodiment of this application. The first chip 310 of the semiconductor device 300 may include a doped layer 313, a first metal wiring layer 314, and a second metal wiring layer 315. Along the Z-axis direction, the first metal wiring layer 314 and the second metal wiring layer 315 are respectively disposed on both sides of the doped layer 313. The surface of the first metal wiring layer 314 away from the doped layer 313 forms a first active surface 311, and the surface of the second metal wiring layer 315 away from the doped layer 313 forms a second active surface 312.

[0081] Therefore, the first metal wiring layer 314 and the second metal wiring layer 315 can share a doped layer 313 to enable the first metal wiring layer 314 and the second metal wiring layer 315 to be electrically connected. This also helps to reduce the distance between the first metal wiring layer 314 and the second metal wiring layer 315 along the Z-axis, which helps to reduce the thickness of the first chip 310, thereby further reducing the thickness of the semiconductor device 300 after packaging.

[0082] It is understood that the aforementioned doped layer 313 refers to the doping of N-type or P-type doped materials on the wafer to form the source, gate, and drain structures of a transistor. Alternatively, doping in appropriate areas on the wafer surface can form different resistors, capacitors, and other devices, which can then be integrated with the aforementioned transistors to form an integrated circuit. Furthermore, when doping the wafer surface, the doped material can fill in uneven recessed structures (e.g., pits or grooves) on the wafer surface, thereby smoothing out the uneven areas and improving the surface flatness of the wafer.

[0083] And please see Figure 8 , Figure 8 This is a schematic diagram of the structure of the first chip 310 provided in this application embodiment, including the doped layer 313, the first metal wiring layer 314, and the second metal wiring layer 315. The first metal wiring layer 314 and the second metal wiring layer 315 are both provided in multiple layers, and the multiple layers of the first metal wiring layer 314 and the multiple layers of the second metal wiring layer 315 can be electrically connected through vias to form an integrated circuit.

[0084] For example, along the Z-axis direction, the multilayer first metal wiring layer 314 includes one first metal wiring layer 314a and multiple first metal wiring layers 314b. The first metal wiring layer 314a is the one furthest from the doped layer 313. The first metal wiring layer 314a is used to connect electronic devices (e.g., the electronic device is the second chip 320 mentioned above) and can also be called a passivation layer. That is, the surface of the first metal wiring layer 314a away from the doped layer 313 forms the first active surface 311 mentioned above.

[0085] Correspondingly, along the Z-axis direction, the multilayer second metal wiring layer 315 includes one second metal wiring layer 315a and multiple second metal wiring layers 315b. The second metal wiring layer 315a is the one furthest from the doped layer 313. The second metal wiring layer 315a is used to connect electronic devices (e.g., the electronic device is the aforementioned substrate 100), that is, to form the aforementioned passivation layer. The surface of the second metal wiring layer 315a away from the doped layer 313 forms the aforementioned second active surface 312.

[0086] Understandable Figure 8The diagram shows only a portion of the layered structure included in the chip. The chip may also include other layered structures; for example, a dielectric layer may be disposed between two adjacent metal wiring layers, and vias may be formed within the dielectric layer. Therefore, Figure 8 This is only a partial illustration of the chip's structure and does not limit the chip's specific structure.

[0087] In some embodiments, please refer to Figure 9 , Figure 9 This is a structural diagram of another chip packaging structure 51 provided in an embodiment of this application. A first groove 316 may be formed on the first surface of the first chip 310, and the bottom surface of the first groove 316 may form the first active surface 311. The second chip 320 is disposed within the first groove 316. Exemplarily, the second chip 320 may be completely disposed within the first groove 316. Alternatively, the second chip 320 may be partially disposed within the first groove 316. In the following embodiments, the example of the second chip 320 being completely disposed within the first groove 316 will be used for illustration.

[0088] In this way, by placing the second chip 320 within the first recess 316, i.e., the second chip 320 is located inside the first chip 310, the second chip 320 does not occupy space along the Z-axis. Therefore, the chip package structure 51 formed by encapsulating the semiconductor structure within the aforementioned molding compound 200, compared to... Figure 6 The structure shown can save at least the thickness of the second chip 320 and the thickness of the adhesive film 600.

[0089] Furthermore, the second chip 320 is electrically connected to the first active surface 311 of the first chip 310, meaning the second chip 320 is electrically connected to the packaging substrate 100 through the first chip 310. Therefore, the arc height dimension of the aforementioned lead 500 bonding can be saved, which is beneficial for further reducing the size of the packaged semiconductor device 300.

[0090] Specifically, as described above, along the Z-axis direction, the thickness of the packaging substrate 100 is approximately 150 μm, the height of the bump 400 is approximately 50 μm, the thickness of the first chip 310 is approximately 150 μm, the thickness of the second chip 320 is approximately 50 μm (the second chip 320 is located within the first groove 316, therefore, it does not occupy the dimension in the Z-axis direction), the molding die gap is approximately 100 μm, and the solder ball height of the packaging substrate 100 and the circuit board 40 is approximately 150 μm. Compared to the structure shown in Figure *, at least 200 μm of thickness can be saved. That is, when the chip packaging structure 51 formed by the semiconductor structure is soldered onto the circuit board 40, the total dimension along the Z-axis direction is approximately 0.6 mm, which is beneficial for further thinning of the electronic device 01.

[0091] Furthermore, the first groove 316 can contain either a single second chip 320 or multiple second chips 320. If multiple second chips 320 are present in the first groove 316, they can be stacked along the Z-axis or spaced apart along a direction parallel to the packaging substrate 100. Additionally, the first surface of the first chip 310 can have either a single first groove 316 or multiple first grooves 316, with each first groove 316 containing at least one second chip 320. This further enhances the integration of the chip packaging structure 51, reducing the space occupied by the chip packaging structure 51 within the electronic device 01, thus contributing to the thinner and lighter design of the electronic device 01.

[0092] Based on this, please refer to Figure 10 and Figure 11 , Figure 10 This is a structural diagram of another semiconductor device 300 provided in an embodiment of this application. Figure 11 for Figure 10 The provided semiconductor device 300 includes a first chip 310, which may include a first region 317 and a second region 318 distributed along the Z-axis. A first groove 316 is formed on the surface of the first region 317 away from the second region 318. Specifically, the surface of the first region 317 away from the second region 318 is the first surface, and the surface of the second region 318 away from the first region 317 is the second surface. The doped layer 313, the first metal wiring layer 314, and the second metal wiring layer 315 are all disposed in the second region 318. This design prevents the first groove 316 from affecting the placement of the doped layer 313, the first metal wiring layer 314, and the second metal wiring layer 315, thereby ensuring the overall reliability of the first chip 310.

[0093] Furthermore, along the Z-axis, the first groove 316 can extend to the second region 318, meaning the first groove 316 can penetrate the first region 317, exposing the second region 318 on the bottom surface of the first groove 316. This allows the first metal wiring layer 314 to be exposed on the bottom surface of the first groove 316, thus forming the aforementioned first active surface 311 on the bottom surface of the first groove 316. In this way, the second chip 320 can be soldered to the bottom surface of the first groove 316, enabling electrical connection between the first chip 320 and the first chip 310, which helps reduce manufacturing complexity.

[0094] In some embodiments, the first metal wiring layer 314 may be disposed on the bottom surface of the first groove 316 so that the bottom surface of the first groove 316 forms the first active surface 311, and the second chip 320 may be soldered and fixed to the first active surface 311, thereby realizing the electrical connection between the second chip 320 and the first chip 310.

[0095] Please see Figure 12 , Figure 12 This is a cross-sectional view of a semiconductor device 300 provided in an embodiment of this application. To further enhance the connection strength between the second chip 320 and the first chip 310, an adhesive material 700, such as underfill glue or MUF filler, can be filled between the second chip 320 and the inner wall of the first groove 316 to fill the gap between the second chip 320 and the first chip 310, thereby improving the connection strength between the second chip 320 and the first chip 310. Then, the semiconductor device 300 can be packaged.

[0096] It is understood that the adhesive material 700 can completely encapsulate the second chip 320, that is, the adhesive material 700 covers the surface of the second chip 320 away from the first active surface 311. Alternatively, the adhesive material 700 can only fill the space between the second chip 320 and the inner wall of the first groove 316, that is, the adhesive material 700 does not cover the surface of the second chip 320 away from the first active surface 311. Therefore, the embodiments of this application do not impose any special limitations on this.

[0097] Based on the above embodiments, please refer to Figure 13 , Figure 13 This is a structural diagram of another chip packaging structure 51 provided in an embodiment of this application. The semiconductor device 300 of the chip packaging structure 51 may further include a third chip 330. A second recess 321 may be formed on the second chip 320, and the third chip 330 is disposed in the second recess 321 and electrically connected to the second chip 320. In this way, the integration of the semiconductor device 300 can be further improved, thereby saving space occupied in the electronic device 01.

[0098] The second chip 320 can have the same structure as the first chip 310, so that the bottom surface of the second groove 321 forms an active surface. The third chip 330 is soldered into the second groove 321, thereby achieving electrical connection between the third chip 330 and the second chip 320, and also electrical connection between the third chip 330 and the first chip 310 and the packaging substrate 100. For example, the second groove 321 can be formed on the side of the second chip 320 away from the bottom surface of the first groove 316. The third chip 330 is electrically connected to the second chip 320, and is also electrically connected to the first chip 310 through the second chip 320, thereby achieving electrical connection between the third chip 330 and the aforementioned packaging substrate 100, to further improve the integration of the semiconductor device 300.

[0099] In other examples, please refer to Figure 14 , Figure 14 This is a structural diagram of a second chip 320 included in the chip packaging structure 51 provided in this application embodiment. The second groove 321 can also be formed on the surface of the second chip 320 facing the bottom surface of the first groove 316. The third chip 330 is fixed within the second groove 321, and the third chip 330 is opposite to the bottom surface of the first groove 316, meaning the third chip 330 can be directly electrically connected to the first chip 310. In this case, only a fixed connection is needed between the third chip 330 and the second chip 320. For example, the third chip 330 can be bonded to the second groove 321 of the second chip 320, and the third chip 330 is opposite to the bottom surface of the first groove 316 of the first chip 310 (i.e., the bottom surface of the first groove 316 of the first chip 310). Figure 11 The first active surface 311 shown can be soldered to make the third chip 330 electrically connected to the first chip 310.

[0100] For other possible examples, please refer to Figure 15 , Figure 15 The chip packaging structure 51 provided in this application embodiment includes a plurality of second chips 320 and a plurality of third chips 330. A plurality of first grooves 316 are provided on the first chip 310. That is, when a plurality of second chips 320 are provided, the above-mentioned second grooves 321 can be provided on each second chip 320, and at least one third chip 330 is provided in the second grooves 321.

[0101] Alternatively, please see Figure 16 , Figure 16 Another chip packaging structure 51 provided in this application embodiment includes a structure diagram of a plurality of second chips 320 and a plurality of third chips 330. In the above chip packaging structure 51, only some of the second chips 320 have a second groove 321, and at least one third chip 330 is disposed in the second groove 321.

[0102] In addition, please see Figure 17 , Figure 17 Another chip packaging structure 51 provided in this application includes a plurality of second chips 320 and a plurality of third chips 330. In this chip packaging structure 51, the third chips 330 disposed on different second chips 320 may have some facing the bottom surface of the first groove 316 and some facing the outside of the first groove 316. Therefore, this application does not impose any special limitations on the placement position and number of the third chips 330.

[0103] In other possible embodiments, the semiconductor device 300 may further include other chips, which may employ the connection structure between the first chip 310 and the second chip 320. For example, a recess may be formed on the third chip 330, and further chips may be disposed within the recess on the third chip 330, thereby further improving the integration of the semiconductor device 300. Since the specific structure is the same as that of the first chip 310 and the second chip 320, it will not be described again.

[0104] This is a detailed description of the structure of the semiconductor device 300. The manufacturing process of the semiconductor device 300 will be described below.

[0105] First, please refer to Figure 18 , Figure 18 This is a top view of wafer 02 provided in an embodiment of this application. Single-crystal silicon is extracted from high-purity silicon ore, grown into cylindrical silicon ingots, and cut into thin slices to form wafer 02. Wafer 02 is polished to smooth its surface, which helps ensure the accuracy of subsequent processes.

[0106] Next, wafer 02 is heated in a high-temperature furnace to allow the surface of wafer 02 (i.e., silicon material) to react with oxygen to generate silicon dioxide, forming an insulating layer or mask layer. Then, circuit patterns are formed on the surface of wafer 02 through processes such as coating with photoresist, exposure, and development. Dry etching or wet etching processes are then used to selectively etch areas not protected by photoresist.

[0107] Next, impurity ions (e.g., boron, phosphorus, etc.) are implanted into the surface layer of the wafer 02 using an ion implantation process to alter conductivity and form... Figure 11 The doped layer 313 is shown. It can be understood that the doped layer 313 is formed along the thickness direction of wafer 02 (i.e., along the Z-axis) through the ion-implanted region. Along a direction parallel to the XY plane, based on the design requirements of the aforementioned circuit pattern, ion implantation can be performed only on a portion of the surface of wafer 02; for example, a portion of the doped layer 313 can form structures such as the source, gate, or drain of a transistor.

[0108] Next, a metal wiring layer is formed by a thin film deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0109] The process involves forming a circuit pattern on the surface of wafer 02, creating multiple metal wiring regions 03. Each metal wiring region 03 comprises multiple metal wiring layers along the thickness direction of wafer 02. Dielectric layers are positioned between adjacent metal wiring layers, and these layers are electrically connected via vias in the dielectric layers, thus forming an integrated circuit for connecting different devices. Wafer 02 is then thinned using grinding and polishing processes to ensure surface flatness.

[0110] In this case, each metal wiring region 03 includes a metal wiring layer that is the second metal wiring layer 315 in the above embodiment (e.g., Figure 11 As shown), and the surface of the second metal wiring layer 315 forms the aforementioned second active surface 312.

[0111] Next, please continue reading. Figure 18 and in conjunction with reference Figure 19 , Figure 19 This is a structural diagram of the first chip 310 provided in an embodiment of this application. Figure 18 The first groove 316 is formed on the surface of the wafer 02 away from the metal wiring region 03, so that the doped layer 313 is exposed on the bottom surface of the first groove 316. Then, the wafer 02 is diced to form a plurality of the first chips 310, each of the first chips 310 having at least one first groove 316.

[0112] In some embodiments, the wafer 02 can be diced to form multiple chips before the first groove 316 is formed on the wafer 02, and then the first groove 316 is formed on a single chip to form the first chip 310. Therefore, this application does not impose any special limitation on the order of the process flow.

[0113] Next, please continue reading. Figure 19 A first metal wiring layer 314 is provided on the bottom surface of the first groove 316 so that the first metal wiring layer 314 is electrically connected to the second metal wiring layer 315. It is understood that the manufacturing method of the first metal wiring layer 314 is the same as that of the second metal wiring layer 315, therefore, it will not be described again.

[0114] Next, please refer to Figure 20 and Figure 21 , Figure 20 Exploded views of the first chip 310 and the second chip 320 provided in the embodiments of this application. Figure 21 for Figure 20 The provided diagram shows the structure of a semiconductor device 300 formed by a first chip 310 and a second chip 320, in which the second chip 320 is soldered within a first groove 316 of the first chip 310.

[0115] It should be noted that the first chip 310 and the second chip 320 can be formed by cutting the same wafer 02, or they can be formed separately by fabricating different wafers 02. Therefore, the embodiments of this application do not limit this.

[0116] Then, please see Figure 22 , Figure 22 for Figure 21 The provided semiconductor device 300 has a structural diagram after the first groove 316 is filled with adhesive material 700. After the second chip 320 is soldered to the first chip 310, adhesive material 700 is filled between the second chip 320 and the inner wall of the first groove 316. For example, underfill adhesive or MUF filler (molded underfill) fills the gap between the second chip 320 and the inner wall of the first groove 316 to form the above-mentioned semiconductor structure.

[0117] Furthermore, when the semiconductor structure also includes other chips, for example, Figure 13 The third chip 330 shown is manufactured by creating a second groove 321 on the second chip 320 and soldering the third chip 330 into the second groove 321, following the above-described process steps. Since the process flow is the same, it will not be repeated.

[0118] Finally, the aforementioned semiconductor device 300 is packaged. Please refer to [link / reference]. Figure 23 , Figure 23 for Figure 22 The provided structural diagram shows the semiconductor device 300 fixed to the substrate 100. First, the semiconductor device 300 is soldered onto the packaging substrate 100. Then, please refer to... Figure 24 , Figure 24 for Figure 23 The provided diagram illustrates the structure of a chip package structure 51 formed after the semiconductor device 300 is packaged. The semiconductor device 300 on the substrate is encapsulated using an encapsulation material, such as epoxy resin. After the encapsulation material cures, a molding layer 200 is formed. The semiconductor device 300 is encapsulated within this molding layer 200, thereby forming the chip package structure 51. This chip package structure 51 can be soldered to the aforementioned... Figure 4On the circuit board 40 shown.

[0119] Based on this, please refer to Figure 25 , Figure 25 This is a structural diagram of a chip package structure 51 including multiple semiconductor devices 300, provided in an embodiment of this application. The chip package structure 51 may include multiple semiconductor devices 300. For example, the multiple semiconductor devices 300 may include a first semiconductor device 300a and a second semiconductor device 300b. The first semiconductor device 300a includes the aforementioned first chip 310 and second chip 320, and the second chip 320 is fixed within a first recess 316 formed on the first chip 310. The second semiconductor device 300b may be a device consisting of only one chip.

[0120] Alternatively, in other possible embodiments, the second semiconductor device 300b may also include a first chip 310 and a second chip 320, but the second semiconductor device 300b forms a different structure than the first semiconductor device 300a. For example, the first semiconductor device 300a adopts... Figure 12 or Figure 22 The structure shown indicates that the second semiconductor device 300b employs... Figure 7 The structure shown is as described. Therefore, the specific structure of the second semiconductor device 300b is not specifically limited in the embodiments of this application.

[0121] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0122] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: A first chip has two opposing surfaces, at least a portion of one of the surfaces forms a first active surface, and at least a portion of the other surface forms a second active surface, wherein the first active surface and the second active surface are electrically connected. The second chip is fixed on the surface where the first active surface is located, and the second chip is electrically connected to the first active surface.

2. The semiconductor device according to claim 1, characterized in that, The first chip includes a doped layer and a first metal wiring layer, the first metal wiring layer being electrically connected to the doped layer, and the surface of the first metal wiring layer away from the doped layer forming the first active surface.

3. The semiconductor device according to claim 2, characterized in that, The first chip further includes a second metal wiring layer, which is disposed on the side of the doped layer away from the first metal wiring layer and is electrically connected to the doped layer.

4. The semiconductor device according to claim 2 or 3, characterized in that, A first groove is formed on the surface where the first active surface is located, and the bottom surface of the first groove forms the first active surface.

5. The semiconductor device according to claim 4, characterized in that, The first chip includes a first region and a second region distributed along the thickness direction, the first groove is formed in the first region, and the doped layer and the first metal wiring layer are both disposed in the second region.

6. The semiconductor device according to claim 5, characterized in that, The first groove extends into the second region.

7. The semiconductor device according to claim 6, characterized in that, The first metal wiring layer of the first chip is disposed on the bottom surface of the first groove.

8. The semiconductor device according to any one of claims 4-7, characterized in that, The surface of the first chip has multiple first grooves, and the second chip is disposed in each of the first grooves.

9. The semiconductor device according to any one of claims 4-8, characterized in that, Multiple second chips are disposed within the first groove.

10. The semiconductor device according to any one of claims 4-9, characterized in that, The space between the second chip and the inner wall of the first groove is filled with adhesive material.

11. The semiconductor device according to any one of claims 4-10, characterized in that, The semiconductor device includes a third chip, and a second groove is formed on the surface of the second chip. The third chip is disposed in the second groove and is electrically connected to the second chip.

12. The semiconductor device according to any one of claims 1-3, characterized in that, Multiple second chips are provided, and all multiple second chips are fixed on the surface where the first active surface is located and are electrically connected to the first active surface.

13. The semiconductor device according to any one of claims 1-12, characterized in that, Both the first chip and the second chip are bare chips.

14. A chip packaging structure, characterized in that, include: Packaging substrate; A molding layer is disposed on the packaging substrate; The first semiconductor device is the semiconductor device according to any one of claims 1-13, wherein the first semiconductor device is encapsulated in the molding compound, and the first chip of the first semiconductor device is connected to the encapsulation substrate.

15. The chip packaging structure according to claim 14, characterized in that, The first semiconductor device is provided in multiple forms, and all of them are encapsulated within the plastic encapsulation layer.

16. The chip packaging structure according to claim 14 or 15, characterized in that, The chip packaging structure also includes a second semiconductor device, which is encapsulated within the molding layer.

17. An electronic device, characterized in that, include: case; The circuit board is disposed within the housing; The chip packaging structure is the chip packaging structure according to any one of claims 14-16, wherein the packaging substrate of the chip packaging structure is fixed on the circuit board and electrically connected to the circuit board.

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