Chip packaging method, structure, heating and leveling device, and chip packaging apparatus

Abstract

The chip packaging method, structure, heating and flattening device and chip packaging equipment are provided. The chip packaging method comprises the following steps: providing a substrate, and a plurality of chip stack structures are attached to the substrate; wherein the chip stack structures and the substrate are attached by an adhesive film, and adjacent chips are attached by the adhesive film; heating the substrate to make the adhesive film reach a semi-melted state; and flattening the plurality of chip stack structures to make the distance from the top surface of the plurality of chip stack structures to the substrate be the same.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a chip packaging method, structure, heating and leveling apparatus, and chip packaging equipment. Background Technology

[0002] With the development of semiconductor technology, electronic devices are becoming increasingly miniaturized while their storage capacity is also increasing. Currently, chip packaging structures in electronic devices can utilize chip stacking (Stack-Die) technology or chip FOW (Flowover Wire) stacking technology to improve storage capacity. However, as the number of stacked chips continues to increase, problems such as height errors, unevenness, and warping can occur in the chip stacking structure. Summary of the Invention

[0003] In view of this, the present disclosure provides a chip packaging method, structure, heating and leveling device, and chip packaging equipment.

[0004] In a first aspect, embodiments of this disclosure provide a chip packaging method, comprising: providing a substrate; having a plurality of chip stack structures bonded to the substrate; wherein the chip stack structures and the substrate, as well as adjacent chips, are bonded together with adhesive films; heating the substrate to make the adhesive films reach a semi-molten state; and leveling the plurality of chip stack structures so that the distance from the top surface of the plurality of chip stack structures to the substrate is the same.

[0005] In some embodiments of this disclosure, heating the substrate includes heating the substrate to a preset temperature; wherein the preset temperature is greater than or equal to 50°C and less than or equal to 100°C.

[0006] In some embodiments of this disclosure, leveling the plurality of chip stack structures includes: applying a preset pressure to the plurality of chip stack structures within a preset time period to level them; wherein the preset time is greater than or equal to 1s and less than or equal to 10s; and the preset pressure is greater than or equal to 3N and less than or equal to 50N.

[0007] In some embodiments of this disclosure, after leveling the plurality of chip stack structures, the method further includes: curing the substrate and the plurality of chip stack structures.

[0008] In some embodiments of this disclosure, a method for attaching the plurality of stacked chip structures to the substrate includes: picking up the chip; having the adhesive film attached to the back side of the chip; and attaching the chip to a target position on the substrate.

[0009] In a second aspect, embodiments of this disclosure provide a chip packaging structure, including: a substrate and a plurality of chip stacked structures; the plurality of chip stacked structures are attached to the substrate; the chip stacked structure includes: a plurality of chips and an adhesive film; the adhesive film is located between the chip stacked structure and the substrate; the adhesive film is also located between adjacent chips; wherein the top surface of the plurality of chip stacked structures is at the same distance from the substrate.

[0010] In some embodiments of this disclosure, the plurality of chip stacking structures include: a first chip stacking structure and a second chip stacking structure; the adhesive film in the first chip stacking structure has a first thickness; the adhesive film in the second chip stacking structure has a second thickness; and the first thickness is greater than the second thickness.

[0011] Thirdly, embodiments of this disclosure provide a heating and leveling apparatus, comprising: a heating plate configured to place a substrate and heat the substrate to bring the adhesive film to a semi-molten state; a plurality of chip stack structures are bonded to the substrate; wherein the chip stack structures and the substrate, as well as adjacent chips, are bonded together by the adhesive film; and a pressing device configured to level the plurality of chip stack structures so that the distance from the top surface of the plurality of chip stack structures to the substrate is the same.

[0012] In some embodiments of this disclosure, the pressing device includes: an integral pressing block; the coverage area of ​​the integral pressing block is greater than or equal to the area of ​​the substrate.

[0013] In some embodiments of this disclosure, the pressing device includes: a pressing base and a plurality of separate pressing blocks; the separate pressing blocks and the pressing base are elastically connected; the spacing between the separate pressing blocks is consistent with the spacing of the chip stack structure on the substrate; the coverage area of ​​each separate pressing block is greater than or equal to the projected area of ​​each chip stack structure on the substrate.

[0014] Fourthly, embodiments of this disclosure provide a chip packaging apparatus, including: a heating and leveling device as described in the above scheme.

[0015] In some embodiments of this disclosure, the chip packaging apparatus further includes: a pickup module configured to pick up a chip; the back of the chip having the adhesive film attached; and a bonding module configured to bond the chip to a target position on a substrate.

[0016] Understandably, to address issues such as height errors, unevenness, and warpage in chip stacking structures, the adhesive film is heated to a semi-molten state before being used to level multiple chip stacks. This ensures that the distance from the top surface of each chip stack to the substrate is the same, eliminating height deviations and addressing unevenness and warpage. This significantly improves the precision of the die-casting process and reduces cumulative height errors. Furthermore, it allows for a reduction in the height of the chip stack, increasing packaging density and providing more design flexibility for the chip packaging structure. Finally, it enhances the bending strength and warpage resistance of the packaging structure. Attached Figure Description

[0017] Figure 1 This is one of the schematic diagrams of the chip packaging structure provided in the embodiments of this disclosure;

[0018] Figure 2 A schematic flowchart illustrating the chip packaging method provided in this embodiment of the disclosure;

[0019] Figure 3 This is one of the structural schematic diagrams of the chip packaging method provided in the embodiments of this disclosure;

[0020] Figure 4 This is a second schematic diagram of the chip packaging method provided in the embodiments of this disclosure;

[0021] Figure 5 This is the third schematic diagram of the chip packaging method provided in the embodiments of this disclosure;

[0022] Figure 6 This is a second schematic diagram of the chip packaging structure provided in the embodiments of this disclosure;

[0023] Figure 7 This is one of the structural schematic diagrams of the heating and leveling device provided in the embodiments of this disclosure;

[0024] Figure 8 This is a second schematic diagram of the structure of the heating and leveling device provided in the embodiments of this disclosure;

[0025] Figure 9 This is one of the structural schematic diagrams of the chip packaging equipment provided in the embodiments of this disclosure;

[0026] Figure 10 This is a second schematic diagram of the structure of a chip packaging device provided in an embodiment of this disclosure. Detailed Implementation

[0027] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0028] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0029] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0030] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0031] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0033] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0034] Figure 1 This is an optional structural diagram of the chip packaging structure provided in the embodiments of this disclosure. Figure 1 The chip package structure 50 shown can be applied to memory chips, processor chips, in-memory computing chips, and various special-purpose chips. The chips in the chip package structure 50 include, but are not limited to, at least one of dynamic random access memory (DRAM), NAND flash memory, and control chips.

[0035] refer to Figure 1The chip packaging structure 50 includes multiple chip stack structures 20 and a substrate 10. The multiple chip stack structures 20 are attached to the top surface of the substrate 10 (the surface along the first direction X and the second direction Z). The multiple chip stack structures 20 can be attached to suitable positions on the top surface of the substrate 10 to meet packaging requirements. Each chip stack structure 20 includes multiple chips stacked along the third direction Z. Using a chip stack structure enables three-dimensional chip packaging, improving integration and performance.

[0036] In this embodiment of the disclosure, reference is made to Figure 1 The substrate 10 can be made of a metal lead frame, an organic material substrate, or a ceramic material substrate. The metal lead frame can be primarily made of copper or alloy materials, with a surface plating (such as silver or nickel), providing high mechanical strength. The organic material substrate can be made of BT resin or epoxy resin laminate, supporting high-density wiring. The ceramic material substrate can be made of alumina or aluminum nitride, possessing excellent thermal conductivity and high-temperature resistance.

[0037] Understandably, attaching the chip stack structure 20 to the substrate 10 provides mechanical support and fixation for the chip stack structure 20, ensuring the stability of the chip during subsequent processing and practical applications, and preventing displacement or damage to the chip due to vibration, impact, or thermal stress. Simultaneously, the chip's input / output pads can be interconnected with the circuitry on the substrate through bonding processes (such as wire bonding and flip-chip bonding), establishing an electrical connection channel that enables signal transmission and power distribution.

[0038] This disclosure provides a chip packaging method, such as... Figure 2 As shown, steps S101 to S103 are included. Each step will be explained in detail.

[0039] S101. A substrate is provided; a plurality of chip stack structures are bonded on the substrate; wherein the chip stack structures and the substrate, as well as adjacent chips, are bonded together with adhesive film.

[0040] In this embodiment of the disclosure, reference is made to Figure 3 The chip stack structure 21 and the substrate 10 can be bonded together using an adhesive film 31, and the chip stack structure 22 and the substrate 10 can be bonded together using an adhesive film 32. Simultaneously, in the chip stack structure 21, adjacent chips 211 can also be bonded together using the adhesive film 31, and in the chip stack structure 22, adjacent chips 221 can also be bonded together using the adhesive film 32. This achieves a fixing effect, securing the chip stack structures 21 and 22 to the substrate 10, and also fixing the individual chips within the chip stack structures 21 and 22.

[0041] In this embodiment of the disclosure, the adhesive film can be a DAF film (Die Attach Film). DAF film has excellent adhesion, isolation, thermal conductivity and corrosion resistance, thus providing good fixation for the chip stack structure, effectively insulating and isolating each chip, and providing good heat dissipation for each chip.

[0042] In some embodiments of this disclosure, a die attach apparatus can be used to attach multiple stacked chip structures onto a substrate. The die attach apparatus can perform die pick and die bond operations. Depending on the number of chips to be attached, the die attach apparatus may perform one or more die pick and die bond operations.

[0043] Specifically, chip mounting equipment uses a robotic arm to pick up chips with adhesive film attached to their backside and then attaches them to a target location on a substrate. This target location can be either the surface of the substrate or the surface of the chip. In other words, chip mounting equipment can attach chips to the surface of a substrate as the bottom chip in a chip stack structure; it can also attach chips to the surfaces of other chips to form a chip stack structure.

[0044] It should be noted that during the die bonding process, the die bonding equipment can heat the adhesive film to improve its adhesion; and after placing the chip in the target position, the die bonding equipment can press the chip together to make the chip bond more firmly.

[0045] However, due to the tolerances of chip thinning, the tolerances of the adhesive film, and the influence of the die-attachment process, height errors will occur between chip stack structures, resulting in unevenness and warping. The die-bonding process can only attach the chips to the target location to form a chip stack structure, but it cannot eliminate the height errors, unevenness, and warping of the chip stack structure.

[0046] Currently, the thickness tolerance of each chip is generally ±5um, and the film tolerance is generally ±2um. Therefore, for a 4-layer chip stack structure, the cumulative tolerance can reach 20um to 28um. Furthermore, the higher the number of layers in the chip stack structure (8 layers, 16 layers, or 32 layers), the greater the cumulative tolerance. This greatly reduces the process space in the Z direction in the packaging design.

[0047] refer to Figure 3There is a tolerance between the thickness of chip 211 in chip stack structure 21 and the thickness of chip 221 in chip stack structure 22, and there is a tolerance between the thickness of adhesive film 31 in chip stack structure 21 and the thickness of adhesive film 32 in chip stack structure 22. Furthermore, the chip mounting process can have different effects on the heights of chip stack structures 21 and 22. For example, during the die bonding process, the bonding degree between chip 211 in chip stack structure 21 and chip 221 in chip stack structure 22 may differ. Under the influence of one or more of the above factors, the heights of chip stack structures 21 and 22 deviate along the third direction Z; that is, the distance h1 from the top surface of chip stack structure 21 to the substrate 10 is different from the distance h2 from the top surface of chip stack structure 22 to the substrate 10.

[0048] S102. Heat the substrate to make the adhesive film reach a semi-molten state.

[0049] In this embodiment of the disclosure, reference is made to Figure 4 To address issues such as height errors, unevenness, and warping in chip stacking structures, the substrate 10 can be heated first using a heating plate 61, causing the adhesive films 31 and 32 to reach a semi-molten state. The adhesive films in the semi-molten state still possess adhesion and a certain degree of fluidity, thus allowing for some deformation.

[0050] In some embodiments of this disclosure, reference is made to Figure 4 The substrate 10 can be heated to a preset temperature, thereby bringing the adhesive film to a semi-molten state. The preset temperature is greater than or equal to 50°C and less than or equal to 100°C; for example, the preset temperature can be 50°C, 60°C, 70°C, 80°C, 90°C, or 100°C.

[0051] S103. Flatten the multiple chip stacked structures so that the distance from the top surface of the multiple chip stacked structures to the substrate is the same.

[0052] In this embodiment of the disclosure, reference is made to Figure 4 When the adhesive films 31 and 32 reach a semi-molten state, the pressing device 62 can be used to flatten the multiple chip stack structures (including chip stack structures 21 and 22) on the substrate 10. The pressing device 62 can apply pressure to the multiple chip stack structures (including chip stack structures 21 and 22) along the third direction Z to flatten the multiple chip stack structures.

[0053] In some embodiments of this disclosure, a preset pressure can be applied to a multi-chip stack structure within a preset time period for leveling. The preset time is greater than or equal to 1 second and less than or equal to 10 seconds; for example, the preset time can be 1 second, 2 seconds, 3 seconds, 4 seconds, 5 seconds, 6 seconds, 7 seconds, 8 seconds, 9 seconds, or 10 seconds. The preset pressure is greater than or equal to 3 N and less than or equal to 50 N; for example, the preset pressure can be 3 N, 5 N, 10 N, 15 N, 20 N, 30 N, 40 N, or 50 N.

[0054] In this embodiment of the disclosure, reference is made to Figure 5 After leveling, the height deviation between chip stack structures 21 and 22 along the third direction Z is eliminated. That is, the distance h1 from the top surface of chip stack structure 21 to the substrate 10 is the same as the distance h2 from the top surface of chip stack structure 22 to the substrate 10. At the same time, the adhesive film 32 in the originally taller chip stack structure 22 is compressed, so that the thickness d1 of the adhesive film 31 in chip stack structure 21 is greater than the thickness d2 of the adhesive film 32 in chip stack structure 22.

[0055] Understandably, to address issues such as height errors, unevenness, and warpage in chip stacking structures, the adhesive film is heated to a semi-molten state before being used to level multiple chip stacks. This ensures that the distance from the top surface of each chip stack to the substrate is the same, eliminating height deviations and addressing unevenness and warpage. This significantly improves the precision of the die-casting process and reduces cumulative height errors. Furthermore, it allows for a reduction in the height of the chip stack, increasing packaging density and providing more design flexibility. Finally, it enhances the bending strength (e.g., three-point bending resistance test results) and warpage resistance of the package structure.

[0056] In some embodiments of this disclosure, after the multiple chip stack structures are leveled, a curing oven can be used to cure the substrate and the multiple chip stack structures. The curing oven can heat the substrate and the multiple chip stack structures to a curing temperature (e.g., 150°C to 180°C) and hold it for a certain time (e.g., 1 hour to 2 hours) to complete the curing process. This curing process can improve mechanical strength, control stress and deformation, prevent aging failure, and enhance reliability.

[0057] This disclosure also provides a chip packaging structure, such as... Figure 6As shown, the chip packaging structure 50 includes a substrate 10 and multiple chip stack structures (including a first chip stack structure 21 and a second chip stack structure 22). The multiple chip stack structures are attached to the substrate 10. The top surfaces of the multiple chip stack structures are at the same distance from the substrate 10; that is, the distance h1 from the top surface of the first chip stack structure 21 to the substrate 10 is the same as the distance h2 from the top surface of the second chip stack structure 22 to the substrate 10.

[0058] In this embodiment of the disclosure, reference is made to Figure 6 The first chip stack structure 21 includes a plurality of chips 211 and an adhesive film 31. The adhesive film 31 is located between the chip stack structure 21 and the substrate 10, and the adhesive film 31 is also located between adjacent chips 211. Correspondingly, the second chip stack structure 22 includes a plurality of chips 221 and an adhesive film 32. The adhesive film 32 is located between the chip stack structure 22 and the substrate 10, and the adhesive film 32 is also located between adjacent chips 221.

[0059] In this embodiment of the disclosure, Figure 6 The multiple chip stack structures shown (including the first chip stack structure 21 and the second chip stack structure 22) are made by heating the substrate 10 to make the adhesive films 31 and 32 reach a semi-molten state, and by leveling the multiple chip stack structures so that the distance from the top surface of the multiple chip stack structures to the substrate 10 is the same (i.e., h1 equals h2).

[0060] In some embodiments of this disclosure, the substrate 10 can be heated to a preset temperature, thereby bringing the adhesive film to a semi-molten state. The preset temperature is greater than or equal to 50°C and less than or equal to 100°C; for example, the preset temperature can be 50°C, 60°C, 70°C, 80°C, 90°C, or 100°C.

[0061] In some embodiments of this disclosure, a preset pressure can be applied to a multi-chip stack structure within a preset time period for leveling. The preset time is greater than or equal to 1 second and less than or equal to 10 seconds; for example, the preset time can be 1 second, 2 seconds, 3 seconds, 4 seconds, 5 seconds, 6 seconds, 7 seconds, 8 seconds, 9 seconds, or 10 seconds. The preset pressure is greater than or equal to 3 N and less than or equal to 50 N; for example, the preset pressure can be 3 N, 5 N, 10 N, 15 N, 20 N, 30 N, 40 N, or 50 N.

[0062] In some embodiments of this disclosure, reference is made to Figure 6 The adhesive film 31 in the first chip stack structure 21 has a first thickness d1, and the adhesive film 32 in the second chip stack structure 22 has a second thickness d2. The first thickness d1 is greater than the second thickness d2.

[0063] In this embodiment of the disclosure, reference is made to Figure 6After leveling, the distance h1 from the top surface of the first chip stack 21 to the substrate 10 is the same as the distance h2 from the top surface of the second chip stack 22 to the substrate 10. At the same time, the adhesive film 32 in the originally taller second chip stack 22 is compressed, so that the first thickness d1 of the adhesive film 31 in the first chip stack 21 is greater than the second thickness d2 of the adhesive film 32 in the second chip stack 22.

[0064] Understandably, to address issues such as height errors, unevenness, and warpage in chip stacking structures, the adhesive film is heated to a semi-molten state before being used to level multiple chip stacks. This ensures that the distance from the top surface of each chip stack to the substrate is the same, eliminating height deviations and addressing unevenness and warpage. This significantly improves the precision of the die-casting process and reduces cumulative height errors. Furthermore, it allows for a reduction in the height of the chip stack, increasing packaging density and providing more design flexibility. Finally, it enhances the bending strength (e.g., three-point bending resistance test results) and warpage resistance of the package structure.

[0065] This disclosure also provides a heating and leveling device, such as... Figure 7 As shown, the heating and leveling device 60 includes a heating plate 61 and a pressing device 62.

[0066] refer to Figure 7 A heating plate 61 is configured to place the substrate 10 and heat the substrate 10, causing the adhesive films 31 and 32 to reach a semi-molten state. Multiple chip stack structures 21 and 22 are bonded to the substrate 10. The chip stack structure 21 and the substrate 10 are bonded together using the adhesive film 31, and the chip stack structure 22 and the substrate 10 are bonded together using the adhesive film 32. Furthermore, in the chip stack structure 21, adjacent chips 211 can also be bonded together using the adhesive film 31, and in the chip stack structure 22, adjacent chips 221 can also be bonded together using the adhesive film 32.

[0067] In some embodiments of this disclosure, the heating plate 61 is further configured to heat the substrate 10 to a preset temperature, thereby bringing the adhesive film to a semi-molten state. The preset temperature is greater than or equal to 50°C and less than or equal to 100°C; for example, the preset temperature can be 50°C, 60°C, 70°C, 80°C, 90°C, or 100°C.

[0068] refer to Figure 7 The slab clamping device 62 is configured to flatten the plurality of chip stack structures 21 and 22 so that the distance from the top surface of the plurality of chip stack structures 21 and 22 to the substrate 10 is the same.

[0069] In some embodiments of this disclosure, the pressing device 62 is further configured to apply a preset pressure to a plurality of chip stack structures within a preset time for leveling. The preset time is greater than or equal to 1 second and less than or equal to 10 seconds; for example, the preset time can be 1 second, 2 seconds, 3 seconds, 4 seconds, 5 seconds, 6 seconds, 7 seconds, 8 seconds, 9 seconds, or 10 seconds. The preset pressure is greater than or equal to 3 N and less than or equal to 50 N; for example, the preset pressure can be 3 N, 5 N, 10 N, 15 N, 20 N, 30 N, 40 N, or 50 N.

[0070] Understandably, to address issues such as height errors, unevenness, and warpage in chip stacking structures, the adhesive film is heated to a semi-molten state before being used to level multiple chip stacks. This ensures that the distance from the top surface of each chip stack to the substrate is the same, eliminating height deviations and addressing unevenness and warpage. This significantly improves the precision of the die-casting process and reduces cumulative height errors. Furthermore, it allows for a reduction in the height of the chip stack, increasing packaging density and providing more design flexibility. Finally, it enhances the bending strength (e.g., three-point bending resistance test results) and warpage resistance of the package structure.

[0071] In some embodiments of this disclosure, such as Figure 7 As shown, the pressing device 62 includes an integral pressing block. The coverage area of ​​the integral pressing block is greater than or equal to the area of ​​the substrate 10.

[0072] It is understandable that the coverage area of ​​the overall pressing block is greater than or equal to the area of ​​the substrate 10. The overall pressing block can cover the entire substrate 10. In this way, the overall pressing block can complete the flattening of all chip stacking structures on the substrate 10 in one go, thereby improving process efficiency.

[0073] In some embodiments of this disclosure, such as Figure 8 As shown, the pressing device 62 includes a pressing base 621 and a plurality of separate pressing blocks 622. The separate pressing blocks 622 and the pressing base 621 are elastically connected, for example, by a spring connection.

[0074] It is understandable that using the elastically connected split pressure block 622 to flatten the multiple chip stack structures 21 and 22 can provide more uniform pressure, thereby optimizing the mechanical compressive stress on the chip stack structures 21 and 22 and avoiding mechanical damage.

[0075] In this embodiment of the disclosure, reference is made to Figure 8The spacing of the split pressing blocks 622 is consistent with the spacing of the chip stacking structures 21 and 22 on the substrate 10. This ensures that the split pressing blocks 622 can accurately press the chip stacking structures 21 and 22.

[0076] Meanwhile, the coverage area of ​​each separate pressure block 322 is greater than or equal to the projected area of ​​the chip stack structure 21 or 22 on the substrate 10. This ensures that the top surface of the chip stack structure is subjected to mechanical compressive stress, ensuring uniform stress distribution, avoiding localized stress, and preventing mechanical damage.

[0077] This disclosure also provides a chip packaging device, such as... Figure 9 As shown, the chip packaging equipment 80 includes a heating and leveling device 60. The heating and leveling device 60 includes the technical features described in the above embodiments. That is, a separate machine can be set up to perform the heating and leveling process.

[0078] In some embodiments of this disclosure, such as Figure 10 As shown, the chip packaging apparatus 80 further includes a pick-up module 71 and a bonding module 72. The pick-up module 71 is configured to pick up a chip with an adhesive film attached to its back side; that is, the pick-up module 71 can perform a die-picking process. The bonding module 72 is configured to bond the chip to a target location on the substrate; that is, the bonding module 72 can perform a die-bonding process.

[0079] In other words, the heating and leveling device 60 can be integrated into the die attach equipment. This way, the chip picking, chip bonding, heating and leveling processes can be completed in one loading and unloading operation, which improves efficiency and reduces mechanical damage.

[0080] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0081] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A chip packaging method, characterized in that, include: Provide substrate; Multiple chip stack structures are bonded to the substrate; wherein, the chip stack structures and the substrate, as well as adjacent chips, are bonded together with adhesive film. The substrate is heated so that the adhesive film reaches a semi-molten state; The multiple chip stack structures are leveled so that the distance from the top surface of the multiple chip stack structures to the substrate is the same.

2. The chip packaging method according to claim 1, characterized in that, The heating of the substrate includes: The substrate is heated to a preset temperature; wherein the preset temperature is greater than or equal to 50°C and less than or equal to 100°C.

3. The chip packaging method according to claim 1, characterized in that, The flattening of the plurality of chip stack structures includes: Within a preset time period, a preset pressure is applied to the multiple chip stacked structures to perform leveling; wherein the preset time is greater than or equal to 1s and less than or equal to 10s; and the preset pressure is greater than or equal to 3N and less than or equal to 50N.

4. The chip packaging method according to claim 1, characterized in that, After leveling the multiple chip stack structures, the method further includes: The substrate and the plurality of chip stack structures are cured.

5. The chip packaging method according to claim 1, characterized in that, A method for attaching the plurality of stacked chip structures to the substrate includes: Pick up the chip; the adhesive film is attached to the back of the chip; The chip is attached to the target position on the substrate.

6. A chip packaging structure, characterized in that, include: Substrate and multiple chip stacking structure; The multiple chip stacked structure is attached to the substrate; The chip stacking structure includes: a plurality of chips and an adhesive film; the adhesive film is located between the chip stacking structure and the substrate; the adhesive film is also located between adjacent chips; The distance from the top surface of the plurality of stacked chips to the substrate is the same.

7. The chip packaging structure according to claim 6, characterized in that, The plurality of chip stacking structures include: a first chip stacking structure and a second chip stacking structure; The adhesive film in the first chip stack structure has a first thickness; the adhesive film in the second chip stack structure has a second thickness; the first thickness is greater than the second thickness.

8. A heating and leveling device, characterized in that, include: A heating plate is configured to place a substrate and heat the substrate so that the adhesive film reaches a semi-molten state. Multiple chip stack structures are bonded to the substrate; wherein the chip stack structures and the substrate, as well as adjacent chips, are bonded together with the adhesive film. A slab clamping device is configured to flatten the plurality of chip stacks so that the distance from the top surface of the plurality of chip stacks to the substrate is the same.

9. The heating and leveling device according to claim 8, characterized in that, The pressing device includes: an integral pressing block; The coverage area of ​​the integral pressing block is greater than or equal to the area of ​​the substrate.

10. The heating and leveling apparatus according to claim 8, characterized in that, The briquetting device includes: a briquetting base and multiple separate briquetting blocks; The split pressing block and the pressing block base are elastically connected; The spacing between the split pressing blocks is consistent with the spacing between the chip stacking structures on the substrate; the coverage area of ​​each split pressing block is greater than or equal to the projected area of ​​each chip stacking structure on the substrate.

11. A chip packaging device, characterized in that, include: The heating and leveling apparatus as described in any one of claims 6 to 8.

12. The chip packaging equipment according to claim 11, characterized in that, The chip packaging equipment also includes: A pickup module is configured to pick up a chip; the adhesive film is attached to the back of the chip; The bonding module is configured to bond the chip to a target location on the substrate.

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