Hydrofluorocarbons and their use in integrated circuit manufacturing processes

Abstract

Disclosed are mixtures configured to etch thin films of integrated circuit materials. The mixtures can include a first compound including one or more of: A, B, and C; and a second compound including one or more of: oxygen, argon, helium, nitrogen, octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), carbonyl fluoride (COF2), difluoromethane (CH2F2), trifluoromethane (CHF3), carbon tetrafluoride (CF4), methyl fluoride (CH3F), octafluorocyclopentene (C5F8), 2,3,3,3-tetrafluoroprop-1-ene (C3H2F4), 2,3,3,3-tetrafluoroprop-1-ene (C3H2F4), hexafluoropropene (C3F6), hexafluorocyclopropane (C3F6), or 1,1,3,3,3-pentafluoropropene (C3HF5). A, B, and C

Description

Cross-references to related applications

[0001] This application claims priority to U.S. Provisional Application No. 63 / 568,638, filed March 22, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure generally describes 1,2,2-trifluoro-2-(trifluoromethoxy)ethylene and its use in integrated circuit manufacturing processes, as well as analogues of 1,2,2-trifluoro-2-(trifluoromethoxy)ethylene and their use in integrated circuit manufacturing processes. Background Technology

[0003] The lateral two-dimensional geometry of integrated circuit devices continues to shrink in size, and consequently, the surface density of these devices continues to increase. With this increased density, the likelihood of electrical interference (including crosstalk and parasitic capacitance) between adjacent devices increases, leading to a degraded overall integrated circuit performance. To mitigate this potential for electrical interference, films of low-dielectric-constant (“low-k”) insulating materials are typically placed in gaps, trenches, vias, and other surface features between adjacent devices.

[0004] However, placing low-k insulating materials in the gaps, trenches, and vias of laterally arranged integrated circuit devices also has its limitations. More specifically, the ability of such low-k insulating materials to eliminate or reduce the aforementioned electrical interference may decrease as the distance between adjacent devices decreases, and therefore the thickness of the low-k insulating material film between adjacent devices also decreases. Therefore, manufacturers have begun to focus on forming integrated circuit devices not only laterally in two dimensions, but also "vertically" in three dimensions.

[0005] As circuits are increasingly oriented vertically, the number of alternating thin films in integrated circuit materials has increased. For example, three-dimensional NOT AND (“3D NAND”) flash memory devices have moved from 24-layer “stacks” of alternating thin films in integrated circuit materials to 32-layer stacks, and even to 48-layer stacks of such alternating thin films. Recently, work has begun to focus on forming 96-layer and 128-layer stacks of 3D NAND flash memory devices that incorporate these alternating thin film integrated circuit materials.

[0006] To retain the advantages of moving to a three-dimensional vertical layout of circuits, integrated circuit manufacturers require new processes and corresponding materials. One such process and set of materials that integrated circuit manufacturers are examining involves forming “channels” in 3D NAND flash memory devices. According to the art, a channel is more or less a cylindrical conduit that extends between the bottommost surface of the bottom layer of alternating thin films of integrated circuit material in the aforementioned 3D NAND stack and the outermost surface of the topmost layer of the same stack of alternating thin film integrated circuit material. Because it is more or less cylindrical, the channel also has a diameter.

[0007] As the number of layers in 3D NAND flash memory devices increases, the aspect ratio of the channels also increases. With this increased aspect ratio, manufacturers often experience more defects during channel formation, including "incomplete etching," "bending," and "twisting." Incomplete etching occurs when such conduits cannot fully extend between the bottommost surface of the alternating thin films of the integrated circuit material and the outermost surface of the topmost layer of the same stack of alternating thin films of the integrated circuit material. Bending occurs when the diameter of the conduit is larger than the preferred diameter at some point along the channel because etching occurs more laterally than longitudinally at that point. Twisting defects occur when the channel maintains the preferred diameter but extends more laterally than longitudinally along its preferred predetermined path. These defects must be avoided when etching channels in 3D flash memory devices.

[0008] In addition to these issues, 3D NAND flash memory manufacturers are also focusing on etched compounds with lower global warming potential than those with higher fluorination. For example, octafluorocyclobutane is a perfluorinated carbon compound, a greenhouse gas, and has a global warming potential approximately 3,200 times higher than carbon dioxide.

[0009] Octafluorocyclobutane is also a hydrofluorocarbon compound that can be used to etch the aforementioned channels. Therefore, integrated circuit manufacturers are looking for alternative hydrofluorocarbon compounds and mixtures that have a lower global warming potential than perfluorocarbons and also help minimize the aforementioned incomplete etching, bending, and twisting defects during channel etching in 3D NAND flash memory devices.

[0010] This disclosure aims to overcome one or more of the above-mentioned problems, and / or other problems related to the prior art. Summary of the Invention

[0011] According to a first aspect of this application, a mixture configured for etching a thin film of an integrated circuit material is disclosed. The mixture may comprise: The first compound comprises one or more of the following: A B and C ;and The second compound comprises one or more of the following: oxygen, argon, helium, nitrogen, octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), carbonyl fluoride (COF2), difluoromethane (CH2F2), trifluoromethane (CHF3), carbon tetrafluoride (CF4), methyl fluoride (CH3F), octafluorocyclopentene (C5F8), 2,3,3,3-tetrafluoroprop-1-ene (C3H2F4), 2,3,3,3-tetrafluoroprop-1-ene (C3H2F4, 1234ze), hexafluoropropene (C3F6), hexafluorocyclopropane (C3F6), or 1,1,3,3,3-pentafluoropropene (C3HF5).

[0012] According to a second aspect of this disclosure, a method for etching a thin film of an integrated circuit material is disclosed. The method may include the step of contacting the surface of the thin film of the integrated circuit material with a plasma containing reactive ions generated by subjecting a mixture configured to etch the thin film of the integrated circuit material to a plasma generating apparatus, thereby removing a portion of the thin film of the integrated circuit material. The mixture may contain: The first compound comprises one or more of the following: A B and C ;and The second compound comprises one or more of the following: oxygen, argon, helium, nitrogen, octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), carbonyl fluoride (COF2), difluoromethane (CH2F2), trifluoromethane (CHF3), carbon tetrafluoride (CF4), methyl fluoride (CH3F), octafluorocyclopentene (C5F8), 2,3,3,3-tetrafluoroprop-1-ene (C3H2F4), hexafluoropropene (C3F6), hexafluorocyclopropane (C3F6), or 1,1,3,3,3-pentafluoropropene (C3HF5).

[0013] Finally, according to a third aspect of this disclosure, a method for patterning a thin film of an integrated circuit material is disclosed. The method may include the steps of: contacting the surface of the thin film with a plasma containing reactive ions generated by subjecting a mixture configured to etch the thin film of the integrated circuit material to a plasma generating apparatus, thereby removing a portion of the thin film and generating a pattern in the thin film of the integrated circuit material. In this method, at least a portion of the thin film is disposed between opposing surfaces of a substrate and a mask material layer, wherein the mask material layer includes pores defined therein, thereby exposing a portion of the thin film surface. In this method, the mixture may comprise a first compound comprising one or more of the following: A B and C ;and The second compound comprises one or more of the following: oxygen, argon, helium, nitrogen, octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), carbonyl fluoride (COF2), difluoromethane (CH2F2), trifluoromethane (CHF3), carbon tetrafluoride (CF4), octafluorocyclopentene (C5F8), 2,3,3,3-tetrafluoroprop-1-ene (C3H2F4), hexafluoropropylene (C3F6), hexafluorocyclopropane (C3F6), or 1,1,3,3,3-pentafluoropropylene (C3HF5), nitrogen trifluoride (NF3), and sulfur hexafluoride (SF6). Attached Figure Description

[0014] Figure 1 This is a side view of a multilayer stack of alternating thin films of integrated circuit materials in a 3D NAND flash memory device, which depicts: (1) defect-free channels etched through the stack; (2) examples of bends and twists in channels extending through the stack; and (3) examples of incomplete etches that failed to extend through the stack.

[0015] Figure 2 This is a flowchart depicting a method configured to etch thin films of integrated circuit materials using the compounds and mixtures disclosed herein.

[0016] Figure 3 It can be used Figure 2 The cross-sectional view of a wafer in a method for etching a thin film of integrated circuit material, as depicted in the figure.

[0017] Figure 4 This is a flowchart depicting a method for configuring thin films of integrated circuit materials using the compounds and mixtures disclosed herein.

[0018] Figure 5A Before patterning occurred Figure 4 The cross-sectional view of a wafer in a method for etching thin films of integrated circuit materials, as depicted in the figure.

[0019] Figure 5B During patterning processing Figure 4 The cross-sectional view of a wafer in a method for etching thin films of integrated circuit materials, as depicted in the figure.

[0020] Figure 5C yes Figure 4 The cross-sectional view of a wafer in a method for etching thin films of integrated circuit materials, as depicted in the paper, illustrates the pattern generated in the thin film of the integrated circuit material.

[0021] Figure 6A -D is a cross-sectional SEM image comparing trenches etched using a mixture of octafluorocyclobutane (C4F8) with trenches etched using a mixture containing compound A disclosed herein, under three different process conditions.

[0022] Figure 7A -D is a cross-sectional SEM image comparing trenches etched using a mixture of octafluorocyclobutane (C4F8) with trenches etched using a mixture containing compound B disclosed herein, under three different process conditions.

[0023] Figure 8A -D is a cross-sectional SEM image comparing trenches etched using a mixture of octafluorocyclobutane (C4F8) with trenches etched using a mixture containing compound C disclosed herein, under three different process conditions. Detailed Implementation

[0024] Example embodiments will be described more fully with reference to the accompanying drawings. Example embodiments are provided so that this disclosure is thorough and fully communicates the scope to those skilled in the art. Numerous specific details, such as examples of specific compositions, components, devices, and methods, are set forth to provide a thorough understanding of embodiments of this disclosure. It will be apparent to those skilled in the art that specific details are not required, example embodiments may be embodied in many different forms, and should not be construed as limiting the scope of this disclosure. In some example embodiments, well-known processes, well-known equipment structures, and well-known techniques are not described in detail.

[0025] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” may also be intended to include the plural forms unless the context clearly indicates otherwise. The terms “comprising,” “including,” “comprising,” and “having” are inclusive and therefore specify the presence of the mentioned features, elements, compositions, steps, integers, operations, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Although the open-ended term “comprising” should be understood as a non-limiting term used to describe and claim the various embodiments shown herein, in some respects it may be understood alternatively as a more restrictive and binding term, such as “consisting of” or “substantially consisting of.” Therefore, for any given embodiment describing compositions, materials, components, elements, features, integers, operations, and / or process steps, this disclosure also specifically includes embodiments that consist of or substantially consist of such described compositions, materials, components, elements, features, integers, operations, and / or process steps. In the case of “consisting of…”, the alternative implementation excludes any additional composition, material, component, element, feature, integer, operation and / or process step. In the case of “consisting substantially of…”, any additional composition, material, component, element, feature, integer, operation and / or process step that substantially affects the basic and new characteristics is excluded from such implementation. However, any composition, material, component, element, feature, integer, operation and / or process step that does not substantially affect the basic and new characteristics may be included in the implementation.

[0026] Any methods, steps, procedures, and operations described herein should not be construed as requiring them to be performed in the specific order discussed or shown, unless specifically identified as such. It should also be understood that additional or alternative steps may be employed unless otherwise stated.

[0027] When a component, element, or layer is referred to as being “on,” “joined to,” “connected to,” or “coupled to” another component or layer, it may be directly on, joined to, connected to, or coupled to another component, element, or layer, or there may be intermediate components or layers present. Conversely, when an element is referred to as being “directly on,” “directly joined to,” “directly connected to,” or “directly coupled to” another component or layer, there may be no intermediate components or layers present. Other terms used to describe relationships between elements should be interpreted in a similar manner (e.g., “between” vs. “directly between,” “adjacent” vs. “directly adjacent,” etc.). As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0028] Although the terms first, second, third, etc., may be used herein to describe various steps, elements, components, regions, layers, and / or portions, these steps, elements, components, regions, layers, and / or portions should not be limited by these terms unless otherwise stated. These terms may be used only to distinguish one step, element, component, region, layer, or portion from another. Terms such as “first,” “second,” and other numerical items, when used herein, do not imply sequence or order unless the context clearly indicates otherwise. Therefore, without departing from the teachings of the exemplary embodiments, the first step, element, component, region, layer, or portion discussed below may be referred to as the second step, element, component, region, layer, or portion.

[0029] Spatial or temporal relative terms, such as “before,” “after,” “inside,” “outside,” “below,” “under,” “lower,” “above,” “upper,” etc., may be used herein for ease of description to depict the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, spatial or temporal relative terms may be intended to cover different orientations of a device or system in use or operation.

[0030] Throughout this disclosure, numerical values ​​represent approximate measurements or limitations of a range to cover minor deviations from a given value and implementations having approximately the mentioned value as well as implementations having exactly the mentioned value. Except for the working examples provided at the end of the detailed specification, all numerical values ​​of parameters (e.g., quantities or conditions) in this specification (including the appended claims) should be understood to be modified in all cases by the term “about,” regardless of whether “about” actually appears before the numerical value. “About” indicates that the numerical value allows for some slight imprecision (having some degree close to precision in the value; approximating or reasonably close to the value; close). If the imprecision provided by “about” is not otherwise understood in this ordinary sense in the art, then “about” as used herein at least indicates a variation that may be caused by common methods of measuring and using these parameters. For example, “about” can include variations of less than or equal to 5%, optionally less than or equal to 4%, optionally less than or equal to 3%, optionally less than or equal to 2%, optionally less than or equal to 1%, optionally less than or equal to 0.5%, and in some respects, optionally less than or equal to 0.1%.

[0031] Furthermore, the disclosure of a range includes the disclosure of all values ​​throughout the range and the disclosure of further subdivisions of the range, including the endpoints and subranges given for the range. Therefore, unless otherwise stated, a range includes endpoints and includes the disclosure of all distinct values ​​throughout the range and the disclosure of further subdivisions of the range. The disclosure of values ​​and ranges of values ​​for a specific parameter (such as temperature, molecular weight, weight percentage, etc.) does not exclude other values ​​and ranges of values ​​that may be used herein. It is conceivable that specific exemplary values ​​of two or more given parameters may define endpoints that can be claimed for the range of values ​​used for that parameter. For example, if parameter X is exemplified herein as having a value A and also exemplified as having a value Z, then parameter X is conceivable to have a range of values ​​from about A to about Z. Similarly, the disclosure of two or more ranges of values ​​for a parameter (whether these ranges are nested, overlapping, or distinct) covers all possible combinations of ranges of values ​​that may be claimed using the endpoints of the disclosed range. For example, if parameter X is exemplified in this document as having a value in the range of 1-10, 2-9, or 3-8, it is also conceivable that parameter X could have other ranges of values ​​including 1-9, 1-8, 1-3, 1-2, 2-10, 2-8, 2-3, 3-10, and 3-9.

[0032] As used herein, the terms “composition” and “material” are used interchangeably to broadly refer to a substance that contains at least preferred chemical components, elements or compounds, but may also contain other elements, compounds or substances, including trace impurities, unless otherwise stated.

[0033] Various aspects of this disclosure will now be described with reference to the accompanying drawings and tables (if applicable), whereby the same reference numerals denote the same elements unless otherwise stated. As mentioned above, in order to maintain the advantages of advancing to three-dimensional vertical layout circuits, integrated circuit manufacturers require new processes and corresponding materials. One such process, as summarized, involves forming channels during the creation of 3D flash memory devices, which minimizes defect formation such as incomplete etching, bending, and twisting. Now turning to Figure 1 The figure depicts a side view of a multilayer stack 10 of alternating thin films of integrated circuit material 12 used in a 3D flash memory device. As shown, a channel 14 can extend between the bottom surface 16 of the bottom layer 18 of the alternating thin films of integrated circuit material 12 in the multilayer stack 10 and the outermost surface 20 of the top layer 22 of the alternating thin films of integrated circuit material 12 in the multilayer stack 10. Without limitation, such alternating thin films of integrated circuit material 12 in the stack 10 are often composed of a silicon nitride (i.e., Si3N4) layer and a subsequent silicon dioxide (i.e., SiO2) layer.

[0034] As in Figure 1 As further shown, defects can occur during the formation of channel 14 in a 3D flash memory device. One such defect is incomplete etching defect 24. More specifically, and as described above, incomplete etching defect 24 occurs when channel 14 fails to extend between the bottom surface 16 of the bottom layer 18 of the alternating thin films of integrated circuit material 12 in the multilayer stack 10 and the relatively top surface 20 of the top layer 22 of the alternating thin films of integrated circuit material 12 in the multilayer stack 10. Another defect that integrated circuit manufacturers may experience during the formation of channel 14 in a 3D flash memory device includes bending defect 26.

[0035] like Figure 1 As shown, a bending defect 26 occurs when the diameter of channel 14 is greater than a preferred predetermined diameter at a point along the channel 14 extending between the bottom surface 16 of the bottom layer 18 of the alternating thin films of integrated circuit material 12 in the multilayer stack 10 and the relative outermost surface 20 of the top layer 22 of the alternating thin films of integrated circuit material 12 in the multilayer stack 10. The thickness of each layer of the alternating thin films of integrated circuit material 12 in the multilayer stack 10 can be as small as one nanometer, and the thickness may be two micrometers, three micrometers, four micrometers, five micrometers or more.

[0036] Finally, another defect that may occur in the formation of channel 14 in a 3D flash memory device is the twisting defect 28. For example... Figure 1As seen in the diagram, a twisting defect 28 occurs when the channel 14 maintains the preferred diameter, but at least some portions of the channel 14 extend more laterally than vertically relative to the preferred path 30. Also as mentioned above, the manufacturer simultaneously seeks to use hydrofluorocarbons with a lower global warming potential than more conventionally used perfluorocarbons (such as octafluorocyclobutane) in the etching process of such channels 14.

[0037] In a first aspect of the invention disclosed herein, novel and non-obvious mixtures configured to have a low global warming potential are provided, which can be used to etch thin films, such as thin films of integrated circuit material 12 in a multilayer stack 10. More specifically, such mixtures may comprise at least one first compound, which includes compounds structurally corresponding to the following: A ; B ;and C .

[0038] In addition to compounds A, B, and C listed above, this mixture configured for etching thin films of integrated circuit materials contains at least one second compound. More specifically, this mixture contains at least one second compound, which includes oxygen (O2), argon (Ar), octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), carbonyl fluoride (COF2), difluoromethane (CH2F2), trifluoromethane (CHF3), carbon tetrafluoride (CF4), octafluorocyclopentene (C5F8), 2,3,3,3-tetrafluoroprop-1-ene (C3H2F4), hexafluoropropylene (C3F6), hexafluorocyclopropane (C3F6), 1,1,3,3,3-pentafluoropropylene (C3HF5), sulfur hexafluoride (SF6), and nitrogen trifluoride (NF3). Like the first compounds described above, these second compounds can also be used as materials that facilitate etching thin films as described herein.

[0039] In addition to the first and second compounds described above, such mixtures typically contain at least one third compound comprising oxygen, argon, helium, xenon, krypton, and nitrogen. Oxygen is typically used as a material to limit the reactive ionic recombination of the first and second polymers described and depicted above at a point along the channel 14 of the alternating thin films of the integrated circuit material 12 in the multilayer stack 10, resulting in the formation of fluoropolymers. This accumulation of fluoropolymers at the bottom of the channel 14 may contribute to the aforementioned incomplete etching defects. Alternatively, this accumulation of fluoropolymers at different points along the channel 14 may also contribute to the formation of bending defects 26 and twisting defects 28.

[0040] As previously mentioned, the at least one third compound may also be selected from argon, helium, xenon, krypton, and nitrogen. Such compounds typically serve as carrier gases for etching processes and, more importantly, help transfer energy to the aforementioned first and second compounds and ionize them.

[0041] In a preferred embodiment of this aspect of the disclosure, the at least one first compound comprises more than or equal to about 1% by volume and less than or equal to about 99% by volume of the mixture. In a more preferred embodiment, the at least one first compound comprises more than or equal to about 10% by volume of the mixture and less than or equal to about 90% by volume of the mixture. In a further preferred embodiment, the at least one first compound comprises more than or equal to about 10% by volume of the mixture and less than or equal to about 80% by volume of the mixture. In a further preferred embodiment, the at least one first compound comprises more than or equal to about 10% by volume of the mixture and less than or equal to about 70% by volume of the mixture. In another preferred embodiment, the at least one first compound comprises more than or equal to about 10% by volume of the mixture and less than or equal to about 60% by volume of the mixture. In yet another preferred embodiment, the at least one first compound comprises more than or equal to about 10% by volume of the mixture and less than or equal to about 50% by volume of the mixture.

[0042] The at least one second compound and the at least one third compound constitute the balance of the aforementioned volume percentage. More specifically, when the at least one first compound is in the range of 1% to 99% of the mixture volume, the at least one second compound, alone or together with the at least one third compound, is in the range of 99% to 1% of the mixture volume. When the at least one first compound accounts for more than or equal to about 10% by volume and less than or equal to about 80% by volume of the mixture, the at least one second compound, alone or together with the at least one third compound, ranges from 90% to 20% by volume of the mixture. In another example, when the at least one first compound accounts for more than or equal to about 10% by volume and less than or equal to about 50% by volume of the mixture, the at least one second compound, alone or together with the at least one third compound, ranges from 90% to 50% by volume of the mixture. Typically, the ratio of the first compound to the second compound in the mixture is between 5:1 and 1:5.

[0043] As previously stated, the mixture described in the first aspect of this disclosure is configured to etch thin films of integrated circuit materials. In many cases, such thin films of integrated circuit materials comprise silicon, silicon oxide, silicon dioxide, silicon carbide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon carbonoxylate, silicon carbonitride, or combinations thereof, where appropriate. However, the mixture described in the first aspect of this disclosure can also be used to etch other thin film materials, including, but not limited to, gallium nitride, aluminum gallium nitride, gallium arsenide, aluminum gallium arsenide, indium phosphide, indium aluminum arsenide, indium gallium arsenide, silicon germanium, silicon bromide, zinc selenide, indium tin oxide, lead zirconium titanate, molybdenum, polycrystalline silicon, photoresist, carbon hard masks, and combinations thereof.

[0044] In practice, the compounds and mixtures described above have been found to be useful in many integrated circuit manufacturing processes, including but not limited to etching thin films in plasma-enhanced etching processes, for example, in... Figure 1 The thin film of integrated circuit material 12 in the multilayer stack 10 depicted herein. Therefore, in the second aspect of this disclosure, and as... Figure 2 The diagram illustrates a flowchart depicting a method configured to etch thin films of integrated circuit materials using the compounds and mixtures disclosed herein. As seen in step 110, a wafer comprising the thin film of integrated circuit material disposed thereon can be positioned within the reaction chamber of a plasma-enhanced etching apparatus.

[0045] Now go to Figure 3 A cross-sectional schematic diagram of an exemplary wafer 210 that can be used in step 110 is disclosed, and Figure 2 Any remaining steps of the process described herein. As seen herein, a wafer may consist of a substrate 212 having a thin film of integrated circuit material 214 disposed thereon. Substrate 212 comprises one of silicon (e.g., monocrystalline silicon) or polycrystalline silicon. In many cases, the thin film of integrated circuit material 214 comprises silicon oxide, silicon dioxide, silicon carbide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon carbonoxy, silicon carbonitride, and combinations thereof where appropriate. In most cases, the thin film 214 of integrated circuit material may be either silicon dioxide or silicon nitride.

[0046] Alternatively or optionally, the thin film 214 of the integrated circuit material disposed on the wafer 210 may also comprise gallium nitride, aluminum gallium nitride, gallium arsenide, aluminum gallium arsenide, indium phosphide, indium aluminum arsenide, indium gallium arsenide, silicon germanium, silicon bromide, zinc selenide, indium tin oxide, lead zirconium titanate, molybdenum, polysilicon, photoresist, carbon hard mask, and combinations thereof. Additionally, the thin film 214 of the integrated circuit material includes a surface 216 that can be contacted by a plasma containing reactive ions configured to etch the thin film 214 of the integrated circuit material. Although Figure 3As not shown herein, the wafer is intended to include thin films of more than one integrated circuit material, such as alternating thin films of the same and / or different materials disposed on a substrate as described herein.

[0047] Now back Figure 2 And at the same time, it also reviewed Figure 3 In step 112, the mixture configured to etch the thin film 214 of the integrated circuit material can flow into the plasma-enhanced etching chamber. This mixture may contain at least one first compound, which includes compounds structurally corresponding to the following: A ; B ;and C .

[0048] In addition to compounds A, B, and C listed above, this mixture configured for etching thin films of integrated circuit materials also contains at least one second compound. More specifically, this mixture contains at least one second compound, which includes oxygen (O2), argon (Ar), octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), carbonyl fluoride (COF2), difluoromethane (CH2F2), trifluoromethane (CHF3), carbon tetrafluoride (CF4), octafluorocyclopentene (C5F8), 2,3,3,3-tetrafluoroprop-1-ene (C3H2F4), hexafluoropropylene (C3F6), hexafluorocyclopropane (C3F6), 1,1,3,3,3-pentafluoropropylene (C3HF5), sulfur hexafluoride (SF6), and nitrogen trifluoride (NF3). Like the first compounds described above, these second compounds can also be used as materials that facilitate etching thin films as described herein.

[0049] In addition to the first and second compounds described above, such mixtures typically contain at least one third compound comprising oxygen, argon, helium, xenon, krypton, and nitrogen. Oxygen is typically used as a material to limit the reactive ionic recombination of the first and second polymers described and depicted above at a point along the channel 14 of the alternating thin films of the integrated circuit material 12 in the multilayer stack 10, resulting in the formation of fluoropolymers. This accumulation of fluoropolymers at the bottom of the channel 14 may contribute to the aforementioned incomplete etching defects. Alternatively, this accumulation of fluoropolymers at different points along the channel 14 may also contribute to the formation of bending defects 26 and twisting defects 28.

[0050] As previously mentioned, the at least one third compound may also be selected from argon, helium, xenon, krypton, and nitrogen. Such compounds typically serve as carrier gases for etching processes and, more importantly, help transfer energy to the aforementioned first and second compounds and ionize them.

[0051] In a preferred embodiment of this aspect of the present disclosure, the at least one first compound comprises greater than or equal to about 1% by volume and less than or equal to about 99% by volume of the mixture. In a more preferred embodiment, the at least one first compound comprises greater than or equal to about 10% by volume of the mixture and less than or equal to about 90% by volume of the mixture. In a further preferred embodiment, the at least one first compound comprises greater than or equal to about 10% by volume of the mixture and less than or equal to about 80% by volume of the mixture. In a further preferred embodiment, the at least one first compound comprises greater than or equal to about 10% by volume of the mixture and less than or equal to about 70% by volume of the mixture. In another preferred embodiment, the at least one first compound comprises greater than or equal to about 10% by volume of the mixture and less than or equal to about 60% by volume of the mixture. In yet another preferred embodiment, the at least one first compound comprises greater than or equal to about 10% by volume of the mixture and less than or equal to about 50% by volume of the mixture.

[0052] The at least one second compound and the at least one third compound constitute the balance of the aforementioned volume percentage. More specifically, when the at least one first compound is in the range of 1% to 99% of the mixture volume, the at least one second compound, alone or together with the at least one third compound, is in the range of 99% to 1% of the mixture volume. When the at least one first compound accounts for more than or equal to about 10% by volume and less than or equal to about 80% by volume of the mixture, the at least one second compound, alone or together with the at least one third compound, ranges from 90% to 20% by volume of the mixture. In another example, when the at least one first compound accounts for more than or equal to about 10% by volume and less than or equal to about 50% by volume of the mixture, the at least one second compound, alone or together with the at least one third compound, ranges from 90% to 50% by volume of the mixture. Typically, the ratio of the first compound to the second compound in the mixture is between 5:1 and 1:5.

[0053] As previously stated, the mixture described in the first aspect of this disclosure is configured to etch thin films of integrated circuit materials. In many cases, such thin films of integrated circuit materials comprise silicon, silicon oxide, silicon dioxide, silicon carbide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon carbonoxylate, silicon carbonitride, or combinations thereof, where appropriate. However, the mixture described in the first aspect of this disclosure can also be used to etch other thin film materials, including, but not limited to, gallium nitride, aluminum gallium nitride, gallium arsenide, aluminum gallium arsenide, indium phosphide, indium aluminum arsenide, indium gallium arsenide, silicon germanium, silicon bromide, zinc selenide, indium tin oxide, lead zirconium titanate, molybdenum, polycrystalline silicon, photoresist, carbon hard masks, and combinations thereof.

[0054] In review Figure 2 At the same time, refer to Figure 3 In step 114, a plasma generation device electronically coupled to the reaction chamber of the plasma-enhanced etching apparatus can be activated to generate a plasma containing a mixture of reactive ions of a thin film 214 configured to etch the interior of the reaction chamber of the plasma-enhanced etching apparatus. Figure 2 In step 116 described in the text, Figure 3 The surface 216 can be contacted by plasma containing a mixture of reactive ions configured to etch the thin film 214 on the wafer 210, thereby removing a portion of the thin film 214 disposed on the wafer 210.

[0055] According to a third aspect of the invention disclosed herein, a method for patterning thin films of integrated circuit materials is disclosed. Now turning to... Figure 4 At the same time, it also reviewed Figures 5A-5C In step 310, the wafer 410 can be positioned inside the reaction chamber of the plasma-enhanced etching apparatus. For example... Figures 5A to 5C As shown in each of them, the wafer 410 may consist of a substrate 420 having a thin film 430 of integrated circuit material disposed thereon between the opposing surfaces 440 of the substrate 420 and the mask material layer 450.

[0056] Substrate 420 comprises silicon (e.g., monocrystalline silicon) or polycrystalline silicon. In many cases, the thin film 430 of the integrated circuit material comprises silicon oxide, silicon dioxide, silicon carbide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon carbonoxy, silicon carbonitride, and, where appropriate, combinations thereof. In most cases, the thin film 430 of the integrated circuit material can be either silicon dioxide or silicon nitride.

[0057] Alternatively or additionally, the thin film 430 of the integrated circuit material disposed between the opposing surfaces 440 comprises gallium nitride, aluminum gallium nitride, gallium arsenide, aluminum gallium arsenide, indium phosphide, indium aluminum arsenide, indium gallium arsenide, silicon germanium, silicon bromide, zinc selenide, indium tin oxide, lead zirconium titanate, molybdenum, polysilicon, and combinations thereof. Furthermore, the mask material layer 450 may comprise a carbon hard mask, a photoresist, a metal mask, and combinations thereof. Finally, and as... Figure 5A As seen in the image, the mask material layer 450 includes one or more apertures 460 that are at least partially defined therethrough. In another case, one or more apertures 460 may be defined entirely through the mask material layer 450. As will be understood by those skilled in the art, the apertures 460 define a pattern in the thin film 430 of the etched integrated circuit material.

[0058] Back Figure 4 And at the same time, still review Figure 5A and Figure 5BIn step 312, the mixture configured to etch the thin film 430 of the integrated circuit material can flow into the plasma-enhanced etching chamber. This mixture may contain at least one first compound, which includes compounds structurally corresponding to the following: A ; B ;and C .

[0059] In addition to compounds A, B, and C listed above, this mixture configured for etching thin films of integrated circuit materials also contains at least one second compound. More specifically, this mixture contains at least one second compound, which includes oxygen (O2), argon (Ar), octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), carbonyl fluoride (COF2), difluoromethane (CH2F2), trifluoromethane (CHF3), carbon tetrafluoride (CF4), octafluorocyclopentene (C5F8), 2,3,3,3-tetrafluoroprop-1-ene (C3H2F4), hexafluoropropylene (C3F6), hexafluorocyclopropane (C3F6), 1,1,3,3,3-pentafluoropropylene (C3HF5), sulfur hexafluoride (SF6), and nitrogen trifluoride (NF3). Like the first compounds described above, these second compounds can also be used as materials that facilitate etching thin films as described herein.

[0060] In addition to the first and second compounds described above, such mixtures typically contain at least one third compound comprising oxygen, argon, helium, xenon, krypton, and nitrogen. Oxygen is typically used as a material to limit the formation of fluoropolymers when the reactive ionic recombination of the first and second polymers described and depicted above occurs at a point along the alternating thin films of the integrated circuit material 12 in the multilayer stack 10. This accumulation of fluoropolymers at the bottom of the channel 14 may contribute to the aforementioned incomplete etching defects. Alternatively, this accumulation of fluoropolymers at different points along the channel 14 may also contribute to the formation of bending defects 26 and twisting defects 28.

[0061] As previously mentioned, at least one third compound may also be selected from argon, helium, xenon, krypton, and nitrogen. Such compounds typically serve as carrier gases for etching processes and, more importantly, help transfer energy to the aforementioned first and second compounds and ionize them.

[0062] In a preferred embodiment of this aspect of the disclosure, at least one first compound comprises more than or equal to about 1% by volume and less than or equal to about 99% by volume of the mixture. In a more preferred embodiment, at least one first compound comprises more than or equal to about 10% by volume of the mixture and less than or equal to about 90% by volume of the mixture. In a further preferred embodiment, at least one first compound comprises more than or equal to about 10% by volume of the mixture and less than or equal to about 80% by volume of the mixture. In a further preferred embodiment, at least one first compound comprises more than or equal to about 10% by volume of the mixture and less than or equal to about 70% by volume of the mixture. In another preferred embodiment, at least one first compound comprises more than or equal to about 10% by volume of the mixture and less than or equal to about 60% by volume of the mixture. In yet another preferred embodiment, at least one first compound comprises more than or equal to about 10% by volume of the mixture and less than or equal to about 50% by volume of the mixture.

[0063] At least one second compound and at least one third compound constitute the balance of the aforementioned volume percentage. More specifically, when at least one first compound is in the range of 1% to 99% of the mixture volume, then at least one second compound, alone or together with at least one third compound, is in the range of 99% to 1% of the mixture volume. When at least one first compound constitutes a portion of the mixture greater than or equal to about 10% by volume and less than or equal to about 80% by volume, then at least one second compound, alone or together with at least one third compound, constitutes a portion of the mixture from 90% to 20% by volume. In another example, when at least one first compound constitutes a portion of the mixture greater than or equal to about 10% by volume and less than or equal to about 50% by volume, then at least one second compound, alone or together with at least one third compound, constitutes a portion of the mixture from 90% to 50% by volume. Typically, the ratio of the first compound to the second compound in such a mixture is between 5:1 and 1:5.

[0064] As previously stated, the mixture described in the first aspect of this disclosure is configured to etch thin films of integrated circuit materials. In many cases, such thin films of integrated circuit materials comprise silicon, silicon oxide, silicon dioxide, silicon carbide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon carbonoxylate, silicon carbonitride, or combinations thereof, where appropriate. However, the mixture described in the first aspect of this disclosure can also be used to etch other thin film materials, including, but not limited to, gallium nitride, aluminum gallium nitride, gallium arsenide, aluminum gallium arsenide, indium phosphide, indium aluminum arsenide, indium gallium arsenide, silicon germanium, silicon bromide, zinc selenide, indium tin oxide, lead zirconium titanate, molybdenum, polycrystalline silicon, photoresist, carbon hard masks, and combinations thereof.

[0065] Next, in step 314, a plasma generation device electronically coupled to the reaction chamber of the plasma-enhanced etching apparatus can be activated to generate a plasma containing a mixture of reactive ions of a thin film 430 of integrated circuit material configured to etch inside the reaction chamber of the plasma-enhanced etching apparatus. Figure 4 In step 316 described in the text, it is possible to make Figure 5A and 5B One or more apertures 460 shown are contacted by plasma containing reactive ions configured to etch a thin film 430 of integrated circuit material, thereby removing any remaining mask material layer 440 and thus fully defining one or more apertures 460 through the entire mask material layer 440 and thereby exposing the surface 470 of the thin film 430 of integrated circuit material that is consistent with the shape and size of the apertures 460 associated with it.

[0066] In step 318, as Figure 4 As shown, Figure 5B Surface 470 can be contacted by plasma containing reactive ions of a mixture configured to etch thin film 430 of integrated circuit material, thereby removing a portion of the thin film 430 disposed on wafer 410. Figure 5C As shown, the removal of this material 430 in step 318 creates a pattern 480 in the thin film 430 of the integrated circuit material. As understood by those skilled in the art of dry etching, the particles of the pattern 480 generated in this process correspond in shape and size to the apertures 460 coupled to it in the mask material layer 440. Some common patterns 480 etched into the thin film 430 of the integrated thin-film circuit material include gaps, trenches, and vias that can subsequently be backfilled with a low-k material. Alternatively, the pattern 480 may include the above. Figure 1 Channel 14 of the 3D flash memory device is depicted in the figure.

[0067] The mixtures described herein advantageously provide thin-film etching and patterning with the desired selectivity. For example, in the case where the thin film comprises silicon dioxide or silicon nitride, the mixture can have an etching selectivity of more than or equal to about 1 for the mask material layer (e.g., metal mask, carbon hard mask, photoresist).

[0068] For illustrative and descriptive purposes, the foregoing description of embodiments has been provided. It is not intended to be exhaustive or limiting of this disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but are interchangeable where applicable and can be used in chosen embodiments, even if not specifically shown or described. It can also be varied in many ways. Such variations should not be considered as departing from this disclosure, and all such modifications are intended to be included within the scope of this disclosure.

[0069] Patterning methods All patterning tests were performed using a PlasmaTherm APEX SLR ICP 200mm reaction chamber. The plasma generation device electrically coupled to the reaction chamber was an inductively coupled plasma generator with a 2 MHz top electrode source and a 13.56 MHz biased bottom electrode / base. The top electrode power could be varied between 0 watts (“W”) and approximately 2000 W, while the bottom electrode / base power could be varied between 0 W and approximately 600 W. The temperature of the bottom electrode / base could be varied between approximately -40°C and 250°C to evaluate the effect of the reduced temperature on pattern formation. The pressure of the reaction chamber could be varied between approximately 1 mTorr and 100 mTorr, and the flow rate of the mixture configured to etch thin films of integrated circuit material could be varied between 1 and 500 standard cubic centimeters per minute (“sccm”). Oxygen, argon, or oxygen and argon were typically flowed into the reaction chamber as part of the mixture configured to etch thin films of integrated circuit material, while up to three other gases could be simultaneously flowed into the reaction chamber along with oxygen and / or argon to aid in patterning in the thin films of integrated circuit material.

[0070] Working Example 1 - Creating trenches using compound A: A .

[0071] Based on blanket-covered wafer screening DOE, several process conditions were selected for patterned wafer etching and compared with the best known method (“BKM”) conditions for octafluorocyclobutane (C4F8). BKM is a term in the art. The table below shows the C4F8 BKM conditions:

[0072] The table below shows three process conditions for running compound A on a patterned wafer:

[0073] All patterned etchings in the table above were performed at a room temperature of 60°C and an electrode temperature of 25°C. The table below shows a comparison of the etching profiles for compound A under three process conditions. CD in all the tables below is defined as the critical dimension, a term used in the art.

[0074] Data shows that compound A exhibits a higher patterned silicon oxide etch rate than C4F8, with slightly reduced selectivity and an improved bottom / top CD ratio of up to 9%.

[0075] Figure 6AThe image shows cross-sectional SEM images of trenches produced by C4F8BKM, and P1, P19, and P20 processes using compound A. The SEM images reveal deeper trenches using compound A with less residual photoresist, demonstrating a higher patterned SiO2 etch rate and slightly reduced selectivity compared to C4F8. The etch distribution also shows straighter sidewalls than with C4F8.

[0076] Working Example 2 - Creating trenches using compound B: B .

[0077] Based on blanket-covered wafer screening DOE, several process conditions were selected for patterned wafer etching and compared with the best known method (“BKM”) conditions for octafluorocyclobutane (C4F8). BKM is a term in the art. The table below shows the C4F8 BKM conditions:

[0078] The table below shows three process conditions for running compound B on a patterned wafer:

[0079] All patterned etching in the table above was performed at a room temperature of 60°C and an electrode temperature of 25°C. The table below shows a comparison of the etching profiles for compound B under three process conditions. CD in the table below is defined as the critical size, a term used in the art.

[0080] Data shows that compound B exhibits a patterned silicon oxide etching rate comparable to C4F8, with slightly lower selectivity and a significant improvement in the bottom / top CD ratio.

[0081] Cross-sectional SEM images of trenches produced by C4F8BKM, and by processes using compound B (P4, P8, and P9) are shown below. Figure 7A -D. SEM images show that the deep trenches using compound B now have less residual photoresist, demonstrating a patterning etch rate comparable to C4F8, but with reduced selectivity. The SEM images also show a significant improvement in the bottom / top ratio compared to C4F8.

[0082] Working Example 3 - Creating trenches using compound C: C .

[0083] Based on blanket-covered wafer screening DOE, several process conditions were selected for patterned wafer etching and compared with the best known method (“BKM”) conditions for octafluorocyclobutane (C4F8). BKM is a term in the art. The table below shows the C4F8 BKM conditions:

[0084] Based on the blanket-covered wafer screening DOE, the selected conditions were chosen for patterned wafer etching. The table below shows three process conditions for running compound C on the patterned wafer:

[0085] All patterned etching in the table above was performed at room temperature of 60°C and electrode temperature of 25°C. The table below shows a comparison of the etching profiles for compound C under three process conditions. CD in all the tables below is defined as the critical size, which is a term used in the art.

[0086] Data shows that compound C exhibits a higher patterned silicon oxide etching rate than C4F8, with slightly reduced selectivity and an improved bottom / top CD ratio.

[0087] Cross-sectional SEM images of trenches produced by C4F8BKM, and by processes using compound C with P6, P7, and P8 are shown below. Figure 8A -D. SEM images show deeper trenches using compound C and less residual photoresist, demonstrating a higher patterned SiO2 etch rate and reduced selectivity than C4F8. The etch distribution also shows straighter sidewalls than C4F8.

[0088] The above description is intended to be representative only, and therefore modifications can be made to aspects of the invention disclosed herein without departing from the scope of this disclosure. These modifications therefore fall within the scope of this disclosure and are intended to fall within the appended claims.

Claims

1. A mixture configured for etching a thin film of an integrated circuit material, the mixture comprising: The first compound comprises one or more of the following: A B and C ;and The second compound comprises one or more of the following: oxygen, argon, helium, nitrogen, octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), carbonyl fluoride (COF2), difluoromethane (CH2F2), trifluoromethane (CHF3), carbon tetrafluoride (CF4), methyl fluoride (CH3F), octafluorocyclopentene (C5F8), 2,3,3,3-tetrafluoroprop-1-ene (C3H2F4), 2,3,3,3-tetrafluoroprop-1-ene (C3H2F4), hexafluoropropene (C3F6), hexafluorocyclopropane (C3F6), or 1,1,3,3,3-pentafluoropropene (C3HF5).

2. The mixture of thin films configured as etching integrated circuit materials according to claim 1, wherein the thin film comprises silicon, silicon oxide, silicon dioxide, silicon carbide, silicon nitride, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, silicon carbonitride, gallium nitride, aluminum gallium nitride, gallium arsenide, aluminum gallium arsenide, indium phosphide, indium aluminum arsenide, indium gallium arsenide, silicon germanium, silicon bromide, zinc selenide, indium tin oxide, lead zirconium titanate, molybdenum, polycrystalline silicon, carbon hard mask, or photoresist material.

3. The mixture of thin films configured for etching integrated circuit materials according to claim 1, wherein the first compound accounts for more than or equal to about 1% of the volume of the mixture and less than or equal to about 99% of the volume of the mixture.

4. The mixture of thin films configured as etching integrated circuit materials according to claim 3, wherein the second compound accounts for more than or equal to about 1% of the volume of the mixture and less than or equal to about 99% of the volume of the mixture, and wherein the first compound and the second compound account for 100% of the volume of the mixture.

5. The mixture of thin films configured for etching integrated circuit materials according to claim 4, wherein the ratio of the first compound to the second compound is between 5:1 and 1:

5.

6. The mixture of thin films configured for etching integrated circuit materials according to claim 1, wherein one or more of the following are satisfied: (i) The first compound contains ;and (ii) The second compound comprises octafluorocyclobutane (C4F8) or hexafluorobutadiene (C4F6).

7. The mixture of thin films configured as etching integrated circuit materials according to claim 1, further comprising a third compound comprising one or more of the following: oxygen, argon, helium, nitrogen, octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), carbonyl fluoride (COF2), difluoromethane (CH2F2), trifluoromethane (CHF3), and carbon tetrafluoride (CF4), octafluorocyclopentene (C5F8), 2,3,3,3-tetrafluoroprop-1-ene (C3H2F4), hexafluoropropylene (C3F6), hexafluorocyclopropane (C3F6), or 1,1,3,3,3-pentafluoropropylene (C3HF5), nitrogen trifluoride (NF3), and sulfur hexafluoride (SF6).

8. The mixture of thin films configured as etching integrated circuit materials according to claim 7, wherein the third compound accounts for more than or equal to about 1% of the volume of the mixture and less than or equal to about 99% of the volume of the mixture, and wherein the first compound, the second compound and the third compound account for 100% of the volume of the mixture.

9. A method for etching a thin film of an integrated circuit material, comprising: A portion of the thin film of the integrated circuit material is removed by contacting the surface of the film with a plasma containing reactive ions generated by subjecting a mixture configured to etch the thin film of the integrated circuit material to a plasma generator. The mixture said mixture comprises a first compound, which comprises one or more of the following: A B and C ; and The second compound comprises one or more of the following: oxygen, argon, helium, nitrogen, octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), carbonyl fluoride (COF2), difluoromethane (CH2F2), trifluoromethane (CHF3), carbon tetrafluoride (CF4), methyl fluoride (CH3F), octafluorocyclopentene (C5F8), 2,3,3,3-tetrafluoroprop-1-ene (C3H2F4), hexafluoropropene (C3F6), hexafluorocyclopropane (C3F6), or 1,1,3,3,3-pentafluoropropene (C3HF5).

10. The method for etching a thin film of an integrated circuit material according to claim 9, wherein the thin film comprises silicon, silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, gallium nitride, aluminum gallium nitride, gallium arsenide, aluminum gallium arsenide, indium phosphide, indium aluminum arsenide, indium gallium arsenide, silicon germanium, silicon bromide, zinc selenide, indium tin oxide, lead zirconium titanate, molybdenum, polycrystalline silicon, carbon hard mask, or photoresist material.

11. The method for etching a thin film of an integrated circuit material according to claim 9, wherein the first compound accounts for more than or equal to about 1% of the volume of the mixture and less than or equal to about 99% of the volume of the mixture.

12. The method of etching a thin film of an integrated circuit material according to claim 11, wherein the second compound accounts for more than or equal to about 1% of the volume of the mixture and less than or equal to about 99% of the volume of the mixture, and wherein the first compound and the second compound account for 100% of the volume of the mixture.

13. The method for etching a thin film of an integrated circuit material according to claim 12, wherein the ratio of the first compound to the second compound is between 5:1 and 1:

5.

14. The method for etching thin films of integrated circuit materials according to claim 9, wherein one or more of the following are satisfied: (i) The first compound contains ;and (ii) The second compound comprises octafluorocyclobutane (C4F8) or hexafluorobutadiene (C4F6).

15. The method for etching thin films of integrated circuit materials according to claim 9, further comprising a third compound, said third compound comprising one or more of the following: oxygen, argon, helium, nitrogen, octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), carbonyl fluoride (COF2), difluoromethane (CH2F2), trifluoromethane (CHF3), carbon tetrafluoride (CF4), methyl fluoride (CH3F), octafluorocyclopentene (C5F8), 2,3,3,3-tetrafluoroprop-1-ene (C3H2F4), hexafluoropropylene (C3F6), hexafluorocyclopropane (C3F6), 1,1,3,3,3-pentafluoropropylene (C3HF5), nitrogen trifluoride (NF3), and sulfur hexafluoride (SF6).

16. The method of etching a thin film of an integrated circuit material according to claim 15, wherein the third compound accounts for more than or equal to about 1% of the volume of the mixture and less than or equal to about 99% of the volume of the mixture, and wherein the first compound, the second compound and the third compound account for 100% of the volume of the mixture.

17. The method for etching a thin film of an integrated circuit material according to claim 9, wherein the thin film comprises a first film and a second film.

18. The method for etching a thin film of an integrated circuit material according to claim 17, wherein the first film and the second film each independently comprise silicon dioxide, silicon nitride, or a mask material.

19. The method of etching a thin film of an integrated circuit material according to claim 18, wherein the first film comprises silicon dioxide and the second film comprises silicon nitride, and the mixture has an etching selectivity greater than or equal to about 1 for silicon dioxide compared to silicon nitride.

20. The method of etching a thin film of an integrated circuit material according to claim 18, wherein the first film comprises silicon dioxide or silicon nitride and the second film comprises a mask material, and the mixture has an etching selectivity of about 1 for silicon dioxide compared to the mask material, or the mixture has an etching selectivity of about 1 for silicon nitride compared to the mask material.

21. The method for etching a thin film of an integrated circuit material according to claim 20, wherein the mask material comprises a carbon hard mask or a photoresist material.

22. A method for patterning a thin film of an integrated circuit material, comprising: The surface of the thin film is brought into contact with a plasma containing reactive ions generated by subjecting a mixture of thin films configured to etch integrated circuit materials to a plasma generator, thereby removing a portion of the thin film and generating a pattern in the thin film of the integrated circuit material; At least a portion of the thin film is disposed between the opposing surfaces of the substrate and the mask material layer, wherein the mask material layer includes pores defined therein, thereby exposing a portion of the surface of the thin film; and The mixture said mixture comprises a first compound, which comprises one or more of the following: A B and C ; and The second compound comprises one or more of the following: oxygen, argon, helium, nitrogen, octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), carbonyl fluoride (COF2), difluoromethane (CH2F2), trifluoromethane (CHF3), carbon tetrafluoride (CF4), octafluorocyclopentene (C5F8), 2,3,3,3-tetrafluoroprop-1-ene (C3H2F4), hexafluoropropylene (C3F6), hexafluorocyclopropane (C3F6), 1,1,3,3,3-pentafluoropropylene (C3HF5), nitrogen trifluoride (NF3), and sulfur hexafluoride (SF6).

23. The method for patterning a thin film of an integrated circuit material according to claim 22, wherein the substrate is selected from silicon, silicon oxide, silicon dioxide, silicon nitride, tantalum, tantalum nitride, titanium nitride, aluminum oxide, copper, tungsten carbonitride, molybdenum, polysilicon, carbon hard mask, photoresist material, and combinations thereof.

24. The method for patterning a thin film of an integrated circuit material according to claim 22, wherein the thin film comprises silicon, silicon oxide, silicon carbide, silicon nitride, silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, gallium nitride, aluminum gallium nitride, gallium arsenide, aluminum gallium arsenide, indium phosphide, indium aluminum arsenide, indium gallium arsenide, silicon germanium, silicon bromide, zinc selenide, indium tin oxide, lead zirconium titanate, molybdenum, polycrystalline silicon, carbon hard mask, or photoresist material.

25. The method for patterning a thin film of an integrated circuit material according to claim 22, wherein the first compound accounts for more than or equal to about 1% of the volume of the mixture and less than or equal to about 99% of the volume of the mixture.

26. The method for patterning a thin film of an integrated circuit material according to claim 25, wherein the second compound accounts for more than or equal to about 1% of the volume of the mixture and less than or equal to about 99% of the volume of the mixture, and wherein the first compound and the second compound account for 100% of the volume of the mixture.

27. The method for patterning a thin film of an integrated circuit material according to claim 26, wherein the ratio of the first compound to the second compound is between 5:1 and 1:

5.

28. The method for patterning a thin film of an integrated circuit material according to claim 22, wherein one or more of the following are satisfied: (i) The first compound contains ;and (ii) The second compound comprises octafluorocyclobutane (C4F8) or hexafluorobutadiene (C4F6).

29. The method for patterning a thin film of an integrated circuit material according to claim 22, wherein the mask material comprises a carbon hard mask or a photoresist material.

30. The method for patterning a thin film of an integrated circuit material according to claim 22, further comprising a third compound comprising one or more of the following: oxygen, argon, helium, nitrogen, octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), carbonyl fluoride (COF2), difluoromethane (CH2F2), trifluoromethane (CHF3), carbon tetrafluoride (CF4), methyl fluoride (CH3F), octafluorocyclopentene (C5F8), 2,3,3,3-tetrafluoroprop-1-ene (C3H2F4), hexafluoropropylene (C3F6), hexafluorocyclopropane (C3F6), or 1,1,3,3,3-pentafluoropropylene (C3HF5), nitrogen trifluoride (NF3), and sulfur hexafluoride (SF6).

31. The method for patterning a thin film of an integrated circuit material according to claim 30, wherein the third compound accounts for more than or equal to about 1% and less than or equal to about 99% of the volume of the mixture, and wherein the first compound, the second compound and the third compound account for 100% of the volume of the mixture.

32. The method for patterning a thin film of an integrated circuit material according to claim 22, wherein the thin film comprises silicon dioxide or silicon nitride, and the mixture has an etch selectivity of the thin film to the mask material greater than or equal to about 1.

33. The method for patterning a thin film of an integrated circuit material according to claim 22, wherein the thin film comprises a first film and a second film.

34. The method for patterning a thin film of an integrated circuit material according to claim 33, wherein the first film comprises silicon dioxide and the second film comprises silicon nitride, and the mixture has an etch selectivity greater than or equal to about 1 for silicon dioxide compared to silicon nitride.

Images