Lighting test method, lighting test system, and electronic device

Abstract

The present disclosure relates to a method of testing light emission of a plurality of light emitting elements spaced apart from each other and each including a second semiconductor layer, an active layer, a first semiconductor layer, and an electrode portion sequentially stacked on a growth substrate. The method of testing light emission of the present disclosure includes the steps of forming an electric field between a probe card electrically contacting the electrode portions on the plurality of light emitting elements and a conductive plate disposed under the growth substrate to face the second semiconductor layer, and testing whether the plurality of light emitting elements are turned on.

Description

Technical Field

[0001] This disclosure relates to a lighting test method and system for light-emitting devices used in display devices, as well as electronic devices including display devices. Background Technology

[0002] A display device may include a light-emitting element. The light-emitting element can emit light, and the display device displays an image by combining the light emitted from the light-emitting element.

[0003] MicroLEDs can be used as light-emitting elements. After forming microLEDs on a growth substrate, the microLEDs can be separated from the growth substrate, transferred, and finally bonded to the electrodes of the display device.

[0004] It should be understood that this background section is intended to provide part of the useful background for understanding the technology. However, this background section may also include ideas, concepts, or knowledge prior to the corresponding valid application date of the subject matter disclosed herein that are not part of what is known or understood by one of ordinary skill in the art. Summary of the Invention

[0005] Technical issues Multiple light-emitting elements can be formed simultaneously on the growth substrate. In this case, defects may occur in some of the multiple light-emitting elements.

[0006] The present invention discloses a lighting test method and lighting test system for testing whether multiple light-emitting elements formed on a growth substrate are defective before performing transfer and bonding.

[0007] Technical solution An embodiment provides a lighting test method for multiple light-emitting elements, wherein the multiple light-emitting elements may be spaced apart from each other and include a second semiconductor layer, an active layer, a first semiconductor layer and an electrode portion stacked sequentially on a growth substrate. The lighting test method includes the following steps: forming an electric field between a probe card and a conductive plate; the probe card electrically contacts the electrode portions on the multiple light-emitting elements; the conductive plate faces the second semiconductor layer below the growth substrate; and testing whether the multiple light-emitting elements are lit.

[0008] The probe card may include: a probe substrate disposed on a plurality of light-emitting elements; and a plurality of probe pins protruding in a direction from the probe substrate toward the plurality of light-emitting elements.

[0009] The electrode portion of each of the multiple light-emitting elements can make electrical contact with the corresponding probe pin among the multiple probe pins.

[0010] In the step of forming an electric field, the growth substrate can be disposed between the conductive plate and the second semiconductor layer.

[0011] In the step of forming an electric field, the conductive plate can directly contact the lower surface of the growth substrate.

[0012] The steps for testing whether multiple light-emitting elements are lit may include: obtaining an image by imaging the multiple light-emitting elements with an optical test unit; and checking whether light is emitted in the areas corresponding to the multiple light-emitting elements in the image.

[0013] The optical testing unit can be located on a probe card and can image multiple light-emitting elements.

[0014] The optical testing unit can be located below the conductive plate and can image multiple light-emitting elements, and the conductive plate can include a light-transmitting material.

[0015] The lighting test method may also include: after testing whether multiple light-emitting elements are lit, removing defective light-emitting elements from the growth substrate.

[0016] An embodiment provides a lighting test system, which may include: a growth substrate; a plurality of light-emitting elements spaced apart from each other and including a second semiconductor layer, an active layer, a first semiconductor layer and an electrode portion stacked sequentially on the growth substrate; a probe card disposed on the plurality of light-emitting elements and movable in a direction toward the plurality of light-emitting elements to electrically contact the electrode portion; a conductive plate disposed below the growth substrate and movable in a direction toward the growth substrate; and an optical test unit disposed on the probe card.

[0017] The probe card may include: a probe substrate disposed on a plurality of light-emitting elements; and a plurality of probe pins protruding in a direction from the probe substrate toward the plurality of light-emitting elements.

[0018] The lighting test system may also include: a power supply, electrical connections to each of the probe cards and conductive plates.

[0019] The second semiconductor layer can directly contact the upper surface of the growth substrate.

[0020] The second semiconductor layer may include: a first doped portion disposed below the active layer and having a first average doping concentration; a second doped portion disposed below the first doped portion and having a second average doping concentration lower than the first average doping concentration; and a third doped portion disposed below the second doped portion and having a third average doping concentration lower than the second average doping concentration.

[0021] The electrode portion may include: an auxiliary electrode on the first semiconductor layer and in electrical contact with the first semiconductor layer; and a bonding electrode on the auxiliary electrode and electrically connected to the auxiliary electrode.

[0022] The auxiliary electrode may include a light-transmitting material.

[0023] The planar area of ​​the bonding electrode can be smaller than the planar area of ​​the first semiconductor layer.

[0024] The electrode portion may also include a reflective electrode disposed between the auxiliary electrode and the bonding electrode.

[0025] The planar area of ​​the reflective electrode can be smaller than the planar area of ​​the first semiconductor layer.

[0026] An embodiment provides a lighting test system, which may include: a growth substrate; a plurality of light-emitting elements spaced apart from each other and including a second semiconductor layer, an active layer, a first semiconductor layer and an electrode portion sequentially stacked on the growth substrate; a probe card disposed on the plurality of light-emitting elements and movable in a direction toward the plurality of light-emitting elements to electrically contact the electrode portion; a conductive plate disposed below the growth substrate and movable in a direction toward the growth substrate; and an optical test unit disposed on the conductive plate, wherein the conductive plate may include a light-transmitting material.

[0027] An embodiment provides an electronic device that may include: a processor that provides input image data; and a display device that displays an image based on the input image data, wherein the display device may include a plurality of light-emitting elements and the plurality of light-emitting elements may be manufactured by performing a lighting test method according to a disclosed embodiment.

[0028] Beneficial effects The illumination test method according to the embodiment provides a method for testing the illumination of multiple light-emitting elements directly formed on a growth substrate. Therefore, illumination defects in the multiple light-emitting elements can be sensed before the multiple light-emitting elements are separated from the growth substrate and before they are transferred and bonded. Attached Figure Description

[0029] The above and other aspects and features of the disclosure will become more apparent from the detailed description of the disclosed embodiments with reference to the accompanying drawings, in which: Figure 1 A block diagram of a display device according to a disclosed embodiment is shown.

[0030] Figure 2 It shows that it includes Figure 1 A block diagram of one of the subpixels in a display device.

[0031] Figure 3 The composition is shown Figure 1 A schematic top view of the display panel of the display device.

[0032] Figure 4 An example is shown. Figure 3A schematic cross-sectional view of the display panel.

[0033] Figure 5 An example is shown. Figure 3 A schematic cross-sectional view of the display panel.

[0034] Figure 6 A schematic top plan view is shown, comprising an array of light-emitting elements formed on a growth substrate.

[0035] Figure 7 It shows along Figure 6 A schematic cross-sectional view taken from line I1-I1'.

[0036] Figure 8 An example of execution is shown. Figure 6 A schematic cross-sectional view of a lighting test system for an array of light-emitting elements.

[0037] Figure 9 It shows the components included in Figure 8 A schematic top-view diagram of the image captured by the optical testing unit in the illumination testing system.

[0038] Figure 10 It shows the basis Figure 9 A schematic cross-sectional view of an embodiment of removing light-emitting elements identified as having lighting defects.

[0039] Figure 11 An example of execution is shown. Figure 6 A schematic cross-sectional view of a lighting test system for an array of light-emitting elements.

[0040] Figure 12 It shows the components included in Figure 11 A schematic top-view diagram of the image captured by the optical testing unit in the illumination testing system.

[0041] Figure 13 An example is shown. Figure 3 A schematic top-down view of one pixel in the pixel array.

[0042] Figure 14 It shows along Figure 13 A schematic cross-sectional view taken by line X1-X1'.

[0043] Figure 15 A block diagram of a display system according to an embodiment is shown.

[0044] Figures 16 to 19 It shows Figure 15 A schematic perspective view illustrating an application example of the display system. Detailed Implementation

[0045] In the following, exemplary embodiments will be described in detail with reference to the accompanying drawings. The following description is intended to provide sufficient disclosure to enable understanding of the operation of the disclosure, and any further disclosure may be omitted to avoid obscuring the scope of the disclosure. The disclosure may be implemented in different forms and is not limited to the embodiments set forth herein. The embodiments described herein are provided for the purpose of describing the technical concept in sufficient detail to enable those skilled in the art to readily practice it.

[0046] In the accompanying drawings, the dimensions, thickness, proportions, and size of elements may be exaggerated for ease of description and clarity. The same reference numerals always refer to the same elements.

[0047] Unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” used herein are intended to include the plural forms as well.

[0048] In the specification and claims, the term "and / or" is intended, for the purposes of its meaning and interpretation, to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a conjunctional or disjunctive sense and can be understood as equivalent to "and / or".

[0049] In the specification and claims, the phrase “at least one of…” is intended, for the purposes of its meaning and interpretation, to include the meaning of “at least one of… selected from the group of…”. For example, “at least one of A and B” can be understood to mean “A, B or A and B”.

[0050] Throughout this specification, when an element is described as being “connected” to another element, this includes not only a “direct connection” but also an “indirect connection” with another element in between. The terminology used herein is for the purpose of describing embodiments and is not intended to limit the scope of disclosure.

[0051] Throughout this specification, when the terms “comprising,” “including,” and / or “having,” and / or the variations thereof are used, it indicates the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but does not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0052] Although the terms first, second, etc., may be used herein to describe various constituent elements, these constituent elements should not be limited by these terms. These terms are used to distinguish one constituent element from another. Therefore, without departing from the publicly stated teachings, the first constituent element discussed below may be referred to as the second constituent element.

[0053] For descriptive purposes, spatial relative terms such as “below,” “under,” “down,” “above,” “above,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” another element or feature would be oriented “above” said other element or feature. Therefore, the term “below” can include both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thus, the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0054] The terms “overlay” or “facade” mean that a first object may be on top of, below, or to the side of a second object, or vice versa. Additionally, the term “overlay” may include stacking, overlapping, facing or oriented towards, extending over, covering or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art.

[0055] The terms "facing" and "oriented" refer to the fact that the first element can be directly or indirectly opposite the second element. When the third element is placed between the first and second elements, although the first and second elements still face each other, they can be understood as being indirectly opposite each other.

[0056] When an element is described as “not overlapping” or “not superimposed” with another element, this can include elements spaced apart from each other, offset from each other, or separated from each other, or any other suitable terminology as will be understood and appreciated by one of ordinary skill in the art.

[0057] Various embodiments are described herein with reference to cross-sectional views as schematic illustrations. Therefore, variations in the shapes shown in the drawings due to factors such as manufacturing techniques and / or tolerances are to be expected. Consequently, the embodiments disclosed herein should not be construed as limited to the shapes of the areas shown, but will include shape deviations caused, for example, by manufacturing processes. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to represent the actual shapes of the areas of the device and are not intended to be limiting.

[0058] As used herein, “about” or “approximately” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0059] Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which they pertain. It will be further understood that, unless expressly defined herein, terms (such as those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense.

[0060] Figure 1 A block diagram of a display device according to a disclosed embodiment is shown.

[0061] Reference Figure 1 The display device DD may include a display panel DP, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0062] The display panel DP may include sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to m-th gate line GLm. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to n-th data line DLn.

[0063] Subpixels (SPs) can generate light of two or more colors. For example, within the scope and spirit of the document, subpixels (SPs) can generate light of colors such as red, green, blue, cyan, magenta, and yellow.

[0064] Two or more sub-pixels SP can constitute a pixel PXL. For example, pixel PXL can include, for example, Figure 1 The three sub-pixels shown are illustrated. Pixel PXL can emit light of various colors and brightnesses based on the combination of light emitted from the sub-pixels included in pixel PXL.

[0065] Gate driver 120 can be connected to sub-pixels SP arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 can output gate signals to first gate lines GL1 to m-th gate lines GLm in response to gate control signal GCS. In embodiments, within the spirit and scope of the disclosure, gate control signal GCS may include a horizontal synchronization signal, a start signal indicating the start of each frame, etc.

[0066] The gate driver 120 may be disposed on one side or one side of the display panel DP. However, the embodiments are not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically separated drivers, and these drivers may be disposed on one side or one side of the display panel DP and on the opposite side or the side opposite to said side or one side. As described above, the gate driver 120 may be disposed in various forms around the display panel DP according to the embodiments.

[0067] Data driver 130 is connected to sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. Data driver 130 receives image data DATA and data control signal DCS from controller 150. Data driver 130 operates in response to data control signal DCS. In embodiments, within the spirit and scope of the disclosure, data control signal DCS may include a source start signal, a source shift clock, a source output enable signal, etc.

[0068] The data driver 130 can receive voltage from the voltage generator 140. The data driver 130 can use the received voltage to apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn. When a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, the data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLn. Therefore, the sub-pixel SP can generate light corresponding to the data signal, and the display panel DP can display an image.

[0069] In one embodiment, gate driver 120 and data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0070] Voltage generator 140 can operate in response to a voltage control signal VCS from controller 150. Voltage generator 140 can be configured to generate multiple voltages and provide the generated voltages to components of display device DD (such as gate driver 120, data driver 130, and controller 150). Voltage generator 140 can generate multiple voltages by receiving an input voltage from outside display device DD and adjusting the received voltage.

[0071] Voltage generator 140 can generate a first electrical voltage and a second electrical voltage. The generated first and second electrical voltages can be provided to the sub-pixel SP via the power line PL. In other embodiments, at least one of the first and second electrical voltages can be provided from outside the display device DD.

[0072] Voltage generator 140 can provide various voltages and / or signals. For example, voltage generator 140 can provide one or more initialization voltages applied to sub-pixel SP. For example, during sensing operations that sense the electrical characteristics of the transistors and / or light-emitting elements of sub-pixel SP, selectable reference voltages can be applied to first data lines DL1 through nth data lines DLn, and voltage generator 140 can generate reference voltages to transmit them to data driver 130. For example, during display operations for displaying an image on display panel DP, a common pixel control signal can be applied to sub-pixel SP, and voltage generator 140 can generate the pixel control signal. In an embodiment, voltage generator 140 can provide pixel control signals to sub-pixel SP via pixel control line PXCL. Figure 1 The illustration shows a pixel control line PXCL connected between the voltage generator 140 and the display panel DP, but the embodiment is not limited to this. For example, the pixel control line PXCL can be connected between the gate driver 120 and the display panel DP. In this case, pixel control signals can be transmitted from the voltage generator 140 to the pixel control line PXCL via the gate driver 120.

[0073] The controller 150 controls various operations of the display device DD. The controller 150 receives input image data IMG and its corresponding control signal CTRL from an external source. In response to the control signal CTRL, the controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS.

[0074] The controller 150 can convert input image data IMG into image data DATA suitable for a display device DD or display panel DP. In an embodiment, the controller 150 can output image data DATA by aligning the input image data IMG to sub-pixels SP suitable for row units.

[0075] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted on a single integrated circuit. For example... Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). In this case, the data driver 130, voltage generator 140, and controller 150 may be functionally separate components within (or in) a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be configured as a component separate from the driver integrated circuit (DIC).

[0076] Figure 2 It shows that it includes Figure 1 A block diagram of a subpixel within a subpixel in a display device. Figure 2 In Figure 1 Among the sub-pixels SP, the sub-pixel SPij set in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) is shown as an example.

[0077] Reference Figure 2 Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0078] The light-emitting element (LD) can be connected between the first power voltage node VDDN and the second power voltage node VSSN. The first power voltage node VDDN can be connected to... Figure 1 One of the power lines PL in the circuit is used to receive the first power voltage. The second power voltage node VSSN can be connected to... Figure 1 Another power line in the PL is used to receive a second power voltage. The first power voltage can have a higher level than the second power voltage.

[0079] The light-emitting element (LD) can be connected between the anode electrode AE ​​and the cathode electrode CE. The anode electrode AE ​​can be connected to a first power voltage node VDDN via a sub-pixel circuit SPC. For example, the anode electrode AE ​​can be connected to the first power voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC. The cathode electrode CE can be connected to a second power voltage node VSSN. The light-emitting element LD is configured to emit light according to the current flowing from the anode electrode AE ​​to the cathode electrode CE.

[0080] Sub-pixel circuits (SPCs) can be connected to Figure 1 The i-th gate line GL1 to the m-th gate line GLm and Figure 1 The first data line DL1 to the nth data line DLn, specifically the j-th data line DLj. In response to the gate signal received via the i-th gate line GL1, the sub-pixel circuit SPC controls the light-emitting element LD to emit light based on the data signal received via the j-th data line DLj. In an embodiment, the sub-pixel circuit SPC may also be connected to... Figure 1 The pixel control line PXCL. In this case, the sub-pixel circuit SPC can further control the light-emitting element LD in response to the pixel control signal received through the pixel control line PXCL.

[0081] For these operations, the subpixel circuit SPC may include circuit elements (such as transistors and one or more capacitors).

[0082] The transistors of the sub-pixel circuit SPC may include P-type transistors and / or N-type transistors. In an embodiment, the transistors of the sub-pixel circuit SPC may include metal-oxide-semiconductor field-effect transistors (MOSFETs). In an embodiment, the transistors of the sub-pixel circuit SPC may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, and oxide semiconductors.

[0083] Figure 3 The composition is shown Figure 1 A schematic top view of the display panel of the display device.

[0084] Reference Figure 3 The display panel DP can include a display area DA and a non-display area NDA. The display panel DP can display images through the display area DA. The non-display area NDA can be positioned around the display area DA.

[0085] The display panel DP may include sub-pixels SP disposed in the display area DA. The sub-pixels SP may be arranged along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the sub-pixels SP may be arranged in a matrix along the first direction DR1 and the second direction DR2. As another example, the sub-pixels SP may be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. In embodiments, the arrangement of the sub-pixels SP can vary. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0086] Two or more sub-pixels SP can form a pixel PXL. Figure 3 The illustration shows that pixel PXL may include three sub-pixels SP1, SP2, and SP3, but the embodiment is not limited thereto. For example, pixel PXL may include two sub-pixels. In the following text, for better understanding and ease of description, it is assumed that pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3.

[0087] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can generate one of various colors such as red, green, blue, cyan, magenta, and yellow. In the following description, for clarity and brevity, it is assumed that the first sub-pixel SP1 is configured to generate red light, the second sub-pixel SP2 is configured to generate green light, and the third sub-pixel SP3 is configured to generate blue light.

[0088] Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include at least one light-emitting element configured to generate light. In an embodiment, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate light of the same color. For example, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate blue light. In an embodiment, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate light of different colors. For example, the light-emitting elements of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may generate red, green, and blue light, respectively.

[0089] As a display panel DP, self-emissive display panels such as LED display panels using micron- or nano-sized light-emitting diodes as light-emitting elements and organic light-emitting display panels using organic light-emitting diodes as light-emitting elements can be used.

[0090] The components used to control the sub-pixel SP can be located in the non-display area NDA. The wiring connected to the sub-pixel SP (e.g., Figure 1 The first gate line GL1 to the m-th gate line GLm, the first data line DL1 to the n-th data line DLn, the power line PL, and the pixel control line PXCL shown can be set in the non-display area NDA.

[0091] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, and controller 150 can be disposed in the non-display area NDA of the display panel DP. In an embodiment, the gate driver 120 can be disposed in the non-display area NDA. In this case, the data driver 130, voltage generator 140, and controller 150 can be implemented as follows: Figure 1 The driver integrated circuit (DIC) is separate from the display panel (DP), and the driver integrated circuit (DIC) can be connected to wiring disposed in the non-display area (NDA). In other embodiments, the gate driver 120 can be implemented together with the data driver 130, voltage generator 140, and controller 150 as a single integrated circuit separate from the display panel (DP).

[0092] In this embodiment, the display area DA can have various shapes. The display area DA can have a closed-loop shape including straight lines and / or curves. For example, the display area DA can have shapes such as polygonal shapes, circular shapes, semi-circular shapes, and elliptical shapes.

[0093] In one embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially rounded. In another embodiment, the display panel DP may be flexible, foldable, or rollable. In these cases, the display panel DP and / or the substrate of the display panel DP may include a material with flexible properties.

[0094] Figure 4 An example is shown. Figure 3 A schematic cross-sectional view of the display panel.

[0095] Reference Figure 4 The display panel DP may include a substrate SUB and a pixel circuit layer PCL, a display panel layer DPL, and a light function layer (or optical function layer) LFL that are sequentially stacked on the substrate SUB on a third direction DR3 that intersects (or crosses) the first direction DR1 and the second direction DR2.

[0096] The substrate SUB can be made of an insulating material such as glass or resin. For example, the substrate SUB may include a glass substrate. As another example, the substrate SUB may include a polyimide (PI) substrate. As yet another example, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes.

[0097] In embodiments, the substrate SUB can be made of a flexible material that is bendable or foldable, and can have a single-layer or multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the embodiments are not limited thereto.

[0098] The pixel circuit layer (PCL) can be disposed on the substrate (SUB). The PCL may include an insulating layer and semiconductor and conductive patterns disposed between the insulating layers. Within the spirit and scope of this disclosure, the conductive patterns of the PCL can be used as circuit elements, wiring, etc.

[0099] The circuit elements of the pixel circuit layer PCL can be constructed Figure 3 Each of the sub-pixels in the SP has a sub-pixel circuit SPC. In other words, the circuit elements of the pixel circuit layer PCL can be configured as transistors and one or more capacitors in the sub-pixel circuit SPC.

[0100] The wiring of the pixel circuit layer (PCL) may include wiring connected to the sub-pixels (SP). The wiring of the pixel circuit layer (PCL) may also include various signal lines and / or voltage lines required to drive the display panel layer (DPL).

[0101] The display panel layer (DPL) can be set on the pixel circuit layer (PCL). The display panel layer (DPL) may include the light-emitting elements of the sub-pixels (SP).

[0102] A light functional layer (LFL) can be disposed on the display panel layer (DPL). The LFL may include a light conversion pattern with color conversion particles and / or scattering particles. For example, the color conversion particles may include quantum dots. Quantum dots can change the wavelength (or color) of light emitted from the display panel layer (DPL). The LFL may also include a light scattering pattern with scattering particles. In embodiments, the light conversion pattern and light scattering pattern may be omitted.

[0103] The optical functional layer (LFL) may also include a color filter layer containing a color filter. The color filter can selectively transmit light of a given wavelength (or a given color). In embodiments, the color filter layer may be omitted.

[0104] A window used to protect the exposed surface (or top surface) of the display panel (DP) can be disposed on the light functional layer (LFL). The window protects the display panel (DP) from external impacts. The window can be bonded or attached to the light functional layer (LFL) using optically transparent adhesive (bonding) components. The window can have a multi-layered structure selected from glass substrates, plastic films, and plastic substrates. The multi-layered structure can be formed through a continuous process or an adhesive process using adhesive layers. All or part of the window can be flexible.

[0105] Figure 5 An example is shown. Figure 3 A schematic cross-sectional view of the display panel.

[0106] Reference Figure 5 The display panel DP' may include a substrate SUB, a pixel circuit layer PCL, a display panel layer DPL, an input sensing layer ISL, and a light functional layer LFL. The substrate SUB, pixel circuit layer PCL, display panel layer DPL, and light functional layer LFL can be configured to be similar to a reference layer. Figure 4 The substrate (SUB), pixel circuit layer (PCL), display panel layer (DPL), and optical functional layer (LFL) described are essentially the same (or similar). Therefore, descriptions of redundant content can be omitted.

[0107] The input sensing layer (ISL) can detect user input on the upper surface (or display surface) of the display panel (DP). The input sensing layer (ISL) may include components suitable for sensing external objects such as a user's hand or a pen. For example, the input sensing layer (ISL) may include touch electrodes.

[0108] Figure 6 A schematic top plan view is shown, comprising an array of light-emitting elements formed on a growth substrate. Figure 7 It shows along Figure 6 A schematic cross-sectional view taken from line I1-I1'.

[0109] Reference Figure 6 and Figure 7 An LDAR (Light Emitting Array) can be formed on a growth substrate SSP. The LDAR can include multiple light-emitting elements (e.g., LD_NOR and LD_DF). There are no limitations on the method for forming the LDAR on the growth substrate SSP, and various known methods can be used. For example, an epitaxial growth process for forming multiple light-emitting elements can be performed.

[0110] The growth substrate SSP can include, for example, a sapphire substrate. However, the material of the growth substrate SSP is not limited to this. The growth substrate SSP can include various known materials suitable for performing the epitaxial growth process described above.

[0111] Multiple light-emitting elements included in the light-emitting element array LDAR can be disposed on a growth substrate SSP and spaced apart from each other. One or more of the multiple light-emitting elements may be defective. For example, the multiple light-emitting elements may include normal light-emitting elements LD_NOR and defective light-emitting elements LD_DF. The normal light-emitting element LD_NOR can be based on the pixel PXL (refer to...) which will be described later. Figure 13 and Figure 14 A light-emitting element (LD_DF) is a light-emitting element that normally emits light when an electrical signal is provided. A defective LD_DF may be a light-emitting element that does not emit light even when an electrical signal is provided. A defective LD_DF may be a light-emitting element that has lost its function, for example, due to the introduction of foreign matter during the epitaxial growth process described above.

[0112] Multiple light-emitting elements can be separated from the growth substrate SSP and provided to the pixel PXL using various known transfer devices and methods. The multiple light-emitting elements disposed in the pixel PXL can be bonded to electrodes (e.g., AE1 to AE3, see...). Figure 14 In this situation, if the defective light-emitting element LD_DF is set and bonded to pixel PXL, pixel PXL may fail to emit light properly. Therefore, the display device DD (refer to...) Figure 1 The display quality may deteriorate.

[0113] To prevent this, the disclosure provides a method for performing a lighting test on multiple light-emitting elements included in the LDAR after the LDAR is formed on a growth substrate SSP, but before the LDAR is separated, transferred, and bonded. See below for further details. Figures 8 to 12 The lighting test method and the system used to perform the lighting test are described in detail below, and will be referred to in the following text. Figure 7Each of the multiple light-emitting elements included in the LDAR (Light Emitting Element Array) is described in more detail.

[0114] Multiple light-emitting elements included in a light-emitting element array (LDAR) can be constructed to be substantially identical to each other. For example, Figure 7 The two normal light-emitting elements LD_NOR and one defective light-emitting element LD_DF shown can be constructed to be substantially identical to each other. In the following description, for clarity and conciseness, the design will be based on... Figure 7 The left side shows a normal light-emitting element LD_NOR for description.

[0115] A normal light-emitting element LD_NOR may include a light-emitting stack EST, an electrode portion EE, and an insulating film 40.

[0116] The light-emitting stack EST may include a first semiconductor layer 10, an active layer 20, and a second semiconductor layer 30. The second semiconductor layer 30, the active layer 20, and the first semiconductor layer 10 may be sequentially stacked on a growth substrate SSP along a fourth direction DR4. Here, the fourth direction DR4 may be the same as the third direction DR3 (see...). Figures 3 to 5 The opposite direction. Additionally, in the description Figures 6 to 12 At that time, the fourth direction DR4 can be referred to as the "upward direction".

[0117] The first semiconductor layer 10 may be configured to provide holes. The first semiconductor layer 10 may have a first polarity. For example, the first semiconductor layer 10 may include at least one p-type semiconductor layer. For example, within the spirit and scope of the disclosure, the first semiconductor layer 10 may include at least one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc. However, the materials included in the first semiconductor layer 10 are not limited thereto, and the first semiconductor layer 10 may be made of various materials. In the disclosed embodiments, the first semiconductor layer 10 may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or p-type dopant).

[0118] An active layer 20 may be disposed between the first semiconductor layer 10 and the second semiconductor layer 30 to provide a region for electron-hole recombination. When electrons and holes recombine in the active layer 20, they transition to a lower energy level, and thus, light with a corresponding wavelength can be generated. The active layer 20 may have a single quantum well structure or a multi-quantum well structure. In the case where the active layer 20 is formed as a multi-quantum well structure, units including a barrier layer, a strain enhancement layer, and a well layer can be repeatedly stacked on top of each other to form the active layer 20. However, the active layer 20 is not limited to the structure described above.

[0119] The second semiconductor layer 30 can be configured to provide electrons. The second semiconductor layer 30 can have a second polarity different from the first polarity. For example, the second semiconductor layer 30 can include at least one n-type semiconductor layer. For example, within the spirit and scope of the disclosure, the second semiconductor layer 30 can include one of gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and can be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), tin (Sn), etc. However, the materials included in the second semiconductor layer 30 are not limited thereto, and the second semiconductor layer 30 can be formed of various materials. In the disclosed embodiments, the second semiconductor layer 30 can include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or n-type dopant).

[0120] In an embodiment, the second semiconductor layer 30 may include a first doped portion 31 disposed below the active layer 20, a second doped portion 32 disposed below the first doped portion 31, and a third doped portion 33 disposed below the second doped portion 32. The first doped portion 31 may be a portion doped with a first average doping concentration. The second doped portion 32 may be a portion doped with a second average doping concentration lower than the first average doping concentration. The third doped portion 33 may be a portion doped with a third average doping concentration lower than the second average doping concentration. The first doped portion 31, the second doped portion 32, and the third doped portion 33 may define the second semiconductor layer 30.

[0121] In this embodiment, the normal light-emitting element LD_NOR can be directly formed on the growth substrate SSP. Therefore, the second semiconductor layer 30 can directly contact the growth substrate SSP. In other words, the lower surface of the second semiconductor layer 30 can directly contact the upper surface of the growth substrate SSP. In this case, other components such as conductive layers may not be disposed between the second semiconductor layer 30 and the growth substrate SSP.

[0122] In an embodiment, the light-emitting stack EST may have a cylindrical shape in which the second semiconductor layer 30, the active layer 20, and the first semiconductor layer 10 are sequentially stacked together along a fourth direction DR4. For example, the light-emitting stack EST may have a cylindrical shape, but the embodiment is not limited thereto.

[0123] The electrode portion EE can be disposed on the light-emitting stack EST. The electrode portion EE may include an auxiliary electrode SE, a reflective electrode RE, and a bonding electrode BDE that are stacked sequentially on top of each other along the fourth direction DR4.

[0124] An auxiliary electrode SE may be disposed on the first semiconductor layer 10. The auxiliary electrode SE may be in electrical contact with the first semiconductor layer 10. In embodiments, the auxiliary electrode SE may be configured to be substantially transparent or translucent to meet a selectable transmittance. For example, the auxiliary electrode SE may comprise a transparent material that is conductive. For example, the auxiliary electrode SE may comprise at least one of various transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the material of the auxiliary electrode SE is not limited to these.

[0125] A reflective electrode RE can be disposed on an auxiliary electrode SE. The reflective electrode RE can be in electrical contact with the auxiliary electrode SE. In embodiments, the reflective electrode RE can comprise a conductive material having a selectable reflectivity. For example, the reflective electrode RE can comprise metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys thereof. However, the material of the reflective electrode RE is not limited to these. Because the reflective electrode RE has a selectable reflectivity, light emitted from the active layer 20 can be more effectively delivered to the optical functional layer LFL, which will be described later (see...). Figure 14 ).

[0126] The bonding electrode BDE can be disposed on the reflective electrode RE. The bonding electrode BDE can be in electrical contact with the reflective electrode RE. In an embodiment, the bonding electrode BDE may include a eutectic metal.

[0127] In an embodiment, at least one of the auxiliary electrode SE and the reflective electrode RE may be omitted. If both the auxiliary electrode SE and the reflective electrode RE are omitted, the bonding electrode BDE may electrically contact the upper surface of the first semiconductor layer 10. If either the auxiliary electrode SE or the reflective electrode RE is omitted, the other electrode may electrically contact the upper surface of the first semiconductor layer 10 and the lower surface of the bonding electrode BDE, respectively.

[0128] In this embodiment, the auxiliary electrode SE may be fully stacked with the first semiconductor layer 10. Each of the reflective electrode RE and the bonding electrode BDE may be stacked with a portion of the first semiconductor layer 10. In other words, the planar area of ​​the auxiliary electrode SE may be substantially the same as the planar area of ​​the first semiconductor layer 10. The planar area of ​​each of the reflective electrode RE and the bonding electrode BDE may be smaller than the planar area of ​​the first semiconductor layer 10.

[0129] The insulating film 40 may cover at least a portion of the outer peripheral surface of the light-emitting stack EST. For example, the insulating film 40 may at least cover the side surface of the active layer 20. The insulating film 40 may include a transparent insulating material. The insulating film 40 may prevent electrical short circuits that may occur if the active layer 20 comes into contact with another conductive component. In embodiments, the insulating film 40 may have a multilayer structure consisting of multiple layers including a transparent insulating material.

[0130] Figure 8 An example of execution is shown. Figure 6 A schematic cross-sectional view of a lighting test system for an array of light-emitting elements.

[0131] Reference Figure 8 The illumination test system SYS1 may include a growth substrate SSP, a light-emitting element array LDAR, a probe card PC, a conductive plate MP, and an optical test unit OU.

[0132] The growth substrate SSP and the light-emitting element array LDAR are as shown in the reference. Figure 6 and Figure 7 The description is as described. Therefore, redundant descriptions can be omitted.

[0133] The probe card PC can be disposed on multiple light-emitting elements LD_NOR and LD_DF included in the light-emitting element array LDAR. The probe card PC can be configured to be relatively movable in a direction toward the multiple light-emitting elements LD_NOR and LD_DF. When the probe card PC is relatively movable in a direction toward the multiple light-emitting elements LD_NOR and LD_DF, the probe card PC can make electrical contact with the electrode portions EE of the multiple light-emitting elements LD_NOR and LD_DF.

[0134] In an embodiment, the probe card PC may include a probe substrate PS disposed on a plurality of light-emitting elements LD_NOR and LD_DF, and probe pins PINs protruding from the probe substrate PS toward the plurality of light-emitting elements LD_NOR and LD_DF. The plurality of probe pins PINs may be configured to correspond one-to-one with the plurality of light-emitting elements LD_NOR and LD_DF. For example, they may be configured to correspond to... Figure 8The three light-emitting elements LD_NOR and LD_DF shown correspond to three probe pins PINa, PINb, and PINc. The probe pins PIN can be portions that are electrically connected to the electrode portions EE of the multiple light-emitting elements LD_NOR and LD_DF. In this case, the probe substrate PS can be electrically connected to the probe pins PIN.

[0135] A conductive plate (MP) can be disposed below the growth substrate (SSP). The conductive plate (MP) can include a conductive material. For example, the conductive plate (MP) can include a metallic material. The conductive plate (MP) can be configured to be relatively movable in the direction toward the growth substrate (SSP). When the conductive plate (MP) is relatively movable in the direction toward the growth substrate (SSP), the conductive plate (MP) can directly contact the lower surface of the growth substrate (SSP).

[0136] An electric field can be created between the probe card PC and the conductive plate MP. For example, the illumination test system SYS1 may also include a power supply PW electrically connected to each of the probe card PC and the conductive plate MP. The power supply PW can create an electric field between the probe card PC and the conductive plate MP.

[0137] An electric field can be formed when the probe card PC is in electrical contact with the electrode portion EE and when the conductive plate MP is in contact with the lower surface of the growth substrate SSP. In this case, a normal light-emitting element LD_NOR can emit light due to the electric field. However, a defective light-emitting element LD_DF may not emit light.

[0138] The optical test unit OU can be mounted on the probe card PC. With an electric field established between the probe card PC and the conductive plate MP, the optical test unit OU can generate an image IMG (referencing) that images multiple light-emitting elements LD_NOR and LD_DF included in the light-emitting element array LDAR. Figure 9 ).

[0139] Figure 9 It shows the components included in Figure 8 A schematic top-view diagram of the image captured by the optical testing unit in the illumination testing system.

[0140] Reference Figure 9 It can form and include Figure 6 The image IMG of the first region AA1, the second region AA2, the third region AA3, the fourth region AA4, the fifth region AA5, and the sixth region AA6 corresponding to the positions of multiple light-emitting elements LD_NOR and LD_DF in the LDAR light-emitting element array.

[0141] The first non-emitting region NEA1, the second non-emitting region NEA2, the third non-emitting region NEA3, the fourth non-emitting region NEA4, the fifth non-emitting region NEA5, and the sixth non-emitting region NEA6 can be defined within the center of the first region AA1, the second region AA2, the third region AA3, the fourth region AA4, the fifth region AA5, and the sixth region AA6. The first non-emitting region NEA1, the second non-emitting region NEA2, the third non-emitting region NEA3, the fourth non-emitting region NEA4, the fifth non-emitting region NEA5, and the sixth non-emitting region NEA6 can be regions corresponding to the bonding electrode BDE and the reflective electrode RE included in the electrode portion EE of the multiple light-emitting elements LD_NOR and LD_DF.

[0142] Region AA1, region AA3, region AA4, region AA5, and region AA6 can be areas in which a normal light-emitting element LD_NOR is installed. Since region AA1, region AA3, region AA4, region AA5, and region AA6 are the light-emitting regions, they can be visually identified as relatively bright areas on the image IMG.

[0143] Conversely, the second region AA2 can be the region in which the defective light-emitting element LD_DF is disposed. Since the second region AA2 is a region in which no light is emitted, it can be visually identified as a relatively dark region on the image IMG. Therefore, based on the image IMG, the defective DF of the defective light-emitting element LD_DF disposed in the second region AA2 can be determined.

[0144] Figure 10 It shows the basis Figure 9 A schematic cross-sectional view of an embodiment of removing light-emitting elements identified as having lighting defects.

[0145] Reference Figure 9 Defective light-emitting elements (LD_DF) can be removed. Therefore, only normal light-emitting elements (LD_NOR) can exist on the growth substrate SSP. There are no restrictions on the methods for removing defective LD_DF, and various known methods can be used. For example, a method can be used to selectively irradiate the region in which the defective LD_DF is disposed using a laser.

[0146] Return to reference Figures 8 to 10 The lighting test method disclosed herein may include: forming an electric field between a probe card PC and a conductive plate MP; and testing whether multiple light-emitting elements included in a light-emitting element array LDAR are lit.

[0147] When an electric field is formed, the probe card PC can make electrical contact with multiple light-emitting elements included in the light-emitting element array LDAR. For example, the probe card PC can make electrical contact with the electrode portion EE that is in electrical contact with the first semiconductor layer 10. Conversely, when an electric field is formed, the conductive plate MP can be spaced apart from the multiple light-emitting elements included in the light-emitting element array LDAR. For example, the conductive plate MP can not be in contact with the second semiconductor layer 30. The growth substrate SSP can be disposed between the conductive plate MP and the second semiconductor layer 30, and the conductive plate MP can contact the lower surface of the growth substrate SSP.

[0148] Thus, even if the conductive plate MP does not directly contact the second semiconductor layer 30, the normal light-emitting element LD_NOR among the multiple light-emitting elements in the light-emitting element array LDAR can still emit light through the formation of an electric field. For example, even if the light-emitting element array LDAR is not separated from the growth substrate SSP, it is possible to test whether the light-emitting element array LDAR is lit.

[0149] The lighting test can be performed by checking whether the regions corresponding to multiple light-emitting elements in the image IMG obtained by the optical test unit OU emit light.

[0150] Figure 11 An example of execution is shown. Figure 6 A schematic cross-sectional view of a lighting test system for an array of light-emitting elements.

[0151] The following description will focus on the lighting test system SYS2 and the reference system. Figure 8 The differences between the lighting test system SYS1 are described, and any omitted descriptions will be replaced with the previous content.

[0152] Reference Figure 11 The illumination test system SYS2 may include a growth substrate SSP, a light-emitting element array LDAR, a probe card PC, a conductive plate MP', and an optical test unit OU'.

[0153] The conductive plate MP' can be constructed to be substantially transparent or translucent to meet a selectable light transmittance. For example, the conductive plate MP' may include a light-transmitting material that is conductive. For example, the conductive plate MP' may include at least one of a variety of transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the material of the conductive plate MP' is not limited to these.

[0154] The optical test unit OU' can be positioned below the conductive plate MP'. With an electric field established between the probe card PC and the conductive plate MP', the optical test unit OU' can generate an image IMG' (refer to) that images multiple light-emitting elements LD_NOR and LD_DF included in the light-emitting element array LDAR. Figure 12 ).

[0155] Figure 12 It shows the components included in Figure 11 A schematic top-view diagram of the image captured by the optical testing unit in the illumination testing system.

[0156] Reference Figure 12 It can form and include Figure 6 The image IMG' of the first region AA1', second region AA2', third region AA3', fourth region AA4', fifth region AA5' and sixth region AA6' corresponding to the positions of multiple light-emitting elements LD_NOR and LD_DF in the LDAR light-emitting element array.

[0157] In this case, due to the optical test unit OU' (reference) Figure 11 Multiple images of light-emitting elements LD_NOR and LD_DF are generated below the conductive plate MP', therefore the reference is not limited. Figure 9 The first non-luminescent region NEA1, the second non-luminescent region NEA2, the third non-luminescent region NEA3, the fourth non-luminescent region NEA4, the fifth non-luminescent region NEA5, and the sixth non-luminescent region NEA6 are described.

[0158] The first region AA1', the third region AA3', the fourth region AA4', the fifth region AA5', and the sixth region AA6' can be regions in which a normal light-emitting element LD_NOR is installed. Since the first region AA1', the third region AA3', the fourth region AA4', the fifth region AA5', and the sixth region AA6' are the regions in which light is emitted, they can be visually identified as relatively bright regions on the image IMG'.

[0159] Conversely, the second region AA2' can be the region in which the defective light-emitting element LD_DF is disposed. Since the second region AA2' is a region in which no light is emitted, it can be visually identified as a relatively dark region on the image IMG'. Therefore, based on the image IMG', the defective DF' of the defective light-emitting element LD_DF disposed in the second region AA2' can be determined.

[0160] Figure 13 An example is shown. Figure 3 A schematic top-down view of one pixel in the pixel array.

[0161] Reference Figure 13 Pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be disposed on a first direction DR1. However, the arrangement of pixel PXL is not limited to this and can be varied in various embodiments. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be arranged in a zigzag pattern.

[0162] The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be respectively disposed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The first anode electrode AE1 can be configured as a sub-pixel circuit SPC connected to the first sub-pixel SP1 (see reference). Figure 2 The anode electrode AE ​​is the first anode electrode of the second sub-pixel SP2. The second anode electrode AE2 can be configured as the anode electrode AE ​​of the sub-pixel circuit SPC connected to the second sub-pixel SP2. The third anode electrode AE3 can be configured as the anode electrode AE ​​of the sub-pixel circuit SPC connected to the third sub-pixel SP3.

[0163] One or more first light-emitting elements LD1, one or more second light-emitting elements LD2, and one or more third light-emitting elements LD3 can be respectively disposed on a first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3. The first light-emitting element LD1 can be connected to the first anode electrode AE1. The second light-emitting element LD2 can be connected to the second anode electrode AE2. The third light-emitting element LD3 can be connected to the third anode electrode AE3. In the case where multiple light-emitting elements are disposed for each sub-pixel, each anode electrode can have a shape extending in a given direction such as the second direction DR2, and the light-emitting elements connected thereto can be disposed in the same direction.

[0164] The first light-emitting element LD1 can be configured as a light-emitting element LD included in the first sub-pixel SP1 (see...). Figure 2 The second light-emitting element LD2 can be configured as a light-emitting element LD included in the second sub-pixel SP2 (see reference). Figure 2 The third light-emitting element LD3 can be configured as a light-emitting element LD included in the third sub-pixel SP3 (see...). Figure 2 When multiple light-emitting elements are arranged in a single sub-pixel, these elements can be connected in parallel between the anode and cathode electrodes to achieve the desired effect. Figure 2 The light-emitting element LD.

[0165] Each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be configured to be analogous to a reference. Figure 7The descriptions are basically the same as those for normal light-emitting elements like LD_NOR.

[0166] Figure 14 It shows along Figure 13 A schematic cross-sectional view taken by line X1-X1'.

[0167] Reference Figure 13 and Figure 14 The pixel circuit layer PCL, the display panel layer DPL, and the light function layer LFL can be sequentially arranged on the substrate SUB.

[0168] The pixel circuit layer (PCL) may include insulating layers, semiconductor patterns, and conductive patterns stacked on top of each other on a substrate (SUB). The insulating layer may include a buffer layer (BFL), one or more interlayer insulating layers (ILD), and one or more passivation layers (PSV1 and PSV2). The semiconductor patterns and conductive patterns may be disposed between the insulating layers. The conductive patterns may include at least one of copper (Cu), molybdenum (Mo), tungsten (W), neodymium aluminum (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0169] For reference Figure 2 The sub-pixel circuit SPC described herein for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (see [link to description]). Figure 2 The pixel circuit layer (PCL) can include transistors and one or more capacitors. The semiconductor and conductive patterns of the PCL can be used as transistors and capacitors in the sub-pixel circuit (SPC). The conductive patterns of the PCL can also be used as wiring (e.g., Figure 1 The first gate line GL1 to the m-th gate line GLm, the first data line DL1 to the n-th data line DLn, the power line PL, and the pixel control line PXCL are included.

[0170] The buffer layer BFL can be disposed on one or more surfaces of the substrate SUB. The buffer layer BFL prevents impurities from diffusing into the circuit elements and wiring included in the pixel circuit layer PCL. The buffer layer BFL may include an inorganic insulating layer comprising inorganic materials. In embodiments, the buffer layer BFL may include at least one of silicon nitride, silicon oxide, silicon oxynitride, and metal oxides such as aluminum oxide. The buffer layer BFL can be configured as a single layer or multiple layers. When the buffer layer BFL is configured as multiple layers, the individual layers may be made of the same material or different materials.

[0171] In one embodiment, one or more barrier layers may be disposed between the substrate SUB and the buffer layer BFL. Each of the barrier layers may comprise polyimide.

[0172] The first transistor T_SP1, the second transistor T_SP2, and the third transistor T_SP3, corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively, can be disposed on the buffer layer BFL. The first transistor T_SP1 can be one of the transistors in the sub-pixel circuit SPC included in the first sub-pixel SP1. The second transistor T_SP2 can be one of the transistors in the sub-pixel circuit SPC included in the second sub-pixel SP2. The third transistor T_SP3 can be one of the transistors in the sub-pixel circuit SPC included in the third sub-pixel SP3. Each of the first transistor T_SP1, the second transistor T_SP2, and the third transistor T_SP3 can be understood as a transistor connected to the anode electrode among the transistors of the corresponding sub-pixel.

[0173] The first transistor T_SP1 may include a semiconductor pattern SCP, a gate electrode GE, a first terminal ET1, and a second terminal ET2. The first terminal ET1 may be one of the source electrode and the drain electrode, and the second terminal ET2 may be the other of the source electrode and the drain electrode. For example, the first terminal ET1 may be the source electrode, and the second terminal ET2 may be the drain electrode.

[0174] A semiconductor pattern SCP can be disposed on a buffer layer BFL. The semiconductor pattern SCP may include a first contact area contacting a first terminal ET1 and a second contact area contacting a second terminal ET2. The region between the first and second contact areas may be a channel region. The channel region may be superimposed on the gate electrode GE of the first transistor T_SP1. The channel region is a substantially undoped semiconductor pattern and may be an intrinsic semiconductor. The first and second contact areas may be doped semiconductor patterns. For example, p-type impurities may be used as impurities, but the embodiments are not limited thereto.

[0175] Semiconductor pattern SCP can include one of various types of semiconductors (e.g., one of amorphous silicon semiconductor, monocrystalline silicon semiconductor, polycrystalline silicon semiconductor, low-temperature polycrystalline silicon semiconductor, and oxide semiconductor).

[0176] Interlayer insulating layers (ILDs) can be sequentially stacked on a semiconductor pattern SCP. The ILDs can be inorganic insulating layers comprising inorganic materials. For example, each of the ILDs may include at least one of silicon nitride, silicon oxide, silicon oxynitride, and metal oxides such as aluminum oxide. However, the ILDs are not limited to these. For example, one of the ILDs may include an organic insulating layer comprising organic materials.

[0177] Interlayer insulating layers (ILDs) can electrically isolate conductive patterns and / or semiconductor patterns disposed between each other. For example, an ILD may include a gate insulating layer (GI) disposed on a semiconductor pattern (SCP). The gate insulating layer (GI) may be disposed between the semiconductor pattern (SCP) and the gate electrode (GE), such that the semiconductor pattern (SCP) is spaced apart from the gate electrode (GE). In an embodiment, the gate insulating layer (GI) may be disposed entirely on the semiconductor pattern (SCP) and the buffer layer (BFL) to cover both the semiconductor pattern (SCP) and the buffer layer (BFL). The number of ILDs can be increased as the number of layers required to form the conductive patterns and / or semiconductor patterns increases.

[0178] The gate electrode GE can be disposed on the gate insulating layer GI. The gate electrode GE can be stacked with the channel region of the semiconductor pattern SCP. In an embodiment, the gate electrode GE can be a monolayer comprising at least one of copper (Cu), molybdenum (Mo), tungsten (W), neodymium aluminum (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). In an embodiment, the gate electrode GE can be a multilayer comprising at least one of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag) as low-resistance materials.

[0179] First terminal ET1 and second terminal ET2 can be disposed on the interlayer insulating layer (ILD). First terminal ET1 and second terminal ET2 can contact the semiconductor pattern SCP through contact holes penetrating the ILD. First terminal ET1 and second terminal ET2 can respectively contact the first contact area and the second contact area of ​​the semiconductor pattern SCP. Each of first terminal ET1 and second terminal ET2 may include at least one of copper (Cu), molybdenum (Mo), tungsten (W), neodymium aluminum (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0180] Although the first terminal ET1 and the second terminal ET2 are shown as separate electrodes electrically connected to the semiconductor pattern SCP, the embodiment is not limited thereto. In an embodiment, the first terminal ET1 may be a first contact area of ​​the semiconductor pattern SCP adjacent to one side or one side of the channel region, and the second terminal ET2 may be a second contact area of ​​the semiconductor pattern SCP adjacent to the other side of the channel region. In this case, the first terminal ET1 may be electrically connected to the light-emitting element LD via a connection member such as a bridging electrode disposed on at least one of the interlayer insulating layers ILD.

[0181] In one embodiment, the first transistor T_SP1 can be configured as a low-temperature polysilicon transistor. However, the embodiment is not limited to this. For example, the first transistor T_SP1 can be configured as an oxide semiconductor transistor. In one embodiment, the sub-pixel circuit of each sub-pixel can include different types of transistors. For example, the first transistor T_SP1 can be configured as a low-temperature polysilicon transistor, and another transistor included in the sub-pixel circuit SPC of the first sub-pixel SP1 can be configured as an oxide semiconductor transistor. In this case, the oxide semiconductor of the corresponding oxide semiconductor transistor can be disposed on one of the interlayer insulating layers (ILD), rather than on the insulating layer of the semiconductor pattern SCP in which the first transistor T_SP1 is disposed.

[0182] In the embodiments, the case where the first transistor T_SP1 is a transistor with a top-gate structure has been described as an example, but the embodiments are not limited thereto. For example, the first transistor T_SP1 may be a transistor with a bottom-gate structure. The structure of the first transistor T_SP1 can be modified in various ways.

[0183] Each of the second transistor T_SP2 and the third transistor T_SP3 can be constructed similarly to the first transistor T_SP1. Therefore, the description of redundant content can be omitted.

[0184] At least some of the various wirings of the display panel DP and / or display device DD can also be provided on the interlayer insulation layer ILD.

[0185] The first passivation layer PSV1 can be disposed on the interlayer insulating layer ILD and the first terminal ET1 and the second terminal ET2. The passivation layer can also be called a protective layer or a via layer. The first passivation layer PSV1 can protect the components disposed below the first passivation layer PSV1 and can provide a flat upper surface.

[0186] The first connection pattern CP1, the second connection pattern CP2, and the third connection pattern CP3 can be disposed on the first passivation layer PSV1. The first connection pattern CP1, the second connection pattern CP2, and the third connection pattern CP3 can penetrate the first passivation layer PSV1 to connect to the first terminals ET1 of the first transistor T_SP1, the second transistor T_SP2, and the third transistor T_SP3, respectively. The first connection pattern CP1, the second connection pattern CP2, and the third connection pattern CP3 can include at least one of copper (Cu), molybdenum (Mo), tungsten (W), neodymium aluminum (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0187] At least some of the various wirings of the display panel DP and / or display device DD may also be disposed on the first passivation layer PSV1.

[0188] The second passivation layer PSV2 can be disposed on the first connection pattern CP1, the second connection pattern CP2, the third connection pattern CP3, and the first passivation layer PSV1. The second passivation layer PSV2 can protect the components disposed below the second passivation layer PSV2 and can provide a flat upper surface.

[0189] Each of the first passivation layer PSV1 and the second passivation layer PSV2 may include an inorganic insulating layer comprising inorganic materials and / or an organic insulating layer comprising organic materials. The inorganic insulating layer may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and metal oxides such as aluminum oxide. The organic insulating layer may include at least one of, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0190] The first passivation layer PSV1 and the second passivation layer PSV2 may comprise the same material as one of the interlayer insulating layers (ILD), but the embodiments are not limited thereto. Each of the first passivation layer PSV1 and the second passivation layer PSV2 may be a single layer, but may also be multiple layers.

[0191] The display panel layer DPL can be disposed on the second passivation layer PSV2. The display panel layer DPL may include a first anode electrode AE1, a second anode electrode AE2 and a third anode electrode AE3, a first diaphragm BNK1, a first light-emitting element LD1, a second light-emitting element LD2 and a third light-emitting element LD3, an outer coating OCL, a cathode electrode CE and a capping layer CPL.

[0192] On the pixel circuit layer PCL, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be respectively disposed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0193] The first anode electrode AE1 can be electrically connected to the first connection pattern CP1 through a contact hole penetrating the second passivation layer PSV2. The second anode electrode AE2 can be electrically connected to the second connection pattern CP2 through another contact hole penetrating the second passivation layer PSV2. The third anode electrode AE3 can be electrically connected to the third connection pattern CP3 through yet another contact hole penetrating the second passivation layer PSV2. Thus, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 can be electrically connected to the first transistor T_SP1, the second transistor T_SP2, and the third transistor T_SP3, respectively.

[0194] A first diaphragm BNK1 can be disposed on a first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3. The first diaphragm BNK1 can have a first opening OP1 exposing portions of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. A first light-emitting element LD1, a second light-emitting element LD2, and a third light-emitting element LD3 can be disposed within the first opening OP1 of the first diaphragm BNK1. Thus, the first diaphragm BNK1 can be configured as a pixel defining film defining an area in which the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 are disposed.

[0195] The first barrier BNK1 is configured to include a light-blocking material to prevent light mixing between adjacent sub-pixels. In embodiments, the first barrier BNK1 may include organic materials. For example, within the spirit and scope of the disclosure, the first barrier BNK1 may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. In embodiments, to further improve light output efficiency, a reflective layer including a reflective material may be further provided on the side surface of the first barrier BNK1 adjacent to the first opening OP1.

[0196] The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be respectively disposed on the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be respectively coupled to, coupled to, or connected to the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be configured to be consistent with a reference... Figure 7 The descriptions of normal light-emitting elements (LD_NOR) are basically the same. Therefore, redundant descriptions can be omitted.

[0197] The bonding electrode BDE of the first light-emitting element LD1 can be connected to the first anode electrode AE1. The bonding electrode of the second light-emitting element LD2 can be connected to the second anode electrode AE2. The bonding electrode of the third light-emitting element LD3 can be connected to the third anode electrode AE3. The upper surface of the second semiconductor layer 30 of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be connected to the cathode electrode CE. Therefore, the first light-emitting element LD1 can be connected between the first anode electrode AE1 and the cathode electrode CE, the second light-emitting element LD2 can be connected between the second anode electrode AE2 and the cathode electrode CE, and the third light-emitting element LD3 can be connected between the third anode electrode AE3 and the cathode electrode CE.

[0198] The outer coating OCL can be disposed in the first opening OP1 in which the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 are disposed. The outer coating OCL can be fixedly bonded to the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 to prevent them from moving. The outer coating OCL can protect the components disposed below the outer coating OCL from foreign matter such as dust and moisture. The outer coating OCL can include at least one of an inorganic insulating layer and an organic insulating layer. For example, the outer coating OCL can include epoxy resin, but the embodiments are not limited thereto.

[0199] In this embodiment, the outer coating OCL may not be disposed on the upper surfaces of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3. The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may protrude into the optical functional layer LFL. The first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 may be at least partially disposed in the second opening OP2 of the second embankment BNK2. For example, the height of the upper surface LTS of each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 from the substrate SUB may be higher than the height of the lowermost end RBE of the reflective layer RFL from the substrate SUB. Therefore, light emitted from the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be provided to the optical functional layer LFL at a relatively high ratio.

[0200] The cathode electrode CE can be disposed on the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3. The cathode electrode CE can be entirely disposed on the first light-emitting element LD1, the first light-emitting element LD1, the second light-emitting element LD2, the third light-emitting element LD3, and the outer coating OCL. The cathode electrode CE can be in contact with the upper surface of the second semiconductor layer 30 of each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3. The cathode electrode CE can be electrically connected to... Figure 2 The second power voltage node VSSN. The second power voltage applied to the second power voltage node VSSN can be transmitted to the first light-emitting element LD1, the second light-emitting element LD2 and the third light-emitting element LD3 through the cathode electrode CE.

[0201] The cathode electrode CE can be configured to be substantially transparent or translucent to meet a selectable transmittance. In embodiments, the cathode electrode CE may comprise at least one of a variety of transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO). However, the material of the cathode electrode CE is not limited to these.

[0202] A capping layer CPL can be disposed on the cathode electrode CE. The capping layer CPL can protect the components below the capping layer CPL (such as the cathode electrode CE and the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3) from external moisture and humidity. The capping layer CPL can include at least one of silicon nitride, silicon oxide, silicon oxynitride, and metal oxides such as aluminum oxide. However, the material of the capping layer CPL is not limited to these.

[0203] The light functional layer LFL can be disposed on the capping layer CPL. The light functional layer LFL may include a second dam BNK2, a reflective layer RFL, a third passivation layer PSV3, a first light conversion pattern CCP1 and a second light conversion pattern CCP2, a light scattering pattern LSP, a low refractive index layer LRL, and a color filter layer CFL.

[0204] The second dike BNK2 can be disposed on the cap layer CPL. The second dike BNK2 can be stacked with the first dike BNK1. The second dike BNK2 can have a second opening OP2 that is stacked with the first opening OP1.

[0205] The second barrier BNK2 can be configured to include a light-blocking material to prevent light mixing between adjacent pixels and between the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. In embodiments, the second barrier BNK2 may include organic materials. For example, within the spirit and scope of the disclosure, the second barrier BNK2 may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0206] A reflective layer RFL may be disposed on the side surface of the second embankment BNK2 adjacent to the second opening OP2. The reflective layer RFL is configured to reflect incident light, thereby improving the efficiency of emitted light. The reflective layer RFL may include a material suitable for reflecting light. The reflective layer RFL may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0207] It is understood that the luminous area EMA and the non-luminous area NEMA for the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are defined by the second dam BNK2. The area superimposed on the second dam BNK2 may correspond to the non-luminous area NEMA. The area superimposed on the second opening OP2 of the second dam BNK2 may correspond to the luminous area EMA.

[0208] On the capping layer CPL, a third passivation layer PSV3 may be disposed in the second opening OP2. The third passivation layer PSV3 can protect the components disposed below the third passivation layer PSV3 and can provide a flat upper surface. The third passivation layer PSV3 may include the same material as one of the first passivation layer PSV1 and the second passivation layer PSV2, but the embodiments are not limited thereto.

[0209] On the third passivation layer PSV3, the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP can be set in the second opening OP2.

[0210] The first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP may include color conversion particles and / or scattering particles. The color conversion particles can convert incident light into different colors by changing the wavelength of the incident light. The color conversion particles can scatter the incident light. In an embodiment, the color conversion particles may be quantum dots. The scattering particles can scatter the incident light.

[0211] In an embodiment, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be configured to emit blue light. In this case, the first light conversion pattern CCP1 may include a first color conversion particle QD1 configured to convert blue light into red light. The second light conversion pattern CCP2 may include a second color conversion particle QD2 configured to convert blue light into green light. The light scattering pattern LSP may include scattering particles SCT that scatter blue light to improve light output efficiency. Therefore, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be set as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. In an embodiment, at least one of the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP may also include a color conversion particle that converts blue light into white light.

[0212] In an embodiment, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be configured to emit red light, green light, and blue light, respectively. In this case, each of the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP can include scattering particles SCT. As described above, the particles included in the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP can be varied according to the color of the light emitted from the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3.

[0213] In this embodiment, the first light conversion pattern CCP1, the second light conversion pattern CCP2, and the light scattering pattern LSP can be omitted.

[0214] A low refractive index layer (LRL) can be disposed on the second embankment (BNK2), the reflective layer (RFL), the first light conversion pattern (CCP1), the second light conversion pattern (CCP2), and the light scattering pattern (LSP). The LRL can have a lower refractive index than the first light conversion pattern (CCP1), the second light conversion pattern (CCP2), and the light scattering pattern (LSP). The LRL can be configured to refract or totally reflect light according to the angle of incidence. The LRL can return light passing through the first light conversion pattern (CCP1), the second light conversion pattern (CCP2), and the light scattering pattern (LSP) back to the first light conversion pattern (CCP1), the second light conversion pattern (CCP2), and the light scattering pattern (LSP). Therefore, the light conversion efficiency and light scattering efficiency of the first light conversion pattern (CCP1), the second light conversion pattern (CCP2), and the light scattering pattern (LSP) can be improved. In an embodiment, the LRL can be omitted in the region corresponding to the third sub-pixel (SP3).

[0215] The color filter layer CFL can be disposed on the low refractive index layer LRL. The color filter layer CFL may include a first color filter CF1, a second color filter CF2, and a third color filter CF3, as well as a light blocking pattern LBP.

[0216] First color filter CF1, second color filter CF2, and third color filter CF3 may be superimposed with first light conversion pattern CCP1, second light conversion pattern CCP2, and light scattering pattern LSP, respectively. Each of the first color filter CF1, second color filter CF2, and third color filter CF3 can selectively transmit light within a desired wavelength range. If the first sub-pixel SP1 is a red sub-pixel, the first color filter CF1 may include a red color filter. If the second sub-pixel SP2 is a green sub-pixel, the second color filter CF2 may include a green color filter. If the third sub-pixel SP3 is a blue sub-pixel, the third color filter CF3 may include a blue color filter. The first color filter CF1, second color filter CF2, and third color filter CF3 may have a refractive index higher than that of the low refractive index layer LRL. However, the embodiments are not limited thereto, and the first color filter CF1, second color filter CF2, and third color filter CF3 may have a refractive index lower than or equal to that of the low refractive index layer LRL.

[0217] A light-blocking pattern (LBP) can be positioned between the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3). It is understood that the luminous area (EMA) and non-luminous area (NEMA) for the first sub-pixel (SP1), the second sub-pixel (SP2), and the third sub-pixel (SP3) are defined by the light-blocking pattern (LBP). Areas overlapping with the light-blocking pattern (LBP) can correspond to the non-luminous area (NEMA). Areas not overlapping with the light-blocking pattern (LBP) can correspond to the luminous area (EMA).

[0218] In embodiments, the light-blocking pattern LBP may include at least one of various types of light-blocking materials. In embodiments, each of the light-blocking patterns LBP may be configured as a multilayer structure in which at least two of the first color filter CF1, second color filter CF2, and third color filter CF3 are stacked. For example, each of the light-blocking patterns LBP may be formed by stacking the first color filter CF1, second color filter CF2, and third color filter CF3. As another example, in the light-blocking pattern LBP, the light-blocking pattern between the first color filter CF1 and the second color filter CF2 may be formed as a multilayer structure in which the first color filter CF1 and the second color filter CF2 are stacked, and in the light-blocking pattern LBP, the light-blocking pattern between the second color filter CF2 and the third color filter CF3 may be formed as a multilayer structure in which the second color filter CF2 and the third color filter CF3 are stacked. The light-blocking pattern between the first color filter CF1 and the third color filter CF3 of adjacent pixels may be formed as a multilayer structure in which the first color filter CF1 and the third color filter CF3 are stacked. In this way, each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 can extend into the non-emitting region NEMA to form a light-blocking pattern LBP.

[0219] Figure 15 A block diagram of a display system according to an embodiment is shown.

[0220] Reference Figure 15 The display system 1000 may include a processor 1100 and a display device 1200.

[0221] Processor 1100 can perform various tasks and calculations. In embodiments, within the spirit and scope of the disclosure, processor 1100 may include an application processor, graphics processor, microprocessor, central processing unit (CPU), etc. Processor 1100 can be connected to and step over (or control) other components of display system 1000 via a bus system.

[0222] The processor 1100 can send image data IMG and control signal CTRL to the display device 1200. The display device 1200 can display an image based on the image data IMG and control signal CTRL. The display device 1200 can be connected to a reference... Figure 1 The described display device DD is similarly constructed. In this case, the image data IMG and the control signal CTRL can be respectively used as... Figure 1 The input image data IMG and the control signal CTRL are provided.

[0223] Display system 1000 may include computing systems that provide image display capabilities, such as smartwatches, mobile phones, smartphones, portable computers, tablet PCs, watch phones, automatic displays, smart glasses, portable multimedia layers (PMPs), navigation systems, and ultra-mobile personal computers (UMPCs). Display system 1000 may include at least one of head-mounted display devices (HMDs), virtual reality (VR) devices, mixed reality (MR) devices, and augmented reality (AR) devices.

[0224] Figures 16 to 19 It shows Figure 15 A schematic perspective view illustrating an application example of the display system.

[0225] Reference Figure 16 , Figure 15 The display system 1000 can be applied to a smartwatch 2000, which includes a display section 2100 and a band section 2200.

[0226] The smartwatch 2000 can be a wearable electronic device. For example, the smartwatch 2000 can have a structure in which the band portion 2200 is mounted on the user's wrist. Here, the display system 1000 and / or display device 1200 can be applied to the display portion 2100, so that image data including time information can be provided to the user.

[0227] Reference Figure 17 , Figure 15 The display system 1000 can be applied to the automotive display system 3000. Here, the automotive display system 3000 may include a computing system disposed inside and / or outside the vehicle to provide image data.

[0228] For example, the display system 1000 and / or display device 1200 may be applied to at least one of the infotainment panel 3100, instrument panel 3200, passenger display 3300, head-up display 3400, side mirror display 3500 and rear seat display 3600 provided in the vehicle.

[0229] Reference Figure 18 , Figure 15 The display system 1000 can be applied to the smart glasses 4000. The smart glasses 4000 can be a wearable electronic device that can be worn on a user's head. For example, the smart glasses 4000 can be a wearable device for augmented reality.

[0230] The smart glasses 4000 may include a frame 4100 and a lens portion 4200. The frame 4100 may include a housing 4110 supporting the lens portion 4200 and legs 4120 for the user to wear. The legs 4120 may be hinged to the housing 4110 to fold or unfold relative to the housing 4110.

[0231] The battery, touchpad, microphone, and camera can be embedded in the frame 4100. Furthermore, a projector that outputs light and a processor that controls optical signals can also be embedded in the frame 4100.

[0232] The lens portion 4200 may include optical components that transmit or reflect light. For example, within the spirit and scope of this disclosure, the lens portion 4200 may include glass, transparent synthetic resin, etc.

[0233] To enable the user's eye to recognize visual information, the lens portion 4200 can reflect an image generated by optical signals transmitted from the projector of the frame 4100 through its rear surface (e.g., the surface facing the user's eye). For example, the user can recognize visual information such as time and date displayed on the lens portion 4200. In this case, the projector and / or the lens portion 4200 can be a display device. The display device 1200 can be applied to the projector and / or the lens portion 4200.

[0234] Reference Figure 19 , Figure 15 The display system 1000 can be applied to a head-mounted display device 500.

[0235] The head-mounted display device 5000 can be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device 5000 can be a wearable device for virtual reality or mixed reality.

[0236] The head-mounted display device 5000 may include a headband 5100 and a display device housing 5200. The headband 5100 may be connected to the display device housing 5200. The headband 5100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 5000 to a user's head. The horizontal strap may be configured to surround the sides of the user's head, and the vertical strap may be configured to surround the top of the user's head. However, the embodiments are not limited thereto. For example, within the spirit and scope of the disclosure, the headband 5100 may be implemented in the form of an eyeglass frame, a helmet, etc.

[0237] The display device housing 5200 can accommodate the display system 1000 and / or the display device 1200.

[0238] While this disclosure has been described in conjunction with embodiments that are considered practical, it will be understood that the disclosure is not limited to the disclosed embodiments, and rather, the disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A method for testing the illumination of multiple light-emitting elements, wherein the multiple light-emitting elements are spaced apart from each other and include a second semiconductor layer, an active layer, a first semiconductor layer, and an electrode portion sequentially stacked on a growth substrate, the method comprising the following steps: An electric field is formed between the probe card and the conductive plate, the probe card makes electrical contact with the electrode portion on the plurality of light-emitting elements, and the conductive plate faces the second semiconductor layer below the growth substrate; as well as Test whether the multiple light-emitting elements are lit.

2. The lighting test method according to claim 1, wherein, The probe card includes: The probe substrate is disposed on the plurality of light-emitting elements; and Multiple probe pins protrude in a direction from the probe substrate toward the multiple light-emitting elements.

3. The lighting test method according to claim 2, wherein, The electrode portion of each of the plurality of light-emitting elements is in electrical contact with the corresponding probe pin among the plurality of probe pins.

4. The lighting test method according to claim 1, wherein, In the step of forming the electric field, the growth substrate is disposed between the conductive plate and the second semiconductor layer.

5. The lighting test method according to claim 4, wherein, In the step of forming the electric field, the conductive plate is in direct contact with the lower surface of the growth substrate.

6. The lighting test method according to claim 1, wherein, The steps for testing whether the plurality of light-emitting elements are lit include: An image is obtained by imaging the plurality of light-emitting elements using an optical testing unit; and Check whether light is emitted in the regions corresponding to the plurality of light-emitting elements in the image.

7. The lighting test method according to claim 6, wherein, The optical testing unit is located on the probe card and images the plurality of light-emitting elements.

8. The lighting test method according to claim 6, wherein, The optical testing unit is located below the conductive plate and images the plurality of light-emitting elements. The conductive plate includes a light-transmitting material.

9. The lighting test method according to claim 1, further comprising: After testing whether the plurality of light-emitting elements are lit, defective light-emitting elements among the plurality of light-emitting elements are removed from the growth substrate.

10. A lighting test system, the lighting test system comprising: Growth substrate; Multiple light-emitting elements, including a second semiconductor layer, an active layer, a first semiconductor layer and an electrode portion stacked sequentially on the growth substrate, wherein the multiple light-emitting elements are spaced apart from each other; A probe card is disposed on the plurality of light-emitting elements and moves in the direction toward the plurality of light-emitting elements to make electrical contact with the electrode portion; A conductive plate is disposed below the growth substrate and moves in a direction toward the growth substrate; as well as An optical testing unit is mounted on the probe card.

11. The lighting test system according to claim 10, wherein, The probe card includes: The probe substrate is disposed on the plurality of light-emitting elements; and Multiple probe pins protrude in a direction from the probe substrate toward the multiple light-emitting elements.

12. The lighting test system according to claim 10, further comprising: The power supply is electrically connected to each of the probe card and the conductive plate.

13. The lighting test system according to claim 10, wherein, The second semiconductor layer is in direct contact with the upper surface of the growth substrate.

14. The lighting test system according to claim 10, wherein, The second semiconductor layer includes: The first doped portion is disposed below the active layer and has a first average doping concentration; A second doped portion is disposed below the first doped portion and has a second average doping concentration lower than the first average doping concentration; and The third doping portion is disposed below the second doping portion and has a third average doping concentration that is lower than the second average doping concentration.

15. The lighting test system according to claim 10, wherein, The electrode portion includes: An auxiliary electrode is located on and electrically contacts the first semiconductor layer; and A bonding electrode is attached to and electrically connected to the auxiliary electrode.

16. The lighting test system according to claim 15, wherein, The auxiliary electrode comprises a light-transmitting material.

17. The lighting test system according to claim 15, wherein, The planar area of ​​the bonding electrode is smaller than the planar area of ​​the first semiconductor layer.

18. The lighting test system according to claim 15, wherein, The electrode portion also includes: A reflective electrode is disposed between the auxiliary electrode and the bonding electrode.

19. The lighting test system according to claim 18, wherein, The planar area of ​​the reflective electrode is smaller than the planar area of ​​the first semiconductor layer.

20. A lighting test system, the lighting test system comprising: Growth substrate; Multiple light-emitting elements, including a second semiconductor layer, an active layer, a first semiconductor layer and an electrode portion stacked sequentially on the growth substrate, wherein the multiple light-emitting elements are spaced apart from each other; A probe card is disposed on the plurality of light-emitting elements and moves in the direction toward the plurality of light-emitting elements to make electrical contact with the electrode portion; A conductive plate is disposed below the growth substrate and moves in a direction toward the growth substrate; as well as An optical testing unit is mounted on the conductive plate. The conductive plate includes a light-transmitting material.

21. An electronic device, the electronic device comprising: The processor provides the input image data; as well as The display device displays an image based on the input image. The display device includes multiple light-emitting elements. The plurality of light-emitting elements are manufactured by performing the lighting test method according to claim 1.

Images