Interlayer coupler with array of mode confinement posts for multi-layer photonic integrated circuits

Abstract

A photonic integrated circuit includes a first optical waveguide in a lower layer, a second optical waveguide in an upper layer, and an interlayer coupler between the waveguides. The coupler has confinement rods formed and encapsulated within a cladding layer that shape the optical mode as it transitions from one waveguide to the other. In one embodiment, the lower waveguide tapers from a nominal width to a narrow section proximate the coupler, while the upper waveguide expands from a narrow section proximate the coupler to its nominal width. The formation method involves CMOS-compatible processes, including deposition of waveguide layers, patterning of the confinement rods, and encapsulation of them within a cladding layer. The disclosure provides a compact, low-loss solution for guiding signals between different vertical levels in an integrated photonic device operating in the vicinity of the 1550 nm wavelength range.

Description

[0001] Related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 558,417, filed February 27, 2024, 35 USC 119(e), which is incorporated herein by reference in its entirety. Background Technology

[0003] Photonic integrated circuits are increasingly being developed for applications requiring compact and efficient optical functionality on a single chip. These integrated devices combine multiple optical components—such as switches, wavelength splitters, mode-size converters, multiplexers and demultiplexers, resonators, polarizers, phase shifters, modulators, and waveguides—side-by-side with electrical signal routing and electronic components, enabling them to perform complex tasks while occupying a small footprint. By leveraging semiconductor fabrication methods, photonic integrated circuits also benefit from the sophistication of microelectronics manufacturing. This has led to the wider adoption of photonic chips in telecommunications, data communications, and sensing applications.

[0004] In particular, silicon photonics has emerged as a leading technology for large-scale photonic integrated circuits. Because silicon photonics utilizes complementary metal-oxide-semiconductor (CMOS) processes, it offers economies of scale, reduced manufacturing costs, and compatibility with existing electronic device manufacturing infrastructure. This is especially relevant in data centers (where photonic links and silicon-based optics can potentially replace or enhance conventional copper interconnects) and in many emerging applications requiring higher bandwidth and lower latency.

[0005] Waveguide structures form the backbone of photonic integrated circuits by guiding light from one component to another on a chip. A waveguide defines the optical path and, in cross-section, consists of a lower refractive index cladding layer surrounding a high refractive index material core. The choice of materials, geometry, and manufacturing techniques affects waveguide performance and influences optical loss, bandwidth, and power consumption.

[0006] In silicon photonics, waveguides are typically formed from crystalline or amorphous silicon, or silicon nitride. Both materials are compatible with conventional CMOS fabrication processes. Silicon waveguides typically rely on single-crystal or polycrystalline silicon for the core, with silica, silicon dioxide (SiO2), or silicon oxynitride used for the cladding. Silicon nitride waveguides, on the other hand, can use silicon nitride for the core, with silica or other oxide materials again used for the cladding. The waveguide cross-section is typically patterned using photolithography, and subsequent etching methods define the waveguide shape within the core layer.

[0007] Another important consideration is the thickness of the waveguide layer, which often depends on the desired optical mode constraints and the target operating wavelength. Waveguides in silicon photonics are typically targeted at near-infrared wavelengths, such as 1310 nm or 1550 nm, aligned with standard telecommunications windows. Precise control over waveguide thickness, etch depth, and material composition is maintained through CMOS process steps such as dry etching, chemical vapor deposition, and thermal oxidation.

[0008] Photonic integrated circuits often combine multiple layers or strata to increase functionality and density. In some cases, the design may require routing different signals at different layers to reduce optical crosstalk, or to integrate specific optical components and / or materials in separate layers. However, challenges arise when optical signals must transition from waveguides located in one layer to waveguides in another. Different waveguide layers may be vertically separated by intermediary materials, leading to potential alignment problems and increased coupling losses (if not properly addressed).

[0009] In conventional designs, simple vertical transitions between waveguides can exhibit significant insertion losses due to mismatches in waveguide geometry or effective refractive index, as optical modes must be guided out of plane. These losses can severely impact the overall efficiency of integrated photonic circuits, especially in complex multilayer designs. Moreover, if the process requires many fine transitions or if any misalignment introduces further losses, the reliability of the chip can be compromised. Summary of the Invention

[0010] Therefore, there is a desire to develop interlayer coupler structures that enable low-loss and broadband optical transfer between waveguides in different layers within photonic integrated circuits. Such solutions should ideally maintain compatibility with CMOS processes to preserve the cost and throughput advantages of silicon-based photonics. By employing more carefully designed couplers, optical signals can be routed between different vertical layers without incurring high losses or introducing significant fabrication complexity.

[0011] In one aspect, the present invention provides a photonic integrated circuit including a first optical waveguide formed in a first vertical horizontal plane of the circuit and a second optical waveguide formed above the first optical waveguide in a second vertical horizontal plane of the circuit. An interlayer coupler is positioned between the two waveguides to guide optical modes between different vertical planes. The interlayer coupler includes a set of limiting rods adjacent to each waveguide, and these rods are manufactured and encapsulated within a cladding layer to shape the optical modes (e.g., the optical modes of the first and second optical waveguides) as the optical modes transition between different vertical planes from one waveguide to another.

[0012] In some embodiments, an inner set of rods and an outer set of rods are arranged on opposite sides of each waveguide. The rods may extend in a direction substantially parallel to the waveguide.

[0013] The rod dimension can be selected to reduce optical loss when transferring signals between waveguides, for example at about 1550 nanometers (nm), or in the range of about 1400 nm to 1700 nm.

[0014] One waveguide can taper from a nominal width section to a narrower section near the center of the interlayer coupler, the nominal width section being sized based on the waveguide width used for transmission between components in the circuit, while another waveguide can extend from a narrow section near the center to the nominal width section.

[0015] Interlayer couplers are formed using processes compatible with semiconductor manufacturing, such as depositing and patterning silicon or silicon nitride waveguide layers for a first and second waveguide, and surrounding them with a cladding material. In one example, silicon oxide or a similar material is used as the cladding layer.

[0016] In another aspect, the present invention provides a method for forming an interlayer coupler in a photonic integrated circuit. A first waveguide is formed in a first layer. Then, a plurality of cladding layers are deposited over the first layer, and a patterned array of mode-limiting rods is patterned in a region above the first waveguide. An additional cladding layer is deposited, and a second waveguide is formed in a second layer above the first waveguide, wherein the rods are structured to guide light between the two waveguides with reduced optical loss.

[0017] In some embodiments, this method further includes patterning an upper mode limiting rod array above the lower mode limiting rod array before forming the second waveguide. The first waveguide may be formed with a tapered portion that narrows toward the interlayer coupler, and the second waveguide may extend from a narrower width near the interlayer coupler to the nominal width, thereby facilitating the transfer of optical signals.

[0018] The limiting rod can be formed with a specific thickness and width, such as a thickness in the range of 50 to 150 nanometers and a width in the range of 150 to 600 nanometers, depending on the desired coupling efficiency and operating wavelength. In some embodiments, the limiting rod can be formed with a specific thickness and width based on waveguide dimensions (e.g., the dimensions of a first waveguide and / or a second waveguide). For example, the limiting rod can be formed with a specific width in the range of 15% to 60% of the waveguide width.

[0019] This approach is performed using conventional CMOS-compatible fabrication steps, such as depositing dielectric cladding, patterning bar arrays, and forming waveguide cores. In one example, the interlayer coupler is deployed in a multilayer stack formed by successive CMOS-compatible deposition and patterning steps.

[0020] The above and other features of the invention, including various new details of construction and combinations of parts, as well as other advantages, will now be described more specifically with reference to the accompanying drawings and pointed out in the claims. It will be understood that the specific methods and devices for carrying out the invention are shown by way of illustration and are not intended to limit the invention. The principles and features of the invention can be used in various and numerous embodiments without departing from the scope of the invention. Attached Figure Description

[0021] In the accompanying drawings, reference numerals refer to the same parts throughout the different views. The drawings are not necessarily drawn to scale; rather, the emphasis has been placed on illustrating the principles of the invention. In the accompanying drawings: Figure 1 Various views of the interlayer coupler (ILC) according to the present invention are included, including a side view, a schematic top view and three cross-sectional views; Figure 2A and Figure 2B These are transmission diagrams for a conventional inter-layer coupler and an inter-layer coupler according to the present invention; and Figure 3A and Figure 3B These are schematic top and side views of an interlayer coupler for a PIC chip according to an embodiment of the present invention. Detailed Implementation

[0022] The invention will now be described more fully below with reference to the accompanying drawings, which illustrate illustrative embodiments of the invention. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0023] As used herein, the term “and / or” includes any and all combinations of one or more of the items listed in connection with the description. Furthermore, all conjunctions used should be understood to have the most inclusive meaning possible. Therefore, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly requires otherwise. Additionally, the singular forms and the articles “a,” “an,” and “the” are intended to also include the plural forms, unless explicitly stated otherwise. It will be further understood that the terms “comprising,” “including,” “containing,” and / or “including,” when used in this specification, specify the presence of the stated feature, integer, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Furthermore, it will be understood that when an element (including a component or subsystem) is mentioned and / or shown as connected or coupled to another element, it may be directly connected or coupled to the other element, or an intermediary element may be present.

[0024] It will be understood that while terms such as “first” and “second” are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, an element discussed below may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the teachings of the invention.

[0025] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms (such as those defined in common dictionaries) should be interpreted as having the meaning consistent with their meaning in the context of the relevant field and will not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

[0026] Figure 1 Various views of the interlayer coupler (ILC) 100 of the PIC chip 100 according to the present invention are depicted. Figure 1 The invention includes portions (A), (B), and (C). Portion (A) provides a side view of the ILC 100 according to the invention. Portion (B) provides a schematic top view of the ILC 100. Portion (C) provides three cross-sectional views of the ILC 100 from the right, center, and left sides. Three dashed lines a, b, and c illustrate the relationship between the side view of portion (A) and the top view of portion (B) and the three corresponding cross-sections of portion (C).

[0027] refer to Figure 1In part (A), interlayer coupler 100 is formed on silicon-on-insulator (PIC) substrate wafer 50, wherein the first waveguide and the second waveguide (i.e., both lower waveguide 110 and upper waveguide 120) are positioned in different layers or layers of the photonic integrated circuit chip 10. For example, lower waveguide 110 is formed in a first or lower vertical level of PIC chip 100, and upper waveguide 120 is formed in a second or upper vertical level of PIC chip 100. Lower waveguide 110 extends from the left side of the figure and continues to the right, terminating near the right edge. Upper waveguide 120 begins in the left region of the figure and extends to the left, substantially overriding lower waveguide 110 but at a higher vertical level within the device stack. Both waveguides 110, 120 are encapsulated by one or more cladding layers 52. The waveguide cores and claddings are formed according to a CMOS-compatible process, and the thickness and composition of these layers are selected to guide optical signals with minimal loss.

[0028] Interlayer coupler 100 enables optical signals to be transmitted between components located in the lower layer of the chip, routed by the lower waveguide 110, and components located in the higher layer, routed by the upper waveguide 120. These signals may originate in the lower waveguide 110 and then transition upwards to the upper waveguide 120, and / or they may propagate in opposite directions.

[0029] According to one aspect of the invention, the coupler 100 includes one or more mode-limiting rod arrays fabricated in a layer between a lower waveguide and an upper waveguide. In the illustrated example, a lower mode-limiting rod horizontal array 132 and an upper mode-limiting rod horizontal array 134 are positioned between corresponding vertical and horizontal sections of the two waveguides. These arrays 132, 134 extend in a direction parallel to the paths of waveguides 110, 120 and occupy regions where the transition of optical modes occurs. The rods are also encapsulated in a cladding layer, thus performing a mode-guiding function. By controlling the geometry and refractive index of these rods and the cladding, the arrays guide optical modes in a manner that reduces scattering loss and enhances the coupling efficiency between the two waveguides 110, 120. In this way, the limiting rod arrays 132, 134 are structured to guide light between the lower waveguide 110 and the upper waveguide 120 with reduced optical loss.

[0030] In practice, the interlayer coupler 100 can be used in many photonic circuits characterized by vertically stacked or multi-layered waveguides. Such circuits can include components such as edge couplers, multiplexers and demultiplexers, polarizers, phase shifters, modulators, filters, resonators, or arrayed waveguides formed in lower layers, as well as other similar optical components fabricated in higher layers. The function of the coupler is to transfer light between these different layers without requiring long detours or separate external coupling structures. In this way, the ILC 100 allows designers to use multiple vertical levels of waveguides while still maintaining low-loss connectivity between them.

[0031] refer to Figure 1 Part (B) shows a top view of an interlayer coupler 100 comprising both a lower waveguide 110 and an upper waveguide 120, along with two sets of limiting rods on either side. On one side, an inner set of rods 11 and an outer set of rods 120 are arranged adjacent to the lower and upper waveguides, while on the opposite side, an inner set of rods 11 and an outer set of rods 120 are similarly arranged. These rods help guide and modify the limiting of propagating optical modes as they transition between layers. The lower waveguide 110 can be viewed as entering from the left portion of the figure, where it connects to other optical components in the lower layer. It begins with a nominal waveguide width segment 112, then gradually narrows its horizontal width at a tapered segment 114, which has a width similar to that used for wiring in the lower layer, extending from left to right until near the midpoint of the coupler. At that midpoint, the lower waveguide continues into a narrower segment 116, which maintains a substantially uniform width for its remaining length up to the right of the attached figure.

[0032] In contrast, the upper waveguide 120 is initially shown in the narrow segment 126 on the right side of the figure. Its horizontal width remains constant until it reaches the central region of the interlayer coupler 100. Beyond that central point, in the extended segment 124, the width of the upper waveguide increases as it moves further to the right until it reaches its nominal waveguide width segment 122, which has a width similar to that used for wiring in the upper layer. Thus, as revealed in the top view, the upper waveguide transitions from a narrower geometry to the nominal width segment, while the lower waveguide transitions from the nominal width down to a narrower segment. Limiting rods located to the left and right of these waveguide paths, including the internal arrays RI, LI and the external arrays RO, LO, work together to guide the optical field or one or more modes between the waveguides, thereby facilitating efficient optical coupling between different vertical layers of the photonic integrated circuit.

[0033] refer to Figure 1 In part (C), the eight individual mode limit bars 132LO, 132LI, 132RI, 132RO, 134LI, 134RI, 134LO, and 134RO of the lower mode limit bar horizontal array 132 and the upper mode limit bar horizontal array 134 are shown in each of the three cross sections along lines a, b, and c.

[0034] In designs suitable for operation at wavelengths of approximately 1550 nm, the quantifications of thickness and width of each confinement bar in the lower and upper mode confinement bar arrays are typically on the order of tens to hundreds of nanometers, for example, thickness or height in the range of approximately 50 nm to 150 nm and lateral width in the range of approximately 150 nm to 600 nm, depending on the selected materials and the expected degree of mode confinement. The bars can be patterned to span lengths from approximately 1 µm to several micrometers (e.g., on the order of tens to hundreds of micrometers), where the overall dimensions of the bars are adjusted to guide and shape the mode as it transitions between the lower and upper waveguides. In some embodiments, the bar dimensions can deviate from these approximate ranges to accommodate specific manufacturing tolerances or to optimize coupling efficiency for specific interlayer spacing, cladding refractive indices, or target photonic device geometries. In some embodiments, each confinement bar in the lower and upper mode confinement bar arrays can have a specific thickness and a specific width based on the waveguide dimensions (e.g., the dimensions of the upper and / or lower waveguides). For example, the limiting rod can be formed with a specific width ranging from 15% to 60% of the waveguide width of the upper and / or lower waveguide.

[0035] In some embodiments, the interlayer coupler 100 is deployed in a multilayer stack formed by successive CMOS-compatible deposition and patterning steps.

[0036] In one example, a method for forming an interlayer coupler 100 may include forming a first waveguide, such as a lower waveguide 110, in a first layer; depositing a plurality of cladding layers, such as a cladding layer 52, over the first layer; patterning one or more constrained rod arrays (e.g., a lower mode constrained rod horizontal array 132 and / or an upper mode constrained rod horizontal array 134) in a region over the lower waveguide 110; depositing additional cladding layers, such as the cladding layer 52; and forming a second waveguide, such as an upper waveguide 120, in a second layer over the lower waveguide 110.

[0037] Figure 2A This is a diagram for transmission in a conventional interlayer coupler.

[0038] More specifically, Figure 2A The graph presents the transmission efficiency (dB) as a function of the slow length (µm) of the conventional interlayer coupler (ILC) transitioning from a 300 nm thick silicon nitride (SiN300) waveguide to a multimode nanophotonic waveguide (mNWG).

[0039] In the illustrated graph, the y-axis is labeled "transmission (dB)" and ranges from -4 dB in 0.5 dB increments to 0 dB. Here, a transmission closer to 0 dB indicates lower optical loss, while a more negative value indicates greater loss.

[0040] The x-axis is labeled “ILC Slow Length (µm)” and spans from 0 to 700 µm, increasing in 100 µm increments. This represents the physical length of the transition section of the interlayer coupler.

[0041] Two transmission curves were plotted to represent the TE (transverse electric) mode and the TM (transverse magnetic) mode.

[0042] The TM mode graph begins at approximately -3 dB at around 50 µm, indicating significant initial loss. However, as the ILC length increases, TM transmission improves rapidly, reaching approximately 0 dB at 250 µm. From this point onward, the TM mode remains stable near 0 dB, indicating efficient coupling of the TM polarization.

[0043] The TE mode graph initially shows worse performance, starting at approximately -4.5 dB at 275 µm, which is a higher loss compared to TM mode. TE transmission gradually improves with increasing length, but only reaches approximately -1.5 dB at 700 µm, indicating that conventional designs are less efficient for TE-polarized light and experience significant coupling loss over longer distances.

[0044] The TM mode achieves near-lossless transmission after 250 µm, indicating that conventional ILC designs work relatively well for TM polarized light.

[0045] However, the TE mode suffers from slower improvements in length and higher insertion loss, which means that conventional interlayer couplers are ill-suited for TE-polarized light.

[0046] The relatively long, slow length (up to 700 µm) means that conventional ILCs require longer structures to achieve acceptable transmission, which limits the integration density in compact photonic circuits.

[0047] Figure 2B It is an interlayer coupler according to the present invention (e.g., Figure 1 The diagram shows the transmission of the interlayer coupler 100.

[0048] More specifically, Figure 2B A graph showing the transmission efficiency (dB) of an interlayer coupler integrating a limiting rod (also known as a nanorod) according to the invention as a function of the ILC slow segment length (µm) is presented.

[0049] The y-axis is labeled “Transmission (dB)” and ranges from -0.4 dB to 0 dB in increments of 0.05 dB.

[0050] The x-axis is labeled “Slow Segment 1 (µm)” and spans from 0 to 400 µm, increasing in increments of 50 µm.

[0051] The vertical line appears at 235 µm and is labeled “Total Length: 470 µm”, indicating the total length of the nanorod-reinforced ILC structure.

[0052] Two transmission curves were plotted to represent TE mode and TM mode.

[0053] The TM mode graph starts at -0.4 dB at 0 µm and improves rapidly, reaching approximately -0.075 dB at 150 µm. After this peak, the TM transmission gradually tapers down slightly to approximately -0.175 dB at 400 µm, still exhibiting very low loss.

[0054] The TE mode graph starts at -0.4 dB at 125 µm, similar to the TM mode but with a slight delay in its improvement. It then increases rapidly, reaching approximately -0.025 dB at 225 µm, indicating exceptionally low loss. After reaching this peak, the TE mode tapers slightly downwards to approximately -0.225 dB at 400 µm, but remains significantly better than the TM mode. Figure 2A middle.

[0055] The transmission loss of both TE and TM modes is significantly lower than that of TM. Figure 2A The effectiveness of nanorod-based ILC is demonstrated in the paper.

[0056] Compared to conventional ILC, these two polarization modes reach peak efficiency much faster (approximately 200 µm), while conventional ILC requires over 700 µm for the TE mode to achieve a level of -1.5 dB.

[0057] Nanorod-based ILCs achieve lower insertion loss with much shorter lengths, making them much more efficient and compact.

[0058] Figure 2A (Conventional ILC) and Figure 2B The comparison between (nanobar-based ILCs) highlights the significant improvements achieved by this invention.

[0059] exist Figure 2A In the TE mode, high loss was observed (initially -4.5 dB, improving only to -1.5 dB at 700 µm), while... Figure 2B In the TE mode, rapid improvements were achieved, reaching approximately -0.025 dB at 225 µm. Figure 2BThe TM mode in the image also shows much lower loss, compared to... Figure 2A Compared to -3 dB, it peaks at -0.075 dB. Therefore, the transmission low in the ILC according to the present invention is significantly lower.

[0060] Figure 2A In conventional ILC, a 700µm depth is required to approach reasonable TE mode transmission, while Figure 2B The nanorod ILCs in this invention achieve better performance at less than 400 µm. This reduction in required length means that photonic circuits can be integrated more compactly and densely, which is a crucial advantage for scaling photonic devices. Therefore, this invention enables the achievement of even shorter required coupling lengths.

[0061] exist Figure 2A In the data, the TM mode performed well, but the TE mode lagged significantly. Figure 2B In the study, the TE and TM modes exhibited nearly equal transmission efficiencies, demonstrating that nanorod-based ILC ensures better polarization performance. Therefore, the currently disclosed ILC provides a more balanced performance between TE and TM.

[0062] Nanorod-enhanced ILCs (e.g., ILC 100) effectively and more efficiently guide light between layers while minimizing scattering losses. This makes it easier to integrate multilayer photonic circuits with lower power losses, making them ideal for applications such as telecommunications, optical interconnects, and sensing (to name a few).

[0063] Figure 3A A schematic top view of another embodiment of the ILC 100 is shown. The inner arrays LI, RI and the outer arrays LO, RO of the limiting rods have varying widths along the length of the ILC 100. The rods are wider near the center and then narrow as they move away from the center.

[0064] Furthermore, different taper sections are used for the lower waveguide 110 and the upper waveguide 120. Here, the lower waveguide 110 and the upper waveguide 120 exhibit a faster narrowing when transitioning into the ILC 100, rather than... Figure 1 The linear tapering portion.

[0065] Figure 3B Another embodiment is shown, in which a four-layer limiting rod array 132, 132', 134', 134 is employed.

[0066] While the invention has been specifically shown and described with reference to preferred embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the scope of the invention as covered by the appended claims.

Claims

1. A photonic integrated circuit, comprising: A first optical waveguide is formed in a first vertical horizontal direction in the circuit. The second optical waveguide is formed in the second vertical horizontal direction of the circuit above the first optical waveguide, and An interlayer coupler is positioned between a first optical waveguide and a second optical waveguide. The interlayer coupler includes a set of limiting rods adjacent to each waveguide. The set of rods is manufactured and encapsulated within a cladding layer to shape the optical modes as the optical modes of the first and second optical waveguides transition between different vertical and horizontal planes.

2. The photonic integrated circuit of claim 1, wherein the set of limiting rods includes at least one set of rods inside and at least one set of rods outside, which are placed on opposite sides of the first and second optical waveguides.

3. The photonic integrated circuit as claimed in any one of claims 1 or 2, wherein the limiting rod extends in a direction substantially parallel to the first and second optical waveguides.

4. The photonic integrated circuit according to any one of claims 1-3, wherein each limiting bar has a thickness in the range of about 50 nanometers to about 150 nanometers and a width in the range of about 150 nanometers to about 600 nanometers.

5. The photonic integrated circuit according to any one of claims 1-4, wherein the first optical waveguide tapers from a nominal waveguide width segment to a narrower width segment approaching the interlayer coupler.

6. The photonic integrated circuit according to any one of claims 1-5, wherein the second optical waveguide extends from a narrower width section near the interlayer coupler to a nominal waveguide width section.

7. The photonic integrated circuit according to any one of claims 1-6, wherein the interlayer coupler is configured to operate at an optical wavelength of approximately 1550 nanometers.

8. The photonic integrated circuit according to any one of claims 1-7, wherein the interlayer coupler is deployed in a multilayer stack formed by successive CMOS-compatible deposition and patterning steps.

9. A method for forming an interlayer coupler in a photonic integrated circuit, the method comprising: The first waveguide is formed in the first layer. Multiple coating layers are deposited above the first layer. A lower-mode limiting rod array is patterned in the region above the first waveguide. An additional cladding layer is deposited, and a second waveguide is formed in a second layer above the first waveguide, wherein the constraining rod array is structured to guide light between the first and second waveguides with reduced optical loss.

10. The method of claim 9, further comprising patterning an upper mode limiting rod array above the lower mode limiting rod array prior to depositing the additional cladding layer and forming the second waveguide.

11. The method of any one of claims 9 or 10, wherein the first waveguide is formed having a tapered portion that narrows toward the central region of the interlayer coupler, and the second waveguide is formed having an extended section that widens away from the central region of the interlayer coupler.

12. The method of any one of claims 9-11, wherein each limiting bar in the lower mode limiting bar array has a thickness in the range of about 50 nanometers to about 150 nanometers and a width in the range of about 150 nanometers to about 600 nanometers.

13. The method of any one of claims 9-12, wherein the lower mode limiting rod array extends in a direction substantially parallel to the first and second waveguides.

14. The method of any one of claims 9-13, wherein the method is performed using a CMOS-compatible process, comprising depositing and patterning silicon or silicon nitride layers for the first and second waveguides and using silicon oxide or a similar material for the cladding layer.

15. The method of any one of claims 9-14, wherein the photonic integrated circuit is configured to operate at an optical wavelength of approximately 1550 nanometers.

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