Confinement rod based spot size converter for fiber-chip coupling in photonic integrated circuits

Abstract

A photonic device and method for low-loss fiber-chip coupling in photonic integrated circuits is disclosed. The waveguide is tapered near the edge, reducing its width by at least 50%, while the confinement rods are arranged in multiple vertical layers above and below the waveguide and are tapered in opposite directions. Together they form complementary "supermodes" that ensure a smooth transition of the optical field. This design mitigates the manufacturing challenges associated with very narrow tapers and enables a smaller footprint compared to conventional edge couplers. By placing the waveguide in the center of the supermodes, the dielectric stack is thinner, facilitating integration with standard silicon photonics processes. The result is a robust, compact, and very efficient solution for fiber-chip interconnects.

Description

[0001] Related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 558,421, filed February 27, 2024, pursuant to 35 USC 119(e), the entirety of which is incorporated herein by reference. Background Technology

[0003] Photonic integrated circuits (PICs) are increasingly being developed for applications requiring compact and efficient optical functionality on a single chip. These integrated devices combine multiple optical components—such as switches, wavelength splitters, modulators, mode-size converters (also known as "spot-size converters"), multiplexers and demultiplexers, resonators, polarizers, phase shifters, and waveguides—side-by-side with electrical signal routing and electronic components. By leveraging semiconductor manufacturing methods, photonic integrated circuits also benefit from the maturity of microelectronics manufacturing. This has led to the wider adoption of photonic chips in telecommunications, data communications, computing, and sensing applications. In many of these applications, a key challenge lies in the effective coupling of light between standard optical fibers and on-chip waveguides due to the mismatch between optical mode size and numerical aperture.

[0004] In particular, silicon photonics has emerged as a leading technology for large-scale photonic integrated circuits and is well-suited for implementing spot-size converters. Because silicon photonics utilizes complementary metal-oxide-semiconductor (CMOS) processes, it offers economies of scale, reduced manufacturing costs, and compatibility with existing electronics manufacturing infrastructure. In data centers and other high-speed communication environments, photonic links and silicon-based optical components can replace or enhance conventional copper interconnects, thereby reducing power consumption and latency. However, minimizing coupling losses between optical fibers and tightly constrained waveguide modes on silicon photonic chips remains a major obstacle.

[0005] Waveguide structures form the backbone of photonic integrated circuits by guiding light from one component to another on a chip. They typically consist of a high-refractive-index core surrounded by one or more low-refractive-index cladding layers. The geometry, material composition, and fabrication methods used to define these waveguides strongly influence optical loss, bandwidth, and overall device performance. While the compact nature of high-refractive-index contrast waveguides (such as silicon-on-insulator) is advantageous for much of the circuitry, it also increases the difficulty of coupling to external components, such as optical fibers, which typically have much larger mode field diameters.

[0006] In silicon photonics, waveguides can be formed from crystalline silicon, amorphous silicon, or silicon nitride, with cladding made of silica, silicon dioxide (SiO2), or silicon oxynitride. These processes utilize photolithography and etching steps to define the waveguide shape, followed by deposition steps to form precise film thicknesses, often achieving optimal mode confinement at telecommunication wavelengths, typically around 1310 nm or 1550 nm. The small cross-sections of these waveguides enable sharp bends and high integration densities, but complicate direct coupling to standard single-mode optical fibers.

[0007] Spot size converters (SSCs) are typically used on-chip to bridge the mode size mismatch between the large optical mode of the fiber and the much smaller mode of the waveguide. SSCs gradually transition between a larger cross-sectional waveguide at and near the chip edge or endface and a smaller waveguide core used inside the chip, effectively expanding or shrinking the optical mode along the propagation direction to minimize coupling loss. Despite the existence of various SSC designs, further improvements are needed to reduce complexity, increase manufacturing tolerance, and achieve lower insertion loss. Summary of the Invention

[0008] In conventional spot-size converter designs, mismatches in waveguide geometry, material refractive index, or manufacturing defects can still lead to significant coupling losses. The fiber-to-waveguide transition remains a critical performance bottleneck, especially for applications requiring high optical power efficiency, minimal insertion loss, and resistance to alignment errors. Furthermore, achieving robust lateral and vertical constraints without excessive complexity in the manufacturing process can be challenging.

[0009] To address these issues, improved spot size converter structures are needed to provide efficient, low-loss coupling between standard fiber and on-chip waveguide modes. This invention provides a solution by using constrained rod (e.g., nanorod) arrays, which are periodic or quasi-periodic arrangements of high-refractive-index rods or pillars integrated within or adjacent to the SSC region. These arrays can tune optical mode transitions, enhance mode matching, and effectively reduce coupling losses. By carefully configuring the rod geometry, spacing, and material composition, this invention provides a more robust and manufacturing-tolerant spot size conversion method, thereby facilitating higher-performance fiber-to-chip interfaces in photonic integrated circuits.

[0010] Compared to existing methods, the functional waveguide is directly integrated into the rod-based converter structure, rather than being placed beneath a large stack of rods. Because waveguide cores typically use high-refractive-index materials (e.g., silicon) and maintain a certain thickness for the primary PIC function, seamlessly integrating them with constraint rods across multiple layers is not an easy task. Achieving this uniform supermode transition while keeping the waveguide in its functional position constitutes an evolution from previous SSC designs.

[0011] By carefully customizing the thickness of the dielectric layer and the geometry of the rod, this design achieves a balance between effective mode expansion, minimal loss, and manufacturability—characteristics not readily apparent from existing inverse conical or top-loaded nanorod schemes.

[0012] By achieving low-loss edge coupling to standard optical fibers within a compact footprint and without necessarily resorting to thick dielectric stacks, the proposed solution offers benefits such as lower insertion loss at the fiber-chip interface, reduced chip thickness, and simpler integration, particularly useful in multilayer PICs where vertical dimensions are extremely valuable; and / or greater design flexibility to adjust the supermode shape through strategic placement and taper of rods in multiple layers.

[0013] Embodiments of the present invention improve upon conventional couplers by placing the functional waveguide at the center of a “supermode” defined by constraint rods. Instead of burying the waveguide under a thick stack, the design layers (above and below the waveguide) can be thinned, ensuring that the waveguide is directly integrated into the constraint rod structure.

[0014] Structurally, this is achieved by progressively narrowing the taper of the waveguide, causing its width to decrease as it approaches the chip edge, reducing the core size, and / or causing the constraint rods to taper towards wider tapers. That is, the rods distributed across multiple layers around the waveguide (above and below the waveguide) simultaneously widen towards the chip edge. This arrangement gradually reshapes the optical field, transitioning from tightly constrained waveguide modes to larger fiber-compatible modes.

[0015] The result is a more efficient supermode that integrates the waveguide core and multiple constraint rod layers into a unified optical structure.

[0016] This invention provides a photonic device and a method for manufacturing an optical fiber for efficiently coupling light between an on-chip waveguide and an external optical fiber (e.g., coupling into and / or out of the on-chip waveguide). The device includes a waveguide disposed in a waveguide layer and having a tapered portion that reduces its width toward the end face of a photonic integrated circuit (PIC) chip. In at least one layer below and at least one layer above the waveguide, constraining rods (e.g., an array of constraining rods) surround the waveguide, their width increasing toward the end face. These features collectively create a spot size converter configured to transition the optical mode from a confined cross-section in the waveguide to a larger cross-section at the chip end face, thereby optimizing fiber coupling.

[0017] In one embodiment, the waveguide may be formed from a high-refractive-index material, such as silicon or silicon nitride. The waveguide layer may be part of a silicon-on-insulator (SOI) platform, with the waveguide core formed in the top silicon device layer of the SOI. This arrangement utilizes standard microelectronic processes.

[0018] This invention envisions multiple constrained rod layers beneath and above a waveguide, wherein at least three distinct rod layers can be used for enhanced mode control. Each rod layer may contain multiple rods whose width increases as the waveguide narrows, thereby providing a complementary tapering pattern to smoothly guide optical modes. Optionally, the waveguide taper angle relative to its longitudinal axis falls between approximately 0.01° and 0.1°. The taper of the constrained rods and / or the waveguide may include: a width variation of approximately several hundred nanometers over a length range of approximately several hundred nanometers, with a taper angle between approximately 0.01° and 0.1°.

[0019] The constraint rod itself can take on various cross-sectional shapes—rectangular, cylindrical, or ribbed—and is typically formed of a dielectric material with a lower refractive index than the waveguide, thereby facilitating supermodes across the waveguide and surrounding rods. To maintain the designed optical field distribution and reduce scattering, the rod and waveguide are typically encapsulated with a cladding layer. In some embodiments, the constraint rod is formed of a dielectric material similar to the dielectric material forming the waveguide.

[0020] To further customize the dimensions, each constraint bar can have a thickness of approximately 200 nanometers to approximately 500 nanometers and a width of approximately 150 nanometers to approximately 600 nanometers. These ranges help shape the mold profile and ensure effective coupling.

[0021] In another embodiment, the photonic device for edge coupling includes a substrate having multiple dielectric layers, including waveguide layers and at least one constraint rod layer, and a tapered waveguide whose width decreases towards the end face. One or more constraint rods in these layers also have widths that increase towards the end face. Together, the rods and the tapered waveguide form a supermode that transitions from a smaller on-chip waveguide to a larger fiber-compatible mode.

[0022] The present invention also relates to a method for manufacturing such a photonic device. The method includes: providing a suitable substrate; forming a waveguide core that tapers towards a chip end face; and arranging constraint bars in layers above and below the waveguide, such that each bar tapers in opposite directions. The waveguide layers may be crystalline silicon or silicon nitride, and can potentially be implemented on an SOI wafer.

[0023] To form the constrained rod, rod-forming material can be deposited in at least two rod-forming layers oriented substantially parallel to the longitudinal axis of the tapered waveguide, the material is then photolithographically patterned and etched. Preferably, the taper angles for fabricating the waveguide tapered portion and the rod are coordinated so that the evolved optical mode—often called a supermode—comprises both the waveguide core and the rod.

[0024] In many embodiments, one or more cladding layers can be deposited to encapsulate the spot size converter region, thereby maintaining optical constraint and reducing unwanted scattering. Alternative rod geometries, such as rectangular, cylindrical, or rib-shaped, can be used. Selecting precise rod dimensions helps achieve the target optical mode size at the end face. Finally, while forming the waveguide tapered portion (by reducing the width by at least 50%), the width of each rod is increased by at least 50% in the same direction, producing a complementary tapered profile that is beneficial for efficient mode conversion.

[0025] In summary, the invention described herein provides a robust method for reducing insertion loss at the fiber-chip interface by controlling the geometry of the waveguide taper and surrounding constraint rods. The layered taper design forms an efficient spot size converter with a smaller footprint and enhanced manufacturing tolerances, enabling higher coupling efficiency for a wide range of photonic applications.

[0026] The above and other features of the invention, including various novel structural details and combinations of components, as well as other advantages, will now be described more fully with reference to the accompanying drawings and pointed out in the claims. It should be understood that the methods and apparatus for specifically implementing the invention are shown for illustrative purposes and not for limiting the invention. The principles and features of the invention can be implemented in various different embodiments without departing from the scope of the invention. Attached Figure Description

[0027] In the accompanying drawings, the reference numerals consistently indicate the same components in different views. The drawings are not necessarily drawn to scale; rather, the focus is on illustrating the principles of the invention. In the accompanying drawings: Figure 1 This includes a top view and various cross-sectional views of a photonic integrated circuit including a spot size converter, based on the currently disclosed invention; Figure 2A , Figure 2B and Figure 2C This is a cross-sectional view of an embodiment of the speckle size converter according to the present invention; and Figure 3A and Figure 3B These are transmission diagrams of a conventional spot size converter and a spot size converter according to the present invention. Detailed Implementation

[0028] The invention will now be described more fully below with reference to the accompanying drawings, which illustrate illustrative embodiments of the invention. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments described herein; these embodiments are provided to make this disclosure exhaustive and complete, and to fully convey the scope of the invention to those skilled in the art.

[0029] The term “and / or” as used herein includes any and all combinations of one or more of the related listed items. Furthermore, all conjunctions used should be understood to be as inclusive as possible. Therefore, unless the context explicitly requires otherwise, the word “or” should be understood as logical “or” rather than logical “XOR”. Additionally, the singular forms and the articles “a,” “one,” and “described” are intended to also include the plural forms unless otherwise explicitly stated. It should also be understood that the terms “includes,” “comprises,” “including,” and / or “comprising” as used in this specification indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. It will be further understood that when an element (including components or subsystems) is referred to and / or shown as connected to or coupled to another element, it may be directly connected to or coupled to the other element, or there may be intermediate elements present.

[0030] It will be understood that although terms such as “first” and “second” are used herein to describe the various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Thus, an element discussed below may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the teachings of the invention.

[0031] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0032] In general, this invention can be categorized as a structural or device-level innovation. It demonstrates a novel approach to array spot size converters, using constraint rods in multiple vertical layers around a centrally located functional waveguide to achieve highly efficient fiber-to-chip coupling with a smaller footprint and reduced complexity compared to conventional methods.

[0033] Figure 1 This includes a top view and various cross-sectional views of the photonic integrated circuit (PIC) chip 10 according to the currently disclosed invention.

[0034] refer to Figure 1Part (A), a top view, shows an array of constraint bars. The constraint bars are arranged around a waveguide 100, which gradually narrows into a spot size converter (SSC) as it approaches the edge or end face 52 of a photonic integrated circuit (PIC) chip 10. Specifically, the waveguide 100 begins with a characteristic width within the chip, but as it approaches the edge, it transitions to a tapered segment 100T, which tapers, for example, linearly, such that its width is reduced by at least 50%, or possibly by 75% or even 80% or more, upon reaching the edge 52 of the chip 10. For example, the width of the waveguide may taper such that its width is reduced by 50% to 90% upon reaching the edge 52 of the chip 10. Simultaneously, the constraint bars taper in the opposite manner, such that the constraint bars increase in width linearly in the direction toward the edge 52. The length of the tapered segment 100T can be on the order of hundreds of micrometers (e.g., hundreds of micrometers) and / or can be based on the operating wavelength of the PIC chip 10 (e.g., increasing as the wavelength decreases), for example, using a relatively large length for a relatively short operating wavelength and a relatively short length for a relatively long operating wavelength.

[0035] In the example shown, the constraint rods are organized in several (e.g., three) layers below waveguide 100 and one or more layers above waveguide 100. Alternatively, rods can be added to the same layers as waveguide 100.

[0036] Specifically, in the example shown, in the lowest layer 0 immediately above the lower cladding layer and the silicon substrate wafer 50 on silicon or insulator, there is a Layer 0 constraint rod 112 extending parallel to and directly below the tapered segment 100T of the waveguide.

[0037] In the next higher Layer 1, there is a group of several (e.g., four) Layer 1 constraint rods 122, 124, 126, and 128 that extend parallel to the tapered segment 100T of the waveguide.

[0038] In the next higher layer, Layer 2, there is a group of several (e.g., four) Layer 2 constraint rods 132, 134, 136, and 138 extending parallel to the taper segment 100T of the waveguide. The taper segment 100T of the waveguide is located in Layer W, which is slightly higher than Layer 2. The presence of rods in the continuous layers of Layer 0, Layer 1, and Layer 2 ensures a gradual correction of the effective refractive index environment around the waveguide, promoting efficient mode conversion. Because the waveguide core rises relative to the lower layer of constraint rods, the rods in Layer 0, Layer 1, and Layer 2 primarily shape the optical field from below.

[0039] Then, in Layer 4 above waveguide 100T, three Layer 4 constraint rods 152, 154, and 156 extend parallel to the tapered segment 100T of the waveguide. These rods provide an upper boundary that complements the lower constraint rods, thereby enhancing vertical and lateral optical constraint.

[0040] Notably, in the region near the chip end face 52, the constraint rods in each layer are designed to taper in the opposite manner to the waveguide tapered portion. As the waveguide narrows at the edge, the constraint rods gradually widen (or increase in cross-sectional size) in the same direction. This complementary taper arrangement—combining waveguide narrowing with rod widening—allows for a smoother transition of optical modes, reducing reflection and scattering losses. By customizing the placement, spacing, and width of the rods in each layer, the spot size converter can more effectively expand or compress the guided modes for coupling with external optical fibers at the chip edge. The taper of the constraint rods and / or waveguide 100 can include width variations on the order of hundreds of nanometers, length variations on the order of hundreds of nanometers, and taper angles between approximately 0.01° and 0.1°.

[0041] Generally, each constraint bar has a thickness ranging from about 50 nanometers to about 150 nanometers and a width at its widest point ranging from about 150 nanometers to about 600 nanometers.

[0042] Figure 1 Part (B) presents a cross-sectional view of the photonic integrated circuit (PIC) chip 100 before the constrained bar array is introduced closer to the chip edge 52. In this particular cross-section, the waveguide 100 located in Layer W passes through the chip as it would normally be in the inner region without any special pattern around it.

[0043] Below Layer W, three material layers—Layer 0, Layer 1, and Layer 2—are stacked on top of the chip's lowest cladding layer and the substrate wafer 50, which can be silicon or silicon-on-insulator. In this pre-constraint formation section, since the constraint bars have not yet begun to form, these lower layers appear as a uniform dielectric film such as SiO2. The waveguide 100, typically composed of a high-refractive-index material such as silicon or silicon nitride, is itself shown in cross-section in Layer W. It is surrounded by a standard cladding material that helps guide light within the waveguide core.

[0044] Above the waveguide layer is Layer 4. In this cross-sectional slice, Layer 4 also remains unpatterned, serving merely as another uniform dielectric film. Closer to the chip edge, Layer 4 eventually houses the upper constraint bars used for spot size transitions. However, in section (B), this cross-section emphasizes the chip baseline structure before the transition region where the constraint bars begin to appear, namely the continuous dielectric layers above and below the waveguide.

[0045] Figure 1 Part (C) provides a cross-sectional snapshot of the photonic integrated circuit (PIC) chip 10 exactly at its edge 52, where the waveguide 100T has been fully tapered to its narrowest width in Layer W. This taper is designed to match as closely as possible the mode size of the outer optical fiber that will couple light at the end face.

[0046] Compared to the reduced cross-section of the waveguide, the constraint bars in each of the lower and upper layers are widened to their maximum width at the chip edges. Specifically, in Layer 0, a single constraint bar 112 is shown at its maximum lateral extent. In Layer 1, four constraint bars (122, 124, 126, 128) are also widened to provide increasingly stronger refractive index contrast near the end face. Similarly, the four bars (132, 134, 136, 138) in Layer 2 reach their maximum width at this boundary, further contributing to the efficient guiding and transition of optical modes to the waveguide tapered section. Finally, in Layer 4, a set of constraint bars (152, 154, 156) appears above the waveguide at their maximum width, providing supplementary top-side constraints to the lower layers.

[0047] This coordinated taper of the waveguide core (narrowed) and the constraint rod (widened) creates a smooth mode transition region, reducing scattering and reflection losses. As a result, light traveling through the fully tapered waveguide 100T at the edges is coupled more efficiently into or out of the external fiber. Therefore, the cross-section shown in section (C) highlights how precisely both the waveguide and rod geometry can be designed to optimize edge coupling performance.

[0048] In some embodiments, the dielectric thickness between the functional waveguide (e.g., waveguide 100) and each constraint bar layer is up to 500 nanometers. The dielectric thickness can be increased with the operating wavelength of the PIC chip 10.

[0049] Figure 2A This is a cross-sectional view of another embodiment of the SSC at edge 52 of the photonic integrated circuit (PIC) chip 10. The waveguide 100T has been narrowed to its minimum width. This taper of the waveguide is designed to more closely match the optical modes of the external optical fiber and reduce coupling loss. Surrounding the waveguide are multiple layers of constraint bars, each carefully configured to widen at the chip edge as the waveguide tapers.

[0050] Below the waveguide, Layer 0 contains a single rod (112), which is shown at its maximum lateral extent at the end face. Above it, Layer 1 includes four rods (122, 124, 126, 128), and Layer 2 has another four rods (132, 134, 136, 138). As in the previous embodiment, these rods in the lower layers collectively guide and shape the light as it transitions through the narrowed waveguide core.

[0051] However, with Figure 1 The version depicted in section (C) differs; Layer 4 has four bars (152, 154, 156, 158) instead of three. These top-level bars also reach their widest dimensions at the chip edges, providing additional control over the vertical constraint of the waveguide. By distributing the optical modes between the lower and upper constraint structures, this design creates a smoother transition region at the junction of the waveguide (100T) and the external fiber.

[0052] Overall, Figure 2A This demonstrates how including additional rods in Layer 4 can provide improved flexibility to customize the electromagnetic field distribution at the end face, making the coupling process more robust against manufacturing and alignment deviations.

[0053] Figure 2B This is a cross-sectional view of another embodiment of the photonic integrated circuit (PIC) chip 10 at edge 52 of the SSC. The waveguide 100T has been tapered to its narrowest width. This taper reduces the optical mode size to more closely match the external fiber, thereby improving coupling efficiency. Surrounding the tapered waveguide is an array of constraint rods arranged in multiple layers, each designed to provide lateral and vertical mode constraints.

[0054] Below the waveguide, Layer 0 contains a single constraint rod (112) that expands to its maximum width near the chip endface. Moving upwards, Layer 1 has four rods (122, 124, 126, 128), all reaching their maximum width at the edges. However, in Layer 2, the design has been simplified compared to earlier embodiments: there are now only two rods (132, 134) instead of four. These two rods still widen as they approach the endface, guiding light through the narrowing waveguide core.

[0055] Above the waveguide in Layer W, Layer 4 contains its own set of rods (152, 154, 156), similarly extending to their widest dimensions at the edges. Together, the rods above and below the waveguide work together to shape the optical mode in this transition region. Choosing to use only two rods from Layer 2 can simplify the manufacturing process or adjust how the mode is constrained, potentially affecting performance metrics such as insertion loss or sensitivity to alignment tolerances.

[0056] Overall, Figure 2B A design variation of the constraint bar arrangement is shown, in which the total number of constraint bars in Layer 2 is reduced, while still providing effective constraint and mode matching for the waveguide at the chip edge.

[0057] Figure 2C This is a cross-sectional view of another embodiment of the SSC at the edge (52) of the photonic integrated circuit (PIC) chip (10). Again, the waveguide (100T) is narrowed to its minimum width to improve coupling with the external optical fiber. As in the previous embodiment, the tapered waveguide is surrounded by constraint bars in multiple layers—Layer 0, Layer 1, Layer 2, and Layer 4—all of which reach their maximum width at the end face.

[0058] In this particular design, there is now an additional Layer 5 above Layer 4. This new layer contains three constraint rods (162, 164, 166), each positioned to help maintain tight control in both the vertical and lateral directions as the optical mode transitions from the narrow waveguide core. By stacking another set of rods on top of the waveguide's top layer, the device provides an enhanced refractive index contrast gradient, potentially reducing reflections and improving overall coupling efficiency.

[0059] Below the waveguide, Layer 0 still comprises a single rod (112), while Layer 1 and Layer 2 each contain multiple rods (122, 124, 126, 128 and 132, 134, respectively). Above the waveguide in Layer 4, the rods (152, 154, 156) also maintain a widened profile near the edges. Now, with Layer 5 also contributing, the constraining rods collectively form a more comprehensive framework for guiding the optical modes.

[0060] This additional layer highlights the flexibility designers have in customizing rod arrangements to meet specific performance requirements. The inclusion of Layer 5 rods (162, 164, 166) illustrates how vertical stacking of rods can be extended to further refine edge coupling behavior, both in balancing manufacturing complexity and optimizing optical constraints.

[0061] Fiber-to-chip optical interconnects play a crucial role in integrating application-specific photonic integrated circuits (PICs) into larger systems. Two main coupling strategies are typically employed: off-plane coupling via grating couplers and in-plane coupling via spot size converters (SSCs). Although grating couplers can facilitate alignment, in-plane coupling remains attractive in many cases due to its potential for lower insertion loss—provided that the waveguide modes on the chip can be expanded to match the larger mode area of ​​the external fiber.

[0062] In practice, most of the functionality of a PIC is performed in a highly constrained waveguide, which provides a small cross-section for efficient switching, modulation, and filtering. Tightly constraining optical modes in these regions reduces chip footprint and power consumption, but when it comes to interfacing with fiber optics, these small modes lead to significant mode size mismatch. SSCs aim to gradually transition from compact waveguide modes on-chip to larger modes better suited for low-loss coupling to fiber, thereby reducing overall insertion loss.

[0063] Figure 3A This is a graph showing the transmission of data from a conventional spot size converter.

[0064] Figure 3A The graph in the figure illustrates the transmission performance of a conventional spot-size converter (SSC) where the waveguide is not part of the layer supporting the supermode. This configuration typically results in a longer device length due to the more gradual mode transition. The graph presents two transmission curves, corresponding to the transverse electric (TE) mode and the transverse magnetic (TM) mode, where transmission loss is measured in decibels (dB) along the y-axis and the taper length L2 is measured in micrometers (μm) along the x-axis.

[0065] In the example shown, the TE curve represents the transmission from the end face side to the waveguide side, while the TM curve represents the transmission from the waveguide side to the end face side.

[0066] The TE mode curve starts at -1.1 dB at approximately 800 μm, increases sharply to -0.2 dB at approximately 1700 μm, and then continues to increase gradually, reaching approximately -0.1 dB at 3000 μm. The TM mode curve starts at -1.1 dB at approximately 500 μm, increases sharply to approximately -0.3 dB at approximately 900 μm, increases more gradually to -0.2 dB between 1100 μm and 1900 μm, and then gradually decreases back to -0.3 dB at 3000 μm.

[0067] A vertical reference line is plotted at 1700 μm, where the TE and TM curves intersect. This indicates a significant transmission improvement at this length. Therefore, conventional SSC designs require a relatively long taper of 1800 μm to achieve sufficient mode conversion and low loss. The total device length required for effective mode conversion is quite large.

[0068] Figure 3B This is a graph showing the transmission of the spot size converter according to the present invention.

[0069] More specifically, Figure 3BThe transmission performance of the spot-size converter (SSC) according to the present invention is shown, wherein waveguides are integrated within (or even at the center of) the supermode layers. This approach results in a significantly shorter device while maintaining high transmission efficiency. The graph presents the transmission results for the TE and TM modes, where transmission is measured in dB along the y-axis and the slow segment length is measured in micrometers (μm) along the x-axis. The y-axis is labeled “Transmission (dB)” and ranges from -0.5 dB to 0 dB in increments of 0.05 dB, and the x-axis is labeled “Slow Segment Length (μm)” and ranges from 0 μm to 500 μm in increments of 50 μm.

[0070] In the example shown, the TE mode curve starts at -0.5 dB at approximately 60 μm, increases sharply to -0.025 dB at approximately 350 μm, and decreases slightly to -0.05 dB at approximately 500 μm. The TM mode curve starts at -0.5 dB at approximately 25 μm, increases sharply to -0.1 dB at approximately 200 μm, and remains almost constant at -0.1 dB until 500 μm.

[0071] A vertical reference line was plotted at 225 μm, where both the TE and TM modes are approximately -0.1 dB, indicating the relationship with... Figure 3A Compared to conventional SSCs, efficient mode switching occurs within a shorter length (e.g., 400 μm). Therefore, for example, the present invention achieves efficient mode switching within a length of less than... Figure 3A Efficient mode conversion is achieved in a device that is one-quarter the length of a conventional SSC.

[0072] Although the invention has been shown and described with particular reference to its preferred embodiments, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the scope of the invention as covered by the appended claims.

Claims

1. A photonic device for coupling light into and / or out of an on-chip waveguide, comprising: A waveguide disposed in a waveguide layer, the waveguide having a tapered portion configured such that its width decreases toward the end face of the photonic integrated circuit chip; A constraining bar array is arranged around the tapered portion of the waveguide in at least one layer below the waveguide layer and at least one layer above the waveguide layer, each constraining bar having a width that increases toward the end face; The tapered waveguide and the constraint rod are configured together to form a spot size converter that transitions the optical mode from a confined cross-section within the waveguide to a larger cross-section at the end face.

2. The photonic device according to claim 1, wherein, The waveguide comprises a high refractive index material selected from the group consisting of silicon and silicon nitride.

3. The photonic device according to claim 2, wherein, The waveguide layer is part of a silicon-on-insulator (SOI) platform, and the waveguide is formed in the top silicon device layer of the SOI platform.

4. The photonic device according to any one of claims 1-3, wherein, The constraint bar array is arranged in at least three different constraint bar layers located below and above the waveguide layer.

5. The photonic device according to claim 4, wherein, Each constraint bar layer contains multiple bars configured such that the bar width increases as the waveguide width decreases to define a complementary tapered pattern.

6. The photonic device according to any one of claims 1-5, wherein, The tapered portion of the waveguide has a tapered angle between 0.01° and 0.1° relative to the longitudinal axis of the waveguide.

7. The photonic device according to any one of claims 1-6, wherein, The constraint bar has a cross-sectional shape selected from a group consisting of rectangular bars, cylindrical bars, or ribbed bars.

8. The photonic device according to claim 7, wherein, The constraint rod is formed of a dielectric material with a refractive index lower than that of the waveguide material, thereby defining a supermode that includes both the waveguide and the constraint rod.

9. The photonic device according to any one of claims 1-8, further comprising an cladding layer surrounding the waveguide and the constraint rod, such that the spot size converter region is encapsulated to maintain the designed optical field distribution.

10. The photonic integrated circuit according to any one of claims 1-9, wherein, Each constraint bar has a thickness ranging from approximately 50 nanometers to approximately 150 nanometers and a width ranging from approximately 150 nanometers to approximately 600 nanometers.

11. A photonic device for edge coupling, comprising: Substrate; Multiple dielectric layers are formed above the substrate, including a waveguide layer and one or more constraint rod layers; A waveguide located in the waveguide layer, the waveguide having a first width through the main portion of the photonic circuit and transitioning to a narrower width at the end face of the photonic circuit; One or more constraint bar arrays are disposed in at least two different constraint bar layers, each constraint bar layer including at least one constraint bar extending toward the end face, the constraint bar taper to a wider cross-section as it approaches the end face; The constraint rod and the tapered waveguide together define a supermode that extends from a narrower waveguide region to a larger mode suitable for coupling with an external optical fiber.

12. A method of manufacturing a photonic device for coupling light between an optical fiber and an on-chip waveguide, the method comprising: A substrate having at least one dielectric layer suitable for forming a waveguide layer is provided; A waveguide core is formed in the waveguide layer, wherein the waveguide core is configured to guide light along the longitudinal axis; A tapered portion defining the waveguide core, wherein the width of the tapered portion decreases towards the end face of the substrate; An array of constraint bars is formed in at least one layer below the waveguide layer and at least one layer above the waveguide layer, wherein each constraint bar has a width that increases toward the end face; A tapered waveguide core and a constrained rod array are arranged to create a spot size converter region at the end face, wherein the spot size converter is configured to transition the optical mode from the waveguide core to a larger mode suitable for coupling with an optical fiber.

13. The method according to claim 12, wherein, The waveguide layer comprises crystalline silicon or silicon nitride, and the waveguide core is formed therein by photolithographic patterning and etching of the waveguide layer.

14. The method according to claim 13, wherein, The substrate provided includes: using a silicon-on-insulator (SOI) wafer such that a waveguide core is formed in a top silicon device layer of the SOI wafer, and the dielectric layer is an oxide layer.

15. The method according to any one of claims 12-14, wherein, Forming a constraint bar array includes: Deposit rod-forming material in at least two constrained rod layers. Photolithography is used to pattern each constraint bar layer, and The etched bar forming material is used to form multiple bars that are substantially parallel to the longitudinal axis orientation of the tapered waveguide core.

16. The method according to claim 15, wherein, The steps of defining the tapered portion of the waveguide core and forming the constrained rod array are coordinated so that the tapered angle of the waveguide core and the corresponding tapered angle of the rods together shape the supermodel containing both the waveguide core and the rods.

17. The method according to any one of claims 12-16, further comprising: One or more cladding layers are deposited above and / or below the waveguide layer and the constraint rod to encapsulate the spot size converter region to maintain optical constraint and reduce scattering loss.

18. The method according to any one of claims 12-17, wherein the constraining bar array is formed having a cross-sectional shape selected from rectangular bars, cylindrical bars, or rib structures, and wherein the size of each bar is selected to achieve a target optical modulus size at the end face.

19. The method according to any one of claims 12-18, wherein forming the tapered portion comprises: The waveguide core width is reduced by at least 50% from the internal region of the photonic device to the end face, and the formation of the constraint rods includes increasing the width of each rod by at least 50% in the same direction, thereby providing a complementary tapered profile for effective mode conversion.

Images