Method and apparatus for scalable exclusive access management in memory systems

Abstract

The present disclosure provides systems, methods, and apparatuses for memory systems to support enhanced exclusive read and write operations and a scalable exclusive monitor architecture. In one aspect, an apparatus includes a processing system comprising one or more shared memory devices and one or more request nodes. The processing system further includes one or more network interface units (NIUs), each of the one or more NIUs comprising an exclusive monitor configured to monitor exclusive access to a shared memory address by a corresponding request node. The processing system includes one or more master nodes coupled to a corresponding shared memory device of the one or more shared memory devices. The processing system further includes an interconnect coupled to each NIU and each master node and configured to couple the one or more request nodes to the one or more shared memory devices. Other aspects and features are also claimed and described.

Description

Cross-references to related applications

[0001] This application claims the benefit of U.S. Patent Application No. 18 / 610,080, filed March 19, 2024, entitled “METHOD AND APPARATUS FOR SCALABLE EXCLUSIVE ACCESS MANAGEMENT IN MEMORY SYSTEMS,” the entire contents of which are expressly incorporated herein by reference. Technical Field

[0002] This disclosure relates generally to system-on-a-chip (SoC) architecture, and more specifically to memory systems for storing data. Several features enable a scalable exclusive monitor architecture and provide improved memory capabilities to enhance exclusive read and write operations. Background Technology

[0003] Computing devices (e.g., laptops, mobile phones, etc.) may include one or more processors to perform various computing functions, such as telephony, wireless data access, and camera / video functions. A memory system is a crucial component of a computing device. The processor may be coupled to the memory system to perform the aforementioned computing functions. For example, the processor may fetch instructions from the memory system to perform computing functions and / or store temporary data involved in performing these computing functions within the memory system.

[0004] Memory systems can utilize memory cells that are inherently volatile. Volatile memory cells retain information for short periods (such as fractions of a second). Refresh operations can be performed on volatile memory cells to maintain information for longer periods. In an example volatile memory cell where information is stored as electrical charge, the charge decays within fractions of a second. The memory cell can be refreshed to extend the time the memory cell retains information before the charge decays beyond the point at which the information is lost. In some cases, refresh operations can be performed repeatedly to extend the storage period of information indefinitely, or simply as long as the circuitry is powered. This refresh operation consumes power, which affects the operation of devices that operate from finite power sources (such as mobile devices that operate on battery power).

[0005] System-on-a-Chip (SoC) architectures may include memory systems with multiple shared memory devices shared by multiple CPUs (such as their cores, chips, or dies). In distributed SoC architectures, multiple CPUs may attempt to access the same shared data. SoCs utilize exclusive data access monitors to track exclusive data access to shared memory. As SoC systems evolve (such as with increased DDR memory channels and / or increased CPUs), the number of exclusive monitors used to track exclusive access to data grows exponentially, occupying a large and increasing portion in larger and / or more advanced SoCs. Summary of the Invention

[0006] The following summary outlines some aspects of this disclosure to provide a basic understanding of the techniques discussed. This summary is not an exhaustive overview of all the intended features of this disclosure, nor is it intended to identify key or essential elements of all aspects of this disclosure, nor to define the scope of any or all aspects of this disclosure. The sole purpose of this summary is to present, in a general form, some concepts of one or more aspects of this disclosure as a prelude to the more detailed description that follows.

[0007] In one aspect, an apparatus includes a processing system comprising: one or more shared memory devices, each of the one or more shared memory devices including a plurality of shared memory addresses; one or more requesting nodes, each requesting node corresponding to a processor of the processing system; one or more network interface units (NIUs), each of the one or more NIUs including an exclusive access monitor configured to monitor exclusive access of a corresponding requesting node to the plurality of shared memory addresses; one or more master nodes, each of the one or more master nodes coupled to a corresponding shared memory device in the one or more shared memory devices; and an interconnect coupled to each of the one or more NIUs and each of the one or more master nodes, and configured to couple the one or more requesting nodes to the one or more shared memory devices.

[0008] In an additional aspect, a method for exclusive access management includes: a requesting node receiving a read data completion message, the read data completion message including data associated with an exclusive read request for a specific memory address of a shared memory device and indicating that the specific memory address has been read; the requesting node activating an exclusive monitor based on the read data completion message; the requesting node transmitting an exclusive write request for the specific memory address to a master node associated with the shared memory device; the requesting node transmitting a snoop query response message for the specific memory address to the master node, the snoop query response message indicating a hit and responding to a snoop query message from the master node associated with the exclusive write request; the requesting node receiving a snoop cleanup message for the specific memory address from the master node in response to the snoop query response message; and the requesting node clearing the exclusive monitor based on the snoop cleanup message for the specific memory address.

[0009] In an additional aspect, a method for exclusive access management includes: transmitting an exclusive read request for a specific memory address from a requesting node to a master node associated with a shared memory device; the master node reading data associated with the specific memory address from the shared memory device; the master node transmitting a read data completion message including the data associated with the specific memory address; the requesting node activating an exclusive monitor based on the read data completion message; transmitting a read completion acknowledgment from the requesting node to the master node; transmitting an exclusive write request for the specific memory address from the requesting node to the master node; and the requesting node receiving data from the master node in response to the exclusive write request for the specific memory address. The process includes: sending a snooping query message for a specific memory address to the master node; sending a snooping query response message for a specific memory address to the master node, the snooping query response message indicating a hit; the master node writing data from the shared memory device to the specific memory address in response to the snooping query response message indicating a hit; the requesting node receiving a snooping cleanup message for the specific memory address from the master node in response to the snooping query response message indicating a hit; the requesting node clearing the exclusive monitor based on the snooping cleanup message for the specific memory address; and the master node sending a write completion message for the specific memory address to the requesting node in response to receiving a snooping cleanup response from each of the requesting nodes.

[0010] In an additional aspect, a method for exclusive access management includes: having a requesting node put an exclusive monitor on standby based on a read data completion message for a specific memory address associated with a shared memory device, the read data completion message being received from a master node and in response to an exclusive read request for the specific memory address from the requesting node; and having the requesting node clear the exclusive monitor based on a snoop cleanup message for the specific memory address received from the master node, the snoop cleanup message being associated with an exclusive write request for the specific memory address from the requesting node.

[0011] In an additional aspect of this disclosure, an apparatus (such as a wireless device) includes at least one processor and memory coupled to the at least one processor. The at least one processor is configured to communicate with the memory system via a memory controller coupled to a channel that couples the processor to the memory system. The processor may be a processor, controller, or other logic circuitry in a host computer.

[0012] In an additional aspect of this disclosure, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform the operations described herein with respect to various aspects of this disclosure.

[0013] The memory system of this disclosure can be embedded within a processor on a semiconductor die or as part of a different semiconductor die. The memory system can be of various types. For example, the memory can be static random access memory (SRAM), dynamic random access memory (DRAM), magnetic random access memory (MRAM), NAND flash memory, or NOR flash memory, etc.

[0014] The methods and apparatuses presented in this disclosure are given as non-limiting examples of low-power double data rate (LPDDR) synchronous dynamic random access memory (SDRAM). For example, an LPDDR memory operating according to the LPDDR specification issued by the Joint Electronic Equipment Committee (JEDEC). One such LPDDR specification could be LPDDR5. Another such LPDDR specification could be LPDDR6.

[0015] Other aspects, features, and specific embodiments will become apparent to those skilled in the art when they review the following description of particular exemplary aspects in conjunction with the accompanying drawings. Although features may be discussed hereinafter with reference to certain aspects and drawings, various aspects may include one or more of the advantageous features discussed herein. In other words, while one or more aspects may be discussed having certain advantageous features, one or more such features may also be used depending on the various aspects. Similarly, although exemplary aspects may be discussed hereinafter as aspects of an apparatus, system, or method, exemplary aspects can be implemented in various apparatuses, systems, and methods.

[0016] This method can be embedded as computer program code in a computer-readable medium, the computer program code including instructions that cause a processor to perform the steps of the method. In some embodiments, the processor may be part of a mobile device including: a first network adapter configured to transmit data, such as recorded images or videos or streaming data, via a first network connection among a plurality of network connections. The processor may be coupled to the first network adapter and memory for storing data to support processing and communication operations performed by the processor. The network adapter may support communication on a wireless communication network such as a 5G NR communication network. The processor may cause data stored in the memory to be transmitted via the wireless communication network.

[0017] The features and technical advantages of the examples according to this disclosure have been summarized rather extensively above in order to better understand the detailed description below. Additional features and advantages will be described below. The disclosed concepts and specific examples can be readily utilized as the basis for modifying or designing other structures for achieving the same purpose of this disclosure. Such equivalent constructions do not depart from the scope of the appended claims. The characteristics of the concepts disclosed herein (both their organization and manner of operation) and their associated advantages will be better understood in conjunction with the accompanying drawings, based on the following description. Each figure in the accompanying drawings is provided for illustrative and descriptive purposes and not as a limitation of the definitions in the claims.

[0018] While aspects and implementations are described herein by way of example, those skilled in the art will understand that additional implementations and use cases may arise in many different arrangements and scenarios. The innovations described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and package arrangements. For example, aspects and / or devices may be implemented via integrated chip implementations and other devices based on non-modular components (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail / purchasing devices, medical devices, AI-enabled devices, etc.). While some examples may or may not specifically point to use cases or applications, applicability to various types of the described innovations is possible. The scope of implementations ranges from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems incorporating one or more aspects of the described innovations. In some practical settings, devices incorporating the described aspects and features may also necessarily include additional components and features for implementing and practicing the claimed and described aspects. For example, the transmission and reception of wireless signals necessarily involve multiple components (e.g., hardware components, including antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processors, interleavers, adders / summers, etc.) for analog and digital purposes. The innovations described herein are intended to be implemented in a variety of devices, chip-level components, systems, distributed arrangements, end-user equipment, etc., with different sizes, shapes, and constructions. Attached Figure Description

[0019] A further understanding of the nature and advantages of this disclosure can be achieved by referring to the following figures. In the figures, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by adding a dash after the reference numerals and a second reference numeral for differentiation between similar components. If only the first reference numeral is used in the specification, the description applies to any one of the similar components having the same first reference numeral, regardless of the second reference numerals.

[0020] Figure 1 A block diagram of an example computing system comprising a host, a memory system, and a channel coupling the host and the memory system, according to one or more aspects of this disclosure, is shown.

[0021] Figure 2 A block diagram of an example computing system comprising a host, a memory system, and a channel coupling the host and the memory system, according to one or more aspects of this disclosure, is shown.

[0022] Figure 3A and Figure 3BA waveform illustrating data transfer via an example channel during a write operation, according to certain aspects of this disclosure, is shown.

[0023] Figure 4A and Figure 4B A waveform illustrating data transfer via an example channel during a read operation according to certain aspects of this disclosure is shown.

[0024] Figure 5 This is a block diagram illustrating an example of a system-on-chip (SoC) supporting exclusive read and write operations according to some embodiments of this disclosure.

[0025] Figure 6 This is a flowchart illustrating operations for exclusive read and write operations according to some embodiments of this disclosure.

[0026] Figure 7 This is a block diagram illustrating an example SoC with a scalable exclusive monitor architecture and support for enhanced exclusive read and write operations according to some embodiments of this disclosure.

[0027] Figure 8 This is a flowchart illustrating examples of enhanced exclusive read and write operations according to some embodiments of this disclosure.

[0028] Figure 9 This is a flowchart illustrating examples of enhanced exclusive read and write operations according to some embodiments of this disclosure.

[0029] Figure 10 This is a flowchart illustrating an example of a method for enhanced exclusive read and write operations according to some embodiments of this disclosure.

[0030] Figure 11 This is a flowchart illustrating an example of a method for enhanced exclusive read and write operations according to some embodiments of this disclosure.

[0031] Similar reference numerals and names in the various figures indicate similar elements. Detailed Implementation

[0032] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to limit the scope of this disclosure. Rather, the detailed description includes specific details for providing a thorough understanding of the subject matter of the invention. It will be apparent to those skilled in the art that these specific details are not necessary in every situation, and in some cases, well-known structures and components are shown in block diagram form for clarity of presentation.

[0033] This disclosure provides systems, apparatus, methods, and computer-readable media that support data processing, including designs and techniques for utilizing exclusive monitors upstream of the requesting node (RN) side of an interconnect and the master node (HN) associated with a shared memory device. The aspects described herein also include support for enhanced exclusive read and write operations, including receiving status information at the HN from the RN to the exclusive monitor (EM) on the RN side of the memory interconnect using snooping messages or other consistency mechanisms.

[0034] Specific implementations of the subject matter described in this disclosure may be implemented to achieve one or more of the following potential advantages or benefits. In some aspects, this disclosure provides a scalable solution for providing exclusive access management to shared data. For example, the EM can be moved to a Network Interface Unit (NIU) associated with or integrated with the RN. Moving the EM to the NIU saves more space and reduces the number of EMs, and the more DDR channels and RNs there are, the more space is saved and the fewer EMs are reduced. The solution is also backward compatible with current exclusive data commands and can leverage existing snooping or data consistency commands and mechanisms to allow the HN to still manage exclusive access to shared memory. In addition, the expansion has no impact on timing, and the area required for the expansion grows linearly rather than exponentially. Furthermore, the scalable architecture of the EM in the NIU provides compatibility and support for a wide range of SoC architectures.

[0035] Figure 1 An example memory device that can incorporate aspects of this disclosure is shown, including an exclusive monitor located on the RN side of the RN-to-memory interconnect. Figure 1 An apparatus 100 is illustrated, comprising a host 110, a memory 150, and a channel 190 coupling the host 110 and the memory 150. The apparatus 100 may be a device in, for example, a computing system (e.g., a server, data center, desktop computer), a mobile computing device (e.g., a laptop computer, a cellular phone, a vehicle, etc.), an Internet of Things (IoT) device, a virtual reality (VR) system, an augmented reality (AR) system, an automotive system (e.g., a driver assistance system, an autonomous driving system), an image capture device (e.g., a standalone digital camera or digital video camera, a camera-equipped wireless communication device such as a mobile phone, a cellular or satellite radio phone, a personal digital assistant (PDA), a panel or tablet computer, a gaming device, a computing device such as a webcam, a video surveillance camera, or other devices with digital imaging or video capabilities), and / or a multimedia system (e.g., a television, an optical disc player, a streaming device).

[0036] Host 110 may include at least one processor, such as a central processing unit (CPU), graphics processing unit (GPU), digital signal processor (DSP), multimedia engine, and / or neural processing unit (NPU). Host 110 may be configured to couple and communicate with memory 150 (e.g., memory 150-1 to 150-4) via channel 190 (e.g., channels 190-1 to 190-4) to perform computing functions (such as data processing, data communication, graphics display, camera, AR or VR rendering, image processing, neural processing, etc.). For example, memory 150-1 to 150-4 may store instructions or data for host to perform computing functions.

[0037] Host 110 may include memory controller 130, which may include controller PHY modules 134-1 to 134-4. Each of controller PHY modules 134-1 to 134-4 may be coupled to a corresponding memory 150-1 to 150-4 via a corresponding channel 190-1 to 190-4. For ease of reference, read and write are referred to from the perspective of host 110. For example, in a read operation, host 110 may receive stored data from one or more memories 150-1 to 150-4 via one or more channels 190-1 to 190-4. In a write operation, host 110 may provide data to be written to one or more memories 150-1 to 150-4 for storage via one or more channels 190-1 to 190-4. Memory controller 130 may be configured to control various aspects of communication to and from memories 150-1 to 150-4, such as the logical layer. The controller PHY modules 134-1 to 134-4 can be configured to control the electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) of signals provided or received on channels 190-1 to 190-4 respectively.

[0038] In some examples, memories 150-1 to 150-4 may be LPDDR DRAM (e.g., LPDDR5, LPDDR6). In some examples, memories 150-1 to 150-4 may be different types of memory, such as one LPDDR5, one LPDDR6, one flash memory, and one SRAM, respectively. Host 110, memories 150-1 to 150-4, and / or channels 190-1 to 190-4 may operate according to LPDDR (e.g., LPDDR5, LPDDR6) specifications. In some examples, each of channels 190-1 to 190-4 may include 16 data bits (e.g., 16 DQs). In some examples, each of channels 190-1 to 190-4 may operate on 32 data bits (e.g., 32 DQs). Figure 1The diagram shows four channels; however, the device 100 may include more or fewer channels, such as eight or sixteen channels.

[0039] exist Figure 2 Additional details are shown of one aspect of an embodiment of a device 100 for providing access to a memory system, such as one of memories 150-1 to 150-4 including logic and control circuitry. Figure 2 Examples Figure 1 The configuration of host 110, memory system 250, and channel 190. Channel 190 between host 110 and memory system 250 may include multiple connections, some of which carry data (e.g., user data or application data), and some of which carry non-data (e.g., address and other signaling information). For example, non-data connections in channel 190 may include a data clock (e.g., WCK) used when providing data to the corresponding memory system 250 on a per-byte basis, and a read data strobe (e.g., RDQS) used when receiving data from the corresponding memory system 250. Channel 190 may also include data masking (e.g., DM for indicating multiple functions performed by signaling connections, sometimes referred to as Data Mask Inversion DMI) signaling for masking certain portions of data during write operations. Channel 190 may also include commands and addresses (e.g., CA[0:n]) and associated CA clocks to provide commands (e.g., read or write commands) to memory system 250.

[0040] Host 110 may include at least one processor 120, which may include a CPU 122, a GPU 123, and / or an NPU 124. Host 110 may also include a memory controller 130 having a controller PHY module 134. Memory controller 130 may be coupled to at least one processor 120 via a bus system 115 to perform various computing functions. The term "bus system" may specify that the elements coupled to the "bus system" can exchange information directly or indirectly between them. In different embodiments, "bus system" may encompass multiple physical connections and intermediate levels such as buffers, latches, registers, etc. Modules may be implemented in hardware, software, or a combination of hardware and software.

[0041] Memory controller 130 can transfer and / or receive data blocks to and / or from other modules, such as at least one processor 120 and / or memory system 250. Memory system 250 may include memory controller 180 having a memory I / O module 160 (e.g., a PHY layer) configured to control electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) to provide or receive signals on the connection of channel 190. For example, memory I / O module 160 may be configured to capture (e.g., sample) data, commands, and addresses from host 110 via channel 190 and output data to host 110 via channel 190. Figure 3A , Figure 3B , Figure 4A and Figure 4B The example illustrates an example technique for communication over channel 190 between memory I / O module 160 and memory controller 130. Memory controller 180 may also include data registers 182A to 182K, which are configured to store data and / or storage configuration settings or other data transmitted between host 110 and memory array 175.

[0042] The memory system 250 may further include a memory array 175, which may include multiple memory cells (e.g., DRAM memory cells, MRAM memory cells, SRAM memory cells, flash memory cells) for storing values. The host 110 may read data stored in the memory array 175 and write data to the memory array 175 via channel 190 and memory I / O module 160. The memory array 175 may be divided into multiple memory banks, where each memory bank is organized into multiple pages.

[0043] Application or user data may be processed by processor 120, which instructs memory controller 130 to store such data and / or retrieve such data from memory system 250. For example, data may be generated during the execution of an application, such as a spreadsheet program that calculates values ​​based on other data. As another example, data may be generated during the execution of an application by receiving user input to, for example, a spreadsheet program. As yet another example, data may be generated during the execution of a game application that generates information about a representation of a scene rendered by a three-dimensional (3-D) application.

[0044] Host 110 is coupled to memory system 250 via channel 190, exemplified for data bytes, DQ[0:7]. Channel 190 and signaling between host 110 and memory system 250 may be implemented according to JEDEC DRAM specifications (e.g., LPDDR5, LPDDR6). As illustrated, channel 190 includes signaling connections for DQ, read data strobe (RDQS), data mask (DM), data clock (WCK), command and address (CA[0:n]), and command and address clock (CK). Host 110 may use the read data strobe (RDQS) during a read operation to strobe data (e.g., time the data) to receive data on DQ. Memory system 250 may use the data mask (DM) during a write operation to mask certain portions of data from being written. Memory system 250 may use the data clock (WCK) to sample data on DQ for write operations. Memory system 250 may use the command and address clock (CK) to time CA (e.g., receive CA). Signal connections for each of the signaling components may include pins at host 110, pins at memory system 250, and one or more conductive traces for electrical connection pins. One or more conductive traces may be part of a single integrated circuit (IC) on a silicon chip containing processor 120 and memory system 250, part of a stacked package (PoP) containing processor 120 and memory system 250, or part of a printed circuit board (PCB) coupled to both processor 120 and memory system 250.

[0045] Memory system 250 may include memory I / O module 160 (e.g., a PHY layer) configured to control electrical characteristics (e.g., voltage level, phase, delay, frequency, etc.) to provide or receive signals on channel 190. For example, memory I / O module 160 may be configured to capture (e.g., sample) data, commands, and addresses from host 110 via channel 190 and output data to host 110 via channel 190. Information transmitted across channel 190 may be stored in registers within memory I / O module 160 of memory system 250 as temporary or short-term storage locations before being stored in longer-term memory array 175.

[0046] The memory system 250 may also include a memory array 175, which may include multiple memory cells (e.g., DRAM memory cells) for storing information. The host 110 may read data stored in the memory array 175 and write data to the memory array 175 via channel 190. In addition, the memory array 175 may be configured to store metadata associated with the stored data, such as ECC (e.g., system or array ECC).

[0047] According to some embodiments of this disclosure, operations for storing information and retrieving information from the memory array 175 can be performed via signals on a separate line of the control channel 190. (See reference...) Figure 3A and Figure 3B An example implementation of signaling for write operations is shown and described. References Figure 4A and Figure 4B An example implementation of the signaling used for the read operation is shown and described.

[0048] Figure 3A and Figure 3B A waveform illustrating data transfer via an example channel during a write operation according to certain aspects of this disclosure is shown. The command and address clock CK can be a differential signal with CK_t and CK_c signal connections. The data clock WCK can be a differential signal with WCK0_t and WCK0_c signal connections. The read data strobe RDQS can be a differential signal with RDQS_t and RDQS_c signal connections. The data mask is labeled DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At T0 (the rising edge of CK_t and the falling edge of CK_c), a CAS command for a write operation to the memory system 250 can be provided by the host 110. At T1, the host 110 can provide a write command to the memory system 250.

[0049] After the write time interval (WL), host 110 may switch data clocks WCK0_t and WCK0_c to provide memory system 250 with a clock for receiving data to be written on the DQ signal connection. At Tc0 through Tc2, memory system 250 may serially receive 16 bytes of data on each of the DQ[0:7] signal connections, timed by data clocks WCK0_t and WCK0_c. Memory system 250 may serially (e.g., based on data clocks WCK0_t and WCK0_c) receive a 16-bit data mask DM0 to mask certain portions of the received data from write operations. In some examples, 16 bytes of data and a 16-bit data mask DM0 may be received by memory system 250, where each bit of the data mask DM0 masks the corresponding byte of the received data. At Tc0 through Tc2, the RDQS_t signal connection may be in Hi-Z condition. During a read operation, the RDQS_t signal connection can be configured to provide the read data strobe (RDQS) from the memory system 250 to the host 110.

[0050] Figure 4A and Figure 4BA waveform illustrating data transfer via an example channel during a read operation according to certain aspects of this disclosure is shown. The command and address clock CK can be a differential signal with CK_t and CK_c signal connections. The data clock WCK can be a differential signal with WCK0_t and WCK0_c signal connections. The read data strobe RDQS can be a differential signal with RDQS_t and RDQS_c signal connections. The data mask is labeled DM0 to indicate that DM0 corresponds to the lower byte of DQ (DQ[0:7]). At T0 (the rising edge of CK_t and the falling edge of CK_c), a CAS command for a read operation on the memory system 250 can be provided by the host 110. At T1, the host 110 can provide a read command to the memory system 250.

[0051] After the time period read delay (RL), memory system 250 can switch the read data strobe RDQS to provide host 110 with a clock for receiving data for read operations on the DQ signal connections. At Tc0 to Tc2, host 110 can serially receive 16 bytes of data on each of the DQ[0:7] signal connections, timed by read data strobes RDQS_t and RDQS_c. Thus, in this example, 16 bytes of data are received by host 110.

[0052] At Tc0 to Tc2, the data mask DM0 signal connection can be in the Hi-Z state. During a write operation, the DM signal connection can be configured to provide the data mask from the host 110 to the memory system 250, which can be timed by WCK0_t and WCK0_c.

[0053] refer to Figure 5 , Figure 5 Block diagram 500 illustrates an example of a system-on-chip (SoC) supporting exclusive read and write operations according to some embodiments of this disclosure. Figure 5 The example SoC includes an architecture for exclusive monitors, where the exclusive monitors reside on the memory side of the CPU-to-memory interconnect, and more specifically, where the exclusive monitors reside within hardware monitors for memory devices. Each hardware monitor (typically referred to as a master node (HN)) is coupled to and associated with a shared memory device, and may include an exclusive monitor (EM) for each CPU accessing a specific shared memory address. Reference Figure 6 Examples and descriptions Figure 5 The operation of the example SoC architecture.

[0054] Figure 5 The example SoC includes multiple CPUs 502, multiple network interface units (NIUs) 504, interconnects 506, multiple master node monitors 508, and multiple shared memory devices 510.

[0055] Multiple CPUs 502 include two or more processing units or processors. Each CPU may include or correspond to a processing core, chip, or chiplet of a SoC. Each CPU may include or correspond to a request node (RN) and may include or have a corresponding interface unit for coordinating with memory via interconnects.

[0056] Each CPU can be configured to process instructions and read data from and write data to multiple shared memory devices 510. Each CPU in the multiple CPUs 502 can be configured to access the same shared memory in the multiple shared memory devices 510 and can participate in exclusive data read and / or data write operations to control data integrity or data contention.

[0057] The multiple network interface units (NIUs) 504 include two or more NIUs, each NIU corresponding to an interface unit associated with and monitoring a CPU among the multiple CPUs 502. In some implementations, the CPU or NIU includes a local exclusive monitor configured to track exclusive access by the CPU to dedicated or non-shared memory addresses.

[0058] Interconnect 506 includes connection circuitry and logic for connecting or coupling each of the plurality of NIUs 504 to each of the plurality of master node monitors 508. Interconnect 506 is configured to connect or couple each of the plurality of CPUs 502 to each of the plurality of shared memory devices 510. For example, interconnect 506 may be configured to provide messages from an RN or CPU to the corresponding HN and memory device. In some implementations, interconnect 506 may include or correspond to a coherence interconnect.

[0059] Multiple master node monitors 508 include two or more master node monitors, each corresponding to a hardware monitor associated with and monitoring a corresponding memory device among the multiple shared memory devices 510. Each master node monitor is configured to monitor or track the address of its associated memory device and can communicate with multiple CPUs 502 via interconnect 506. A master node monitor may include or correspond to a master node (HN) associated with one or more memory devices. A master node (HN) can handle or coordinate access to its corresponding one or more memory devices. For example, an HN can coordinate data read and data write operations on the multiple shared memory devices 510.

[0060] exist Figure 5In the example, each master node monitor has multiple exclusive monitors 550, which are configured to store the status of memory addresses to indicate whether they have been accessed. These statuses can include standby or cleared. When a monitor is cleared or not standby, read instructions (such as Read Data Exclusive (RDE), Load, Load Exclusive, or Read Exclusive) can be used to make the monitor standby for a specific address. When standby, write instructions (such as Write Data Exclusive (WDE), Store, Store Exclusive, Write Unique Exclusive (WUE), or Write Exclusive) can clear the monitor for a specific address.

[0061] Exclusive monitors may include local exclusive monitors for local or non-shared memory addresses and global exclusive monitors for shared memory addresses. Each master node monitor may have a large number of global exclusive monitors, as each master node monitor has a separate global exclusive monitor for each address of each RN (e.g., each CPU). For illustration, in an example with 4 CPUs... Figure 5 In the example, each master node monitor has four global exclusive monitors per address. Global monitors track access to shared memory regions and may ignore or not indicate which RN has tagged the address. Local monitors track which RN has accessed a given memory region and may be located in either the HN or an RN.

[0062] Multiple shared memory devices 510 include two or more memory devices shared among multiple CPUs 502. Each memory device may include multiple memory addresses. Memory addresses may include dedicated memory addresses for a specific CPU and shared memory addresses accessible by one or more CPUs. Memory devices may include or correspond to volatile memory or non-volatile memory. In some embodiments, the memory device includes or corresponds to RAM. In some such embodiments, a RAM-based memory device corresponds to a DRAM device including DRAM cells. In other embodiments, a RAM-based memory device corresponds to another type of RAM, such as SRAM, NVRAM, ECC RAM, SDRAM, DDR, GDDR, MRAM, etc. In other embodiments, the memory device includes or corresponds to flash memory, ROM, etc.

[0063] exist Figure 5 In the diagram, the on-chip network (NoC) 590 is illustrated by a dashed box and includes multiple NIUs 504, interconnects 506, and multiple HN monitors 508. The NoC 590 is a network-based communication system for the SoC and is configured to handle communication between components / modules of the SoC.

[0064] exist Figure 5In the example, multiple CPUs 502 include four CPUs 512-518, multiple NIUs 504 include four NIUs 522-528, multiple master node monitors 508 include four HNs 532-538, and multiple shared memory devices 510 include four shared memory devices 542-548. Each of the four HNs 532-538 includes multiple exclusive monitors 550 (e.g., global exclusive monitors) to track exclusive access to the shared memory. Figure 5 In the example, each HN includes four exclusive monitors EM RN0-RN4, and each of the four CPUs 512-518 has one exclusive monitor. (Reference) Figure 6 describe Figure 5 The operation of components in the example SoC.

[0065] although Figure 5 The examples illustrate a specific implementation where the SoC architecture includes four of each component; however, in other implementations, the SoC may include varying numbers of components. For example, there may be more or fewer CPUs, NIUs, HNs, memory devices, or combinations thereof. For illustration, in another specific implementation, the SoC may include two CPUs and three memory devices, and in yet another specific implementation, the SoC may include five CPUs and two memory devices.

[0066] refer to Figure 6 , Figure 6 Example read and write operations are illustrated for an example of a SoC architecture according to some embodiments of this disclosure. Figure 6 Examples of the operation of one or more components of the SoC (including its RN and HN) during exclusive read and exclusive write operations are illustrated. Figure 6 In this context, the SoC and its components may include Figures 1 to 5 Either the memory or the SoC component.

[0067] Figure 6 This is a flowchart 600 illustrating operations for exclusive read and write operations according to some embodiments of this disclosure. Exclusive read and write operations can be performed by, for example... Figure 5 The illustrated SoC architecture implements an EM layout located on the memory or HN side of the CPU-to-memory interconnect. The EM may reside in each memory device or in each HN associated with it.

[0068] exist Figure 6 The diagram illustrates multiple request nodes (RNs) and host nodes (NHs), which perform the described operations. Figure 6As illustrated in the example, Figure 600 includes a first requesting node 602 (RN0), a second requesting node 604 (RN1), and a first master node 606 (HN0). The first requesting node 602 (RN0) and the second requesting node 604 (RN1) may include or correspond to... Figure 5 CPU 502 and / or Figure 5 The first requesting node 602 (RN0) may include or correspond to the first CPU 512, the first NIU 522, or both, and the second requesting node 604 (RN1) may include or correspond to the second CPU 514, the second NIU 524, or both. The first master node 606 (HN0) may include or correspond to... Figure 5 Any of the master node monitors in master node monitor 508. In some specific implementations, operation can be performed by... Figure 1 The memory controller 130 of the host 110 Figure 2 The memory controller 180 of the memory system 250 Figure 5 One or more SoC components in the SoC are executed.

[0069] The operation includes sending a read data exclusive command at 610 by the first requesting node 602 (RN0). For example, the first requesting node 602 (RN0) sends a first read data exclusive command to the first master node 606 (HN0) for a first address (addr0) of a first shared memory device (e.g., Mem0).

[0070] A read-exclusive command is a command to read data at a specific shared memory address, and the requesting node indicates that it wants to exclusively track that data. While the data is exclusively tracked, other devices may be able to access the data at the shared memory address and optionally even write to the shared memory address (e.g., modify the data). However, if the data is modified by another requesting node, all other requesting nodes with exclusive monitors tracking the specific shared memory address may later be unable to write the data without performing another read operation.

[0071] At 615, the first master node 606 (HN0) reads data from memory and puts the exclusive monitor on standby. For example, the first master node 606 (HN0) reads data from a first shared memory device (e.g., Mem0) stored at a first address based on a read data exclusive command. For illustration, the first master node 606 (HN0) communicates with the first shared memory device (e.g., Mem0) to obtain data at the first address. The first master node 606 (HN0) puts the global exclusive monitor on standby based on reading data and receiving a first read data exclusive command. For example, the first requesting node 602 (RN0) puts the corresponding global exclusive monitor associated with the first requesting node 602 (RN0) and for the first shared memory address on standby based on receiving the first read data exclusive command. For illustration, the first master node 606 (HN0) puts the global exclusive monitor (EM RN0) on standby at the first master node 606 (HN0) corresponding to the first requesting node 602 (RN0).

[0072] At 620, the first master node 606 (HN0) sends a read data complete command. For example, the first master node 606 (HN0) sends a read data complete command to the first requesting node 602 (RN0), which includes or indicates data stored at a first address that is read from a first shared memory device (e.g., Mem0) based on and in response to a read data exclusive command and putting an exclusive monitor on standby.

[0073] At 625, the second requesting node 604 (RN1) sends a read data exclusive command. For example, the second requesting node 604 (RN1) sends a second read data exclusive command to the first master node 606 (HN0) for a first address (addr0) of the first shared memory device (e.g., Mem0).

[0074] At 630, the first master node 606 (HN0) reads data from memory and puts the exclusive monitor on standby. For example, the first master node 606 (HN0) reads data from a first shared memory device (e.g., Mem0) stored at a first address based on a read data exclusive command. For illustration, the first master node 606 (HN0) may communicate with the first shared memory device (e.g., Mem0) to obtain data at the first address, or it may retrieve data from a cache. The first master node 606 (HN0) puts the global exclusive monitor on standby based on reading data and receiving a second read data exclusive command. For example, the second requesting node 604 (RN1) puts the corresponding global exclusive monitor associated with the second requesting node 604 (RN1) and used for the first shared memory address on standby based on receiving a second read data exclusive command. For illustration, the first master node 606 (HN0) puts the second global exclusive monitor (EMRN1) corresponding to the second requesting node 604 (RN1) on standby.

[0075] At 635, the first master node 606 (HN0) sends a read data complete command. For example, the first master node 606 (HN0) sends a second read data complete command to the second requesting node 604 (RN1), which includes or indicates data stored at a first address that is read from the first shared memory device (e.g., Mem0) based on and in response to the second read data exclusive command.

[0076] At 640, the second requesting node 604 (RN1) sends a write data exclusive command. For example, the second requesting node 604 (RN1) sends a write data exclusive command to the first master node 606 (HN0) for a first address (addr0) of the first shared memory device (e.g., Mem0). For illustration, the second requesting node 604 (RN1) may determine to send the write data exclusive command for the first address based on received data and / or received a second read data completion command.

[0077] At 645, the first master node 606 (HN0) writes data to memory and clears the exclusive monitor. For example, the first master node 606 (HN0) determines the first shared memory address to write data to the first shared memory device based on whether the second exclusive monitor (EM RN1) of the second requesting node 604 (RN1) is set or ready. Then, the first master node 606 (HN0) may clear the first exclusive monitor and the second exclusive monitor (EM RN0 and EM RN1) based on the completion of the data write to memory (such as receiving a write data completion message from DRAM).

[0078] At 650, the first master node 606 (HN0) sends a write data complete command. For example, the first master node 606 (HN0) sends a write data exclusive complete command to the second requesting node 604 (RN1), which includes or indicates that a data write to a first address of a first shared memory device (e.g., Mem0) based on and in response to the write data exclusive command has been successfully completed.

[0079] At 655, the first requesting node 602 (RN0) sends a write data exclusive command. For example, the first requesting node 602 (RN0) sends a second write data exclusive command to the first master node 606 (HN0) for a first address (addr0) of a first shared memory device (e.g., Mem0). For illustration, the first requesting node 602 (RN0) may determine to send the write data exclusive command for the first address based on received data and / or received a first read data completion command.

[0080] At 660, the first master node 606 (HN0) does not write data to memory. For example, the first master node 606 (HN0) determines, based on whether the first exclusive monitor (EM RN0) of the first requesting node 602 (RN0) is cleared or not on standby, that a second write data exclusive command from the first requesting node 602 (RN0) will not write data to the first shared memory address of the first shared memory device. The first master node 606 (HN0) may ignore the write command.

[0081] At 665, the first master node 606 (HN0) sends a write data failure command. For example, the first master node 606 (HN0) sends a write data exclusive failure command to the first requesting node 602 (RN0), which indicates that data should not be written to the first shared memory address based on and in response to determining that data should not be written to memory. The first requesting node 602 (RN0) can then proceed with another or a third read command, similar to the read data exclusive command at 610, to access the updated data at the first address and put the corresponding exclusive monitor (EM RN0) back on standby before attempting (retrying) to write the updated data to the first address.

[0082] refer to Figure 7 , Figure 7 This is a block diagram 700 illustrating an example of a SoC with a scalable EM architecture and support for enhanced exclusive read and write operations according to some embodiments of this disclosure. Figure 7 The example SoC includes an architecture for an exclusive monitor, where the exclusive monitor resides on the RN side of the RN-to-memory interconnect and resides in the NIU. Each NIU is associated with an RN ( Figure 7The example CPU is coupled and associated with the shared memory, and may include an exclusive monitor (EM) for each shared memory address that is accessed by the RN or that is entitled to access. (See reference) Figure 8 Examples and descriptions Figure 7 The operation of the example SoC architecture.

[0083] and Figure 5 Compared to the example SoC architecture, Figure 7 The example SoC architecture has fewer overall exclusive monitors because the exclusive monitors are moved "upstream" and closer to the RN. For illustration, redundant exclusive monitors for a specific RN (and memory address) distributed across multiple hardware monitors on different memory devices can now be combined at a single NIU. By moving the exclusive monitors upstream and to the other side of the RN-to-memory interconnect, the master node monitor (or HN) can utilize consistency operations (e.g., snooping requests and messages) to determine the state of the exclusive monitors for read and write operations (e.g., exclusive read and exclusive write operations) and manage the state of the exclusive monitors (e.g., standby or cleared).

[0084] Figure 7 The example SoC includes multiple request nodes (such as CPU 702), multiple network interface units (NIU) 704, interconnects 706, multiple master node monitors 708, and multiple shared memory devices 710.

[0085] Multiple CPUs 702 include two or more processing units or processors. A CPU may include or correspond to a processing core, chip, or chiplet of a System-on-a-Chip (SoC). Multiple CPUs 702 may include or correspond to... Figure 5 Multiple CPUs 502.

[0086] Each CPU can be configured to process instructions and read data from and write data to multiple shared memory devices 710. Each CPU in the multiple CPUs 702 can be configured to access the same shared memory in the multiple shared memory devices 710 and can participate in exclusive data read and / or data write operations to control data integrity or data contention.

[0087] Multiple Network Interface Units (NIUs) 704 include two or more NIUs, each NIU corresponding to an interface unit associated with and monitoring a CPU among the multiple CPUs 702. The multiple NIUs 704 may include or correspond to... Figure 5 Multiple NIU504s. In some implementations, the CPU or NIU includes a local monitor configured to track exclusive CPU access to dedicated or non-shared memory addresses.

[0088] exist Figure 7 In the example, each NIU has multiple exclusive monitors 750, which are configured to store the status of memory addresses to indicate whether they have been accessed. These statuses can include standby or cleared. When a monitor is cleared or not standby, read instructions (such as Read Data Exclusive (RDE), Load, Load Exclusive, or Read Exclusive) can be used to make the exclusive monitor for a specific address standby. When standby, write instructions (such as Write Data Exclusive (WDE), Store, Store Exclusive, Write Unique Exclusive (WUE), or Write Exclusive) can clear the exclusive monitor for a specific address.

[0089] exist Figure 7 In the examples, exclusive monitors include extended or distributed exclusive monitors. Figure 7 Exclusive monitors can be viewed as extended or distributed exclusive monitors because they are extended or distributed from HN to RN. Exclusive monitors can also be viewed as merged or public exclusive monitors because previous exclusive monitors for a particular RN (such as EM RN0 at each HM) can be merged at that particular RN (i.e., a single RN) or are public for that particular RN.

[0090] Exclusive monitors may include exclusive monitors for local or non-shared memory addresses (often referred to as local exclusive monitors), exclusive monitors for shared memory addresses (often referred to as global exclusive monitors), or combinations thereof. The exclusive monitor is located at the master node monitor (HN) or on the memory side of the interconnect 706. Figure 5 Compared to the example, in Figure 7 In the example, the exclusive monitor is moved to the NIU, and the NIU may include more than Figure 5 The corresponding master node monitor has fewer exclusive monitors. For example, an NIU might require only one exclusive monitor per thread or per memory address, and the exclusive monitor for the RN (e.g., CPU) will not be duplicated across different NIUs or master node monitors. For instance, a second NIU or master node monitor may not include exclusive monitors for the first, third, or fourth CPU, such as... Figure 5 The master node. In this way, redundant exclusive monitors can be eliminated, thereby greatly reducing the number of exclusive monitors. This reduction in exclusive monitors, due to the reduced area used, can significantly reduce chip size. For example, Figure 7 The area used for dedicated monitoring devices can be reduced to Figure 5 The square root of the original area used to exclusively monitor the device.

[0091] However, since the master node monitor can still be used to control exclusive access to shared memory addresses, it can communicate with the NIU's exclusive monitor to determine its status, thereby determining when and how to execute data write and read commands, such as exclusive data write or read commands.

[0092] Interconnector 706 includes connection circuitry and logic for connecting or coupling each of a plurality of NIUs 704 to each of a plurality of master node monitors 708. Interconnector 706 is configured to connect or couple each of a plurality of CPUs 702 to each of a plurality of shared memory devices 710. For example, interconnector 706 may be configured to provide messages from an RN or CPU to the corresponding HN and memory device. Interconnector 706 may include or correspond to Figure 5 The interconnect 506. In some specific implementations, the interconnect 706 may include or correspond to a conforming interconnect.

[0093] Multiple master node monitors 708 include two or more memory devices, each memory device corresponding to a master node monitor associated with and monitoring a memory device in the multiple shared memory devices 710. Each master node monitor is configured to interact with multiple NIUs 704s (such as their dedicated monitors 750) to determine the status of data in the shared memory, thereby controlling the operation of the master node monitors 708 and the multiple shared memory devices 710. The multiple master node monitors 708 may include or correspond to Figure 5 Multiple master node monitors 508. A master node monitor may include or correspond to a master node (HN) associated with one or more memory devices. A master node (HN) may process or coordinate access to its corresponding one or more memory devices. For example, an HN may coordinate data read and data write operations to multiple shared memory devices 710.

[0094] Multiple shared memory devices 710 include two or more memory devices shared among multiple CPUs 702. Each memory device may include multiple memory addresses. Memory addresses may include dedicated memory addresses for a specific requesting node (e.g., a CPU) and shared memory addresses accessible by one or more requesting nodes (e.g., CPUs). Memory devices may include or correspond to volatile memory or non-volatile memory. In some embodiments, the memory device includes or corresponds to RAM. In some such embodiments, a RAM-based memory device corresponds to a DRAM device including DRAM cells. In other embodiments, a RAM-based memory device corresponds to another type of RAM, such as SRAM, NVRAM, ECC RAM, SDRAM, DDR, GDDR, MRAM, etc. In other embodiments, the memory device includes or corresponds to flash memory, ROM, etc.

[0095] exist Figure 7 In the diagram, NoC 790 is illustrated by a dashed box and includes multiple NIU 704s, interconnects 706, and multiple HN monitors 708. NoC 790 is a network-based communication system for the SoC and is configured to handle communication between components / modules of the SoC, and may include or correspond to... Figure 5 The NoC 590. For example, the NoC 790 can handle communication between RNs themselves, between RNs and memory devices, and between RNs and... Figure 7 Communication between other components of the SoC, not shown in the diagram. Figure 7 In the example, EM has been from, for example Figure 5 The bottom of the NoC 590 in the SoC is moved to, as Figure 7 The top of the NoC in the SoC. The movement of the EM within the NoC 790 distributes the EM throughout the NoC 790 and brings them physically closer to the RN.

[0096] although Figure 7 The examples illustrate a specific implementation where the SoC architecture includes four of each component; however, in other implementations, the SoC may include varying numbers of components. For example, there may be more or fewer CPUs, NIUs, HNs, memory devices, or combinations thereof. For illustration, in another specific implementation, the SoC may include two CPUs and three memory devices, and in yet another specific implementation, the SoC may include five CPUs and two memory devices. Additionally or alternatively, although... Figure 7 The examples illustrate that RNs are specific implementations of CPUs, but in other implementations, RNs may include or correspond to one or more other types of processors or ICs, such as DSPs, ISPs, GPUs, NPUs, video encoders, modems, etc.

[0097] exist Figure 7 In the example, multiple CPUs 702 include four CPUs 712-718, multiple NIUs 704 include four NIUs 722-728, multiple master node monitors 708 include four HNs 732-738, and multiple shared memory devices 710 include four shared memory devices 742-748. The four NIUs 722-728 include multiple dedicated monitors 750 (e.g., RN-based dedicated monitors). Figure 7 In the example, each NIU includes an exclusive monitor (e.g., EM RN0 or EM RN1) corresponding to a specific CPU among the four CPUs 712-718. (See reference) Figure 8 and Figure 9 describe Figure 7 The operation of components in the example SoC.

[0098] refer to Figure 8 , Figure 8 Example read and write operations are illustrated for an example of a SoC architecture according to some embodiments of this disclosure. Figure 8 Examples of the operation of one or more components of the SoC (including its RN and HN) during exclusive read and exclusive write operations are illustrated. Figure 8 In this context, the SoC and its components may include Figures 1 to 5 and Figure 7 Either the memory or the SoC component.

[0099] Figure 8 This is a flowchart 800 illustrating operations for enhanced exclusive read and write operations according to some embodiments of this disclosure. The enhanced exclusive read and write operations can be performed by, for example... Figure 7 The illustrated SoC architecture implements a more scalable EM layout with the EM located on the CPU or RN side of the CPU-to-memory interconnect. The EM can be located in each CPU or in each NIU.

[0100] exist Figure 8 The diagram illustrates multiple request nodes (RNs) and host nodes (NHs), which perform the described operations. Figure 8 As illustrated in the example, Figure 800 includes a first requesting node 802 (RN0), a second requesting node 804 (RN1), and a first master node 806 (HN0). The first requesting node 802 (RN0) and the second requesting node 804 (RN1) may include or correspond to... Figure 7 CPU 702 and / or Figure 7Any of the NIU 704. For example, the first requesting node 802 (RN0) may include or correspond to the first CPU 712, the first NIU 722, or both, and the second requesting node 804 (RN1) may include or correspond to the second CPU 714, the second NIU 724, or both. The first master node 806 (HN0) may include or correspond to Figure 7 Any of the master node monitors in master node monitor 708. In some specific implementations, operation can be performed by... Figure 1 The memory controller 130 of the host 110 Figure 2 The memory controller 180 of the memory system 250 Figure 7 One or more SoC components in the SoC are executed.

[0101] The operation includes sending a read data exclusive command at 810 by the first requesting node 802 (RN0). For example, the first requesting node 802 (RN0) sends a first read data exclusive command to the first master node 806 (HN0) for a first address (addr0) of a first shared memory device (e.g., Mem0).

[0102] A read-exclusive command is a command that reads data at a specific shared memory address and requests the node to indicate that the data should be tracked exclusively. While the data is being tracked exclusively, other devices may be able to access the data at the shared memory address and optionally even write to the shared memory address (e.g., modify the data). However, if the data is changed by another node, all other nodes may later be unable to write the data without performing another read operation.

[0103] At address 815, the first master node 806 (HN0) reads data from memory. For example, the first master node 806 (HN0) reads data from a first shared memory device (e.g., Mem0) stored at a first address based on a read data exclusive command. For illustration, the first master node 806 (HN0) communicates with the first shared memory device (e.g., Mem0) to obtain data at the first address. Figure 6 In contrast, the first master node 806 (HN0) reads data without putting the exclusive monitor (such as an RN-based exclusive monitor) on standby, because the exclusive monitor now resides on the other side of interconnect 706, such as at the NIU, as referenced. Figure 7 The example described.

[0104] At 820, the first master node 806 (HN0) sends a read data complete command. For example, the first master node 806 (HN0) sends a read data complete command to the first requesting node 802 (RN0), which includes or indicates data stored at a first address that was read from the first shared memory device (e.g., Mem0) based on and in response to a read data exclusive command.

[0105] At 825, the first requesting node 802 (RN0) puts the exclusive monitor into standby mode. For example, the first requesting node 802 (RN0) puts the corresponding exclusive monitor associated with the first requesting node 802 (RN0) and used for the first shared memory address into standby mode based on receiving a read data completion command. For illustration, the first requesting node 802 (RN0) puts the exclusive monitor (EM Mon0) into standby mode at the first NIU 722 corresponding to the first requesting node 802 (RN0).

[0106] At 830, the first requesting node 802 (RN0) sends a read data acknowledgment. For example, the first requesting node 802 (RN0) sends a first read data exclusive acknowledgment message to the first master node 806 (HN0) in response to a first read data exclusive command for a first shared memory address and in response to putting the monitor on standby and / or receiving a first read data completion message. The read data acknowledgment message may be transmitted in response to the standby status of the exclusive monitor (EM Mon0) at the first NIU 722 and indicates that the exclusive monitor (EM Mon0) at the first NIU 722 has successfully become standby.

[0107] At 835, the second requesting node 804 (RN1) sends a read data exclusive command. For example, the second requesting node 804 (RN1) sends a second read data exclusive command to the first master node 806 (HN0) for a first address (addr0) of the first shared memory device (e.g., Mem0).

[0108] At address 840, the first master node 806 (HN0) reads data from memory. For example, the first master node 806 (HN0) reads data from a first shared memory device (e.g., Mem0) stored at a first address based on a read data exclusive command. For illustration, the first master node 806 (HN0) may communicate with the first shared memory device (e.g., Mem0) to obtain data at the first address, or it may retrieve data from a cache. Figure 6 In contrast, the first master node 806 (HN0) reads data without putting a dedicated monitor (such as this dedicated monitor) on standby, because the dedicated monitor now resides on the other side of interconnect 706, such as at the NIU, as referenced. Figure 7 The example described.

[0109] At 845, the first master node 806 (HN0) sends a read data complete command. For example, the first master node 806 (HN0) sends a read data complete command to the second requesting node 804 (RN1), which includes or indicates data stored at a first address that was read from the first shared memory device (e.g., Mem0) based on and in response to a second read data exclusive command.

[0110] At 850, the second requesting node 804 (RN1) puts the exclusive monitor into standby mode. For example, the second requesting node 804 (RN1) puts the corresponding second exclusive monitor associated with the second requesting node 804 (RN1) and used for the first shared memory address into standby mode based on receiving a second read data completion command. For illustration, the second requesting node 804 (RN1) puts the second exclusive monitor (EM Mon1) into standby mode at the second NIU 724 corresponding to the second requesting node 804 (RN1).

[0111] At 855, the second requesting node 804 (RN1) sends a read data acknowledgment. For example, the second requesting node 804 (RN1) sends a second read data acknowledgment message to the first master node 806 (HN0) in response to a second read data exclusive command for the first shared memory address and in response to putting the monitor on standby and / or receiving a second read data completion message. In some implementations, the second read data acknowledgment message is transmitted in response to the standby of the second exclusive monitor (EMMon1) at the second NIU 724 and indicates that the second exclusive monitor (EMMon1) at the second NIU 724 has successfully become standby.

[0112] At 860, the second requesting node 804 (RN1) sends a write data exclusive command. For example, the second requesting node 804 (RN1) sends a write data exclusive command to the first master node 806 (HN0) for a first address (addr0) of a first shared memory device (e.g., Mem0). For illustration, the second requesting node 804 (RN1) may determine to send the write data exclusive command for the first address based on determining that the corresponding second exclusive monitor (EM Mon1) at the second NIU 724 is ready for the first address.

[0113] At 865, the first master node 806 (HN0) performs a snooping consistency operation. For example, the first master node 806 (HN0) performs a snooping consistency operation on a first address of a first shared memory device (e.g., Mem0) based on a write data exclusive command. For illustration, the first master node 806 (HN0) may send one or more snooping messages to check the exclusive monitor status (e.g., standby or cleared) and receive a snooping response indicating that status, as referenced. Figure 9 Further described. In some specific implementations, the first master node 806 (HN0) optionally performs operations to manage and / or clear the exclusive monitor of the requesting node (e.g., at the NIU).

[0114] At 870, the first master node 806 (HN0) writes data to memory. For example, the first master node 806 (HN0) writes data to a first address of the first shared memory device (e.g., Mem0) based on a write-data-exclusive command. For illustration, the first master node 806 (HN0) may communicate with the first shared memory device (e.g., Mem0) to write or modify data at the first address. The first master node 806 (HN0) may write data based on a snooping consistency operation performed at 865, as referenced... Figure 9 The example described above illustrates this. For illustration, the first master node can write data or acknowledge the data write after successfully completing the sniffer consistency operation.

[0115] At 875, the first master node 806 (HN0) performs exclusive monitor management operations. For example, the first master node 806 (HN0) sends one or more snoop clear messages to requesting nodes based on writing a date to memory, to clear the exclusive monitor for a first address of the first shared memory device (e.g., Mem0). For illustration, the first master node 806 (HN0) may send a first snoop clear message to a first requesting node 802 (RN0) and a second snoop clear message to a second requesting node 804 (RN1).

[0116] At 880, the first master node 806 (HN0) sends a write data complete command. For example, the first master node 806 (HN0) sends a write data exclusive complete command to the second requesting node 8046 (RN1), which includes or indicates that a data write to a first address of a first shared memory device (e.g., Mem0) based on and in response to the write data exclusive command has been successfully completed. Although in Figure 8 In the example, data is exemplified as being written or indicated as written at 870 before the write data complete command, but in some other implementations, data may be written to memory and / or acknowledged as written to the second request node 804 (RN1) at 880, simultaneously with the sending of the write data complete command, or this may occur after the sending of the write data complete command at 880.

[0117] Figure 9 This is a flowchart 900 illustrating operations for enhanced exclusive read and write operations according to some embodiments of this disclosure. The enhanced exclusive read and write operations can be performed by, for example... Figure 7The illustrated SoC architecture implements a more scalable EM layout with the EM located on the CPU or RN side of the CPU-to-memory interconnect. The EM can be located in each CPU or in each NIU.

[0118] exist Figure 9 The diagram illustrates multiple request nodes (RNs) and host nodes (NHs), which perform the described operations. Figure 9 As illustrated in the example, Figure 900 includes a first requesting node 902 (RN0), a second requesting node 904 (RN1), and a first master node 906 (HN0). The first requesting node 902 (RN0) and the second requesting node 904 (RN1) may include or correspond to... Figure 7 CPU 702 and / or Figure 7 Any of the NIU 704. For example, the first requesting node 902 (RN0) may include or correspond to the first CPU 712, the first NIU 722, or both, or correspond to Figure 8 The first requesting node 802 (RN0) and the second requesting node 904 (RN1) may include or correspond to the second CPU 714, the second NIU 724, or both, or correspond to Figure 8 The second requesting node 804 (RN1). The first master node 906 (HN0) may include or correspond to Figure 7 Master node monitor 708 or Figure 8 Either of the first master nodes 806 (HN0). In some specific implementations, the operation can be performed by... Figure 1 The memory controller 130 of the host 110 Figure 2 The memory controller 180 of the memory system 250 Figure 7 One or more SoC components in the SoC are executed.

[0119] At position 910, the second requesting node 904 (RN1) sends a write data exclusive command. For example, the second requesting node 904 (RN1) sends a write data exclusive command to the first master node 906 (HN0) for the first address (addr0) of the first shared memory device (e.g., Mem0), which is similar to... Figure 8 860 and as referenced Figure 8 As described in 860. For example, the second requesting node 904 (RN1) may determine to send a write data exclusive command for the first address based on the determination that the corresponding second exclusive monitor (EMMon1) at the second NIU 724 for the first address (addr0) is ready.

[0120] After 910, the first master node 906 (HN0) performs a similar action. Figure 8 865 and as referenced Figure 8 The snooping consistency operation described in 865. Figure 9 In the example, the first master node 906 (HN0) sends a snoop query command to the second requesting node 904 (RN1) at 915. For example, the first master node 906 (HN0) sends a first snoop query command to the second requesting node 904 (RN1) to query the status of the exclusive monitor for the first address corresponding to the second requesting node 904 (RN1). For illustration, since the exclusive monitor is now located at or near the second requesting node 904 (RN1), such as in the corresponding second NIU (e.g., NIU 724), the first master node 906 (HN0) may send a snoop message or other consistency message to determine the status or condition of the second exclusive monitor (EM Mon1) for the first address.

[0121] At 920, the second requesting node 904 (RN1) sends a snoop response command. For example, the second requesting node 904 (RN1) sends a snoop response to a snoop query from the first master node 906 (HN0) for a first address (addr0) of the first shared memory device (e.g., Mem0). For illustration, the second requesting node 904 (RN1) may send a snoop response indicating the status (e.g., standby or cleared) of a second exclusive monitor for the first shared address. Figure 9 In the example, it is already ready. In order to send a snooping response, the second requesting node 904 (RN1) can cause the second NIU 724 to transmit the snooping response based on the state of the second exclusive monitor, or the second requesting node 904 (RN1) can communicate with the second NIU 724 to determine the state, and then send a snooping response command, such as via the second NIU 724, based on the determined state.

[0122] At 925, the first master node 906 (HN0) writes data to memory. For example, the first master node 906 (HN0) writes data to a first address of a first shared memory device (e.g., Mem0) based on a write data exclusive command and in response to a snoop response command. For illustration, the first master node 906 (HN0) may write data based on a snoop response command indicating that a second exclusive monitor of the second NIU 724 is ready. The ready state of the second exclusive monitor may indicate that the data received by the second requesting node 904 (RN1) in a read command prior to the write command is current or consistent (i.e., the data at the first address has not changed).

[0123] After writing data 925, the first master node 906 (HN0) performs a similar operation. Figure 8 875 and as referenced Figure 8The snooping consistency operation described in 875 is used to update the state of the exclusive monitor (e.g., clear the exclusive monitor). Figure 9 In the example, the first master node 906 (HN0) sends a first snoop cleanup command to the first requesting node 902 (RN0) at 930, and a second snoop cleanup command to the second requesting node 904 (RN1) at 935. For illustration, the second snoop cleanup command may instruct the first master node 906 (HN0) to write data to a first shared address of the first shared memory device to clear the corresponding exclusive monitor for the first address.

[0124] Despite Figure 9 The example illustrates two snoop clear messages, but the device can send more or fewer snoop clear messages. For example, the first master node 906 (HN0) can send a snoop clear message to each requesting node and / or NIU. As another example, the first master node 906 (HN0) can send a snoop clear message only to each requesting node and / or NIU that has requested or recently requested data from that address.

[0125] At 940, the first requesting node 902 (RN0) clears the first exclusive monitor in response to receiving the first snoop clear command, and at 945, the second requesting node 904 (RN1) clears the second exclusive monitor in response to receiving the second snoop clear command. For example, the requesting nodes may receive the snoop clear command and then instruct their corresponding NIU to clear the identified exclusive monitor. Alternatively, the requesting nodes may not clear or even receive the snoop clear command, and the attached NIU may, based on... Figure 7 The interconnect 706 receives a snoop clear command from the first master node 906 (HN0) to clear the identified exclusive monitor.

[0126] After clearing the corresponding exclusive monitor, the requesting node can send a snooping cleanup response command to indicate the updated status of the exclusive monitor. Figure 9 In the example, the first requesting node 902 (RN0) sends a first snoop cleanup response command at 950, and the second requesting node 904 (RN1) sends a second snoop cleanup response command at 955. Alternatively, the attached NIU may send a snoop cleanup response command in response to clearing the exclusive monitor or changing its state, and indicate the updated state of the exclusive monitor to the first master node 906 (HN0) that sent the snoop cleanup command.

[0127] At 960, the first master node 906 (HN0) sends a write data complete command. For example, the first master node 906 (HN0) sends a write data exclusive complete command to the second requesting node 904 (RN1), which includes or indicates that a data write to a first address of a first shared memory device (e.g., Mem0) based on and optionally in response to a write data exclusive command has been successfully completed. Although in Figure 9 In the example, data is exemplified as being written or indicated as written at 960 before the write data complete command, but in some other implementations, data may be written to memory and / or acknowledged as written to the second request node 904 (RN1) at 960, simultaneously with the sending of the write data complete command, or this may occur after the sending of the write data complete command at 960.

[0128] At 965, the first requesting node 902 (RN0) sends a write data exclusive command. For example, the first requesting node 902 (RN0) sends a second write data exclusive command to the first master node 906 (HN0) for a first address (addr0) of a first shared memory device (e.g., Mem0). For illustration, the first requesting node 902 (RN0) may determine to send the write data exclusive command for the first address based on received data and / or received a first read data completion command. Alternatively, in other implementations, the first requesting node 902 (RN0) may determine that it cannot send the second write data exclusive command to the first master node 906 (HN0) for the first address (addr0) of the first shared memory device (e.g., Mem0) because the corresponding exclusive monitor (EM Mon0) at the first NIU 722 is no longer in standby and has a cleared state for the first address.

[0129] After 965, the first master node 906 (HN0) will not write data to memory based on the second write data exclusive command. For example, the first master node 906 (HN0) will write data to memory based on a second snooping or consistency operation (such as...). Figure 8 Operation at 865 and / or Figure 9 The operation at 915 and 920 (similar to a snooping or consistency operation) determines that the corresponding exclusive monitor (EM Mon0) of the first requesting node 902 (RN0) at the first NIU 722 is cleared or not on standby, and determines that data should not be written to the first shared memory address of the first shared memory device. The first master node 906 (HN0) may ignore the second write data exclusive command based on performing a snooping or consistency operation and determining that the monitor (EM Mon0) of the first requesting node 902 (RN0) at the first NIU 722 is cleared or not on standby.

[0130] At 970, the first master node 906 (HN0) sends a write data failure command. For example, the first master node 906 (HN0) sends a write data exclusive failure command to the first requesting node 902 (RN0), which indicates that data should not be written to the first shared memory address based on and in response to determining that data should not be written to memory. Then, the first requesting node 902 (RN0) can continue to perform read commands to access updated data and put the corresponding exclusive monitor back on standby before attempting (retrying) the write data, such as... Figure 8 The exclusive command to read data at address 810.

[0131] Although a reference has been made to an exclusive monitor or an exclusive monitor that tracks exclusive access to memory regions marked as shared, Figures 5 to 9 Examples, but Figures 5 to 9 The concepts and operations can be applied to local exclusive monitors or exclusive monitors that track exclusive access to dedicated memory regions (e.g., non-shared memory regions). For example, in some implementations, a local exclusive monitor may be moved from the HN to the RN (e.g., the associated NIU) to keep all exclusive monitors on the CPU side of the interconnect. In such examples, the local exclusive monitor may function the same as a regular local monitor, and the HN may use snooping operations to check the status of the local exclusive monitor, as referenced. Figure 8 and Figure 9 As described. Alternatively, if a particular CPU does not have dedicated memory, a local exclusive monitor may not be used, or a conventional arrangement of local exclusive monitors may be used and the local exclusive monitor may remain in the HN. Local exclusive monitors do not face the same expansion problems as exclusive monitors or exclusive monitors used for shared memory addresses.

[0132] Therefore, relocating the EM to the NIU provides significant area savings for the EM while maintaining backward compatibility with the SoC's write and read data exclusivity commands. Relocating the EM to the NIU does not affect the timing of SoC operations, and the architecture is compatible with multi-die and chiplet SoCs. Furthermore, inter-die interfaces remain unaffected.

[0133] refer to Figure 10 , Figure 10 This is a flowchart illustrating a method 1000 for enhanced exclusive read and write operations according to some embodiments of this disclosure. In some specific embodiments, the method may be... Figure 7 The SoC can perform enhanced exclusive read and write operations. For example, request nodes, NIUs, interconnects, HNs, and memory devices can perform such operations.

[0134] Method 1000 includes receiving a read data completion message at block 1002 by a requesting node. This read data completion message includes data associated with an exclusive read request for a specific memory address of a shared memory device and indicates that the specific memory address has been read. For example, the requesting node may read data from a read data completion command received in response to transmitting a read data command, as referenced. Figures 7 to 9 As described. For illustration, the second requesting nodes 804, 904 (RN1) read data from a first shared memory address at 845 in response to a read data exclusive command. The read command may include or correspond to RDE, RE, memory, memory exclusive, or other similar read commands.

[0135] At box 1004, method 1000 includes having the requesting node put the exclusive monitor on standby based on a read data completion message. For example, the requesting node may put the corresponding exclusive monitor on standby at its corresponding NIU, as referenced. Figures 7 to 9 As described. For example, the second requesting node 804, 904 (RN1) responds to receiving the read data exclusive completion command at 845 and puts the second exclusive monitor on standby at the second NIU at 850.

[0136] At block 1006, method 1000 includes transmitting an exclusive write request for a specific memory address from a requesting node to a master node associated with the shared memory device. For example, the requesting node may transmit the exclusive write request for a specific memory address to the master node associated with the shared memory device, as referenced in [reference missing]. Figures 7 to 9 As described. For example, the second requesting nodes 804, 904 (RN1) send a write data exclusive command to the first master nodes 806, 906 (HN0) at 855, 910.

[0137] At block 1008, method 1000 includes a requesting node transmitting a snoop query response message for a specific memory address to a master node, the snoop query response message indicating a hit, and responding to a snoop query message from the master node associated with an exclusive write request. For example, the requesting node may transmit a snoop query response message for a specific memory address to the master node, the snoop query response message indicating a hit, and responding to a snoop query message from the master node associated with an exclusive write request, as referenced... Figures 7 to 9 As described. For example, the second requesting nodes 804, 904 (RN1) perform a snooping consistency operation at 865, such as sending a snooping response command to the first master nodes 806, 906 (HN0) at 920 in response to receiving a snooping query command at 915.

[0138] At block 1010, method 1000 includes receiving a snoop cleanup message for a specific memory address from the master node in response to a snoop query response message. For example, the requesting node may receive a snoop cleanup message for a specific memory address from the master node in response to a snoop query response message, as referenced in [reference]. Figures 7 to 9 As described. For example, the second requesting nodes 804, 904 (RN1) receive the snooping cleanup command from the first master nodes 806, 906 (HN0) at 935.

[0139] At block 1012, method 1000 includes clearing the exclusive monitor by a requesting node based on a snooping cleanup message for a specific memory address. For example, the requesting node can clear the exclusive monitor by changing its state from standby to cleared based on a snooping cleanup message for a specific memory address, as referenced. Figures 7 to 9 As described. For example, the second requesting nodes 804, 904 (RN1) clear the second exclusive monitor at the second NIU at 945 by changing their state from standby to clear / not standby based on receiving a snooping cleanup command at 935.

[0140] refer to Figure 11 , Figure 11 This is a flowchart illustrating a method 1100 for enhanced exclusive read and write operations according to some embodiments of the present disclosure. In some specific embodiments, the method may be... Figure 7 The SoC can perform operations. For example, request nodes and NIUs can perform enhanced exclusive read and write operations.

[0141] Method 1100 includes, at block 1102, the requesting node idling an exclusive monitor based on a read data completion message for a specific memory address associated with a shared memory device, the read data completion message being received from the master node and in response to an exclusive read request for the specific memory address from the requesting node. For example, the requesting node may idling the corresponding exclusive monitor at the NIU associated with the requesting node based on receiving a read data completion command received in response to a transmit read data command, as referenced. Figures 7 to 9 As described. For illustration, the second requesting nodes 804, 904 (RN1) receive a read data exclusive completion command at 845 in response to a read data exclusive command, and put the exclusive monitor on standby at 850. As another example, the first requesting nodes 802, 902 (RN0) put their corresponding exclusive monitor on standby at 825. The read command may include or correspond to RDE, RE, storage, storage exclusive, or other similar read commands.

[0142] At block 1104, method 1100 includes clearing an exclusive monitor by a requesting node based on a snoop cleanup message received from the master node for a specific memory address, the snoop cleanup message being associated with an exclusive write request for the specific memory address from the requesting node. For example, the requesting node can clear the exclusive monitor by changing its state from standby to cleared based on the snoop cleanup message for the specific memory address, as referenced. Figures 7 to 9 As described. For example, the second requesting nodes 804, 904 (RN1) clear the second exclusive monitor at the second NIU at 945 by changing their state from standby to clear / not standby based on receiving a snooping cleanup command at 935.

[0143] In a first aspect, an apparatus includes a processing system comprising: one or more shared memory devices, each of the one or more shared memory devices including a plurality of shared memory addresses; one or more central processing units (CPUs); one or more network interface units (NIUs), each of the one or more NIUs including an exclusive access monitor configured to monitor exclusive access to the plurality of shared memory addresses by a corresponding CPU of the one or more CPUs; one or more master nodes, each of the one or more master nodes coupled to a corresponding shared memory device of the one or more shared memory devices; and interconnects coupled to each of the one or more NIUs and each of the one or more master nodes, and configured to couple the one or more CPUs to the one or more shared memory devices.

[0144] In a second aspect, individually or in combination with one or more of the foregoing aspects, each of the one or more request nodes is coupled to a corresponding NIU in the one or more NIUs, wherein the one or more request nodes include one or more types of processors, and wherein the one or more types of processors include a central processing unit (CPU), a graphics processing unit (GPU), an image processing unit (ISP), a digital signal processor (DSP), a neural processing unit (NPU), a video encoder / decoder, a modem, or a combination thereof.

[0145] In a third aspect, individually or in combination with one or more of the foregoing aspects, each of the one or more NIUs includes a plurality of local exclusive monitors for non-shared memory addresses.

[0146] In the fourth aspect, either alone or in combination with one or more of the above aspects, the master node does not include an exclusive monitor.

[0147] In a fifth aspect, either alone or in combination with one or more of the foregoing aspects, the master node does not include an exclusive monitor for each of the plurality of shared memory addresses.

[0148] In a sixth aspect, individually or in combination with one or more of the foregoing aspects, each of the one or more shared memory devices is coupled to a corresponding master node in the one or more master nodes.

[0149] In a seventh aspect, either alone or in combination with one or more of the foregoing aspects, the interconnect is a consistent interconnect and is configured to couple each of the one or more requesting nodes to each of the one or more shared memory devices.

[0150] In the eighth aspect, individually or in combination with one or more of the foregoing aspects, each of the one or more NIUs is configured to couple each of the one or more request nodes to each of the one or more shared memory devices via the interconnect and the corresponding master node of each of the one or more shared memory devices.

[0151] In the ninth aspect, individually or in combination with one or more of the foregoing aspects, each of the one or more master nodes is configured to manage snooping operations to check the status of the exclusive monitor at the NIU.

[0152] In a tenth aspect, individually or in combination with one or more of the foregoing aspects, a particular NIU among the one or more NIUs is configured to: issue a read data exclusive command for a particular memory address among the plurality of shared memory addresses, and based on the read data exclusive command, to make the exclusive monitor of the particular exclusive monitor of the particular NIU stand by for the particular memory address.

[0153] In the eleventh aspect, individually or in combination with one or more of the foregoing aspects, a particular NIU among the one or more NIUs is configured to issue a unique exclusive write data command for the particular memory address based on the determination that the exclusive monitor for the particular memory address among the plurality of shared memory addresses is ready.

[0154] In a twelfth aspect, either alone or in combination with one or more of the foregoing aspects, the particular NIU is configured to: send a snoop query response command for the particular memory address based on receiving a snoop query command from a particular master node associated with a shared memory device including the particular memory address; and clear the exclusive monitor of the particular NIU for the particular memory address based on receiving a snoop clear command from the particular master node in response to the snoop query response command.

[0155] In a thirteenth aspect, individually or in combination with one or more of the foregoing aspects, the processing system is configured to: receive a read data completion message by a first requesting node, the read data completion message including data associated with an exclusive read request for a specific memory address of a first shared memory device and indicating that the specific memory address has been read; put a first exclusive monitor on standby by the first requesting node based on the read data completion message; transmit an exclusive write request for the specific memory address to a first master node associated with the first shared memory device by the first requesting node; transmit a snooping query response message for the specific memory address to the first master node by the first requesting node, the snooping query response message indicating a hit and responding to a snooping query message from the first master node and associated with the exclusive write request; receive a snooping cleanup message for the specific memory address from the first master node in response to the snooping query response message; and clear the first exclusive monitor by the first requesting node based on the snooping cleanup message for the specific memory address.

[0156] In a fourteenth aspect, individually or in combination with one or more of the foregoing aspects, the processing system is configured to cause the processing system to: transmit an exclusive read request for a specific memory address from a first requesting node to a first master node associated with a first shared memory device; have the first master node read data associated with the specific memory address from the first shared memory device; have the first master node transmit a read data completion message including the data associated with the specific memory address; have the first requesting node put a first exclusive monitor on standby based on the read data completion message; transmit a read completion confirmation from the first requesting node to the first master node; transmit an exclusive write request for the specific memory address from the first requesting node to the first master node; and have the first requesting node, in response to the exclusive write request for the specific memory address, read data from the first shared memory device. The first master node receives a snooping query message for the specific memory address; the first requesting node transmits a snooping query response message for the specific memory address to the first master node, the snooping query response message indicating a hit; the first master node writes data from the first shared memory device to the specific memory address in response to the snooping query response message indicating a hit; the first requesting node receives a snooping cleanup message for the specific memory address from the first master node in response to the snooping query response message indicating a hit; the first requesting node clears the first exclusive monitor based on the snooping cleanup message for the specific memory address; and the first master node transmits a write completion message for the specific memory address to the first requesting node in response to receiving a snooping cleanup response from each of the requesting nodes.

[0157] In a fifteenth aspect, alone or in combination with one or more of the foregoing aspects, a method for exclusive access management includes: a requesting node receiving a read data completion message, the read data completion message including data associated with an exclusive read request for a specific memory address of a shared memory device and indicating that the specific memory address has been read; the requesting node activating an exclusive monitor based on the read data completion message; the requesting node transmitting an exclusive write request for the specific memory address to a master node associated with the shared memory device; the requesting node transmitting a snooping query response message for the specific memory address to the master node, the snooping query response message indicating a hit and responding to a snooping query message from the master node and associated with the exclusive write request; the requesting node receiving a snooping cleanup message for the specific memory address from the master node in response to the snooping query response message; and the requesting node clearing the exclusive monitor based on the snooping cleanup message for the specific memory address.

[0158] In a sixteenth aspect, alone or in combination with one or more of the foregoing aspects, the method further includes: transmitting an exclusive read request for a specific memory address from a requesting node to a master node associated with a shared memory device; having the master node read data associated with the specific memory address from the shared memory device; and transmitting a read completion confirmation from the requesting node to the master node.

[0159] In a seventeenth aspect, alone or in combination with one or more of the foregoing aspects, the method further includes: the requesting node receiving a snooping query message for the specific memory address from the master node in response to the exclusive write request for the specific memory address.

[0160] In an eighteenth aspect, the method further includes: the master node writing data from the shared memory device to the specific memory address in response to the snooping query response message indicating the hit.

[0161] In a nineteenth aspect, the method further includes: the master node transmitting a write completion message for the specific memory address to the requesting node in response to receiving a snoop cleanup response from each of the plurality of requesting nodes.

[0162] In a twentieth aspect, the method further includes: before the transmission of the exclusive write request, a second requesting node transmits a second exclusive write request to the master node for the specific memory address; the second requesting node puts a second exclusive monitor on standby based on a second read data completion message; and the second requesting node clears the second exclusive monitor based on a second snoop cleanup message for the specific memory address received from the master node, wherein the second requesting node is unable to transmit the second write data request to the specific memory address because the second exclusive monitor is not on standby (i.e., cleared).

[0163] In a twenty-first aspect, the method further includes: after the transmission of the exclusive write request, the second requesting node transmits a third exclusive write request for the specific memory address to the master node; the second requesting node puts the second exclusive monitor on standby (e.g., puts it back on standby) based on a third read data completion message; and the requesting node transmits a second exclusive write request for the specific memory address to the master node associated with the shared memory device based on the fact that the second exclusive monitor is on standby for the specific memory address.

[0164] In a twenty-third aspect, the method further includes: a method for exclusive access management, the method comprising: transmitting an exclusive read request for a specific memory address from a requesting node to a master node associated with a shared memory device; the master node reading data associated with the specific memory address from the shared memory device; the master node transmitting a read data completion message including the data associated with the specific memory address; the requesting node activating an exclusive monitor based on the read data completion message; transmitting a read completion confirmation from the requesting node to the master node; transmitting an exclusive write request for the specific memory address from the requesting node to the master node; and the requesting node receiving a request for exclusive access from the master node in response to the exclusive write request for the specific memory address. The process includes: a snooping query message for a specific memory address; a snooping query response message for the specific memory address transmitted by the requesting node to the master node, the snooping query response message indicating a hit; the master node writing data from the shared memory device to the specific memory address in response to the snooping query response message indicating a hit; the requesting node receiving a snooping cleanup message for the specific memory address from the master node in response to the snooping query response message indicating a hit; the requesting node clearing the exclusive monitor based on the snooping cleanup message for the specific memory address; and the master node transmitting a write completion message for the specific memory address to the requesting node in response to receiving a snooping cleanup response from each of the requesting nodes.

[0165] In a twenty-fourth aspect, the method further includes: a method for exclusive access management comprising: having a requesting node put an exclusive monitor on standby based on a read data completion message for a specific memory address associated with a shared memory device, the read data completion message being received from a master node and in response to an exclusive read request for the specific memory address from the requesting node; and having the requesting node clear the exclusive monitor based on a snoop cleanup message for the specific memory address received from the master node, the snoop cleanup message being associated with an exclusive write request for the specific memory address from the requesting node.

[0166] In the description of the embodiments herein, numerous specific details (such as examples of specific components, circuits, and processes) are set forth to provide a thorough understanding of this disclosure. As used herein, the term "coupled" means a direct connection or a connection via one or more intermediate components or circuits. Moreover, specific terminology is set forth in the following description and for purposes of explanation in order to provide a thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that practicing the teachings disclosed herein may not require these specific details. In other instances, known circuits and devices are illustrated in block diagram form to avoid obscuring the teachings of this disclosure.

[0167] Certain portions of the following detailed description are presented using other symbolic representations of programs, logic blocks, processes, and data bit operations within computer memory. In this disclosure, programs, logic blocks, processes, etc., are conceived as a self-consistent sequence of steps or instructions that produce a desired result. These steps are those that require physical manipulation of physical quantities. Although not strictly necessary, these physical quantities typically take the form of electrical or magnetic signals that can be stored, transferred, combined, compared, and otherwise manipulated within a computer system.

[0168] In the accompanying drawings, a single block can be described as performing one or more functions. The one or more functions performed by this block can be performed in a single component or across multiple components, and / or can be performed using hardware, software, or a combination of hardware and software. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps are described below in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure. Additionally, the example device may include components other than those shown, including well-known components such as processors, memory, etc.

[0169] Unless otherwise specifically stated, it will be apparent from the following discussion that, throughout this application, the use of terms such as “access,” “receive,” “transmit,” “use,” “select,” “determine,” “normalize,” “multiply,” “average,” “monitor,” “compare,” “apply,” “update,” “measure,” “derive,” “set,” “generate,” etc., refers to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented as physical quantities in the registers, memories, or other such information storage, transmission, or display devices of the computer system.

[0170] The terms "device" and "apparatus" are not limited to one or a specific number of physical objects (such as a smartphone, a camera controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more components that can implement at least some parts of this disclosure. Although the description and examples herein use the term "device" to describe various aspects of this disclosure, the term "device" is not limited to a particular configuration, type, or number of objects. As used herein, an apparatus can include a device or part of a device for performing the described operations.

[0171] Certain components in a device or apparatus described as “component for access,” “component for receiving,” “component for transmitting,” “component for use,” “component for selection,” “component for determination,” “component for normalization,” “component for multiplication,” or other similarly named terms referring to one or more operations on data (such as image data) may refer to processing circuitry (e.g., application-specific integrated circuit (ASIC), digital signal processor (DSP), graphics processing unit (GPU), central processing unit (CPU)) configured to perform the described function by means of hardware, software, or a combination of hardware configured by software.

[0172] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0173] This article references Figures 1 to 2 The components, functional blocks, and modules described include processors, electronic devices, hardware devices, electronic components, logic circuits, memory, software code, firmware code, etc., or any combination thereof. Software should be interpreted broadly as instructions, instruction sets, code, code segments, program code, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, and / or functions, regardless of whether it is referred to as software, firmware, middleware, microcode, hardware description languages, or other terms. Furthermore, the features discussed herein can be implemented via dedicated processor circuitry, via executable instructions, or a combination thereof.

[0174] Those skilled in the art will understand that one or more blocks (or operations) described with reference to the accompanying drawings included with this specification can be combined with one or more blocks (or operations) described in another drawing with reference to the accompanying drawings. For example, one or more blocks (or operations) of FIG3 can be combined with... Figure 1 or Figure 2 A combination of one or more boxes (or operations).

[0175] Those skilled in the art will also recognize that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure. Those skilled in the art will also readily recognize that the order or combination of components, methods, or interactions described herein is merely illustrative, and that components, methods, or interactions of various aspects of this disclosure can be combined or performed in ways other than those illustrated and described herein.

[0176] The various exemplary logics, logic blocks, modules, circuits, and algorithmic processes described in conjunction with the specific implementations disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. The interchangeability of hardware and software has been generally described in terms of functionality and illustrated in the various exemplary components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0177] Hardware and data processing means for implementing the various exemplary logic units, logic blocks, modules, and circuits described herein can be implemented or executed using general-purpose single-chip or multi-chip processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic units, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. In some embodiments, the processor may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. In some embodiments, specific processes and methods may be performed by circuitry specific to a given function.

[0178] In one or more aspects, the described functionality may be implemented in hardware, digital electronic circuits, computer software, firmware, including the structures disclosed in this specification and their structural equivalents or any combination thereof. Implementation of the subject matter described in this specification may also be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a computer storage medium for execution by a data processing apparatus or for controlling the operation of a data processing apparatus.

[0179] If implemented in software, the functionality can be stored as one or more instructions or code on or transmitted through a computer-readable medium. The processes of the methods or algorithms disclosed herein can be implemented in a processor-executable software module that can reside on a computer-readable medium. Computer-readable media include both computer storage media and communication media, including any medium that can be implemented to transfer a computer program from one location to another. Storage media can be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other medium capable of storing desired program code in the form of instructions or data structures and accessible to a computer. Additionally, any connection may be appropriately referred to as a computer-readable medium. As used herein, disks and optical discs include compact optical discs (CDs), laser discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically magnetically reproduce data, while optical discs optically reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operation of a method or algorithm may reside as a set of code and instructions or any combination of code and instructions on a machine-readable medium and a computer-readable medium that may be incorporated into a computer program product.

[0180] Various modifications to the specific embodiments described in this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other specific embodiments without departing from the spirit or scope of this disclosure. Therefore, the claims are not intended to be limited to the specific embodiments shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles disclosed herein, and the novel features thereof.

[0181] Additionally, those skilled in the art will readily recognize that, for the convenience of describing the accompanying drawings, contrasting terms such as “upper” and “lower” or “front” and “back” or “top” and “bottom” or “forward” and “backward” are sometimes used, indicating relative positions on a correctly oriented page corresponding to the orientation of the drawings, and may not reflect the correct orientation of any device as implemented.

[0182] As used herein, the term "coupled to," in various tenses of the verb "couple," can mean that element A is directly connected to element B, or that other elements can be connected between elements A and B (i.e., element A and element B are indirectly connected) to perform certain intended functions. In the context of electrical components, the term "coupled to" can also be used herein to mean that conductors, traces, or other conductive materials are used to electrically connect elements A and B (and any components electrically connected between them). In some examples, the term "coupled to" means the transfer of electrical energy between elements A and B to perform certain intended functions.

[0183] In some examples, the term "electrical connection" means having current or being configured to have current flowing between components A and B. For example, in addition to wires, traces, or other conductive materials and components, components A and B may also be connected via resistors, transistors, or inductors. Furthermore, for radio frequency functions, components A and B may be "electrically connected" via capacitors.

[0184] Certain features described in this specification in the context of a single embodiment may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as operating in certain combinations and even originally claimed in this way, one or more features from the claimed combination may be removed from that combination in some cases, and the claimed combination may be for sub-combinations or variations thereof.

[0185] Similarly, although operations are depicted in a specific order in the figures, this should not be construed as requiring such operations to be performed in the indicated specific order or sequential order, or to perform all illustrated operations to achieve the desired result. Furthermore, the figures may schematically depict one or more example processes in the form of flowcharts. However, other operations not depicted may be combined with the schematically illustrated example processes. For example, one or more additional operations may be performed before, after, simultaneously with, or between any illustrated operation. In some contexts, multitasking and parallel processing may be advantageous. Moreover, the separation of the various system components in the embodiments described above should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, some other embodiments also fall within the scope of the appended claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired result.

[0186] As used herein (including the claims), the term "or" in a list of two or more items means that any one of the listed items may be used alone, or any combination of two or more listed items may be used. For example, if a composition is described as containing component A, B, or C, the composition may contain A alone; B alone; C alone; a combination of A and B; a combination of A and C; a combination of B and C; or a combination of A, B, and C. Moreover, as used herein (including the claims), "or" in a list of items beginning with "at least one of" indicates a separate list, such that a list such as "at least one of A, B, or C" refers to A or B or C or AB or AC or BC or ABC (i.e., A and B and C) or any combination of any of these items.

[0187] The term “substantially” is defined as being largely, but not necessarily entirely, of the specified content (and includes the specified content; for example, substantially 90 degrees includes 90 degrees, and substantially parallel includes parallel), as understood by one of ordinary skill in the art. In any specific implementation of the disclosure, the term “substantially” may be used in place of “[percentage]” of the specified content, where percentage includes 0.1%, 1%, 5%, or 10%.

[0188] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus, the apparatus comprising: Processing system, the processing system comprising: One or more shared memory devices, each of the one or more shared memory devices including a plurality of shared memory addresses; One or more request nodes, each request node corresponding to a processor of the processing system; One or more Network Interface Units (NIUs), each of the one or more NIUs including an exclusive monitor, the exclusive monitor being configured to monitor exclusive access by a corresponding requesting node among the one or more requesting nodes to the plurality of shared memory addresses; One or more master nodes, each of the one or more master nodes being coupled to a corresponding shared memory device in the one or more shared memory devices; and An interconnect, coupled to each of the one or more NIUs and each of the one or more master nodes, and configured to couple the one or more requesting nodes to the one or more shared memory devices.

2. The device of claim 1, wherein each of the one or more request nodes is coupled to a corresponding NIU in the one or more NIUs, wherein the one or more request nodes include one or more types of processors, and wherein the one or more types of processors include a central processing unit (CPU), a graphics processing unit (GPU), an image processing unit (ISP), a digital signal processor (DSP), a neural processing unit (NPU), a video encoder / decoder, a modem, or a combination thereof.

3. The device of claim 1, wherein each of the one or more NIUs includes a plurality of local exclusive monitors for non-shared memory addresses.

4. The device according to claim 1, wherein the master node does not include a global exclusive monitor.

5. The device of claim 1, wherein the master node does not include a global exclusive monitor for each of the plurality of shared memory addresses.

6. The device of claim 1, wherein each of the one or more shared memory devices is coupled to a corresponding master node in the one or more master nodes.

7. The device of claim 1, wherein the interconnect is a coherent interconnect and is configured to couple each of the one or more requesting nodes to each of the one or more shared memory devices.

8. The device of claim 1, wherein each of the one or more NIUs is configured to couple each of the one or more request nodes to each of the one or more shared memory devices via the interconnect and a corresponding master node of each of the one or more shared memory devices.

9. The device of claim 1, wherein each of the one or more master nodes is configured to manage snooping operations to check the status of the exclusive monitor at the one or more NIUs.

10. The device of claim 1, wherein a particular NIU among the one or more NIUs is configured to: issue a read data exclusive command for a particular memory address among the plurality of shared memory addresses, and, based on the read data exclusive command, make the exclusive monitor of the particular NIU's specific exclusive monitor standby for the particular memory address.

11. The device of claim 10, wherein a particular NIU of the one or more NIUs is configured to: issue a unique exclusive write data command for the particular memory address based on the determination that the exclusive monitor for the particular memory address among the plurality of shared memory addresses is ready.

12. The device of claim 11, wherein the particular NIU is configured to: Based on receiving a snooping query command from a specific master node associated with a shared memory device including the specific memory address, a snooping query response command is sent for the specific memory address; and Based on receiving a snoop clearing command from the specific master node in response to the snoop query response command, the exclusive monitor for the specific NIU is cleared for the specific memory address.

13. The apparatus of claim 1, wherein the processing system is configured to cause the processing system to: The first requesting node receives a read data completion message, which includes data associated with an exclusive read request for a specific memory address of the first shared memory device and indicates that the specific memory address has been read. The first requesting node activates the first exclusive monitor based on the read data completion message. The first requesting node transmits an exclusive write request for the specific memory address to the first master node associated with the first shared memory device; The first requesting node transmits a snooping query response message for the specific memory address to the first master node. The snooping query response message indicates a hit and is in response to a snooping query message from the first master node associated with the exclusive write request. The first requesting node receives a snoop cleanup message for the specific memory address from the first master node in response to the snoop query response message; as well as The exclusive monitor is cleared by the first requesting node based on the snooping cleanup message for the specific memory address.

14. The apparatus of claim 1, wherein the processing system is configured to cause the processing system to: The first requesting node transmits an exclusive read request for a specific memory address to the first master node associated with the first shared memory device; The first master node reads data associated with the specific memory address from the first shared memory device; The first master node transmits a read data completion message including the data associated with the specific memory address; The first requesting node activates the first exclusive monitor based on the read data completion message. A read completion confirmation is sent from the first requesting node to the first master node; The first requesting node transmits an exclusive write request for the specific memory address to the first master node; The first requesting node receives a pry query message for the specific memory address from the first master node in response to the exclusive write request for the specific memory address; The first requesting node transmits a snooping query response message for the specific memory address to the first master node, and the snooping query response message indicates a hit; The first master node writes data from the first shared memory device to the specific memory address in response to the snooping query response message indicating the hit; The first requesting node receives a snoop cleanup message for the specific memory address from the first master node in response to the snoop query response message indicating the hit; The first requesting node clears the first exclusive monitor based on the snooping cleanup message for the specific memory address; as well as The first master node sends a write completion message for the specific memory address to the first requesting node in response to receiving a snoop cleanup response from each of the requesting nodes.

15. A method for exclusive access management, the method comprising: The requesting node receives a read data completion message, which includes data associated with an exclusive read request for a specific memory address of a shared memory device and indicates that the specific memory address has been read; The requesting node activates the exclusive monitor based on the read data completion message. The requesting node transmits an exclusive write request for the specific memory address to the master node associated with the shared memory device; The requesting node transmits a snooping query response message for the specific memory address to the master node, the snooping query response message indicating a hit, and responding to a snooping query message from the master node associated with the exclusive write request; The requesting node receives a snoop cleanup message for the specific memory address from the master node in response to the snoop query response message; as well as The requesting node clears the exclusive monitor based on the snooping cleanup message for the specific memory address.

16. The method according to claim 15, further comprising: The requesting node transmits an exclusive read request for a specific memory address to the master node associated with the shared memory device; The master node reads data associated with the specific memory address from the shared memory device. as well as The requesting node sends a confirmation of read completion to the master node.

17. The method according to claim 15, further comprising: The requesting node receives a pry message for the specific memory address from the master node in response to the exclusive write request for the specific memory address.

18. The method according to claim 15, further comprising: The master node writes data from the shared memory device to the specific memory address in response to the snooping query response message indicating the hit.

19. The method according to claim 15, further comprising: The master node sends a write completion message for the specific memory address to the requesting node in response to receiving a snoop cleanup response from each of the multiple requesting nodes.

20. A method for exclusive access management, the method comprising: The requesting node transmits an exclusive read request for a specific memory address to the master node associated with the shared memory device; The master node reads data associated with the specific memory address from the shared memory device. The master node transmits a read data completion message including the data associated with the specific memory address; The requesting node activates the exclusive monitor based on the read data completion message. A confirmation of read completion is sent from the requesting node to the master node; The requesting node transmits an exclusive write request for the specific memory address to the master node; The requesting node receives a pry message for the specific memory address from the master node in response to the exclusive write request for the specific memory address; The requesting node transmits a snooping query response message for the specific memory address to the master node, and the snooping query response message indicates a hit; The master node writes data from the shared memory device to the specific memory address in response to the snooping query response message indicating the hit; The requesting node receives a snoop cleanup message for the specific memory address from the master node in response to the snoop query response message indicating the hit; The requesting node clears the exclusive monitor based on the snooping cleanup message for the specific memory address; as well as The master node transmits a write completion message for the specific memory address to the requesting node in response to receiving a snoop cleanup response from each of the requesting nodes.

Images