Command control of radio frequency elements in a system on a chip

Abstract

The present disclosure provides various techniques for command control of RF units in a system on a chip. A communication interface can receive command information from a host device, and a control circuit can process the command information according to different command groups, including local commands, global commands, and fast beam steering commands. In some embodiments, the command information can support access to SRAM circuits and register circuits, continuous read or write operations, selective applicability across multiple devices, and transfer of RF state information from storage circuits to RF-oriented circuits. In some embodiments, the fast beam steering commands can support local operations, global operations, subarray-based operations, manually-provided address updates, or automatically-incremented address updates. The disclosed techniques can support scalable command processing, coordinated RF state transfer, and efficient control of multiple RF channels and multiple devices.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 784,254, filed April 6, 2025, entitled “High-Speed ​​Generic Master IO Protocol,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to analog circuit design, and more specifically, to the control of radio frequency components in integrated circuits and wireless communication systems. Background Technology

[0004] Radio frequency (RF) systems and their applications have become an indispensable part of modern society, including, for example, sixth-generation (6G) telecommunications networks and beyond, Wi-Fi systems, satellite and non-terrestrial networks (NTN), sensor-interconnected communication (ISAC), vehicle-to-everything (V2X) systems, Internet of Things (IoT) applications, industrial and private networks, defense and aerospace systems, and medical and wearable devices.

[0005] As RF systems become increasingly complex, integrated circuits are often designed to include multiple RF units, such as transmit channels, receive channels, beamforming channels, gain control units, phase control units, and associated control circuitry, on a single semiconductor die or in a tightly integrated package. In many implementations, these RF units are controlled by a digital controller or an external host device via a communication interface. For example, serial control schemes can be used to write configuration values ​​to registers, read status information, load beam status data, or otherwise manage the operation of the RF units.

[0006] As the number of RF units increases and the number of programmable operating states expands, controlling such RF units can become increasingly complex. In particular, systems supporting multiple channels, multiple devices, or both can involve significant control traffic and repetitive device management operations. These considerations may become even more critical in systems operating under stringent timing, coordination, or scalability constraints.

[0007] Additional challenges may arise when RF operations involve the states of multiple stores, repetitive updates, or coordination across different parts of the system. In some applications, control signaling is expected to adapt to various operating conditions, including initialization, configuration, state selection, and changes in RF behavior during operation. As system size and functional density increase, the way control information is delivered and applied can have an increasingly significant impact on the complexity of the implementation and the overall system operation.

[0008] Furthermore, in systems that receive command information over time via a communication interface, the controller design can be affected by the format, ordering, and interpretation of the incoming command information. Therefore, improved techniques for command control of RF units in on-chip systems are still needed. Attached Figure Description

[0009] In the accompanying drawings, one or more embodiments of the present disclosure are shown by way of example and not limitation, wherein the same reference numerals denote similar elements. These drawings are not necessarily drawn to scale.

[0010] Figure 1 An example functional block diagram is shown in which the master device provides control signaling to a destination system-on-chip (SoC) that implements one or more of the technologies disclosed herein.

[0011] Figure 2 An example SoC architecture is shown, which demonstrates Figure 1 Some implementation details of the SoC implementation.

[0012] Figure 3 It shows what can be used as Figure 2 An example of a channel-addressable static random access memory (SRAM) structure as part of a digital control circuit.

[0013] Figure 4 It shows what can be used as with Figure 3 An example register structure that is part of a two-level latch arrangement associated with an SRAM structure.

[0014] Figure 5 An example command protocol is shown, illustrating example read / write mode and example fast beam manipulation mode.

[0015] Figure 6 An example command format for local SRAM write operations is shown.

[0016] Figure 7 An example command format for a local SRAM read operation is shown.

[0017] Figure 8 An example command format for local register write operations is shown.

[0018] Figure 9 An example command format for local register read operations is shown.

[0019] Figure 10 An example command format for global register write operations is shown.

[0020] Figure 11An example command format for global SRAM write operations is shown.

[0021] Figure 12 An example command format for local fast beam manipulation operations is shown.

[0022] Figure 13A and Figure 13B Together, an example command format for global fast beam manipulation operations is shown.

[0023] Figure 14 An example timing diagram for writing data to SRAM is shown.

[0024] Figure 15 An example timing diagram for reading data from SRAM is shown.

[0025] Figure 16 An example timing diagram for writing data to a register is shown.

[0026] Figure 17 An example timing diagram for reading data from a register is shown.

[0027] Figure 18 An example timing diagram is shown for submitting data from SRAM to RF circuitry in a local fast beam manipulation operation.

[0028] Figure 19 An example timing diagram is shown for submitting data from SRAM to RF circuitry during global fast beam manipulation operations. Detailed Implementation

[0029] In many radio frequency (RF) applications, a system-on-a-chip (SoC) may include multiple RF units and digital control circuitry that manages the operation of those RF units. For example, the digital control circuitry may receive command information from a master device, interpret the command information, and use the command information to configure, update, or otherwise control RF-related circuitry within the SoC. As the number of supported RF units, operating states, and control scenarios increases, the command architecture used to communicate with and control the SoC becomes an increasingly important aspect of the overall system design.

[0030] As mentioned above, an RF system may include multiple radio frequency units, multiple programmable operating states, and, in some cases, multiple integrated circuits coupled to a common control path. Therefore, controlling such an RF system can become increasingly complex, especially when control signaling is expected to support initialization, configuration, state selection, recurring updates, and coordinated operation across multiple RF channels or devices. These considerations may become even more important when command information is received over time via a communication interface, and the receiving control circuitry is expected to interpret and act upon the incoming command information under stringent timing, scalability, and implementation constraints.

[0031] Therefore, this section introduces techniques for command control of RF units within a System-on-a-Chip (SoC). In some embodiments, the SoC's communication interface can receive command information from a host device, and the SoC's control circuitry can process the command information based on different command groups, command types, or both. In some embodiments, the command information can support local command processing, global command processing, fast beam steering, or suitable combinations thereof. In some embodiments, the command information can also support continuous access operations, selective applicability across multiple devices, phased transmission of RF status information, and transmission of stored RF status information to the RF circuitry under selected operating conditions.

[0032] In summary, embodiments of this disclosure can provide a command architecture well-suited for controlling RF units within a SoC under various operating conditions. In some embodiments, the disclosed techniques can support efficient processing of command information for operations on a single device, operations on multiple devices, repetitive access operations, and RF state update operations. In some embodiments, the disclosed techniques can also support scalable control of the RF unit while accommodating implementation considerations associated with the coordinated transmission of communication interface signaling, command interpretation, and RF state information within the SoC.

[0033] Furthermore, in some embodiments, the disclosed techniques can provide a command framework applicable to different operating contexts within the same SoC or across multiple SoCs. For example, the same general command framework can be configured to support device-specific access, broader multi-device access, selective control of subsets of devices, and state transitions associated with RF operation. Therefore, the disclosed techniques can facilitate command processing in a flexible, scalable manner suitable for a wide range of RF-enabled systems and applications.

[0034] Numerous specific details are set forth below to provide a thorough understanding of the currently disclosed techniques. In other embodiments, the techniques described herein may be practiced without these specific details. In other instances, well-known features such as particular manufacturing techniques have not been described in detail to avoid unnecessarily obscuring this disclosure. References to “embodiment,” “an embodiment,” etc., in this specification mean that a particular feature, structure, material, or characteristic described is included in at least one embodiment of this disclosure. Therefore, the appearance of these phrases in this specification does not necessarily refer to the same embodiment. On the other hand, such references are not necessarily mutually exclusive. Furthermore, particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. Moreover, it should be understood that the various embodiments shown in the accompanying drawings are merely illustrative representations and are not necessarily drawn to scale.

[0035] Certain details concerning the structures or processes typically associated with integrated circuit design, including the physical layout of typical passive components (e.g., inductors, capacitors, resistors, filters, and related sub-components), may not be set forth in the following description, as including such well-known details could obscure important aspects of the disclosed technology. Furthermore, while the following disclosure illustrates several embodiments of different aspects of this disclosure, several other embodiments may have different configurations or different components than those described in this section. Therefore, the introduced technology may have other embodiments with or without the elements described below.

[0036] For the purposes of this discussion, the terms “coupling” and “connection” and their derivatives may be used to describe structural relationships between components. It should be understood that these terms are not intended to be synonyms for each other. Rather, in certain embodiments, “connection” may be used to indicate that two or more elements are in direct contact with each other. Unless otherwise stated in the context, the term “coupling” may be used to indicate that two or more elements are in direct or indirect contact with each other (with other intermediate elements between them), or that two or more elements cooperate or interact with each other (e.g., as in a causal relationship), or both. Notwithstanding the foregoing, and unless otherwise stated or explicitly stated in the context, references to “series connection” or “parallel connection” of components refer to their functional electrical relationship, not to the requirement of uninterrupted physical conductors.

[0037] For the purposes of this discussion, an "upstream" device refers to a device that is located earlier in the daisy-chain command distribution path than one or more "downstream" devices, where "upstream" and "downstream" describe relative positions in the chain, rather than any specific upload or download operation.

[0038] Figure 1An example system 100 is illustrated, in which a master device 110 provides command signaling to a target system-on-chip (SoC) 120 that implements one or more of the techniques disclosed herein. The master device 110 can be implemented using any of a variety of control platforms, such as a field-programmable gate array (FPGA), a microcontroller unit (MCU), a processor-based control board, a personal computer, or other suitable controller. In some embodiments, the master device 110 can generate command information for configuring, updating, or otherwise controlling one or more radio frequency (RF) signaling units 150 of the SoC 120. In some embodiments, the master device 110 can also receive readback or status information from the SoC 120. The master device 110 may also include interface-based processing and / or control circuitry 118, which may include artificial intelligence-based processing, algorithmic beam control logic, calibration logic, or other control functions that provide command information to the SoC 120. Note that the examples described in this disclosure are provided for illustrative purposes only. Actual implementations may vary, and the disclosed techniques can be similarly applied to various other embodiments.

[0039] As further shown, the master device 110 can communicate with the SoC 120 via a communication path including a data interface 112 and one or more control signals 114. The data interface 112 may include a data input path DATA_in and a data output path DATA_out. In some embodiments, the communication path between the master device 110 and the SoC 120 can be implemented using any of a variety of input / output (I / O) technologies. For example, a general purpose input / output (GPIO) interface, a serial peripheral interface (SPI), a serializer / deserializer (SerDes) interface, or other suitable interface technologies can be used to implement the communication path. Although many examples described below use SPI-based implementations for ease of explanation, the disclosed technologies are not limited to SPI and can be similarly applied to other I / O technologies. For example, in some SerDes-based implementations, protocol behavior may remain substantially similar to the corresponding SPI-based implementation, while command framing may be adapted to meet interface-specific constraints. In some embodiments, such as due to constraints associated with FPGA modules or associated interface logic, the command and data lengths of a SerDes-based implementation may be arranged as multiples of a selected word length, such as thirty-two bits. In some embodiments, a synchronization symbol, an end symbol, or both may be added to the command stream. For example, control signal 114 may include clock, chip select, enable, framing, reset, or other control signals that define transaction timing or operational states for communication between master device 110 and SoC 120. In some embodiments, data interface 112 may carry a command stream that includes command fields and associated data fields for controlling circuitry within SoC 120.

[0040] SoC 120 may include a mixed-signal TX / RX unit 130, a digital unit 140, and an RF signal unit 150. The mixed-signal TX / RX unit 130 may receive command streams and associated control signaling from the master device 110 and may provide corresponding signals to the digital unit 140. The digital unit 140 may process the command streams and generate control information for the RF signal unit 150. The RF signal unit 150 may include multiple RF channels 150(0), 150(1), 150(2) to 150(N-1), where N may be any suitable positive integer.

[0041] Still referencing Figure 1The mixed-signal TX / RX unit 130 may include a high-speed I / O receiver 134, and in some embodiments, may include a daisy-chain repeater 136. The high-speed I / O receiver 134 may receive data 132, which may be provided as a single-ended signal, differential signal, or other suitable signaling format, and may provide corresponding signals to the digital unit 140 for command decoding and control. In some embodiments, the daisy-chain repeater 136 may forward command information to one or more downstream devices through repeater ports (e.g., shown as Repeater_port_0 to Repeater_port_N-1). Therefore, Figure 1 An example is shown in which the master device can communicate with the target SoC, which includes command processing circuitry for controlling multiple RF signaling units, and optionally includes repeater circuitry for extending command signaling to additional devices.

[0042] Figure 2 It shows the corresponding Figure 1 An example system-on-chip (SoC) architecture 200 of one embodiment of SoC 120 is shown. SoC architecture 200 includes a mixed-signal transmit / receive (TX / RX) unit 230, a digital unit 240, and a radio frequency (RF) signaling unit 250. In the illustrated embodiment, the mixed-signal TX / RX unit 230 is coupled to external interface signals such as CDN, CSB, CLOCK, DATA_in, and DATA_out. For example, CDN can provide a reset signal, such as an active-low reset signal; CSB can provide an enable or chip select signal for interface transactions; CLOCK can provide a clock signal for communication and command processing; DATA_in can carry incoming commands and associated data information; and DATA_out can carry readbacks or other output information from SoC architecture 200. The mixed-signal TX / RX unit 230 can receive command information and associated signaling from master device 110 and can provide corresponding signals to digital unit 240 for command processing. RF signal unit 250 may include multiple channel-indexed RF paths, for example shown as channel_0, channel_1 to channel_(N-1), where N can be any suitable positive integer.

[0043] In some embodiments, the mixed-signal TX / RX unit 230 can achieve the above-mentioned... Figure 1At least a portion of the communication interface discussed. For example, the mixed-signal TX / RX unit 230 can receive a command stream on DATA_in and provide readback information on DATA_out. In some embodiments, the communication path can correspond to a Serial Peripheral Interface (SPI) based interface, where DATA_in and DATA_out correspond to the SPI data input and output paths, CLOCK corresponds to the SPI clock, and CSB corresponds to the active-low interface enable signal. In some embodiments, SCLK and SDI can support data rates up to about 100 MHz or 100 Mbps, respectively, while SDO can support lower output rates, such as about 25 Mbps on a shared bus, and can remain in a high-impedance state when invalid. However, the disclosed techniques are not limited to SPI, and other interface technologies can be similarly applied. In some embodiments, the mixed-signal TX / RX unit 230 can condition, convert, deserialize, or otherwise prepare received signaling for use by circuitry in the digital unit 240.

[0044] Digital unit 240 may include a digital controller, a successive approximation register analog-to-digital converter (SARADC) and / or a temperature (T) sensor block, a static random access memory (SRAM) block shown as 16×16 SRAM, and a register block shown as 16×16 registers. The digital controller may receive command information from mixed-signal TX / RX unit 230 and may decode the received command information to identify command groups, command types, addresses, data values, or combinations thereof. Based on the decoded command information, the digital controller may generate internal control signals, such as regRD, writeDA, sramRD, sramADDR, and sramRE / WE, for accessing the SRAM and register structures. For example, regRD may carry read data from a register; writeDA may carry data to be written to the SRAM or register; sramADDR may identify an SRAM address; sramRD may carry SRAM read data; and sramRE / WE may indicate SRAM read enable and write enable operations. In some embodiments, the SARADC / T sensor block can provide operating condition information, such as analog readings or temperature-related information, to the digital controller, enabling the corresponding configuration or bias settings to be managed within the SoC architecture 200.

[0045] In some embodiments, the SRAM 16×16 and registers 16×16 may together form part of the memory circuitry of the SoC architecture 200. The SRAM 16×16 may store RF status information, such as gain information, phase information, beam status information, or other channel-related RF information. The registers 16×16 may store register-based information, such as bias settings, control values, calibration values, or other configuration information associated with the operation of the RF signal unit 250 or related circuitry. In some embodiments, the digital unit 240 may also include additional register resources, such as an 8-bit Reg×12 shown, which may be used to control or configure analog-related circuitry, such as low-dropout regulators (LDOs), bandgap circuits (BGs), switches, or other auxiliary circuitry. In some embodiments, the digital controller may access the SRAM 16×16 and registers 16×16 using different command types, enabling the writing, reading, updating, or otherwise managing of RF status information and register-based information under the control of a received command stream.

[0046] As further shown, digital unit 240 may include a per-channel storage element, shown as a reset-set flip-flop (RS FF), positioned between the SRAM and register structure and the RF signal unit 250. In some embodiments, the RS FF may provide active storage for RF channel control information, while the SRAM 16×16 and register 16×16 may hold pending information that will later be submitted to the RF signal unit 250. For each RF channel, the illustrated RS FF block may receive a 16-bit value associated with SRAM information and / or a 16-bit value associated with register information. In some embodiments, the RS FF block may be implemented as part of a two-stage latch arrangement, wherein pending data is first loaded and then, in response to a Fast_LOAD signal, transferred to an active RF-oriented storage device.

[0047] The Fast_LOAD signal can be generated by a digital controller or provided as an external signal. In some embodiments, the Fast_LOAD signal can be generated from a dedicated hardware load pin or from a load bit embedded in a received command. According to one or more implementations, Fast_LOAD can enable updated beam status information or updated register information to be transmitted to RF-oriented storage elements for one or more RF channels. When the Fast_LOAD signal is asserted, pending information associated with the SRAM and register structures can be transmitted to the valid RSFF storage device driving the RF signal unit 250. In some embodiments, each RF channel may include a bias register having one or more enable bits that enable a data path from the SRAM circuitry to the corresponding RF output channel. For example, bits 30 and 31 of the bias register can be used to enable a data path such that RF status information stored in the SRAM circuitry can be routed to the RF circuitry of the corresponding RF channel. In this way, the SoC architecture 200 can support staged loading of RF status information, which is then transmitted to the RF signal unit 250 in a controlled manner.

[0048] Figure 3 It shows what can be used as Figure 2 This example illustrates a channel-addressable static random access memory (SRAM) structure 300 as part of the digital control circuitry of a SoC architecture 200. In the illustrated embodiment, the SRAM structure 300 may form part of a 16×16 block of SRAM for digital cells 240 and may store radio frequency (RF) status information to be processed for one or more RF channels. As shown, the SRAM structure 300 may be channel-addressable while sharing common address, data, and control lines with other SRAM structures. In this way, the SRAM structure 300 can support command-driven access to the stored RF status information while reducing the wiring overhead associated with separate dedicated control lines for each RF channel.

[0049] In some embodiments, the SRAM structure 300 includes channel identifier comparison logic that compares the received channel identifier Channel ID[3:0] with the locally associated channel value Channel[3:0]. For example, each bit of the received Channel ID[3:0] can be compared with the corresponding bit of the local Channel[3:0], and the resulting comparison outputs can be combined to generate a match signal. When the match signal is valid, the SRAM structure 300 can respond to an incoming command transaction. When the match signal is not valid, the SRAM structure 300 can remain inactive for that transaction. Therefore, the comparison logic can allow multiple channel-specific SRAM structures to share a common bus while still enabling channel-selective access.

[0050] As further illustrated, a set of shared access signals can be provided to SRAM structure 300, such as Address[6:0], Data In[7:0], write enable, read enable, and clock. In some embodiments, these shared access signals can be gated by a match signal such that when a channel identifier matches a local channel value, a signal is delivered to internal SRAM control circuitry. The internal control circuitry can then control read or write operations within SRAM structure 300. In this way, common address, data, and control signals can be reused across multiple channel-specific SRAM structures, while channel comparison determines which SRAM structure is active for a given transaction.

[0051] In the illustrated embodiment, the SRAM structure 300 includes two SRAM banks, shown as SRAM-A and SRAM-B. Each SRAM bank may include a bit cell bank, a row decoder, a column decoder, and / or a sense amplifier, as well as a corresponding control unit. In some embodiments, the two SRAM banks may together store different portions of a wider RF status word. For example, SRAM-A may store the low byte portion of a 16-bit RF status word, while SRAM-B may store the high byte portion of a 16-bit RF status word. As shown, SRAM-A can provide Data Out[7:0], and SRAM-B can provide Data Out[15:8], allowing the outputs of the two banks together to define a wider range of RF status values ​​for downstream circuitry. Note that although... Figure 3 Two SRAM banks are shown, but SRAM storage devices can be physically implemented in other ways. For example, depending on the implementation requirements of a particular application, a single physical SRAM with a width of 16 bits can be logically divided into two 8-bit banks, four 4-bit banks, or another suitable number of logical bank portions.

[0052] Each SRAM bank is also coupled to a two-stage output storage arrangement comprising a level 1 reset-set flip-flop (RS-FF) and a level 2 RS-FF. Data read from the corresponding SRAM bank can first be loaded into the level 1 RS-FF. Then, a Fast_LOAD signal can transfer the data stored in the level 1 RS-FF to the level 2 RS-FF. In some embodiments, the level 1 RS-FF can hold the output data to be processed, while the level 2 RS-FF can hold the valid output data provided on the data output bus. Therefore, the SRAM structure 300 can support a staged transfer arrangement in which stored RF status information is first read from the SRAM storage device and then selectively submitted to the valid output storage device in response to Fast_LOAD. In some embodiments, the output data provided by the SRAM structure 300 can be supplied to downstream register structures, RF channel storage circuitry, RF signal units, or combinations thereof.

[0053] Figure 4 It shows what can be used as Figure 2 An example register structure 400 is provided for the digital control circuitry portion of the System-on-Chip (SoC) architecture 200. In some embodiments, register structure 400 may be formed with... Figure 3 This is a portion of the two-stage latch arrangement associated with the static random access memory (SRAM) structure 300. In the illustrated embodiment, the register structure 400 may form a portion of the register 16×16 block of the digital unit 240 and may store pending control information for one or more parts of the SoC architecture 200. For example, the register structure 400 may store bias information, control values, calibration information, or other register-based information associated with the operation of radio frequency (RF) signal units, analog-related circuitry, or other circuitry within the SoC architecture 200. As shown, the register structure 400 may be register-based addressable while sharing common address, data, and control lines with other register structures.

[0054] In some embodiments, register structure 400 includes register identifier comparison logic that compares the received register identifiers Register ID[6:0] with the locally associated register addresses Reg Address[6:0]. For example, each bit of the received Register ID[6:0] can be compared with the corresponding bit of the local Reg Address[6:0], and the resulting comparison outputs can be combined to generate a match signal. When the match signal is valid, register structure 400 can respond to an incoming command transaction. When the match signal is not valid, register structure 400 can remain inactive for that transaction. In this way, multiple register structures can share a common bus while still supporting selective register access.

[0055] As further illustrated, a set of shared access signals, such as Data In[7:0], write enable, read enable, and clock, can be provided to register structure 400. In some embodiments, these shared access signals can be strobed by a match signal such that when a received register identifier matches a local register address, a signal is delivered to internal register circuitry. The internal register circuitry can then perform a write operation, a read operation, or both, based on a control signal that is set to valid. In some embodiments, when a read enable condition is present and register structure 400 is selected, data held in register structure 400 can be provided to upstream circuitry for reading back via a shared output path, such as Data Out[7:0]. In some embodiments, register structure 400 can selectively drive the shared output path when addressed for readback, while other register structures remain inactive to avoid bus contention. Thus, register structure 400 can support addressable access to selected registers while allowing reuse of common address, data, and control resources across multiple register structures.

[0056] In the illustrated embodiment, register structure 400 is shown as an 8-bit register structure comprising a first-level storage arrangement identified as a Level 1 Data Flip-Flop (DFF) and a second-level storage arrangement identified as a Level 2 DFF. In some embodiments, the Level 2 storage arrangement may alternatively be implemented using a Reset-Set Flip-Flop (RS-FF) or another suitable latch or flip-flop structure. Data written to register structure 400 may first be captured as pending data in the Level 1 DFF. Then, a Fast_LOAD signal may cause the pending data stored in the Level 1 DFF to be transferred to the Level 2 storage arrangement, such that the Level 2 storage arrangement provides valid output data on Data Out[7:0]. In this way, register structure 400 may support a staged transfer arrangement in which register data is first loaded into the pending storage level and then selectively committed to the valid storage level in response to Fast_LOAD.

[0057] In some embodiments, Figure 4 The phased transmission arrangement can be related to the above regarding Figure 3 The described staged transmission arrangement is used together. For example, register-based information and static random access memory (SRAM)-based information can both be loaded into the first-stage storage device and later submitted to the effective RF-oriented circuitry in a coordinated manner.

[0058] Having understood the example system architecture, memory architecture, and staged transmission structure described above, we will now discuss example command protocols that can be used to access SRAM circuits, access register circuits, and control the transmission of RF status information to RF circuits. See below for reference. Figure 5 The accompanying drawings further illustrate example command groups, command types, command formats, and timing relationships that can be used in various embodiments.

[0059] Figure 5 An example command protocol is shown, in which Table 500 describes example read / write mode commands and Table 505 describes example fast beam manipulation mode commands. Figure 5 The command protocol can be provided by Figure 2 The digital controller is implemented to interpret command information received from the master device via the communication interface and control static random access memory (SRAM) circuitry, register circuitry, radio frequency (RF) signal units, or suitable combinations thereof. Therefore, Figure 5 This provides a protocol-level view of how the SoC architecture 200 distinguishes different categories of commands and routes them to the appropriate storage or RF control functions. In the discussion below, single-chip commands that require identifier matching during execution can also be referred to as local commands, and multi-chip commands that do not require identifier matching during execution can also be referred to as global commands.

[0060] Table 500 illustrates example read / write mode commands. In the illustrated arrangement, read / write mode commands include local commands and global commands. Local commands may include local SRAM write commands, local SRAM read commands, local register write commands, and local register read commands. Global commands may include global register write commands and global SRAM write commands. In the illustrated example, the communication interface supports, for example, eight programming modes, and the command mode can be selected using, for example, the three most significant bits of the command. The mode field (e.g., shown as MODE[2:0]) together with the submode field (e.g., shown as sMODE[1:0]) can identify which command is invoked (where applicable). Table 500 also shows representative command lengths for the illustrated implementation, such as a 24-bit command format for local read / write commands and a 16-bit command format for certain global write commands.

[0061] The command arrangement reflected in Table 500 supports both read and write operations, and further supports both single-step and continuous operations. For example, after issuing an initial command, the master device can continue to provide additional data values, additional address values, or both, allowing the digital controller to continue executing the commanded operation without re-issuing the command header. This arrangement reduces command overhead and can improve efficiency when multiple data words, multiple addresses, or both are involved. Local commands can be processed when the chip address or identifier carried by the command matches the identifier associated with the receiving device. In contrast, global commands can be processed without requiring such device address matching, thereby allowing multiple SoCs on a shared bus to receive the same incoming command stream and act on the same incoming command stream. This shared bus arrangement simplifies command distribution from a single master device to multiple SoCs while still allowing access from individual devices where appropriate.

[0062] Table 505 illustrates example fast beam control mode commands. The fast beam control command family includes local fast beam control commands and global fast beam control commands. Local fast beam control commands can be used to transmit RF status information associated with a selected SRAM address for a selected device. Global fast beam control commands can be used to update RF channels for selected subarrays across all devices or across devices sharing a communication path. As further shown in Table 505, global fast beam control commands are differentiated based on a handover enable setting. When handover enable is disabled, successive updates can be explicitly provided, such as by appending additional address information for subsequent state changes. When handover enable is enabled, the controller can automatically advance the state of successive stores after the initial command. Table 505 also shows representative command length relationships, such as 16+8. N bits and 16+2 N bits, where N can represent the number of additional values ​​or update instances.

[0063] Figure 5 The command protocol can also be used in conjunction with the above regarding Figures 2-4 The described phased transfer architecture works collaboratively. For example, SRAM and register circuits can use two levels of output storage, and a load signal such as RFLOAD can transfer information to be processed from the first storage level to the second storage level, making the updated value valid together. Therefore, the command protocol can not only support reading and writing information from the storage, but also coordinate the transfer of RF-related information to the valid RF-oriented circuitry. RF load operations can also be considered an exception to normal address matching behavior, allowing RF load operations to be universally performed by all devices on the shared bus, regardless of whether the chip address carried by the command matches a specific device.

[0064] The command stream itself can also be arranged according to implementation considerations. For example, the command information can be sent first the most significant bit and last the least significant bit, and input / output data can be latched on a selected clock edge (such as the rising clock edge). The command field can also be arranged so that command interpretation can be performed effectively when the command is received. Therefore, Tables 500 and 505 together illustrate example command families, command classifications, and mode selection mechanisms that can be used to access SRAM circuitry, access register circuitry, and control fast beam manipulation and RF status transmission within the SoC architecture 200.

[0065] Figure 6 An example command format for a local static random access memory (SRAM) write operation 600 is shown. For example, command format 600 can be used to write radio frequency (RF) status information into the SRAM circuitry of a selected device. In some embodiments, the local SRAM write operation 600 can be used to populate beam states stored in the SRAM for multiple RF channels of a device. For example, the stored beam states may include phase information, gain information, or both. In the illustrated format, the command may include a mode selection field, an SRAM number field, a channel selection field, a transmit / receive selection field, an SRAM address field, a chip address field, and one or more reserved bits, followed by one or more additional data portions.

[0066] In the illustrated embodiment, the mode selection field MODE[2:0] occupies bits [23:21] and can identify the command as a local SRAM write operation 600. For example, the value 000 can identify the local SRAM write mode shown. The bit

[20] shown as sramNO can identify which SRAM byte or SRAM portion to write. This can be useful in cases where a wide RF status word is stored across multiple SRAM portions, such as where the low byte is stored in one SRAM portion and the high byte is stored in another. The bits [19:16] shown as sramCH[3:0] can identify the selected RF channel. In the illustrated example, the 4-bit channel field can identify up to sixteen RF channels. In embodiments that support both transmit and receive operations, the bit

[15] shown as TXRX can identify whether the write operation is associated with a transmit path or a receive path. In some embodiments that support only transmit operations or only receive operations, the TXRX field can be omitted.

[0067] Bits [14:8] shown as sramADDR[6:0] can identify the SRAM address to which the write operation is directed. In the illustrated embodiment, the SRAM address can identify the starting SRAM address for the local SRAM write operation 600. Bits [7:1] shown as chipAddr[6:0] can identify the target device address, such that the local SRAM write operation 600 is processed by the selected device. Bit [0] is shown as a reserved or unimportant bit. In some embodiments, the most significant bit of the command can be sent first, and the command field can be arranged such that when the command is received, command interpretation can begin from the high-order bit. This field arrangement can simplify hardware interpretation by allowing the controller to identify the command type and associated target information before receiving all additional data.

[0068] The local SRAM write operation 600 can support continuous write operations. For example, after the initial command identifies the selected mode, SRAM portion, channel, transmit / receive settings, starting SRAM address, and target device, additional data words can be appended without re-issuing the command header. In the example shown, the appended data is shown in 8-bit portions because each write can correspond to one SRAM byte. In the case of using two 8-bit words in the full RF state, such as one word for phase information and one word for gain information, the local SRAM write operation 600 can continuously write those byte values ​​to the selected SRAM storage device.

[0069] In some embodiments, consecutive local SRAM write operations can be performed in a defined order. For example, starting from a starting SRAM address, successive data words can be written to consecutive RF channels. After all RF channels associated with the starting SRAM address have been written, the write operation can continue from the first RF channel at the next SRAM address. This order can be repeated, allowing multiple stored beam states to be loaded efficiently across multiple channels. Therefore, command format 600 can support bulk programming of RF status information with reduced command overhead because the master device does not need to repeatedly retransmit the complete command header for each channel write or each consecutive SRAM address.

[0070] Figure 6The I / O pin table further illustrates example controller signal behavior associated with local SRAM write operations 600. For example, writeDA[7:0] can carry write data during an SRAM write operation, while sramRD[7:0] can remain idle. Similarly, sramWE can be set to valid to indicate write enable, while sramRE can remain invalid during a write operation. Signals such as sramCLK can provide a clock for SRAM access. These signal relationships help illustrate how the digital controller decodes... Figure 6 The command field shown above is followed by an example of an internal implementation of a local SRAM write operation 600.

[0071] Therefore, the local SRAM write operation 600 provides an example of a command format that can select a target device, identify the selected RF channel and SRAM section, specify the starting SRAM address, and support the continuous writing of additional data into the SRAM circuit to store RF status information.

[0072] Figure 7 An example command format for a local static random access memory (SRAM) read operation 700 is shown. Command format 700 can be used, for example, to read radio frequency (RF) status information from the SRAM circuitry of a selected device. In some embodiments, the local SRAM read operation 700 can be used to access beam states for multiple RF channels of a device stored in the SRAM. For example, each beam state may include two 8-bit words containing phase information, gain information, or both for the corresponding RF channel. In the illustrated format, the command may include a mode selection field, an SRAM number field, a channel selection field, a transmit / receive selection field, an SRAM address field, a chip address field, and one or more reserved bits, followed by one or more output data portions provided on a serial data output path.

[0073] In the illustrated embodiment, the mode selection field MODE[2:0] occupies bits[23:21] and can identify the command as a local SRAM read operation 700. For example, the value 001 can identify the illustrated local SRAM read mode. Bits

[20] shown as sramNO can identify which SRAM byte or SRAM portion to read. This can be useful in cases where a wide RF status word is stored across multiple SRAM portions, such as where a low byte is stored in one SRAM portion and a high byte is stored in another. Bits[19:16] shown as sramCH[3:0] can identify the selected RF channel. In the illustrated example, the 4-bit channel field can identify up to sixteen RF channels. In embodiments that support both transmit and receive operations, bits

[15] shown as TXRX can identify whether the read operation is associated with a transmit path or a receive path. In some embodiments that support only transmit operations or only receive operations, the TXRX field can be omitted.

[0074] Bits [14:8] shown as sramADDR[6:0] can identify the SRAM address from which the read operation begins. In the illustrated embodiment, the SRAM address can identify the starting SRAM address for the local SRAM read operation 700. Bits [7:1] shown as chipAddr[6:0] can identify the target device address, such that the local SRAM read operation 700 is processed by the selected device. Bit [0] is shown as a reserved or unimportant bit. As with other command formats described herein, the most significant bit of the command can be sent first, and the command field can be arranged such that when the command is received, command interpretation can begin from the higher-order bit.

[0075] The local SRAM read operation 700 can support continuous read operations. For example, after the initial command identifies the selected mode, SRAM portion, channel, transmit / receive settings, starting SRAM address, and target device, the digital controller can continue the read operation without re-issuing the command header. In some embodiments, beam status data can be retrieved sequentially across multiple RF channels starting from the starting SRAM address. This arrangement can reduce the overhead associated with repeated command issuance and improve efficiency when multiple stored beam states need to be read from the SRAM circuitry.

[0076] In some embodiments, successive local SRAM read operations can be performed in a defined sequence corresponding to the organization of stored beamstates. For example, data can be read on multiple RF channels associated with a starting SRAM address, and then read activity can continue for additional stored state locations as the operation continues. This arrangement can be useful when the master device reads back the stored beamstate information for verification, calibration, diagnostics, or other control purposes. Thus, local SRAM read operation 700 can provide efficient access to stored phase and gain information across multiple channels and beamstate entries.

[0077] Figure 7 The I / O pin table further illustrates example controller signal behavior associated with the local SRAM read operation 700. For example, writeDA[7:0] can remain idle during a read operation, while sramRD[7:0] can become active to provide read data from the SRAM circuitry via the controller. Similarly, sramWE can remain inactive, while sramRE can be active to indicate read enable. Signals such as sramCLK can provide a clock for SRAM access. These signal relationships help illustrate how the digital controller performs during decoding. Figure 7 The command field shown at the top is followed by an example of an internal implementation of a local SRAM read operation 700.

[0078] Therefore, the local SRAM read operation 700 provides an example of a command format that can select the target device, identify the selected RF channel and SRAM section, specify the starting SRAM address, and support sequential reading of stored RF status information from the SRAM circuitry.

[0079] Figure 8 An example command format for a local register write operation 800 is shown. Command format 800 can be used, for example, to write register-based information to a selected device. Such local register write operations can be used to configure and control device-specific settings, such as chip-level configuration settings, radio frequency (RF) channel parameters, bias values, gain values, phase values, or other control information stored in register circuitry. In the format shown, the command may include a mode selection field, an RF load (RFLOAD) field, a submode field, a register address field, a chip address field, one or more reserved bits, and one or more additional data portions.

[0080] In the illustrated embodiment, the mode selection field MODE[2:0] occupies bits [23:21] and can identify the command as a local register write operation 800. For example, the value 010 can identify the local register access family shown, and the submode field SMODE[1:0] can further identify a local register write operation, such as by the value 00. Bit

[20] shown as the RFLOAD field can indicate whether the newly written register information is to be retained in the first memory level or transferred to the second memory level for valid use. In the illustrated example, bits [17:15] are shown as indifferent bits. Bits [14:8] shown as regADDR[6:0] can identify the target register address. Bits [7:1] shown as the chip address field can identify the selected device, such that the local register write operation 800 is processed by the addressed device while other devices on the shared bus remain unaffected. Bit [0] is shown as reserved or indifferent bits.

[0081] The arrangement of fields in Command Format 800 also facilitates hardware parsing by the digital controller. For example, higher-order bits can identify the command family and sub-mode before the register address and chip address are fully received. Additionally, the chip address field can be located later in the command word because identifier comparison places less burden on the controller compared to previous mode decoding. Reserved bits at the end of the command word also provide additional timing margin, such as one bit of time, for the Serial Peripheral Interface (SPI) controller or other interface circuitry to complete parsing and prepare the corresponding internal control signals.

[0082] The local register write operation 800 can support sequential write operations. For example, after the initial command identifies the command mode, RFLOAD setting, submode, starting register address, and target device, additional data words can be appended without re-issuing the command header. In some embodiments, each appended data word can correspond to an 8-bit register write value. The target register address can be automatically incremented as subsequent appended data words are received. This arrangement can reduce command overhead and improve efficiency when programming multiple consecutive register locations.

[0083] The RFLOAD field controls when newly written register data becomes valid. When the RFLOAD field indicates a first state, such as RFLOAD=0, the written data can be stored in a first-level or buffer register, while the valid RF-facing register remains unchanged. When the RFLOAD field indicates a second state, such as RFLOAD=1, the written data can be transferred from the first-level register to the second-level valid register. In some embodiments, transfers can be made to all devices on the shared bus regardless of chip address matching, allowing for coordinated application of update settings. This arrangement can support phased loading of new register information, followed by controlled activation of the new information.

[0084] Figure 8 The I / O pin table further illustrates example controller signal behavior associated with local register write operations 800. For example, writeDA[7:0] can be active to carry register write data, while regRD[7:0] can remain idle during the write operation. The register clock signal, shown as regCLK, can be active during the write operation, and the register write enable signal, shown as regWE, can also be active, causing the addressed register circuitry to capture the incoming data. Thus, the I / O pin table illustrates how the digital controller can decode... Figure 8 The command field shown above is followed by an example of an internal local register write operation 800.

[0085] Therefore, the local register write operation 800 provides an example of a command format that can select the target device, identify the register address, support writing additional data values ​​on continuously incrementing register addresses, and selectively control when the written register information becomes valid in RF-oriented circuitry.

[0086] Figure 9 An example command format for a local register read operation 900 is shown. Command format 900 can be used, for example, to read register-based information from a selected device. Such a local register read operation can be used to obtain device-specific settings, such as bias settings, gain values, phase information, or other register-based control information. In some embodiments, local register read operation 900 can also be used to obtain values ​​associated with on-chip sensing or monitoring circuitry, such as temperature sensor information, power detector information, or other state-related information stored in register circuitry. In the illustrated format, the command may include a mode selection field, a submode field, a register address field, a chip address field, one or more reserved bits, and one or more output data portions provided on a serial data output path.

[0087] In the illustrated embodiment, the mode selection field MODE[2:0] occupies bits [23:21] and can identify the command as belonging to the local register access family. For example, the value 010 can identify the local register access family shown, and the submode field SMODE[1:0] can further identify local register read operations, such as by the value 01. In the illustrated example, bit

[20] is shown as an indifferent bit. Bits [17:15] are also shown as indifferent bits. Bits [14:8] shown as regADDR[6:0] can identify the target register address. Bits [7:1] shown as the chip address field can identify the selected device, such that the local register read operation 900 is processed by the addressed device, while other devices on the shared bus remain inactive. Bit [0] is shown as a reserved or indifferent bit.

[0088] The arrangement of fields in Command Format 900 facilitates hardware parsing by the digital controller. For example, higher-order bits can identify command families and submodes before the register address and chip address are fully received. Furthermore, the use of submode fields allows local register access families to distinguish different operations while reusing the same higher-level mode selection. In this way, the command space can be expanded without requiring separate three-bit mode values ​​for each different command.

[0089] The local register read operation 900 can support continuous read operations. For example, after the initial command identifies the command mode, submode, starting register address, and target device, the digital controller can continue the read operation without re-issuing the command header. In some embodiments, an 8-bit data word can be output for each selected read interval, such as every eight Serial Peripheral Interface (SPI) clock cycles. As the read operation continues, the target register address can be automatically incremented, allowing consecutive register positions to be read sequentially. The read sequence can continue until a transaction end condition occurs, such as when the chip select signal is driven high. This arrangement can reduce command overhead and improve efficiency when multiple consecutive register values ​​need to be retrieved.

[0090] Figure 9 The I / O pin table further illustrates example controller signal behavior associated with a local register read operation 900. For example, writeDA[7:0] can remain idle during a read operation, while regRD[7:0] can be active to provide register data from the selected device. The register clock signal, shown as regCLK, can be active during a read operation, allowing the addressed register circuitry to output the requested data. Thus, the I / O pin table illustrates how the digital controller can decode... Figure 9 The command field shown at the top is followed by an example of an internal local register read operation 900.

[0091] Therefore, the local register read operation 900 provides an example of a command format that can select the target device, identify the starting register address, and support sequential reading of register information from consecutively addressed register locations.

[0092] Figure 10 An example command format for a global register write operation 1000 is shown. Command format 1000 can be used, for example, to write register-based information across multiple devices coupled to a shared communication path. Such a global register write operation can be used to update configuration information for multiple devices without requiring separate device-specific write transactions. In the format shown, the command may include a mode selection field, a subarray enable field, a subarray select field, a register address field, one or more reserved bits, and one or more additional data portions.

[0093] In the illustrated embodiment, the mode selection field MODE[2:0] occupies bits [15:13] and can identify the command as a global register write operation 1000. For example, the value 011 can identify the illustrated global register write mode. Bit

[12] is shown as a reserved or uninterested bit. Bit

[11] shown as the subarray enable field SE can indicate whether the command is to be applied to all devices on the shared bus or only to the selected device subarray. When the subarray enable field indicates subarray selection, bits [10:8] shown as regSARR[2:0] can identify the selected subarray. Bit [7] is shown as a reserved or uninterested bit. Bits [6:0] shown as regADDR[6:0] can identify the destination register address. The additional data portion can then provide the write data for the addressed register location.

[0094] The global register write operation 1000 can be used after device-specific parameters have already been established via a local register write operation. For example, a local register write operation can be used to program the subarray address for each device. Subsequently, when the subarray enable field indicates a first state, such as SE=0, the global register write operation 1000 can be processed to apply to all devices coupled to the shared communication interface. When the subarray enable field indicates a second state, such as SE=1, the subarray selection field can be compared with the stored subarray address for each device, such that the write operation is applied only to devices with a matching subarray specification. In this way, command format 1000 can support both full-bus global writes and selective subgroup writes using the same overall command family.

[0095] The Global Register Write Operation 1000 also supports sequential write operations. For example, after the initial command identifies the command mode, subarray selection behavior, and starting register address, additional data words can be appended without re-issuing the command header. When subsequent appended data words are received, the destination register address can be automatically incremented, allowing sequential writing of consecutive register locations. This arrangement reduces command overhead and improves efficiency when writing common configuration values ​​across multiple devices and multiple register locations.

[0096] Global register write operation 1000 can further collaborate with the staged transfer architecture described above. For example, register data written using command format 1000 can first be captured in the first storage level and then transferred to the effective storage level in response to a load condition (such as an RFLOAD condition). In some implementations, the load condition can cause effective radio frequency (RF) channel registers across multiple devices to be updated immediately. This arrangement can support the coordinated application of updated register values ​​throughout a multi-device system.

[0097] Figure 10 The I / O pin table further illustrates example controller signal behavior associated with a global register write operation 1000. For example, regRD[7:0] can remain idle during the write operation, while the register clock signal regCLK can be active, and the register write enable signal regWE can be active, causing the register write data to be captured at the addressed register location. The I / O pin table also shows RFLOAD, which is active in the example shown, thus illustrating an implementation where newly written register information is transmitted for effective use during a global write operation. Therefore, the I / O pin table illustrates how the digital controller can decode... Figure 10 The command field shown above is followed by an example of an internal global register write operation 1000.

[0098] Therefore, the Global Register Write Operation 1000 provides an example of a command format that can identify the target register address, supports writes across all devices or across selected device subarrays, supports continuous writing of additional data values ​​across continuously incrementing register addresses, and coordinates the application of updated register information in a multi-device layout.

[0099] Figure 11An example command format for a global static random access memory (SRAM) write operation 1100 is shown. Command format 1100 can be used, for example, to write radio frequency (RF) status information across multiple devices coupled to a shared communication path. Such a global SRAM write operation can be useful when common beam status information needs to be loaded into the SRAM circuitry of multiple devices without requiring separate device-specific write transactions. In the shown format, the command may include a mode selection field, an SRAM number field, a channel selection field, a transmit / receive selection field, an SRAM address field, and one or more additional data portions.

[0100] In the illustrated embodiment, the mode selection field MODE[2:0] occupies bits[15:13] and can identify the command as belonging to a global SRAM write family. For example, a value of 100 can identify a first global SRAM write mode, and a value of 101 can identify a second global SRAM write mode. Bits

[12] shown as sramNO can identify which SRAM byte or SRAM portion to write. This can be useful in cases where a wide RF status word is stored across multiple SRAM portions, such as where a low byte is stored in one SRAM portion and a high byte is stored in another. Bits[11:8] shown as sramCH[3:0] can identify the selected RF channel. In embodiments that support both transmit and receive operations, bits[7] shown as TXRX can identify whether the write operation is associated with a transmit path or a receive path. In some embodiments that support only transmit operations or only receive operations, the TXRX field can be omitted. Bits[6:0] shown as sramADDR[6:0] can identify the starting SRAM address.

[0101] The global SRAM write operation 1100 can support different write behaviors depending on the selected mode value. When MODE[2:0]=100, each successive data word can be written to one RF channel at a time, starting from the initial SRAM address. When additional data words are appended, the write operation can continue through the consecutive RF channels associated with the current SRAM address. After all channels associated with the current SRAM address have been written, the operation can continue at the next SRAM address, again starting from the first RF channel. This arrangement can be useful when different channel-specific RF status values ​​need to be loaded sequentially across multiple devices.

[0102] When MODE[2:0]=101, each data word can be written to all RF channels at the current SRAM address simultaneously. When additional data words are appended, the operation can continue at subsequent SRAM addresses, allowing the same address-indexed state progression to be written across all channels. This arrangement can be useful when a common RF state mode needs to be loaded for all channels across multiple devices. Therefore, command format 1100 can support both a channel-by-channel global write mode and a simultaneous global write mode for all channels within the same general command family.

[0103] The global SRAM write operation 1100 also supports continuous write operations. For example, after the initial command identifies the selected mode, SRAM portion, channel information, transmit / receive settings, and starting SRAM address, additional data words can be appended without re-issuing the command header. As long as the appended data words continue to be received, the digital controller can continue loading data based on the write behavior associated with the selected mode. This arrangement reduces command overhead and improves efficiency when programming multiple SRAM locations across multiple devices.

[0104] Figure 11 The I / O pin table further illustrates example controller signal behavior associated with a global SRAM write operation 1100. For example, writeDA[7:0] can be active to carry SRAM write data, while sramRD[7:0] can remain idle during a write operation. Similarly, sramWE can be active to indicate write enable, while sramRE can remain inactive during a write operation. Signals such as sramCLK can provide a clock for SRAM access. Thus, the I / O pin table illustrates how the digital controller can provide a clock for SRAM access during decoding. Figure 11 The command field shown at the top is followed by an example of an internal global SRAM write operation 1100.

[0105] Therefore, the global SRAM write operation 1100 provides an example of a command format that can write RF status information across multiple devices, supports different global write behaviors depending on the selected mode, and supports continuous writing of additional data values ​​starting from the initial SRAM address.

[0106] Figure 12An example command format for a local fast beam manipulation operation 1200 is shown. Command format 1200 can be used, for example, to transmit radio frequency (RF) status information associated with a selected static random access memory (SRAM) address for a selected device. In some embodiments, local fast beam manipulation operation 1200 can be used to rapidly load stored gain information, phase information, or both from SRAM circuitry onto the RF channel circuitry of a device on a communication bus. In the illustrated format, the command may include a mode selection field, an RF load (RFLOAD) field, a sub-mode field, a transmit / receive selection field, an SRAM address field, a chip address field, one or more reserved bits, and one or more indifferent bits.

[0107] In the illustrated embodiment, the mode selection field MODE[2:0] occupies bits [23:21] and can identify the command as Local Fast Beam Control Operation 1200. For example, the value 110 can identify the illustrated Local Fast Beam Control mode. Bit

[20] shown as the RFLOAD field can indicate whether the data associated with the selected SRAM address is to be kept buffered or latched for effective use. Bits [19:18] shown as SMODE[1:0] can define the submode field. In the illustrated example, bits [17:16] are shown as indifferent bits. In embodiments that support both transmit and receive operations, bit

[15] shown as TXRX can identify whether the operation is associated with the transmit path or the receive path. In some embodiments that support only transmit operations or only receive operations, the TXRX field can be ignored. Bits [14:8] shown as sramADDR[6:0] can identify the selected SRAM address. Bits [7:1] shown as chip address fields can identify the selected device so that the local fast beam manipulation operation 1200 is handled by the addressed device while other devices on the shared bus remain unaffected. Bit [0] is shown as reserved or ignored.

[0108] The Local Fast Beam Control Operation 1200 can support a buffered update mechanism. For example, when a command is issued, it is not necessary to immediately update the RF channel of the selected device with the gain information, phase information, or both associated with the selected SRAM address. Instead, the data associated with the selected SRAM address can first be loaded into a buffer register within the device. This arrangement allows for advance preparation of beam state updates while reducing unexpected intermediate changes at the effective RF output.

[0109] The RFLOAD field can then determine when the buffered data becomes valid. When the RFLOAD field indicates that the buffered data has not yet been applied, the data can remain in the first-level or buffer storage device, while the valid RF-facing registers remain unchanged. When the RFLOAD field indicates a valid load condition, the buffered data can be transferred to the valid RF channel register for application at the RF channel. In some implementations, RFLOAD-triggered updates can be applied to all devices in local fast beam control mode, regardless of chip address matching of the load event itself. This arrangement can support coordinated beam state activation while still allowing preloading of selected devices via local fast beam control command format 1200.

[0110] The Local Fast Beam Control Operation 1200 can also support address tracking. For example, the SRAM address used in the Local Fast Beam Control Operation 1200 can be stored in a dedicated register of the device. Therefore, the currently buffered SRAM address can be identified by reading back from this dedicated register. This is useful for determining which stored beam state entry is currently buffered for application to the RF channel.

[0111] Figure 12 The I / O pin table also illustrates example controller signal behavior associated with the local fast beam manipulation operation 1200. For example, writeDA[7:0] can remain idle, and sramRD[7:0] can also remain idle because the operation targets reading data from the SRAM circuitry to the RF-facing circuitry, rather than outputting SRAM data via a serial data output path. Similarly, sramWE can remain invalid, while sramRE can be enabled, allowing the selected SRAM entry to be accessed. Signals such as sramCLK can provide a clock for SRAM access. Thus, the I / O pins illustrate how the digital controller can decode... Figure 12 The command field shown at the top is followed by an example of a local fast beam manipulation operation 1200 implemented internally.

[0112] Therefore, the Local Fast Beam Control Operation 1200 provides an example of a command format that can select a target device, identify an SRAM address containing RF status information, support buffer loading of the RF status information, and selectively control when to transmit the buffered RF status information to the valid RF channel circuitry.

[0113] Figure 13A and Figure 13BAn example command format for a global fast beam manipulation operation 1300 and its associated I / O pin table 1305 are shown together. Command format 1300 can be used, for example, to update radio frequency (RF) status information across multiple devices coupled to a shared communication path. In some implementations, global fast beam manipulation operation 1300 can be used to cause all RF channels of all devices or all RF channels of a selected device subarray to transition to a new beam state based on gain information, phase information, or both stored in static random access memory (SRAM) circuitry. Figure 13A As shown, the global fast beam control operation 1300 can support different control behaviors based on the mode switching settings identified as MS, and also supports different device selection behaviors based on the subarray enable settings identified as SE.

[0114] In the illustrated embodiment, bits [15:13] shown as MODE[2:0] can identify the command as Global Fast Beam Control Operation 1300. For example, the value 111 can identify the illustrated Global Fast Beam Control mode. Bit

[12] shown as Mode Switch (MS) bit can control whether the subsequent SRAM or Lookup Table (LUT) address is explicitly provided or auto-incremented. Bit

[11] shown as Subarray Enable (SE) bit can control whether the command is applied globally to all devices on the shared bus or selectively to a specified device subarray. Bits [10:8] shown as regSARR[2:0] can identify the subarray index. In embodiments that support both transmit and receive operations, bit [7] shown as TXRX can identify whether the operation is associated with a transmit path or a receive path. Bits [6:0] shown as sramADDR[6:0] can identify the starting SRAM address.

[0115] The SE bit can support both true global operations and subarray operations. When the SE bit indicates a first state, such as SE=0, the global fast beamforming operation 1300 can be applied to all devices coupled to the shared bus. When the SE bit indicates a second state, such as SE=1, the global fast beamforming operation 1300 can be applied only to devices whose stored subarray addresses match the subarray index carried in the command. In some embodiments, the subarray addresses can be stored in the same register resource used for global register write operations. This arrangement allows a single command format to support both full array control and subarray control, thereby increasing flexibility in systems comprising multiple devices sharing a common command path.

[0116] The MS bit can support different manipulation and update behaviors. For example... Figure 13AAs shown in the upper example, when the MS bit indicates a first state, such as MS=0, the global fast beam manipulation operation 1300 can operate in a manually provided address mode. In this mode, the initial command can identify a first SRAM address, and then subsequent address values ​​can be appended for subsequent RF state updates. Thus, the master device can explicitly specify each new LUT or SRAM address associated with each subsequent beam state transition. This arrangement can be useful where the update sequence is not strictly sequential or where an explicit state selection is expected for each manipulation step. Note that in the illustrated embodiment, bits [7] of each subsequent address are shown as unapplicable (NA) because the TXRX selection for the global fast beam manipulation operation 1300 can be determined by the initial command.

[0117] like Figure 13A As further illustrated in the lower example, when the MS bit indicates a second state, such as MS=1, the global fast beamforming operation 1300 can operate in auto-increment mode. In this mode, the initial command can identify the starting SRAM address, and subsequent state transitions can be performed via auto-incrementing addresses. In some embodiments, after the initial command, all RF channels can be updated to the next LUT state at defined intervals, such as every two clock cycles. This arrangement can reduce command overhead during fast beamforming because the master device does not need to explicitly append a new address value for each successive state transition.

[0118] Figure 13A The latching behavior associated with the global fast beam control operation 1300 is also illustrated. In both MS=0 and MS=1 modes, the valid LUT state can be latched onto the RF channel on a selected clock edge (such as a rising clock edge). For consecutive LUT address sequences, no additional action is required other than continuing the command sequence. In some embodiments, when using MS=1 mode and the user wishes to maintain the selected LUT state, the user can provide an additional clock cycle after the update interval, or the transaction can be terminated, such as by setting the driver chip selection signal high. This latching behavior provides a practical way to continue fast beam state transitions or maintain the selected state at desired points in the sequence.

[0119] Figure 13BThe I / O pin table 1305 also illustrates example controller signal behavior associated with the global fast beam manipulation operation 1300. For example, writeDA[7:0] can remain idle, and sramRD[7:0] can also remain idle because the operation is aimed at applying stored SRAM information to RF-facing circuitry, rather than outputting the SRAM contents via a serial data output path. Similarly, sramWE can remain invalid, while sramRE can be enabled, allowing the selected SRAM entry to be accessed. Signals such as sramCLK can provide a clock for SRAM access. Figure 13B Additional pads or signal entries corresponding to RFLOAD are also shown. In the example shown, when a latching event occurs, the RFLOAD signal can be enabled, allowing information derived from the buffered SRAM to be transmitted for effective use by the RF circuitry.

[0120] Therefore, the global fast beam manipulation operation 1300 can support coordinated beam state updates across all devices or across selected device subarrays, while also allowing for explicitly provided address progression or auto-incrementing address progression. This arrangement can support fast manipulation updates with reduced command overhead and also provides flexibility in how subsequent beam states are selected and latched for effective RF operation. Figure 13A and Figure 13B An example of the command format and associated controller behavior for performing global fast beam manipulation in a multi-device RF system is shown.

[0121] Now that I understand Figures 5-13B The example command formats are given below; the following discussion will focus on example timing relationships that may arise when these command formats are processed by the disclosed SoC architecture. Now regarding... Figure 14 The accompanying figures further illustrate example timing behaviors associated with SRAM access, register access, and the transfer of RF status information to the RF circuitry under various command modes.

[0122] Figure 14 An example timing diagram 1400 for writing data to static random access memory (SRAM) is shown. Timing diagram 1400 can correspond to, for example, a local SRAM write operation (such as those described above). Figure 6 The command format described), global SRAM write operations (such as those mentioned above) Figure 11 The command format described, or another SRAM write command that includes an initial command followed by additional data values. In the example shown, timing diagram 1400 illustrates the DATA_BUS signal, clock signal, command and data sequence, SRAM clock pulse signal, and SRAM data signal.

[0123] like Figure 14 As shown, the command and data sequence can begin with a command portion, shown as a 24-bit command, followed by an additional data portion, shown as 8-bit DATA[0], 8-bit DATA[1], 8-bit DATA[2], and 8-bit DATA[3]. The 24-bit command portion can identify, for example, the selected command mode, SRAM number, channel, transmit / receive specification, SRAM address, and chip address. After receiving the command portion, the additional data portion can be provided without re-issuing the command header. This arrangement can support continuous write operations and reduce command overhead when multiple data values ​​need to be written to the SRAM circuitry.

[0124] The DATA_BUS and CLOCK signals can operate together, causing the command bit and additional data bits to be presented serially over time. In implementations such as those based on a Serial Peripheral Interface (SPI), the command bit and data bit can be latched based on a selected clock edge, such as the rising clock edge. The example shown labels both the data bus and the clock at 100 MHz, thus illustrating an example operating rate. However, other operating rates can also be used.

[0125] Timing diagram 1400 also illustrates that, after receiving the command section, an internal SRAM write process can be performed using an SRAM clock pulse generated by the controller circuitry. In the example shown, the first SRAM write pulse occurs after the command section and after an additional delay, which is shown, for example, as one internal clock cycle. Thereafter, the corresponding SRAM data values ​​can be loaded sequentially. For example, DATA[0], DATA[1], DATA[2], and DATA[3] can be written into the SRAM memory in response to the corresponding SRAM clock pulse. Thus, timing diagram 1400 illustrates an example in which serially received additional data values ​​are converted into internal SRAM write activities.

[0126] The relationship between the command section and the internal SRAM write timing, as illustrated, also reflects the possibility that command decoding can be completed before the write data is submitted to the SRAM circuitry. For example, upon receiving a 24-bit command, the digital controller can determine the selected write mode, identify the target memory location, and prepare the internal SRAM control signals before writing the first additional data value. This phased interpretation and write timing improves implementation robustness because the controller can establish an appropriate write path before submitting the additional write data.

[0127] Timing diagram 1400 can also represent continuous SRAM programming behavior. Once a command header is received, additional data values ​​can continue to arrive on the DATA_BUS signal, and corresponding SRAM write events can continue to be generated without retransmitting the command header. Therefore, multiple SRAM locations can be efficiently programmed using a single command header followed by a sequence of additional data values. This can be useful, for example, when writing beam status information across multiple channels, multiple SRAM addresses, or both.

[0128] therefore, Figure 14 An example of how to time the command section and the additional data section to write data to the SRAM circuit is shown, and how to convert serially received write data into internal SRAM write pulses and corresponding SRAM data updates is also shown.

[0129] Figure 15 An example timing diagram 1500 for reading data from static random access memory (SRAM) is shown. Timing diagram 1500 may correspond to, for example, a local SRAM read operation, such as those described above. Figure 7 The command format is described. In the example shown, timing diagram 1500 illustrates the DATA_BUS signal, clock signal, command and data sequences, SRAM clock pulse signal, and SRAM data signal.

[0130] like Figure 15 As shown, the command and data sequence can begin with a command section, shown as a 24-bit command, followed by output data sections, shown as 8-bit DATA[0], 8-bit DATA[1], 8-bit DATA[2], and 8-bit DATA[3]. The 24-bit command section can identify, for example, the selected command mode, SRAM number, channel, transmit / receive specification, SRAM address, and chip address. After receiving the command section, the controller can begin returning SRAM data corresponding to the addressed memory location and can continue returning additional data values ​​without re-issuing the command header. This arrangement can support continuous read operations and reduce command overhead when multiple SRAM values ​​need to be retrieved.

[0131] The DATA_BUS and CLOCK signals can operate together to receive command bits serially over time and subsequently provide output data bits serially. In implementations such as those based on a Serial Peripheral Interface (SPI), the command bits and output data bits can be latched based on a selected clock edge, such as the rising clock edge. The example shown labels both the data bus and the clock at 100 MHz, thus illustrating an example operating rate. However, other operating rates can also be used.

[0132] Timing diagram 1500 also shows a processing interval that can occur after receiving the 24-bit command portion and before the output data is available. In the example shown, this interval is shown as a processing time of two clock cycles. During this interval, the digital controller can decode the command, identify the selected SRAM location, initiate the SRAM read operation, and prepare the corresponding output path. Subsequently, an internal SRAM clock pulse can be generated so that the SRAM data is read and placed on the SRAM data signal. The SRAM data signal shown then displays the successive values ​​DATA[0], DATA[1], DATA[2], and DATA[3] corresponding to the sequentially acquired data values.

[0133] Timing diagram 1500 also shows that readout can continue after the initial read wait time. Once the command header has been received and the first data value is available, subsequent SRAM data values ​​can be returned sequentially. This arrangement is consistent with continuous local SRAM read behavior, where the controller can sequentially retrieve stored beam status data without re-issuing commands. For example, this timing can be useful when the master device reads back stored phase information, gain information, or other RF status information for verification, calibration, diagnostics, or related control purposes.

[0134] Furthermore, the separation between the command interval and the subsequent data return interval indicates that the controller can complete command interpretation before the SRAM data is returned by the driver. This timing relationship improves implementation robustness because the selected read path can be established before the output data is presented. Therefore, Figure 15 This illustrates an example of how, during an SRAM read operation, a command portion can be followed by a processing interval and then by sequential SRAM data output.

[0135] Figure 16 An example timing diagram 1600 for writing data to a register is shown. Timing diagram 1600 can correspond to, for example, a local register write operation (such as those mentioned above). Figure 8 The command format described), global register write operations (such as those mentioned above) Figure 10 The command format described, or a register write command that includes an initial command followed by additional data values. In the example shown, timing diagram 1600 illustrates the DATA_BUS signal, clock signal, command and data sequence, register clock pulse signal, and register data signal.

[0136] like Figure 16As shown, the command and data sequence can begin with a command portion, shown as a 24-bit command, followed by an additional data portion, shown as 8-bit DATA[0], 8-bit DATA[1], 8-bit DATA[2], and 8-bit DATA[3]. The command portion can identify, for example, the selected command mode, RF load settings, sub-mode, register address, and chip address. After receiving the command portion, the additional data portion can be provided without re-issuing the command header. This arrangement can support continuous write operations and reduce command overhead when writing multiple register values.

[0137] The DATA_BUS and CLOCK signals can operate together, causing the command bit and additional data bits to be presented serially over time. In Serial Peripheral Interface (SPI) based implementations, the command bit and data bit can be latched based on a selected clock edge (such as the rising clock edge). The example shown labels both the data bus and the clock at 100 MHz, thus illustrating an example operating rate. Other operating rates can also be used.

[0138] Timing diagram 1600 also illustrates that, after receiving the command section, an internal register write process can be performed using register clock pulses generated by the controller circuitry. In the example shown, the first register write pulse occurs after the command section and after an additional delay, which is shown, for example, as one internal clock cycle. Subsequently, the corresponding register data values ​​can be loaded sequentially. For example, DATA[0], DATA[1], DATA[2], and DATA[3] can be written into register memory in response to the corresponding register clock pulses. Thus, timing diagram 1600 illustrates an example in which serially received additional data values ​​are converted into internal register write activities.

[0139] The illustrated relationship between the command section and the internal register write timing also reflects that command decoding can be completed before the write data is committed to the register circuitry. For example, after receiving the command section, the digital controller can determine the selected write mode, identify the target register location, and prepare the internal register control signals before writing the first additional data value. This phased interpretation and write timing improves implementation robustness because the controller can establish an appropriate write path before committing the additional write data.

[0140] Timing diagram 1600 can also represent sequential register programming behavior. Once a command header is received, additional data values ​​can continue to arrive on the DATA_BUS signal, and corresponding register write events can continue to be generated without retransmitting the command header. In implementations with auto-incrementing target register addresses, successive additional data values ​​can be written to consecutively addressed register locations. This arrangement can be useful, for example, when multiple control registers, bias registers, or other register-based settings need to be programmed sequentially.

[0141] therefore, Figure 16 An example is shown of how the command section and the additional data section can be timed to write data to the register circuit, and it is also shown how serially received write data can be converted into internal register clock pulses and corresponding register data updates.

[0142] Figure 17 An example timing diagram 1700 for reading data from a register is shown. Timing diagram 1700 may correspond to, for example, a local register read operation, such as those described above. Figure 9 The command format described. In the example shown, timing diagram 1700 illustrates the DATA_BUS signal, clock signal, command and data sequence, register clock pulse signal, register data signal, and DATA_out signal.

[0143] like Figure 17 As shown, the command and data sequence can begin with a command section, illustrated as a 24-bit command. The command section can identify, for example, the selected command mode, the selected sub-mode, the starting register address, and the chip address. Upon receiving the command section, the digital controller can begin the register read procedure and return the register data via the DATA_out path. This arrangement can support local register read operations without requiring a separate command header for each returned register value.

[0144] The DATA_BUS and CLOCK signals can operate together to serially receive command bits over time. In Serial Peripheral Interface (SPI) based implementations, command bits can be latched based on a selected clock edge (such as the rising clock edge). The example shown labels both the data bus and clock at 100 MHz to illustrate an example operating rate. Other operating rates can also be used.

[0145] Timing diagram 1700 also shows that after receiving the command section, internal register read activities can be performed using register clock pulses generated by the controller circuitry. In the example shown, the register data signals represent the values ​​obtained from successive register addressings, shown as 8-bit Addr[0], 8-bit Addr[1], 8-bit Addr[2], and 8-bit Addr[3]. This indicates that after the initial command identifies the starting register address, the read operation can be performed through consecutively addressed register locations. Then, the DATA_out signal represents the corresponding return data values, shown as 8-bit DATA[0], 8-bit DATA[1], and 8-bit DATA[2], which can be provided serially from the selected device.

[0146] The spacing between the command interval, the internal register read interval, and the subsequent DATA_out interval indicates that a processing interval may exist before data is read back to the external drive. During this interval, the digital controller can decode the command, identify the selected register path, access the addressed register location, and prepare the output path for returning the requested data. This timing relationship improves implementation robustness because the addressed register data path can be established before the read-back data is placed on the DATA_out signal.

[0147] Timing diagram 1700 also reflects continuous register read behavior. Once the initial command is received, the read sequence can continue from one register location to the next without re-issuing the command header. In some implementations, an 8-bit data word can be output for each selected read interval (such as every eight SPI clock cycles), and the read sequence can continue until a transaction termination condition occurs, such as when the chip select signal is driven high. This arrangement can reduce command overhead and improve efficiency when multiple successive register values ​​need to be obtained for verification, calibration, sensing, diagnostics, or other control purposes.

[0148] therefore, Figure 17 This illustrates an example of how an internal register access activity can be performed after a register read command during a local register read operation, followed by sequential data return on the DATA_out path.

[0149] Figure 18 An example timing diagram 1800 is shown for submitting data from static random access memory (SRAM) to radio frequency (RF) circuitry in a local fast beam manipulation operation. Timing diagram 1800 may correspond to, for example, a local fast beam manipulation operation, as described above. Figure 12The command format is described. In the example shown, timing diagram 1800 illustrates the DATA_BUS signal, clock signal, command and address sequences, SRAM clock pulse signal, and SRAM data signal.

[0150] like Figure 18 As shown, the command and address sequence can begin with a command portion, illustrated as a 24-bit command. This 24-bit command can identify, for example, the selected command mode, RF load settings, transmit / receive specifications, SRAM address, and chip address. Compared to read operations that return SRAM data on the serial output path, local fast beamforming operations can use this command to identify the SRAM entry whose contents will be applied to the RF-oriented circuitry. Therefore, timing diagram 1800 shows this command used to select stored RF status information, rather than returning that information as ordinary read-back data.

[0151] After receiving the command portion, an internal SRAM access can occur. In the example shown, timing diagram 1800 illustrates the SRAM access interval after the command interval and an additional internal delay, for example, shown as one clock cycle and one SRAM access time. During this interval, the digital controller can decode the command, identify the selected SRAM address, and allow the corresponding SRAM entry to be accessed. The SRAM data signal then displays a wide data value, shown as Data[511:0], indicating that a set of stored RF status information associated with multiple RF channels can be read from the SRAM circuitry for beam manipulation operations.

[0152] Timing diagram 1800 also shows that the SRAM clock pulse signal can be activated after the command is decoded, allowing the selected SRAM entry to be accessed. In some embodiments, the accessed SRAM data can be loaded into a buffer register or another first memory level first, rather than being immediately applied to the active RF channel circuitry. This staged loading allows the selected beam state information to be prepared for later activation while reducing unintended intermediate state changes at the RF output.

[0153] In some implementations, subsequent effective RF loading conditions can allow information derived from the buffered SRAM to be transferred to effective RF-oriented storage. Therefore, local fast beam manipulation operations can separate the selection of SRAM entries from the activation of the selected RF state. This arrangement can be useful when beam state changes need to be prepared in advance and then applied at a selected time. Therefore, Figure 18 The timing relationships shown reflect how local fast beam manipulation commands can enable SRAM-residing RF status information to be internally accessed and loaded for subsequent transmission to the RF circuitry.

[0154] Timing diagram 1800 can also be interpreted as illustrating that selected SRAM entries can contain a set of RF state values ​​for multiple RF channels. In this way, local fast beamforming operations can internally access a wider stored dataset and prepare that data for coordinated applications across RF channels, instead of serially returning one byte at a time on the readback path. This improves update efficiency when multiple RF channels need to transition to a new stored beamstate.

[0155] therefore, Figure 18 An example of how a local fast beam manipulation command can be timed is shown, enabling access to the selected SRAM entry after command decoding and preparation of the corresponding SRAM data for transfer from the SRAM circuitry to the RF-oriented circuitry.

[0156] Figure 19 An example timing diagram 1900 is shown for submitting data from static random access memory (SRAM) to radio frequency (RF) circuitry during global fast beam manipulation operations. Timing diagram 1900 can correspond to, for example, the above-mentioned... Figure 13A and Figure 13B The global fast beam control command format is described. In the example shown, timing diagram 1900 illustrates the DATA_in bus signals, clock signals, command and address sequences, SRAM clock pulse signals, and SRAM data signals.

[0157] like Figure 19 As shown, the command and address sequence can begin with a command portion, illustrated as a 16-bit command. The 16-bit command can identify, for example, the selected command mode, mode switching settings, subarray enable settings, subarray index, transmit / receive designation, and SRAM address. Compared to register read operations or SRAM read-back operations, global fast beamforming operations can use this command to identify the RF state information residing in the SRAM for application to RF-oriented circuitry across multiple devices. Therefore, timing diagram 1900 reflects a command-driven state selection operation, rather than a typical serial read-back of SRAM contents.

[0158] After receiving the command portion, an internal SRAM access can occur. In the example shown, timing diagram 1900 illustrates the internal delay after the command interval, e.g., one clock cycle, followed by the SRAM access interval, e.g., shown as one SRAM access time. During this interval, the digital controller can decode the command, determine whether the command is globally applicable or applicable to a selected subarray, identify the selected SRAM address, and initiate access to the corresponding SRAM entry. The SRAM data signal then displays a wide data value, shown as Data[511:0], indicating that a set of stored RF status information associated with multiple RF channels can be obtained from the SRAM circuitry for coordinated RF updates.

[0159] Timing diagram 1900 also illustrates that the SRAM clock pulse signal can be activated after the command is decoded, allowing the selected SRAM entry to be accessed. In some embodiments, depending on the state of the subarray enable setting, the accessed SRAM data can be used to update all RF channels of all devices on the shared bus, or all RF channels of the selected device subarray. This arrangement can support simultaneous or substantially simultaneous beamstate updates across a multi-device system, which can improve coordination when multiple devices participate in common beamforming or phased array operation.

[0160] Figure 19 The timing behavior shown can also be used with different control update modes. For example, when the mode switching setting indicates manual address provision mode, the command can identify the initial SRAM address and provide subsequent address values ​​for subsequent RF state transitions. When the mode switching setting indicates auto-increment mode, the command can identify the starting SRAM address, and subsequent state transitions can be performed using the incremented SRAM address. In either case, timing diagram 1900 shows internal access to the selected SRAM entry, and the obtained SRAM data is used for RF state transfers rather than for serial output readback.

[0161] In some embodiments, a latch event or load event can then make the RF status information derived from the SRAM valid at the RF-oriented circuitry. For example, as mentioned above regarding... Figure 13A and 13B As described, the RFLOAD event can occur in coordination with Global Fast Beam Control (GFB), causing information derived from the buffered SRAM to be latched into the active RF channel circuitry. Therefore, GFB operation can separate command reception and SRAM access from the final activation of the selected RF state, providing controlled timing for coordinated multi-device beam state transitions.

[0162] therefore, Figure 19 An example is shown of how global fast beam manipulation commands can be timed so that selected SRAM entries are accessed after the command is decoded, and the corresponding SRAM data is prepared for transfer from the SRAM circuitry to RF-oriented circuitry across multiple devices.

[0163] Overall, Figures 14-19Example timing relationships associated with command-driven SRAM circuit access, command-driven register circuit access, and command-driven transfer of RF status information from memory circuitry to RF-oriented circuitry are illustrated. As these examples show, different command families can involve different command lengths, different internal processing intervals, and different relationships between incoming serial command information and corresponding internal clocks, data movements, and activation events. The timing diagrams also demonstrate that the disclosed command architecture can support continuous access operations, staged transfer operations, and coordinated RF status updates under different command modes.

[0164] For illustrative and descriptive purposes, the foregoing description of various embodiments of the claimed subject matter has been provided. It is not intended to be exhaustive or to limit the claimed subject matter to the precise forms disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to best illustrate the principles of the invention and its practical application, thereby enabling those skilled in the art to understand the claimed subject matter, the various embodiments, and the various modifications suitable for the particular intended use.

[0165] While the detailed description depicts certain embodiments and contemplated best modes, the technology can be practiced in many ways, however detailed the detailed description may appear. Embodiments can vary significantly in their implementation details while still being covered by the specification. Specific terms used in describing certain features or aspects of the various embodiments should not be construed as implying that the term is redefined herein as limited to any particular characteristic, feature, or aspect of the technology associated with that term. Generally, the terms used in the following claims should not be construed as limiting the technology to the specific embodiments disclosed in the specification, unless such terms are expressly defined herein. Therefore, the actual scope of this technology includes not only the disclosed embodiments but also all equivalent ways of practicing or implementing the embodiments.

[0166] The language used in this specification has been chosen primarily for readability and guidance purposes. It may not have been chosen to define or limit the subject matter. Therefore, it is intended that the scope of this technology is not limited to the specific implementations, but rather to any claims published in the application based thereon. Thus, the disclosure of various embodiments is intended to illustrate, and not limit, the scope of the technology as set forth in the appended claims. Furthermore, it should be noted that the various circuits disclosed herein can be described using computer-aided design tools and expressed (or represented) as data and / or instructions embodied in various computer-readable media in terms of their behavior, register transfers, logic components, transistors, layout geometry, and / or other characteristics. Formats of documents and other objects in which such circuit expressions can be implemented include, but are not limited to, formats supporting behavioral languages ​​such as C, Verilog, and VHDL; formats supporting register-level description languages ​​such as RTL; formats supporting geometric description languages ​​such as GDSII, GDSIII, GDSIV, CIF, MEBES; and any other suitable formats or languages. Computer-readable media in which such formatted data and / or instructions can be embodied include, but are not limited to, various forms of non-volatile storage media (e.g., optical, magnetic, or semiconductor storage media).

Claims

1. A computing device, comprising: The communication interface is coupled to the data input bus to receive command data streams and to the data output bus to output data. The memory circuit is configured to store radio frequency (RF) status information. RF circuits; as well as A control circuit, coupled to the communication interface, the memory circuit, and the RF circuit, wherein the control circuit is configured to: Receive commands from the data input bus; Determine whether the command belongs to the local command group, the global command group, or the fast beam control command group; The command is processed when it belongs to the local command group and the address field of the command matches an identifier associated with the computing device. When the command belongs to the global command group, the command is processed without requiring the address field to match the identifier associated with the computing device; and When the command belongs to the fast beam control command group, RF status information is transmitted to the RF circuit.

2. The computing device according to claim 1, wherein, The control circuit is configured to determine which group the command belongs to based on the initial multiple most significant bits (MSB) of the command.

3. The computing device according to claim 2, wherein, The control circuit is configured to perform the determination upon receiving the initial plurality of most significant bits and before receiving all remaining bits of the command.

4. The computing device according to claim 1, in, The local command group facilitates memory access for a specified device coupled to the communication interface, and The local command group includes local SRAM access type and local register access type.

5. The computing device according to claim 4, in, The local SRAM access types include local SRAM write commands and local SRAM read commands, and The control circuitry is configured to support continuous local SRAM access without re-issuing commands, while additional data associated with the commands continues to be received from or output through the communication interface.

6. The computing device according to claim 5, in, The command identifies the starting SRAM address, and During continuous local SRAM write operations, the control circuit is configured to write successive data words into consecutive RF channels starting from the starting SRAM address, and to continue writing from the first RF channel at the next SRAM address after all RF channels at the starting SRAM address have been written.

7. The computing device according to claim 5, in, The command identifies the starting SRAM address, and During continuous local SRAM read operations, the control circuit is configured to sequentially acquire beam status data across multiple RF channels, starting from the initial SRAM address, without re-issuing commands.

8. The computing device according to claim 4, in, The local register access types include local register write commands and local register read commands, and The control circuitry is configured to support continuous access to local registers without re-issuing commands, while additional data associated with the commands continues to be received from or output through the communication interface.

9. The computing device according to claim 8, in, The command identifies the starting register address, and During continuous local register write operations, the control circuit is configured to write successive data words to continuously incrementing register addresses, starting from the starting register address.

10. The computing device according to claim 8, in, The command identifies the starting register address, and During continuous local register read operations, the control circuit is configured to output a data word every defined number of bus clock cycles and continue sequential register reads from the starting register address until the chip select signal is set to invalid.

11. The computing device according to claim 1, in, The global command group facilitates memory access for all devices coupled to the communication interface, and The global command group includes global register write type and global SRAM write type.

12. The computing device according to claim 11, in, The control circuit is configured to execute commands in the global command group as commands applicable to all devices coupled to the communication interface, regardless of whether the device address matches, when subarray selection is disabled.

13. The computing device according to claim 11, in, The control circuit is configured to, for a command in the global command group, when subarray selection is enabled, compare the subarray selection information carried by the command with the subarray address stored in the computing device to determine whether the command is applicable to the computing device.

14. The computing device according to claim 13, in, The control circuitry is configured to consider a command valid only after a local register write command that previously programmed the subarray address of the computing device has been executed.

15. The computing device according to claim 11, wherein, The global register write type supports continuous writing by writing successive additional data words received through the communication interface to a continuously incrementing register address, starting from the starting address identified in the initial command.

16. The computing device according to claim 11, in, The command identifies the starting SRAM address, and The global SRAM write types include: In the first mode, starting from the initial SRAM address, each successive data word is sequentially written to the corresponding RF channel; and The second mode, in which each successive data word is written simultaneously to all RF channels, starting from the initial SRAM address.

17. The computing device according to claim 16, wherein, The global SRAM write type supports continuous write operations by automatically advancing the target SRAM address as long as additional data words continue to be appended to the command.

18. The computing device according to claim 1, in, The fast beam manipulation command group facilitates control of the RF circuitry, and The fast beam control command group includes local fast beam control type and global fast beam control type.

19. The computing device according to claim 18, in, The command includes a specified SRAM address, and The local fast beam manipulation type causes gain and / or phase data from a specified SRAM address to be loaded into a buffer register before being loaded into the valid RF channel register.

20. The computing device according to claim 19, wherein, The control circuit is configured to transfer buffered data to the valid RF channel register only in response to a valid RF load condition.

21. The computing device according to claim 19, wherein, The control circuit is configured to store SRAM address information for the local fast beam manipulation type in a dedicated register, enabling the identification of the currently buffered SRAM address.

22. The computing device according to claim 18, wherein, The global fast beam manipulation type supports: A first selection mode, wherein the command applies to all devices coupled to the communication interface; and The second selection mode, wherein the command is only applicable to devices whose stored subarray addresses match the subarray selection information associated with the command.

23. The computing device according to claim 18, in, The command identifies the starting SRAM address, and The control circuit is configured to automatically advance from the starting SRAM address to subsequent SRAM addresses in order to update the RF status information used for the RF circuit.

24. The computing device according to claim 23, wherein, The RF status information used in the RF circuit is automatically updated at defined clock intervals.

25. The computing device according to claim 18, in, The command identifies the starting SRAM address, and The control circuit is configured to update the RF status information for the RF circuit based on successive SRAM addresses manually provided after the command.

26. The computing device according to claim 1, wherein, The control circuit is configured as follows: The RF status information received through the communication interface is written into the first-level register structure; and In response to the RF loading condition, the RF status information is transferred from the first-level register structure to the second-level register structure that drives the RF circuit.

27. The computing device according to claim 26, wherein, The RF loading condition is applied by activating the dedicated RF loading pin or by activating the RF loading position carried in the command.

28. The computing device according to claim 26, wherein, The RF loading condition enables the control circuit to transfer the RF status information from the first-level register structure to the second-level register structure for all devices coupled to the communication interface.

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