Protection of data keys used in cryptographic processing

Abstract

A set of data keys arranged in a particular order is obtained. The set of data keys includes a plurality of data keys. The plurality of data keys includes a protected key. The protected key is prevented from being in a selected position within the particular order. The set of data keys is encrypted into a single encryption key. The single encryption key is an encryption of the plurality of data keys. The single encryption key is returned. The single encryption key is to be decrypted to obtain a plurality of decrypted keys. At least one decrypted key of the plurality of decrypted keys is a decrypted protected key to be used for encryption of a confidential value.

Description

Technical Field

[0001] One or more aspects generally relate to cryptographic processing within a computing environment, and more particularly to the protection of data keys used in cryptographic processing. Background Technology

[0002] Cryptography is used to protect data. Various cryptographic algorithms exist, including XTS-AES (XEX (XOR-Encryption-XOR) Tweakable Block Cipher with Ciphertext Stealing - Advanced Encryption Standard) and others. The XTS-AES standard uses a confidential value (e.g., a tweaked value) to provide additional protection. This confidential value is encrypted using a data key called the protected key.

[0003] The processing related to the use of protected data keys needs to be enhanced. Summary of the Invention

[0004] By providing a computer program product, the shortcomings of the prior art are overcome and additional advantages are provided. The computer program product includes a collection of one or more computer-readable storage media and program instructions, which are collectively stored in the collection of one or more computer-readable storage media, for causing at least one computing device to perform computer operations. The computer operations include obtaining a set of data keys arranged in a specific order. The data key set includes multiple data keys. The multiple data keys include a protected key. The protected key is prevented from being placed in a selected position within the specific order. The data key set is encrypted into a single encryption key. The single encryption key is used to encrypt the multiple data keys. The single encryption key is returned. The single encryption key is decrypted to obtain multiple decrypted keys. At least one of the multiple decrypted keys is a decrypted protected key to be used to encrypt a confidential value.

[0005] This document describes and claims protection for computer-implemented methods, computer systems, and computer program products related to one or more aspects. Each embodiment of the computer program product may be an embodiment of each computer system and / or each computer-implemented method, and vice versa. Furthermore, the embodiments are separable from and optional of each other. Furthermore, the embodiments may be combined with each other. Each embodiment of the computer program product may be combined with aspects and / or embodiments of each computer system and / or computer-implemented method, and vice versa. Additionally, services related to one or more aspects are described herein, and protection may be claimed therein.

[0006] Additional features and advantages are achieved through the techniques described herein. Other embodiments and aspects are described in detail herein and are considered part of the claimed aspects. Attached Figure Description

[0007] One or more aspects are specifically pointed out and explicitly claimed by way of example in the claims at the end of the specification. The foregoing of one or more aspects, as well as the object, features, and advantages, will become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 An example of a computing environment for combining and using one or more aspects of this disclosure is described;

[0009] Figure 2 Depicting one or more aspects according to this disclosure Figure 1 An example of further details of the processors in the processor set;

[0010] Figure 3A Depicting one or more aspects according to this disclosure Figure 1 An example of a submodule of the key protection module;

[0011] Figure 3B Depicting one or more aspects according to this disclosure Figure 3A An example of a submodule of the execution submodule;

[0012] Figure 4A An example of cryptographic key protection processing of a procedure according to one or more aspects of this disclosure is described;

[0013] Figure 4B An example of cryptographic key protection processing of a processor according to one or more aspects of this disclosure is described;

[0014] Figure 5A An example is depicted showing the format of instructions for performing cryptographic key management operations in accordance with one or more aspects of this disclosure;

[0015] Figures 5B-5C Depicting one or more aspects of this disclosure by Figure 5A An example of the contents of a general-purpose register used by instructions for executing cryptographic key management operations;

[0016] Figure 5D Depicting one or more aspects of this disclosure by Figure 5A An example of a parameter block used by instructions for performing cryptographic key management operations;

[0017] Figures 6A-6B Examples of encrypting a key according to one or more aspects of this disclosure are depicted;

[0018] Figure 7AAn example of the format of a cryptographic message instruction according to one or more aspects of this disclosure is described;

[0019] Figures 7B-7D Depicting one or more aspects of this disclosure by Figure 7A An example of the contents of the registers used by the cryptographic message instruction;

[0020] Figures 7E-7F Depicting one or more aspects of this disclosure by Figure 7A An example of the contents of the general-purpose registers used by the cryptographic message instructions;

[0021] Figure 7G Depicting one or more aspects of this disclosure by Figure 7A An example of the parameter block used by the password message instruction;

[0022] Figure 8A An example of a computational operation performed according to one or more aspects of this disclosure is depicted;

[0023] Figure 8B An example of an encryption operation performed in accordance with one or more aspects of this disclosure is depicted;

[0024] Figure 8C An example of a decryption operation performed according to one or more aspects of this disclosure is depicted; and

[0025] Figures 9A-9B Another example of a computing environment for combining and using one or more aspects of this disclosure is described. Detailed Implementation

[0026] According to one or more aspects of this disclosure, an ability is provided for protecting a protected key used in the encryption / decryption of confidential data. In one example, the confidential data is an adjustment value used for encryption / decryption, and the protected key is a key used to encrypt / decrypt the adjustment value. Protecting the protected key provides additional protection for the confidential data. For example, by protecting the protected key used to encrypt the adjustment value, it becomes more difficult to discover and use the adjustment value.

[0027] In one or more aspects, a set of data keys (e.g., multiple data keys) is encrypted into a single encrypted data key. The data keys in the set of data keys are arranged in a specific order, and in one example, the specific order prevents the protected key from being in a selected position (e.g., the first position in the set of data keys).

[0028] In one example, if the data key set only includes the protected key, a pseudo data key is generated and included in the selected location. In another example, the data key set is encrypted into a single encrypted data key by a schema instruction. The output of the schema instruction is the single encrypted data key (also referred to herein as a single encryption key, a multiple-key encryption key, etc.).

[0029] In one example, cryptographic block chaining is used to encrypt a set of data keys into a single encrypted data key to protect (multiple) protected keys. Cryptographic block chaining uses a cryptographic key applied to a block to encrypt a sequence of bits as a block (called a plaintext block). The first plaintext block in the chain is XORed with, for example, an initialization vector or an initial chain value to create a random or pseudo-random output, which is then encrypted to provide the encrypted block. The next plaintext block in the chain is similarly XORed and subsequently encrypted, but now XORed with the previously encrypted block, and so on. In one example, the size of the data blocks used in cryptographic block chaining is at most the size of a single data key.

[0030] As noted, in one example, the cryptographic block chaining technique feeds the output of the current ciphertext block to the next ciphertext block to scramble the next data key portion, thereby protecting the next ciphertext block. However, an initial chaining value of zero can be used to effectively bypass the scrambling of the first data key portion. Since the program does not provide initial chaining values ​​for non-first ciphertext block portions (data key portions), scrambling non-first data key portions provides additional protection for all non-first data key portions.

[0031] In one or more aspects, a single encryption key representing a set of data keys is decrypted to provide multiple decrypted keys, one or more of which are used to encrypt confidential data. For example, a decrypted protected key is used to encrypt an adjusted value. One or more other decrypted keys among the multiple decrypted keys are used to encrypt plaintext (e.g., a message). Other examples are also possible.

[0032] In one or more aspects, the decryption of a single encryption key and the encryption of confidential data (and / or the encryption of plaintext) are performed by a single schema instruction, wherein the decrypted key is protected from being clearly seen outside of instruction processing, thereby further protecting the confidential data to be encrypted using the decrypted data key. In one or more aspects, the single schema instruction used to decrypt the single encryption key and encrypt using the decrypted key is different from another schema instruction used to encrypt a set of data keys into a single encryption key.

[0033] One or more aspects of this disclosure are incorporated into, performed by, and / or used by a computing environment. As an example, a computing environment can have a variety of architectures and types, including but not limited to: personal computing, client-server, distributed, virtual, simulation, partitioned, non-partitioned, cloud-based, quantum, grid, time-sharing, clustered, peer-to-peer, wearable, mobile, having one or more nodes, having one or more processors, and / or any other type of environment and / or configuration capable of performing processes such as key protection, cryptographic processing (e.g., encryption and / or decryption), and / or one or more other aspects of this disclosure. The aspects of this disclosure are not limited to a specific architecture or environment.

[0034] Various aspects of this disclosure are described by narrative text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in embodiments of a computer program product (CPP). For any flowchart, operations may be performed in a sequence different from that shown in a given flowchart, depending on the art involved. For example, also according to the art involved, two operations shown in consecutive flowchart frames may be performed in reverse order, as a single integrated step, concurrently, or with at least partial temporal overlap.

[0035] Computer Program Product Embodiment (“CPP Embodiment” or “CPP”) is a term used in this disclosure to describe a collection of one or more storage media (also referred to as “media”) collectively included in a collection of one or more storage devices, which collectively include machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A “storage device” is any tangible device capable of holding and storing instructions for use by a computer processor. Without limitation, a computer-readable storage medium can be an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include: floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), optical disc read-only memory (CD-ROM), digital versatile optical disc (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punch cards or pits / platforms formed in the main surface of the disk), or any suitable combination of the foregoing. The term "computer-readable storage medium" as used in this disclosure should not be construed as storing transient signals in their own form, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides, optical pulses through fiber optic cables, electrical signals transmitted through wires, and / or other transmission media. As those skilled in the art will understand, during normal operation of a storage device, data is typically moved at some incidental points in time, such as during access, defragmentation, or garbage collection, but this does not make the storage device transient, because the data is not transient when it is stored.

[0036] Reference Figure 1An example of a computing environment for performing, combining, and / or using one or more aspects of this disclosure is described. In one example, computing environment 100 includes an example of an environment for performing at least some computer code (such as key protection code or module 150) related to performing the methods of the present invention. In addition to block 150, computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end user equipment (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this embodiment, computer 101 includes a processor set 110 (including processing circuitry 120 and cache 121), communication infrastructure 111, volatile memory 112, persistent storage device 113 (including operating system 122 and block 150 as described above), a peripheral device set 114 (including a user interface (UI) device set 123, storage device 124, and Internet of Things (IoT) sensor set 125), and a network module 115. Remote server 104 includes a remote database 130. Public cloud 105 includes gateway 140, cloud orchestration module 141, host physical machine set 142, virtual machine set 143, and container set 144.

[0037] Computer 101 may be a desktop computer, laptop computer, tablet computer, smartphone, smartwatch or other wearable computer, mainframe computer, quantum computer, or any other form of computer or mobile device now known or to be developed in the future capable of running programs, accessing networks, or querying databases (such as remote database 130). As is well understood in the field of computer technology, and according to the technology, the execution of computer-implemented methods can be distributed among multiple computers and / or multiple locations. On the other hand, in this description of computing environment 100, in order to keep the description as simple as possible, the detailed discussion focuses on a single computer, specifically computer 101. Even Figure 1 The computer 101 is not shown in the cloud, but it may be located in the cloud. On the other hand, unless it is explicitly stated that it needs to be located in the cloud to some extent, the computer 101 is not required to be located in the cloud.

[0038] Processor set 110 includes one or more computer processors of any type now known or to be developed in the future. Processing circuitry 120 may be distributed across multiple packages, such as multiple coordinated integrated circuit chips. Processing circuitry 120 may implement multiple processor threads and / or multiple processor cores. Cache 121 is memory located within the processor chip package(s) and is typically used for data or code that should be readily accessible to the threads or cores running on processor set 110. Cache memory is typically organized into multiple levels based on its relative proximity to the processing circuitry. Alternatively, some or all of the cache of the processor set may be located “off-chip.” In some computing environments, processor set 110 may be designed to use qubits and perform quantum computing.

[0039] Typically, computer-readable program instructions are loaded onto computer 101 to cause the processor set 110 of computer 101 to perform a series of operational steps and thereby implement a computer-implemented method, such that the instructions thus executed instantiate the method specified in the flowcharts and / or the descriptive description of the computer-implemented method included in this document (collectively, the "method of the invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 121 and other storage media discussed below. The processor set 110 accesses the program instructions and associated data to control and direct the execution of the method of the invention. In computing environment 100, at least some of the instructions for performing the method of the invention may be stored in block 150 of persistent storage device 113.

[0040] Communication structure 111 is a signal transmission path that allows the various components of computer 101 to communicate with each other. Typically, this structure consists of switches and conductive paths, such as switches and conductive paths that form buses, bridges, physical input / output ports, etc. Other types of signal communication paths can be used, such as fiber optic communication paths and / or wireless communication paths.

[0041] Volatile memory 112 is any type of volatile memory now known or to be developed in the future. Examples include dynamic random access memory (RAM) or static RAM. Typically, volatile memory is characterized by random access, but this is not necessarily the case unless explicitly stated otherwise. In computer 101, volatile memory 112 is located in a single package and inside computer 101, but alternatively or additionally, volatile memory may be distributed across multiple packages and / or located externally relative to computer 101.

[0042] The persistent storage device 113 is any form of non-volatile storage device for a computer, now known or to be developed in the future. The non-volatility of this storage device means that the stored data is retained regardless of whether power is supplied to the computer 101 and / or directly to the persistent storage device 113. The persistent storage device 113 may be a read-only memory (ROM), but typically at least a portion of the persistent storage device allows data to be written, deleted, and rewritten. Some common forms of persistent storage devices include hard disks and solid-state storage devices. The operating system 122 may take many forms, such as various known proprietary operating systems or operating systems employing an open-source portable operating system interface type with a kernel. The code included in box 150 typically includes at least some computer code relating to performing the methods of the present invention.

[0043] Peripheral device set 114 includes a collection of peripheral devices for computer 101. Data communication connections between peripheral devices and other components of computer 101 can be implemented in various ways, such as Bluetooth connectivity, near field communication (NFC) connectivity, connections formed via cables (such as Universal Serial Bus (USB) type cables), plug-in connections (e.g., secure digital (SD) cards), connections formed via local area communication networks, and even connections formed via wide area networks such as the Internet. In various embodiments, UI device set 123 may include components such as displays, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. Storage device 124 is an external storage device (such as an external hard drive) or a pluggable storage device (such as an SD card). Storage device 124 may be persistent and / or volatile. In some embodiments, storage device 124 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments requiring computer 101 to have a large amount of storage (e.g., computer 101 locally stores and manages a large database), this storage can be provided by peripheral storage devices designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple geographically distributed computers. The IoT sensor set 125 consists of sensors that can be used for Internet of Things (IoT) applications. For example, one sensor could be a thermometer, while another could be a motion detector.

[0044] Network module 115 is a collection of computer software, hardware, and firmware that allows computer 101 to communicate with other computers via WAN 102. Network module 115 may include hardware (such as a modem or Wi-Fi transceiver), software for packetizing and / or de-packetizing data for transmission over a communication network, and / or web browser software for transmitting data over the Internet. In some embodiments, the network control and network forwarding functions of network module 115 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing software-defined networking (SDN), the control and forwarding functions of network module 115 are performed on physically separate devices, such that the control function manages several different network hardware devices. Typically, computer-readable program instructions for performing the methods of the present invention can be downloaded to computer 101 from an external computer or external storage device via a network adapter card or network interface included in network module 115.

[0045] WAN 102 is any wide area network (e.g., the Internet) known now or developed in the future that is capable of transmitting computer data over non-local distances using any technology used for transmitting computer data. In some embodiments, WAN 102 may be replaced and / or supplemented by a local area network (LAN) (such as a Wi-Fi network) designed to transmit data between devices located in a local area. WANs and / or LANs typically include computer hardware such as copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and edge servers.

[0046] End User Equipment (EUD) 103 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computer 101) and can take any of the forms discussed above in connection with computer 101. EUD 103 typically receives helpful and useful data from the operation of computer 101. For example, assuming computer 101 is designed to provide recommendations to the end user, these recommendations are typically transmitted from network module 115 of computer 101 to EUD 103 via WAN 102. In this way, EUD 103 can display or otherwise present the recommendations to the end user. In some embodiments, EUD 103 can be a client device, such as a thin client, a thick client, a mainframe computer, a desktop computer, etc.

[0047] Remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. Remote server 104 may be controlled and used by the same entity operating computer 101. Remote server 104 represents (multiple) machines that collect and store helpful and useful data for use by other computers, such as computer 101. For example, if computer 101 is designed and programmed to provide recommendations based on historical data, then that historical data can be provided to computer 101 from a remote database 130 of remote server 104.

[0048] Public cloud 105 is any computer system available to multiple entities, providing on-demand availability of computer system resources and / or other computing capabilities (especially data storage (cloud storage) and computing power) without direct active management by the user. Cloud computing typically leverages resource sharing to achieve consistency and economies of scale. Direct and active management of the computing resources of public cloud 105 is performed by the computer hardware and / or software of cloud orchestration module 141. The computing resources provided by public cloud 105 are typically implemented by virtual computing environments running on various computers constituting host physical machine set 142, which is the entire set of physical computers in and / or available to public cloud 105. Virtual computing environments (VCEs) typically take the form of virtual machines from virtual machine set 143 and / or containers from container set 144. It should be understood that these VCEs can be stored as images and can be transferred between various physical machine hosts as images or after VCE instantiation. Cloud orchestration module 141 manages the transfer and storage of images, deploys new instances of VCEs, and manages active instances of VCE deployments. Gateway 140 is a collection of computer software, hardware, and firmware that allow public cloud 105 to communicate via WAN 102.

[0049] Virtualized Computing Environments (VCEs) will now be explained further. A VCE can be stored as an "image." New active instances of a VCE can be instantiated from an image. Two common types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to an operating system feature where the kernel allows multiple isolated user-space instances, called containers, to exist. From the perspective of programs running within these isolated user-space instances, these instances typically behave like a real computer. Computer programs running on a regular operating system can utilize all the resources of that computer, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, programs running inside a container can only use the contents of the container and the devices allocated to that container; this feature is called containerization.

[0050] Private cloud 106 is similar to public cloud 105, except that its computing resources are available only to a single enterprise. While private cloud 106 is depicted as communicating with WAN 102, in other embodiments, private cloud can be completely disconnected from the internet and accessible only via a local / private network. A hybrid cloud is a combination of multiple clouds of different types (e.g., private, community, or public cloud types) and is typically implemented by different vendors. Each of the multiple clouds remains a separate and discrete entity, but the larger hybrid cloud architecture is joined together through standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the multiple component clouds. In this embodiment, both public cloud 105 and private cloud 106 are part of a larger hybrid cloud.

[0051] The computing environment described above is merely one example of a computing environment used in conjunction with, to execute, and / or use one or more aspects of this disclosure. Other examples are also possible. For instance, in one or more embodiments, Figure 1 One or more components / modules are not included in the computing environment and / or are not used in one or more aspects of this disclosure. Furthermore, in one or more embodiments, additional and / or other components / modules may be used. Other variations are also possible.

[0052] In one example, a processor (e.g., the processor of processor set 110) includes multiple functional components (or subsets thereof) for executing instructions. Figure 2 In one example, these functional components include, for example: an instruction fetch component 200 for fetching instructions to be executed; an instruction decoding / operand fetch component 202 for decoding the fetched instructions and obtaining the operands of the decoded instructions; one or more instruction execution components 204 for executing the decoded instructions; a memory access component 206 for accessing memory as necessary to execute instructions; and a write-back component 208 for providing the results of the executed instructions. During instruction processing, one or more components may access and / or use one or more registers 210. Furthermore, one or more components may access and / or use a key protection module 150. Additionally, fewer and / or other components may be used in one or more aspects of this disclosure.

[0053] In one example, a key protection module (e.g., key protection module 150) is used according to one or more aspects of this disclosure. According to one or more aspects of this disclosure, the key protection module (e.g., key protection module 150) includes code or instructions for protecting data keys (also referred to as keys or cryptographic keys) and / or performing other tasks. In one example, the key protection module (e.g., key protection module 150) includes various sub-modules for protecting data keys. Sub-modules are, for example, computer-readable program code (e.g., instructions) in a computer-readable medium (e.g., a storage device (e.g., persistent storage device 113, cache 121, storage device 124, other storage devices)). Computer-readable storage media may be part of one or more computer program products, and computer-readable program code may be executed by one or more computing devices and / or using one or more computing devices (e.g., one or more computers, such as computer(s) 101 and / or other computers; one or more servers, such as remote server(s) 104 and / or other remote servers; one or more devices, such as end-user devices(s) 103 and / or other end-user devices; one or more processors or nodes, such as processor(s) or nodes(s) of processor set 110 (e.g., processor 200) and / or other processors or nodes(s); processing circuitry, such as processing circuitry 120 of processor set 110 and / or other processing circuitry; and / or other computing devices, etc.). One or more and / or portions of a submodule may be executed using additional and / or other computers, servers, devices, processors, nodes, processing circuitry, and / or computing devices. Many examples are possible.

[0054] Reference Figure 3A An example of a key protection module 150 is described. In one example, the key protection module 150 includes: a parameter block update submodule 300 for updating one or more parameter blocks to be used by one or more instructions in accordance with one or more aspects of this disclosure; an issuing submodule 310 for issuing one or more instructions to be used in accordance with one or more aspects of this disclosure; and an execution submodule 320 for performing one or more selected functions and / or operations of the selected instructions to be used in accordance with one or more aspects of this disclosure.

[0055] Reference Figure 3BFurther details of the execution submodule 320 are described below. In one example, the execution submodule 320 includes: an instruction acquisition submodule 322 for acquiring (e.g., receiving, being provided, pulling, retrieving, taking, etc.) a selected instruction to be executed (e.g., executing a cryptographic key management operation instruction and / or a cryptographic message instruction); and an instruction execution submodule 330 for executing the selected instruction. The instruction execution submodule 330 includes, for example: an operand acquisition submodule 332 for acquiring one or more operands and / or other information for the selected instruction; an execution function / operation submodule 334 for executing one or more functions / operations of the selected instruction; and a return submodule 336 for returning the result of the executed instruction.

[0056] According to one or more aspects of this disclosure, one or more of the submodules (e.g., submodules 300-322, 330-336) are at least used to perform key protection processing. In one example, refer to... Figure 4A The cryptographic key protection process of program 400 is performed by one or more computing devices (e.g., one or more computers, such as computer(s) 101 and / or other computers; one or more servers, such as remote server(s) 104 and / or other remote servers; one or more devices, such as end-user devices(s) 103 and / or other end-user devices; one or more processors or nodes, such as processor(s) or nodes (e.g., processor 200) of processor set 110 and / or other processors or nodes; processing circuitry, such as processing circuitry 120 of processor set 110 and / or other processing circuitry; and / or other computing devices, etc.). Additional and / or other computers, servers, devices, processors, nodes, processing circuitry, and / or computing devices may be used to perform this process and / or aspects thereof. Many examples are possible.

[0057] Reference Figure 4A In one example, the cryptographic key protection process of program 400 (also referred to as process 400) provides a set of 410 data keys (e.g., multiple data keys) in the parameter block of an encryption instruction. In one example, the encryption instruction is an instruction to perform cryptographic key management operations, and the format and content of the parameter block depend on the function to be performed by the instruction. In one example, process 400 provides multiple (e.g., two or another number) plaintext XTS-AES algorithm data keys (e.g., key 1, key 2, etc.) in the parameter block (e.g., using the parameter block to update submodule 300). In one example, one of the keys (e.g., key 2) is a protected key because it is used to encrypt confidential data (e.g., adjustment values). This protected key (e.g., key 2) is placed in a position other than the first position within the parameter block, such as the last key in the data key set (or a key other than the first key).

[0058] To further illustrate, in one or more aspects, the data keys in the data key set placed in the parameter block are arranged in a specific order. In one example, this specific order includes placing protected keys (e.g., keys used to encrypt / decrypt confidential data such as adjustment values ​​and / or other confidential data) in any position other than the first position. In one example, if all data keys in the data key set are protected keys, then a pseudo-data key is placed in the first position. In one example, the specific order (other than the first position) follows the order in which the hardware uses the data keys. Other examples are also possible.

[0059] Process 400 issues a 415 encryption instruction (e.g., using issue submodule 310) to encrypt multiple keys. For example, process 400 issues an instruction to perform a cryptographic key management operation, and in one example, issues a specific function of an AES-XTS dual-key (e.g., or multiple-key (e.g., two or more)) encryption function, referred to herein as an instruction to perform a cryptographic key management operation. This function is executed by one or more computing devices (e.g., one or more processors 200; (multiple) other computing devices) (e.g., using execution submodule 320) to generate a single encryption key (referred herein to as a single encryption key multi-key) by encrypting multiple data keys, as described below. Figure 4B Further description.

[0060] Process 400 obtains 420 as a single encryption key for multiple encryption keys. For example, process 400 obtains (e.g., receives, retrieves, takes out, is provided, pulls, etc.) an encrypted XTS-AES multiple (e.g., dual) key (e.g., an encrypted multiple key as a single encryption key) by executing the key encryption function of the cryptographic key management operation instruction.

[0061] Process 400 provides 430 as a single encryption key within a parameter block of a selected instruction (e.g., a selected cipher instruction) (e.g., updating submodule 300 with a parameter block). As an example, the selected instruction is a cipher message instruction. The encryption key as a single encryption key includes, for example, multiple (e.g., two) XTS-AES algorithm data keys (e.g., key 1 and key 2), and the data key for confidential data (e.g., an adjustment value) (e.g., key 2) is the last key (or, if more than two keys exist, it is in a position other than the first position).

[0062] Process 400 issues 435 (e.g., using issue submodule 310) a selected function for a selected cipher instruction. For example, process 400 issues a cipher message instruction, and as an example, issues a cipher message instruction with the full XTS-AES function. The selected function is executed by one or more computing devices (e.g., one or more processors 200; (multiple) other computing devices) and returns the result of that function, as described below. Figure 4B Further description.

[0063] Process 400 yields the result of the selected cipher instruction 440.

[0064] Reference Figure 4B Further details describe an example of one or more computing devices performing a function / operation issued by process 400. In one example, the cryptographic key protection process of processor 450 is performed by one or more computing devices (e.g., one or more computers, such as computer(s) 101 and / or other computers; one or more servers, such as remote server(s) 104 and / or other remote servers; one or more devices, such as end-user devices(s) 103 and / or other end-user devices; one or more processors or nodes, such as processor(s) or nodes(s) of processor set 110 (e.g., processor 200) and / or other processors or nodes(s); processing circuitry, such as processing circuitry 120 of processor set 110 and / or other processing circuitry; and / or other computing devices, etc.). Additional and / or other computers, servers, devices, processors, nodes, processing circuitry, and / or computing devices may be used to perform this process and / or aspects thereof. Numerous examples are possible. According to one or more aspects of this disclosure, one or more submodules (e.g., submodules 320-336) are used to perform the cryptographic key protection process.

[0065] Reference Figure 4B In one example, the cryptographic key protection process of processor 450 (also referred to as process 450) acquires the functionality of encryption instructions issued by 460 (e.g., receiving, retrieving, extracting, being provided, pulling, etc.) for encrypting multiple keys. For example, it acquires issued instructions to perform cryptographic key management operations (e.g., using the acquisition instruction submodule 322), which indicates the encryption function to be performed and includes a parameter block with a set of plaintext data keys to be encrypted (e.g., key 1, key 2).

[0066] Process 450 uses the system key to perform the 465 encryption function and returns a result (e.g., an encryption multi-key as a single encryption key). For example, the processor executes (e.g., using the execution instruction submodule 330) the obtained execution cryptographic key management operation instructions to use the system's AES wrapper key (WK).a This process encrypts multiple (e.g., two) XTS-AES data keys (e.g., key 1 and key 2) into a multi-key, as described in further detail below. The generation of a single encryption key is performed such that the single encryption key cannot be used to perform cryptographic operations that use only the protected key (e.g., extracting the encrypted protected key). The cryptographic key management operation returns the encrypted multi-key as a single encryption key within a parameter block (e.g., the same area in the parameter block where the plaintext data keys were originally located).

[0067] Based on the return of a multi-key encryption as a single encryption key to the program, in one example, the program issues a selected function of cryptographic instruction, wherein the multi-key encryption as a single encryption key is provided, the selected function being obtained by process 450. For example, process 450 obtains one of the cryptographic message full XTS-AES functions of 470 (e.g., receiving, retrieving, extracting, being provided, pulling, etc.) of the cryptographic message instruction issued by the program. Thus, in one example, a function (e.g., an encrypted data key function, such as a function of a schema instruction) encrypts a data key, providing a multi-key encryption as a single encryption key, which is input to another function (e.g., a cryptographic message function of another schema instruction). The cryptographic message function is different from the encrypted data key function, and in one example, one schema instruction is a schema instruction different from the other schema instruction. The cryptographic message function performs an operation to decrypt the multi-key encryption as a single encryption key, thereby providing multiple data keys in plaintext form, and then performs corresponding cryptographic operations using the respective plaintext keys, as described herein.

[0068] For example, based on obtaining a selected function (e.g., a full XTS-AES function for a cryptographic message), process 450 executes the instruction to perform multiple operations of the selected functions 472 and 475. For instance, process 450 uses the system key to perform a 472 data key decryption operation (data key decryption operation of the selected function of the cryptographic instruction) on an encrypted multi-key that serves as a single encryption key, to obtain the original (plaintext) multiple XTS-AES algorithm data keys. As an example, process 450 performs (e.g., using execution submodule 330) a decryption operation on the selected function of a cryptographic message to obtain an encrypted multi-key (e.g., a dual key) that serves as a single encryption key from a parameter block, and decrypts it using the system's AES wrapper key (WKa) to obtain multiple XTS-AES algorithm data keys (e.g., key 1, key 2, etc.) in plaintext form. In one example, each plaintext key (e.g., key 1, key 2, etc.) is obtained based on a specific key position format. This is the same key position format used in instructions that generate encrypted data key instructions that serve as encrypted multi-keys (e.g., instructions for executing cryptographic key management operations). Encryption data key instructions and cryptographic message instructions work together to protect confidential data and (multiple) protected keys.

[0069] Then, process 450 executes the encryption operation of the selected function of the cryptographic instruction 475 (e.g., the XTS-AES algorithm) to encrypt the adjustment value using a protected key (e.g., key 2) and the ciphertext message (e.g., plaintext) using a data key (e.g., key 1). In one example, for the XTS-AES algorithm, the encrypted adjustment value is multiplied by another value (e.g., the next alpha power) to provide a mask, referred to herein as TAU, which, together with key 1, is used to encrypt the plaintext block, thereby providing an encrypted ciphertext block as the cryptographic result. This process is further described below.

[0070] Process 450 returns the generated password result to the program at 480 (e.g., using return submodule 336).

[0071] As mentioned above, key protection processing uses various instructions, including cryptographic key management operation instructions and cryptographic message instructions, examples of which are described below. (See reference...) Figures 5A-5D This describes an example of cryptographic key management operation instructions, and refers to... Figures 7A-7G This is an example describing a password message instruction. Other examples are also possible.

[0072] An example of a cryptographic key management operation instruction is executing a cryptographic key management operation instruction. In one example, a cryptographic key management operation instruction (such as executing a cryptographic key management operation instruction) is a single, architecturally-structured hardware machine instruction at the hardware / software interface. As an example, it is part of an instruction set architecture. An example of an instruction set architecture that combines and / or uses cryptographic key management operation instructions and / or aspects of this disclosure is the z / Architecture® instruction set architecture provided by International Business Machines Corporation, Armonk, NY. An embodiment of the z / Architecture instruction set architecture is described in the publication entitled “z / Architecture Principles of Operation” (IBM Publication No. SA22-7832-13, 14th Edition, May 2022), the entire contents of which are incorporated herein by reference. However, the z / Architecture instruction set architecture is merely an example architecture; other architectures and / or other types of computing environments of International Business Machines Corporation and / or other entities / companies may include and / or use one or more aspects of this disclosure. z / Architecture and IBM are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction.

[0073] Reference Figure 5A In one example, the instruction 500 for performing a cryptographic key management operation includes at least one opcode field 502, which has an opcode indicating that this is an operation for performing cryptographic key management. In a particular example, the instruction 500 for performing a cryptographic key management operation has a format called a register-to-register format with extended opcodes, for example, having 32 bits. In this particular example, the instruction 500 for performing a cryptographic key management operation has an opcode field 502 (e.g., bits 0-15). Although there is one opcode field 502 in this example, there may be more than one opcode field in other examples. For example, there may be an opcode field at the beginning of the instruction format and an opcode field at the end of the instruction format. Other examples are also possible.

[0074] In one example, the instruction performing the cryptographic key management operation uses several implicit general-purpose registers, such as general-purpose register 0 (GR0) and general-purpose register 1 (GR1). These registers are called implicit registers because one or more fields of the instruction do not explicitly reference them; however, the instruction uses these registers. Figure 5BAn example of general-purpose register 0 is depicted. In one example, general-purpose register 0 (510) includes function code 512 (e.g., located in bits 57-63), which specifies the function to be performed by instructions executing cryptographic key management operations. Furthermore, in one example, selected bits (e.g., bit 56 of general-purpose register 0) will include zero; otherwise, a canonical anomaly is identified. The other bits of general-purpose register 0 are ignored. This is only one example. In other examples, one or more bits, or no bits, will include specific values, such as zero. Furthermore, in other examples, values ​​other than zero may be used. Many examples are possible.

[0075] Example function codes that may be used for one or more aspects of this disclosure include, for example, a function code specifying, for example, the encryption function of AES-XTS (Advanced Encryption Standard-XEX (XOR Encryption XOR) Adjustable Block Cipher with Ciphertext Stealing) 128 dual-key (e.g., function code 20); another function code specifying, for example, the encryption function of AES-XTS 256 dual-key (e.g., function code 22); and so on. While example functions and / or function codes may be specified, additional, fewer, and / or other functions / function codes may also be specified and used. Many examples are possible.

[0076] Figure 5C An example of general-purpose register 1 is depicted. In one example, general-purpose register 1 (520) includes the address 522 of a parameter block in a storage device (e.g., memory, storage unit, etc.). For example, address 522 is, for example, the logical address of the leftmost byte of the parameter block in the storage device. In one example, the address location in the general-purpose register depends on the addressing mode. For example, in 24-bit addressing mode, the contents of bits 40-63 of general-purpose register 1 constitute the address, and the contents of bits 0-39 are ignored. In 31-bit addressing mode, the contents of bits 33-63 of general-purpose register 1 constitute the address, and the contents of bits 0-32 are ignored. In 64-bit addressing mode, the contents of bits 0-63 of general-purpose register 1 constitute the address. In access register mode, access register 1 specifies the address space containing the parameter block. Other examples are also possible.

[0077] Reference Figure 5D This describes an example of a parameter block used by the AES-XTS 128 dual-key encryption function. In one example, the parameter block used by the AES-XTS 128 dual-key encryption function (e.g., parameter block 530) includes, for example: cipher key 1 (K1) 532 (e.g., byte offsets 0-15), cipher key 2 (K2) 534 (e.g., byte offsets 16-31), and the AES wrapper key verification mode (WK). aVP) 536 (e.g., byte offsets 32-63). In one example, a 32-byte cryptographic dual key including K1 and K2 in the parameter block, for example, byte offsets 0-31, is called the cryptographic key block. In other examples, the parameter block may include more than two keys, and the encryption function is a multi-key function. Furthermore, other examples are also possible, including other sizes of the parameter block (e.g., depending on the function to be performed) and / or other information.

[0078] In one example, the parameter block used by the encrypted AES-XTS 256 dual-key function is similar to the reference. Figure 5D The parameter block is described; however, for this function, cipher key 1 (K1) 532 is located, for example, at byte offsets 0-31; cipher key 2 (K2) 534 is located, for example, at byte offsets 32-63; and AES wrap key verification mode (WK) a VP) 536 is located, for example, at byte offsets 64-95. In one example, the 64-byte cryptographic dual key including K1 and K2, located at, for example, byte offsets 0-63 in the parameter block, is called the cryptographic key block. In other examples, the parameter block may include more than two keys, and the encryption function is a multi-key function. Furthermore, other examples are also possible, including other sizes of the parameter block (e.g., depending on the function to be performed) and / or other information.

[0079] In one example, a cryptographic key management operation instruction is executed (e.g., using the execution instruction submodule 330). Based on the execution of this instruction, an opcode is obtained, indicating that this is a key management operation (e.g., using the obtain operand submodule 332). Furthermore, a function code specifying, for example, an AES-XTS dual-key (or multi-key) encryption function, and the address of the parameter block to be used are obtained (e.g., using the obtain operand submodule 332). The specified function is executed (e.g., using the execute function / operation submodule 334).

[0080] For each function (e.g., encryption AES-XTS 128 dual-key function, encryption AES-XTS 256 dual-key function, etc.), the cryptographic key block (e.g., 32 bytes, 64 bytes respectively) obtained from, for example, parameter block 530 is encrypted using the AES wrapper key. In one example, the wrapper key is obtained from one or more wrapper key registers provided for this configuration. The encryption result (e.g., encryption multi-key as a single encryption key) is placed back into the byte offsets of the parameter block (e.g., 0-31, 0-63 respectively). The contents of the AES wrapper key verification mode register provided for this configuration are placed into, for example, AES wrapper key verification mode 536 of the parameter block (e.g., byte offsets 32-63, 64-95 respectively).

[0081] Figure 6AAn example of encrypting a key (such as a 128-bit AES key) is depicted. In one example of encryption process 600, key 610 (such as a 128-bit AES key) is encrypted 620 using the AES algorithm and a wrapper key 630 (e.g., a 256-byte AES wrapper key) to produce a result 640 (such as an encrypted 128-bit AES key). Figure 6A In this context, K is the unencrypted key (e.g., a 128-bit AES key). <n>It is the length of the project in bytes, and WK a (K) is the encrypted 128-bit AES key.

[0082] also, Figure 6B An example of encrypting a key (such as a 256-bit AES key) is depicted. In one example of encryption process 650, key 660 (such as a 256-bit AES key (e.g., K1, K2)) is encrypted 670 using the AES algorithm and a wrapper key 680 (e.g., a 256-byte AES wrapper key) to produce a result 690 (such as an encrypted 256-bit AES key). Figure 6B In this context, K is the unencrypted key (e.g., a 256-bit AES key). <n>It represents the length of the project in bytes, ⊕ is bitwise OR, and WK a (K) is the encrypted 256-bit AES key.

[0083] In one example, a single data key size is used as the maximum cryptographic (encryption / decryption) data block size for, for example, encryption functions, so that each data key portion is encrypted / decrypted as a separate data block. This leverages an additional XOR 665 (which can be bypassed using a zero initial linker value in the first block) to alter the encryption / decryption result, providing protection for non-first data key portions.

[0084] Other examples and variations are also possible.

[0085] Example program exceptions that may occur during the execution of cryptographic key management operation instructions include: access (retrieve, parameter block; store, parameter block; retrieve and store, cryptographic counter); operations (e.g., if Message Security Auxiliary Extension 3 is not installed); privileged operations; specifications; transaction constraints; etc. Additional, fewer, and / or other program exceptions may occur in other embodiments and / or other architectures.

[0086] In the description of instructions for performing cryptographic key management operations (such as instruction 500), a specific location, specific field, and / or specific size (e.g., specific bytes and / or bits) may be specified. However, other locations, fields, and / or sizes may be provided. Furthermore, while it may be specified that a bit be set to a specific value (e.g., one or zero), this is merely an example. In other examples, if the bit is set, it may be set to a different value, such as the opposite value or another value. Many variations are possible.

[0087] In one embodiment, the instruction may include additional fields, and these fields may be separate and independent of each other; however, in other embodiments, more than one field may be combined. Furthermore, while the example type of register is used, other types of registers may be used. Other examples are also possible.

[0088] Instructions for performing cryptographic key management operations (such as executing cryptographic key management operation instructions) may have additional, fewer, and / or other fields. Many variations are possible.

[0089] While various examples are provided for one or more formats for this instruction, additional and / or other formats may be used. Furthermore, this processing may be used for purposes other than those described herein.

[0090] Examples of cryptographic instructions used in one or more aspects of this disclosure include, for example, cryptographic message instructions. In one example, a cryptographic message instruction is a single, structured hardware machine instruction at the hardware / software interface. As an example, a cryptographic message instruction is part of an instruction set architecture. An example of an instruction set architecture that combines and / or uses cryptographic message instructions and / or aspects of this disclosure is the z / Architecture® instruction set architecture provided by International Business Machines Corporation, Armonk, NY. However, the z / Architecture instruction set architecture is merely an example architecture; other architectures and / or other types of computing environments of International Business Machines Corporation and / or other entities / companies may include and / or use one or more aspects of this disclosure.

[0091] Reference Figure 7A In one example, the cryptographic message instruction 700 includes: at least one opcode field 702 having an opcode indicating that this is a cryptographic message operation; a register field (R1) 704; and another register field (R2) 706. In a particular example, the cryptographic message instruction 700 has a format called a register-to-register format with extended opcodes, for example, having 32 bits. In this particular example, the cryptographic message instruction 700 has an opcode field 702 (e.g., bits 0-15), a register field (R1) 704 (e.g., bits 24-27), and another register field (R2) 706 (e.g., bits 28-31). Although there is one opcode field 702 in this example, more than one opcode field may exist in other examples. For example, there may be an opcode field at the beginning of the instruction format and an opcode field at the end of the instruction format. Other examples are also possible.

[0092] In one example, refer to Figure 7B Register field (R1) 704 specifies register 710 (R1), which contains the address 712 of the first operand of the instruction. Additionally, in one example, refer to... Figure 7C Register field (R2) 706 specifies register 720 (R2), which contains the address 722 of the second operand of the instruction. (See reference...) Figure 7D Another register 730 (R2+1) includes the length 732 of the second operand.

[0093] In one example, the R1 field specifies a general-purpose register, and will specify an even-numbered register other than, for example, general-purpose register 0; otherwise, a canonical anomaly is identified. The R2 field specifies a pair of even-odd general-purpose registers, and will specify an even-numbered register other than, for example, general-purpose register 0. In other examples, registers of other types than general-purpose registers may be used. Furthermore, registers other than even-numbered registers may be used. Many examples are possible.

[0094] In one example, the positions of the leftmost bytes of the first and second operands are specified by the contents of general-purpose registers R1 and R2, respectively. The number of bytes in the second operand position is specified, for example, in general-purpose register R2+1. In one example, the first and second operands have the same length.

[0095] As part of the operation, the addresses in general-purpose registers R1 and R2 are incremented by the number of bytes processed, and the length in general-purpose register R2+1 is decremented by the same number. The formation and updating of addresses and lengths depend, for example, on the addressing mode.

[0096] For example, in 24-bit addressing mode, bits 40-63 of general-purpose registers R1 and R2 constitute the addresses of the first and second operands, respectively, and bits 0-39 are ignored. Bits 40-63 of the updated address replace the corresponding bits in general-purpose registers R1 and R2. Carries out from, for example, bit position 40 of the updated address are ignored, and bits 32-39 of general-purpose registers R1 and R2 are set to, for example, zero. In 31-bit addressing mode, bits 33-63 of general-purpose registers R1 and R2 constitute the addresses of the first and second operands, respectively, and bits 0-32 are ignored. Bits 33-63 of the updated address replace the corresponding bits in general-purpose registers R1 and R2. Carries out from, for example, bit position 33 of the updated address are ignored, and bits 32 of general-purpose registers R1 and R2 are set to zero. In 64-bit addressing mode, the contents of bits 0-63 of general-purpose registers R1 and R2 constitute the addresses of the first and second operands, respectively; bits 0-63 of the updated address replace the contents of general-purpose registers R1 and R2, and carry, for example, generated from bit position 0, is ignored. Other examples are also possible.

[0097] In both 24-bit and 31-bit addressing modes, the contents of bits 32-63 of general-purpose register R2+1 form a 32-bit unsigned binary integer, specifying the number of bytes in the first and second operands, and the contents of bits 0-31 are ignored; bits 32-63 of the updated value replace the corresponding bits in general-purpose register R2+1. In 64-bit addressing mode, the contents of bits 0-63 of general-purpose register R2+1 form a 64-bit unsigned binary integer, specifying the number of bytes in the first and second operands; and the updated value replaces the contents of general-purpose register R2+1.

[0098] In one example, in 24-bit or 31-bit addressing modes, the contents of bits 0-31 of general-purpose registers R1, R2, and R2+1 remain unchanged.

[0099] In register access mode, registers 1, R1, and R2 specify the address space containing the parameter block, the first operand, and the second operand, respectively.

[0100] Furthermore, in one example, the cipher message instruction uses several implicit general-purpose registers, such as general-purpose register 0 (GR0) and general-purpose register 1 (GR1). These registers are called implicit registers because one or more fields of the instruction do not explicitly reference them; however, the instruction uses these registers. Examples of these registers are described below.

[0101] In reference Figure 7E In one example, general-purpose register 0 (740) includes, for example:

[0102] Modifier 744 (e.g., bit 56): When the function code (e.g., bits 57-63 of general-purpose register 0) is, for example, non-zero, the modifier field 744 (e.g., bit 56) includes a modifier control (e.g., a modifier bit) that indicates whether the function should perform encryption or decryption. When the modifier field 744 is, for example, zero, the function performs encryption on the second operand (e.g., the value in R2); when the modifier field 744 is, for example, one, the function performs decryption on the second operand; and

[0103] Function code 746 (e.g., bits 57-63): Function code field 746 includes a function code that specifies the function to be performed by the cryptographic message instruction. The instruction is configured to specify and implement multiple functions. Example functions used according to one or more aspects of this disclosure include, for example, a function code (e.g., function code 90) that specifies, for example, a cryptographic message full XTS encryption AES 128 dual-key function for the cryptographic message instruction; and so on. While example functions and / or function codes are specified, additional, fewer, and / or other functions / function codes may also be specified and used. Many examples are possible.

[0104] Furthermore, in one example, depending on the selected function code, selected bits, such as one or more bits 0-55 of general-purpose register 0, are ignored. This is just one example. In other examples, one or more bits, or no bits, will include specific values, such as zero. Additionally, in other examples, values ​​other than zero may be used. Many examples are possible. For instance, when specifying the cipher message full XTS encryption AES 128 function for the cipher message instruction, bits 0-31 of general-purpose register 0 are ignored, and bits 32-55 of general-purpose register 0 are reserved and will contain selected values, such as zero; otherwise, the program may not be able to run incompatiblely in the future. Other examples are also possible for this instruction and for each function.

[0105] Figure 7F An example of general-purpose register 1 is depicted. In one example, general-purpose register 1 (750) includes the address 752 of a parameter block in a storage device (e.g., memory, storage unit, etc.). For example, address 752 is, for example, the logical address of the leftmost byte of the parameter block in the storage device. In one example, the address location in the general-purpose register depends on the addressing mode. For example, in 24-bit addressing mode, the contents of bits 40-63 of general-purpose register 1 constitute the address, and the contents of bits 0-39 are ignored. In 31-bit addressing mode, the contents of bits 33-63 of general-purpose register 1 constitute the address, and the contents of bits 0-32 are ignored. In 64-bit addressing mode, the contents of bits 0-63 of general-purpose register 1 constitute the address. In access register mode, access register 1 specifies the address space containing the parameter block. Other examples are also possible.

[0106] Reference Figure 7G This describes an example of a parameter block used by the Cipher Message Full XTS Encryption AES 128 function. In one example, the parameter block used by the Cipher Message Full XTS Encryption AES 128 function (e.g., parameter block 760) includes, for example, the encryption key (WK). a (K) 762 (e.g., byte offset 0-31); Adjustment value (i) 764 (e.g., byte offset 32-47); Next alpha power (NAP) 766 (e.g., byte offset 48-63); and AES wrapper key verification mode (WK) a VP) 768 (e.g., byte offset 64-95). In one example, the adjustment value and the next power of alpha are in little-endian format, for example. However, in one example, the 8 bits in each byte of the parameter block are not in bit-inverted format, i.e., the leftmost bit of the byte is bit 0 and the rightmost bit of the byte is bit 7. Additional, less, and / or other information is also possible, as are other examples and variations.

[0107] In one example, a cryptographic message instruction is executed (e.g., using the Execute Instruction submodule 330). Based on the execution of this instruction, an opcode is obtained (e.g., using the Obtain Operand submodule 332), indicating that this is a cryptographic operation, along with the addresses of the first and second operands and the parameter block to be used. Furthermore, a function code specifying, for example, a cryptographic function and a modifier control specifying encryption or decryption are obtained (e.g., using the Obtain Operand submodule 332). The specified function / operation is executed (e.g., using the Execute Function / Operation submodule 334).

[0108] In the operation of a cryptographic message instruction (e.g., instruction 700), in one example, the second operand (e.g., the second operand in register R2) is cryptographically processed using the cryptographic key in the parameter block (e.g., encryption key 762) as specified by the function code, and the result is placed at the first operand location (e.g., the address specified in R1). For the XTS function, the cryptographic processing can use the next alpha power in the parameter block (e.g., next alpha power 766).

[0109] In one example, for the full XTS encryption AES 128 function for ciphertext messages, the contents of the parameter block at byte offsets 64-95 (e.g., AES wrapper key verification mode 768) are compared with the contents of the AES wrapper key verification mode register. If they do not match, the parameter block position remains unchanged, and the operation is completed by setting a condition code (e.g., 1). If they match, the contents of the parameter block at byte offsets 0-31 (e.g., encryption cipher key 762; e.g., encryption multi-key as a single encryption key) are decrypted using the AES wrapper key to obtain a pair of keys: 128-bit cipher key 1 (K1) (also known as the data key, from the left half) and 128-bit cipher key 2 (K2) (also known as the adjustment key, from the right half). The 128-bit adjustment value (i) is located at byte offsets 32-47 of the parameter block (e.g., adjustment value 764), and the 128-bit next alpha power (NAP) is located at byte offsets 48-63 of the parameter block (e.g., next alpha power 766).

[0110] In one example, such as Figure 8A As shown, a 128-bit adjustment value (i) 800 is encrypted using a 128-bit adjustment key (K2) 802 and an AES encryption algorithm (AESe) 804, and the result 806 is multiplied by the next alpha power (NAP) 810 808 to produce TAU 812 (e.g., the XTS parameter; also known as the mask). The multiplication operation is performed in GF(2 128 ) to execute.

[0111] Encryption is performed when the modifier (M) bit in general-purpose register 0 is zero. In one example, such as... Figure 8B The illustration shows the encryption of a 16-byte plaintext block (P1, P2, ..., Pn) 820 in operand 2 using the AES encryption algorithm (AES e) 822 as an example.

[0112] Except for the first one, the TAU used is the TAU 842 and GF (2) from the previous one. 128 The result is obtained by multiplying the value 2 (846) in the first plaintext block by 844. To encrypt the first plaintext block, the initial TAU 840 is used.

[0113] Except for the first block, the next alpha power (NAP) used is the next alpha power (NAP) of the previous block 832 and GF(2 128 The result is obtained by multiplying the value 2 (836) in the first plaintext block by 834. For the first plaintext block, the initial next alpha power (NAP) 830 is used from the parameter block (e.g., the next alpha power 766).

[0114] In one example, such as Figure 8B The process described involves XORing (⊕) 850 of the TAU of each block with the corresponding plaintext (P) block 820. Then, the result of the XOR operation is encrypted (e) 822 using the AES encryption algorithm with a 128-bit data key (K1) 852. The result of the encryption operation is XORed with the TAU (e.g., the result of multiplying 840, 842, and 846 respectively) 854 to produce the ciphertext (C) block 858. The next alpha power (NAP) of this block is then XORed with GF (2^2 / ... 128 Multiply the value of 2 in ) to obtain the next alpha power (NAP) of the next block. Then multiply the TAU of the block by GF(2). 128 Multiply the value 2 in ) to get the TAU of the next block.

[0115] The ciphertext blocks (C1, C2, ..., Cn) are stored in operand 1. The final result of the TAU multiplication is called the output TAU.

[0116] Decryption is performed when the modifier bit in general-purpose register 0 is one. In one example, such as... Figure 8C The diagram depicts the decryption of a 16-byte ciphertext block (C1, C2, ..., Cn) 880 in operand 2 using the AES decryption algorithm (AES d) 882.

[0117] Except for the first one, the TAU used is the TAU 872 from the previous one and GF (2 128 The result is obtained by multiplying the value 2 (876) in the first ciphertext block by 874. To decrypt the first ciphertext block, the initial TAU 870 is used.

[0118] Except for the first block, the next alpha power (NAP) used is the next alpha power (NAP) of the previous block 862 and GF(2 128 The result is obtained by multiplying the value 2 (866) in the first ciphertext block by 864. For the first ciphertext block, the initial next alpha power (NAP) 860 from the parameter block is used.

[0119] In one example, the TAU of each block is XORed with the corresponding ciphertext block 880 (890). Then, using the 128-bit data key (K1) (892), the result of the XOR operation is decrypted using the AES decryption algorithm (882). The result of the decryption operation is XORed with the TAU (the result of multiplying 870, 872, and 876 respectively) (894) to produce the plaintext block 898. The next power of alpha (NAP) of this block is then XORed with GF (2^3). 128 Multiply the value of 2 in ) to obtain the next alpha power (NAP) of the next block. Then multiply the TAU of the block by GF(2). 128 Multiply the value 2 in ) to get the TAU of the next block.

[0120] The plaintext blocks (P1, P2, ..., Pn) are stored in operand 1. The final result of the TAU multiplication is called the output TAU.

[0121] The function completes processing after the last input text block is processed with a password and a condition code (e.g., 0) is set. When the operation ends due to partial completion, a condition code (e.g., 3) is set. The next alpha power (NAP) is stored in the Next Alpha Power (NAP) field of the parameter block.

[0122] Example result condition codes for password message instructions include: 0 Normal completion; 1 Validation pattern mismatch; 2 -; 3 Partial completion.

[0123] In one example, the result is obtained as if processing were proceeding block by block to the right, starting from the left end of both the first and second operands. The cryptographic operation ends when the number of bytes of the second operand specified in the general-purpose register R2+1 has been processed and placed at the first operand location, or when a number of blocks less than the length of the second operand, as determined by the central processing unit (CPU), has been processed. The number of blocks determined by the CPU depends on the model and can be a different number each time the instruction is executed. The number of blocks determined by the CPU is typically, for example, non-zero. In some uncommon cases, this number can be zero, and a condition code (e.g., 3) can be set if no progress is made. However, the CPU prevents this no-progress situation from recurring indefinitely.

[0124] The result in the first operand position or the next alpha power field is unpredictable if, for example, any of the following occurs: the cryptographic key field or the encryption key field overlaps with any part of the first operand; the next alpha power field overlaps with any part of the first operand or the second operand; or the first operand and the second operand have a destructive overlap. Destructive overlap of operands is said to occur when processing is performed from left to right and one byte at a time, and the first operand position is used as the source after data has been shifted into it.

[0125] As an example, normal completion occurs when the cryptographic operation ends. Partial completion occurs when fewer blocks than the length of the second operand, as determined by the central processing unit, have been processed.

[0126] When an operation terminates due to normal completion, the condition code is set (e.g., 0), and the result in R2+1 is zero. When an operation terminates due to partial completion, the condition code is set (e.g., 3). In this case, in one example, if the central processing unit is enabled to update, for example, a counter in a cryptographic counter set, all second operands have been processed, and the appropriate counter is unavailable, the result placed in general-purpose register R2+1 is zero; otherwise, the result placed in general-purpose register R2+1 is non-zero.

[0127] In one example, PER (Program Event Log) store change events can be identified for both the first operand location and the stored portion of the parameter block. PER zero-address detection events can be identified for both the first operand location and the second operand location, as well as the parameter block. When a PER event is detected for one or more of these locations, identifying which location is in the PER access flag and the PER ASCE (Address Space Control Element) ID is unpredictable.

[0128] In one example, when a storage change PER event is detected, less than 4K additional bytes are stored in the first operand location before the event is reported.

[0129] When the second operand length is initially zero, the following occurs in one example: The parameter block, the first operand, and the second operand are not accessed, and the general-purpose registers R1, R2, and R2+1 are not modified. If the CPU is not enabled to update counters in the cryptographic counter set, the condition code is set (e.g., 0). If the CPU is enabled to update counters in the cryptographic counter set, and the appropriate counter is accessible, the appropriate counter is updated and the condition code is set (e.g., 0). If the CPU is enabled to update counters in the cryptographic counter set, and the appropriate counter is inaccessible, the condition code remains unchanged, and an access exception is identified for the location of the appropriate counter.

[0130] When the contents of fields R1 and R2 are the same, the contents of the specified register are incremented only by the number of bytes processed, rather than by twice the number of bytes processed.

[0131] As observed by the central processing unit, other central processing units, and channel programs, references to parameter blocks and storage operands can be multiple access references, accesses to these storage locations are not necessarily block-concurrent, and the order of these accesses or references is undefined.

[0132] In some less common cases, instruction execution can be accomplished by setting a condition code (e.g., 3) without updating registers to reflect the last cell of the processed first and second operands. The size of the processed cell in this case depends on the situation and model, but is limited to ensuring that processed but unreported portions of the first and second operands do not overlap in the memory. For example, in all cases, change bits are set where applicable for the processed first operand location, and a PER memory change event is reported.

[0133] For the function of comparing the Packet Key Verification Mode field in the execution parameter block with the Packet Key Verification Mode register, it is unpredictable whether an access exception and PER zero address detection event will be identified for the first operand and the second operand when the comparison result is a mismatch.

[0134] Access exceptions can be reported for portions of the operands larger than those processed in a single execution of the instruction; however, access exceptions will not be detected for positions exceeding the operand length or exceeding the currently processed position, such as positions exceeding 4KB. In one or more examples, for full XTS functionality, the entire parameter block can be tested for storage type access, even if a portion of the parameter block may not be stored. As an example, for all other functionality, only the stored portion of the parameter block can be tested for storage type access.

[0135] Examples of program exceptions that may occur during the execution of cryptographic message instructions include: access (retrieve, operand 2, cryptographic key and cryptographic key 1, cryptographic key 2, wrap key verification mode and adjustment value; store, operand 1; retrieve and store, XTS parameter, next alpha power (NAP) and cryptographic counter); operation (if message security aids are not installed); specification; transaction constraints.

[0136] Below is an example of execution priority:

[0137] 1.-6. Exceptions with the same priority as normal program interruption conditions.

[0138] 7.A Second instruction half-word access exception.

[0139] 7.B Operational error.

[0140] 7.C Transaction Constraints

[0141] 8. Specification exceptions caused by invalid function codes or invalid register numbers.

[0142] 9. Canonical exceptions due to invalid operand length.

[0143] 10. Access exception when accessing the password counter and the second operand length is initially zero.

[0144] 11. Condition code 0 is generated because the length of the second operand was initially zero.

[0145] 12.A.1 Access exception when accessing parameter blocks.

[0146] 12.A.2. Condition code 1 generated due to a mismatch in the verification pattern.

[0147] 12.B Access exception when accessing the first operand or the second operand.

[0148] 13. Condition code 3, which is generated due to partial completion (the length of the second operand is still non-zero).

[0149] 14. Condition code 3 is generated because the length of the second operand is reduced to zero and an access exception condition is detected when accessing the password counter.

[0150] 15. Condition code 0 is generated due to normal completion (the length of the second operand was initially non-zero, but decreased to zero).

[0151] In the description of cryptographic message instructions (such as cryptographic message instruction 700) herein, a specific location, specific field, and / or specific size (e.g., specific bytes and / or bits) can be specified. However, other locations, fields, and / or sizes can be provided. Furthermore, while it is possible to specify that a bit be set to a specific value (e.g., one or zero), this is merely an example. In other examples, if the bit is set, it can be set to a different value, such as the opposite value or another value. Many variations are possible.

[0152] In one embodiment, the fields of the instruction are separate and independent; however, in other embodiments, more than one field may be combined. Furthermore, while the example type of register is used, other types of registers may be used. Other examples are also possible.

[0153] Password message instructions (such as password message instructions) may have additional, fewer, and / or other fields. For example, one or more fields of a password message instruction (such as password message instructions) may be optional. Many variations are possible.

[0154] While various examples are provided for one or more formats for each instruction, additional and / or other formats may be used. Furthermore, this processing may be used for purposes other than those described herein.

[0155] In one or more aspects, key protection capabilities are provided to protect selected keys (referred to as protected keys) (such as adjusted value encryption keys and / or other keys) from being discovered and / or used. Protection is provided for the protected keys by placing them in a specific order (e.g., not in the first position in the dataset) of the set of data keys to be encrypted, and encrypting the set of data keys into a single encrypted data key, making these keys more difficult to discover. Multiple data keys are represented as a single key, and their order differs from the order in which they are used (e.g., the reverse order). In one example, this protects the protected key from being used by other single-key algorithms.

[0156] Furthermore, by using a single schema instruction to decrypt a single encrypted data key to generate multiple raw plaintext keys, and then using one or more of these raw plaintext keys to encrypt confidential data (e.g., adjusted values) with the single schema instruction, the confidential data can be used in cryptographic operations performed by the single schema instruction, thereby providing additional protection for both the confidential data and the protected keys.

[0157] In one or more aspects, a single encryption key (generated by encrypting multiple keys) received from one function (e.g., a function executing cryptographic key management operation instructions) is provided to another function (e.g., a function executing cryptographic message instructions) to perform (multiple) cryptographic operations. In one or more aspects, the single encryption key is decrypted using another function (e.g., a cryptographic operation function) to obtain multiple raw plaintext keys. Each plaintext key is obtained based on a specific key position format, and a corresponding cryptographic operation is performed using each plaintext key. At least one of the keys is a protected key.

[0158] In one or more aspects, cryptographic techniques are used to compute a single encryption key such that the single encryption key cannot be used to perform cryptographic operations that use only a protected key (e.g., extracting an encrypted protected key).

[0159] In one or more aspects, cryptographic block chaining is used to protect a set of protected data keys. In one or more aspects, the size of the data blocks used in the cryptography (encryption / decryption) is no larger than the size of a single data key, in order to conceal the set of protected data keys.

[0160] Although this document describes one or more examples of computing environments for combining and using one or more aspects of this disclosure, Figures 9A-9B Another embodiment of a computing environment for combining and using one or more aspects of this disclosure is described.

[0161] First refer to Figure 9A In this example, the computing environment 36 includes, for example, a native central processing unit (CPU) 37 based on an architecture having an instruction set architecture, a memory 38, and one or more input / output devices and / or interfaces 39 coupled to each other via, for example, one or more buses 40 and / or other connections.

[0162] The native central processing unit 37 includes one or more native registers 41, such as one or more general-purpose registers and / or one or more special-purpose registers used during processing within the environment. These registers include information representing the state of the environment at any given point in time.

[0163] Furthermore, the native central processing unit 37 executes instructions and code stored in memory 38. In a particular example, the central processing unit executes emulator code 42 stored in memory 38. This code enables the computing environment configured in this architecture to emulate another architecture (different from this architecture) and execute software and instructions developed based on the other architecture.

[0164] Reference Figure 9B Further details relating to emulator code 42 are described below. The object instructions 43 stored in memory 38 include software instructions (e.g., machine instruction related) developed for execution in an architecture other than the native CPU 37. For example, object instructions 43 may be designed to execute on a processor based on a different instruction set architecture, but are emulated on the native CPU 37, which may be, for example, an instruction set architecture. In one example, emulator code 42 includes an instruction fetch routine 44 for fetching one or more object instructions 43 from memory 38, and optionally providing a local buffer for the fetched instructions. Emulator code 42 also includes an instruction translation routine 45 for determining the type of the fetched object instruction and translating the object instruction into one or more corresponding native instructions 46. This translation includes, for example, identifying the function to be performed by the object instruction and selecting the native instruction(s)(s) for performing that function.

[0165] Furthermore, the emulator code 42 includes an emulation control routine 47 for executing native instructions. The emulation control routine 47 enables the native central processing unit 37 to execute a native instruction routine that emulates one or more previously obtained object instructions, and upon completion of this execution, returns control to the instruction fetch routine to emulate obtaining the next object instruction or a set of object instructions. Execution of the native instruction 46 may include: loading data from memory 38 into a register; storing data from a register back into memory; or performing a certain type of arithmetic or logical operation determined by a translation routine.

[0166] Each routine is implemented, for example, in software, which is stored in memory and executed by the native central processing unit 37. In other examples, one or more routines or operations are implemented in firmware, hardware, software, or some combination thereof. The registers of the emulated processor can be emulated using the native central processing unit register 41, or by using locations in memory 38. In embodiments, the object instruction 43, the native instruction 46, and the emulator code 42 may reside in the same memory or may be distributed across different storage devices.

[0167] According to one or more aspects of this disclosure, example instructions that can be simulated are those that perform cryptographic key management operations and cryptographic messages, as well as the instructions described herein.

[0168] The computing environments described herein are merely examples of computing environments that can be used. One or more aspects of this disclosure can be used with many types of environments. The computing environments provided herein are merely examples. Each computing environment can be configured to include one or more aspects of this disclosure. For example, each computing environment can be configured to implement key protection processing and / or perform one or more other aspects of this disclosure.

[0169] One or more aspects of this disclosure are related to computer technology and facilitate processing within a computer, thereby improving its performance. For example, by using a single instruction (e.g., a cryptographic instruction) to perform encryption and decryption, processing speed is increased and latency is reduced. Furthermore, security within the computing environment is improved by protecting selected data keys (such as protected keys used to encrypt / decrypt confidential data). This improves processing within the processor, computer system, and / or computing environment.

[0170] Other aspects, variations and / or embodiments are also possible.

[0171] In addition to the above, one or more aspects may be provided, supplied, deployed, managed, or serviced by a service provider that offers client environment management. For example, the service provider may create, maintain, and support computer code and / or computer infrastructure for one or more clients to execute one or more aspects. In return, the service provider may receive payments from clients, for example, under subscription agreements and / or fee agreements. Additionally or alternatively, the service provider may receive payments by selling advertising content to one or more third parties.

[0172] In one aspect, an application can be deployed to perform one or more embodiments. As an example, deploying an application includes providing computer infrastructure operable to perform one or more embodiments.

[0173] Alternatively, a computing infrastructure can be deployed that includes integrating computer-readable code into a computing system, wherein the code, in combination with the computing system, is capable of executing one or more embodiments.

[0174] In another aspect, a process for integrating computing infrastructure can be provided, which includes integrating computer-readable code into a computer system. The computer system includes a computer-readable medium, wherein the computer medium includes one or more embodiments. The code, combined with the computer system, is capable of executing one or more embodiments.

[0175] While various embodiments have been described above, these are merely examples. For instance, other instructions, instruction formats, operands, and / or registers may be used. Furthermore, other cryptographic algorithms may be used. Additionally, additional, fewer, and / or other modules / submodules may be used. While a particular submodule may be provided as an example of performing a specific operation or task, one or more additional and / or other submodules may be used. Submodules may be combined, and submodules may be separated into other submodules. Many variations are possible.

[0176] Various aspects and embodiments are described herein. Furthermore, many variations are possible without departing from the spirit of the aspects of this disclosure. It should be noted that, unless otherwise inconsistent, each aspect or feature described and / or claimed herein, and its variations, may be combined with any other aspect or feature.

[0177] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a / an" and "the" are also intended to include the plural forms. It should also be understood that when the term "comprises / comprising" is used in this specification, it specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0178] The corresponding structures, materials, actions, and equivalents of all means or steps plus functional elements (if any) in the following claims are intended to include any structure, material, or action used to perform the function in combination with other elements specifically claimed. The description of one or more embodiments is given for illustrative and descriptive purposes and is not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art. This embodiment was chosen and described to best illustrate aspects and practical application, and to enable others skilled in the art to understand the various embodiments with various modifications suitable for the particular intended use.< / n> < / n>

Claims

1. A computer program product, comprising: A collection of one or more computer-readable storage media; as well as Program instructions, collectively stored in the collection of the one or more computer-readable storage media, are used to cause at least one computing device to perform computer operations including the following: Obtain a set of data keys arranged in a specific order, the set of data keys including multiple data keys, the multiple data keys including a protected key, wherein the protected key is prevented from being in a selected position within the specific order; The data key set is encrypted into a single encryption key, which is the encryption of the plurality of data keys; and The single encryption key is returned, and it is decrypted to obtain multiple decrypted keys, at least one of which is a decrypted protected key to be used for encrypting the confidential value.

2. The computer program product according to claim 1, wherein, The computer operation further includes: decrypting the single encryption key to obtain the plurality of decrypted keys, the plurality of decrypted keys including the decrypted protected key.

3. The computer program product according to claim 2, wherein, The computer operation further includes encrypting the confidential value using the decrypted protected key.

4. The computer program product according to claim 3, wherein, Decrypting the single encryption key and encrypting the confidential value using the decrypted protected key are performed using a single structured instruction.

5. The computer program product according to claim 3, wherein, The plurality of decrypted keys also include a decrypted key, and the computer operation further includes: encrypting plaintext using the decrypted key.

6. The computer program product according to claim 5, wherein, Decrypting the single encryption key, encrypting the confidential value using the decrypted protected key, and encrypting the plaintext using the decrypted key are all performed using a single structured instruction.

7. The computer program product according to claim 6, wherein, The single encryption key is provided to the single architecture instruction in a parameter block that is input to the single architecture instruction, which is different from the selected architecture instruction used to encrypt the set of data keys into the single encryption key.

8. The computer program product according to any of the preceding claims, wherein, Encryption of the data key set is performed by a selected schema instruction, which obtains the data key set in the input parameter block of the selected schema instruction.

9. The computer program product according to any of the preceding claims, wherein, The selected position is the first position within the data key set.

10. The computer program product according to any of the preceding claims, wherein, The confidential value is an adjustment value, and the protected key is a key used to encrypt the adjustment value.

11. The computer program product according to any of the preceding claims, wherein, Based on the fact that the data keys in the data key set, excluding the pseudo data key, are protected keys, the data key set includes the pseudo data key at the selected location.

12. The computer program product according to any of the preceding claims, wherein, The specific order includes an arrangement of one or more data keys in the data key set according to their usage order.

13. A computer system, comprising: At least one computing device; A collection of one or more computer-readable storage media; as well as Program instructions, collectively stored in a collection of the one or more computer-readable storage media, are used to cause the at least one computing device to perform computer operations including the following: Obtain a set of data keys arranged in a specific order, the set of data keys including multiple data keys, the multiple data keys including a protected key, wherein the protected key is prevented from being in a selected position within the specific order; The data key set is encrypted into a single encryption key, which is the encryption of the plurality of data keys; and The single encryption key is returned, and it is decrypted to obtain multiple decrypted keys, at least one of which is a decrypted protected key to be used for encrypting the confidential value.

14. The computer system according to claim 13, wherein, The computer operation further includes: decrypting the single encryption key to obtain the plurality of decrypted keys, the plurality of decrypted keys including the decrypted protected key; and encrypting the confidential value using the decrypted protected key.

15. The computer system according to claim 14, wherein, Decrypting the single encryption key and encrypting the confidential value using the decrypted protected key are performed using a single structured instruction.

16. The computer system according to any one of claims 13 to 15, wherein, Based on the fact that the data keys in the data key set, excluding the pseudo data key, are protected keys, the data key set includes the pseudo data key at the selected location.

17. A computer-implemented method, comprising: Obtain a set of data keys arranged in a specific order, the set of data keys including multiple data keys, the multiple data keys including a protected key, wherein the protected key is prevented from being in a selected position within the specific order; The data key set is encrypted into a single encryption key, which is the encryption of the plurality of data keys; and The single encryption key is returned, and it is decrypted to obtain multiple decrypted keys, at least one of which is a decrypted protected key to be used for encrypting the confidential value.

18. The computer-implemented method according to claim 17, wherein, The computer operation further includes: decrypting the single encryption key to obtain the plurality of decrypted keys, the plurality of decrypted keys including the decrypted protected key; and encrypting the confidential value using the decrypted protected key.

19. The computer-implemented method according to claim 18, wherein, Decrypting the single encryption key and encrypting the confidential value using the decrypted protected key are performed using a single structured instruction.

20. The computer-implemented method according to any one of claims 17 to 19, wherein, Based on the fact that the data keys in the data key set, excluding the pseudo data key, are protected keys, the data key set includes the pseudo data key at the selected location.

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