Display device

Abstract

A novel display device is provided. The display device includes first to seventh transistors, a capacitor, and a light emitting element. A second terminal of the sixth transistor and a second terminal of the seventh transistor are electrically connected to an initialization line. A second terminal of the light emitting element is electrically connected to a common potential line. A gate of the sixth transistor is supplied with a first control signal. A back gate of the sixth transistor is supplied with a second control signal. A gate of the seventh transistor is supplied with a third control signal. A back gate of the seventh transistor is supplied with a fourth control signal. The potential of the initialization line is lower than the potential of the common potential line. The low potential of the second control signal and the low potential of the fourth control signal are different from the low potential of the first control signal and the low potential of the third control signal.

Description

Technical Field

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one aspect of the present invention is not limited to the aforementioned technical fields. The technical field of one aspect of the invention disclosed in this specification relates to an object, method, driving method, or manufacturing method. Furthermore, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter. Specifically, as examples of the technical field of one aspect of the present invention disclosed in this specification, examples include semiconductor devices, display devices, light-emitting devices, energy storage devices, optical devices, imaging devices, lighting devices, computing devices, control devices, storage devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, electronic devices, their driving methods, or their manufacturing methods. Background Technology

[0003] As a result of recent technological innovations, display devices have become commonplace, and in order to be competitive in this context, products with higher added value are required.

[0004] For example, display devices using transistors containing oxide semiconductors (also known as OS transistors) in a semiconductor layer having a channel formation region and transistors containing low-temperature polysilicon (LTPS) in a semiconductor layer having a channel formation region (also known as LTPS transistors) are known (see Patent Document 1). Display devices using OS transistors and LTPS transistors can be high-value-added display devices with features such as high resolution, low power consumption, high switching speed, and / or narrow bezels. Sometimes, the structure combining LTPS transistors and OS transistors is referred to as LTPO.

[0005] [Preliminary Technology Documents]

[0006] [Patent Literature]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 2018-5237

[0008] [Non-patent literature]

[0009] [Non-Patent Literature 1] Takashi Koida, “High Mobility Transparent Conductive Film”, National Institute of Advanced Industrial Science and Technology (AIST), Japan, AIST Solar Power Generation Research Results Presentation 2019, website:<URL:https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf> Summary of the Invention

[0010] The technical problem that the invention aims to solve

[0011] OS transistors exhibit low off-state current characteristics. Therefore, in display devices including pixel circuits with LTPO structures, they can be driven at low drive frequencies, achieving low power consumption. On the other hand, NBTIS (Negative Bias Temperature Illumination Stress) tests reveal that stresses such as light, heat, and voltage cause variations in the threshold voltage of OS transistors. Structures that cause a negative drift in the threshold voltage of OS transistors are effective in addressing these NBTIS-induced threshold voltage variations. However, when the off-state current of the OS transistor increases, it may be impossible to maintain the data voltage within the pixel circuit when driven at low drive frequencies. This could potentially degrade the display quality of the display device.

[0012] To suppress the negative drift of the threshold voltage of the OS transistor, it is effective to provide a back gate electrode opposite to the gate electrode across the channel forming region and control the potential of the back gate electrode. For example, a structure that supplies the same control signal to both the gate electrode and the back gate electrode can be cited. However, in a structure that supplies the same control signal to the back gate electrode as to the gate electrode, if the low-level potential of the control signal is high, for example, higher than the source potential of the OS transistor, it is insufficient to suppress the negative drift of the OS transistor's threshold voltage. Therefore, the reliability of the display device may be reduced.

[0013] One objective of this invention is to provide a display device with good display quality. Furthermore, one objective of this invention is to provide a display device with high reliability. Additionally, one objective of this invention is to provide a novel display device.

[0014] Note that the above-listed objectives do not preclude the existence of other objectives. One embodiment of the invention does not need to achieve all of the above-listed objectives. Other objectives besides those listed above can be understood and extracted from this specification, drawings, claims, etc.

[0015] means of solving technical problems

[0016] One aspect of the present invention is a display device comprising first to seventh transistors, a capacitor, and a light-emitting device. The first to fifth transistors each include a gate, a first terminal, and a second terminal. The sixth and seventh transistors each include a gate, a back gate, a first terminal, and a second terminal. The first terminal of the first transistor is electrically connected to the first terminals of the second and third transistors. The second terminal of the third transistor is electrically connected to the first terminals of the fourth and sixth transistors. The second terminal of the fourth transistor is electrically connected to the first terminals of the light-emitting device and the fifth transistor. The second terminal of the light-emitting device is electrically connected to a common potential line. The gate of the third transistor is connected to the second terminal of the sixth transistor, the first terminal of the seventh transistor, and the capacitor. The first terminal of the transistor is electrically connected. The second terminals of the fifth transistor and the seventh transistor are both electrically connected to the initialization line. The gate of the sixth transistor is electrically connected to the first gate line supplied with the first control signal. The back gate of the sixth transistor is electrically connected to the second gate line supplied with the second control signal. The gate of the seventh transistor is electrically connected to the third gate line supplied with the third control signal. The back gate of the seventh transistor is electrically connected to the fourth gate line supplied with the fourth control signal. The first control signal and the second control signal are logically identical. The third control signal and the fourth control signal are logically identical. The low-level potential of the second control signal and the low-level potential of the fourth control signal are different from the low-level potential of the first control signal and the low-level potential of the third control signal.

[0017] One aspect of the present invention is a display device comprising first to seventh transistors, a capacitor, and a light-emitting device. The first to fifth transistors each include a gate, a first terminal, and a second terminal; the sixth and seventh transistors each include a gate, a back gate, a first terminal, and a second terminal. The first terminal of the first transistor is electrically connected to a data line; the second terminal of the first transistor is electrically connected to the first terminals of the second and third transistors; the second terminal of the second transistor is electrically connected to a current supply line; the second terminal of the third transistor is electrically connected to the first terminals of the fourth and sixth transistors; the second terminal of the fourth transistor is electrically connected to the first terminals of the light-emitting device and the fifth transistor; the second terminal of the fifth transistor is electrically connected to an initialization line; the second terminal of the light-emitting device is electrically connected to a common potential line; and the gate of the third transistor... The second terminal of the sixth transistor, the first terminal of the seventh transistor, and the first terminal of the capacitor are electrically connected. The second terminal of the capacitor is electrically connected to the current supply line. The second terminal of the seventh transistor is electrically connected to the initialization line. The gate of the sixth transistor is electrically connected to the first gate line supplied with the first control signal. The back gate of the sixth transistor is electrically connected to the second gate line supplied with the second control signal. The gate of the seventh transistor is electrically connected to the third gate line supplied with the third control signal. The back gate of the seventh transistor is electrically connected to the fourth gate line supplied with the fourth control signal. The first control signal and the second control signal are logically identical. The third control signal and the fourth control signal are logically identical. The potential of the initialization line is lower than the potential of the common potential line. The low-level potentials of the second control signal and the fourth control signal are lower than the potential of the initialization line.

[0018] One aspect of the present invention is a display device comprising first to seventh transistors, a capacitor, and a light-emitting device. The first to fifth transistors each include a gate, a first terminal, and a second terminal. The sixth and seventh transistors each include a gate, a back gate, a first terminal, and a second terminal. The first terminal of the first transistor is electrically connected to a data line. The second terminal of the first transistor is electrically connected to the first terminals of the second and third transistors. The second terminal of the second transistor is electrically connected to a current supply line. The second terminal of the third transistor is electrically connected to the first terminals of the fourth and sixth transistors. The second terminal of the fourth transistor is electrically connected to the first terminals of the light-emitting device and the fifth transistor. The second terminal of the fifth transistor is electrically connected to an initialization line. The second terminal of the light-emitting device is electrically connected to a common potential line. The gate of the third transistor is connected to the first terminal of the sixth transistor. The first terminal of the second transistor, the first terminal of the seventh transistor, and the first terminal of the capacitor are electrically connected. The second terminal of the capacitor is electrically connected to the current supply line. The second terminal of the seventh transistor is electrically connected to the initialization line. The gate of the sixth transistor is electrically connected to the first gate line supplied with the first control signal. The back gate of the sixth transistor is electrically connected to the second gate line supplied with the second control signal. The gate of the seventh transistor is electrically connected to the third gate line supplied with the third control signal. The back gate of the seventh transistor is electrically connected to the fourth gate line supplied with the fourth control signal. The first control signal and the second control signal are logically identical. The third control signal and the fourth control signal are logically identical. The potential of the initialization line is lower than the potential of the common potential line. The potential of the initialization line is lower than the potential of the data line. The low-level potential of the second control signal and the low-level potential of the fourth control signal are lower than the potential of the initialization line.

[0019] In one aspect of the display device of the present invention, it is preferred that the first to fifth transistors are p-channel transistors, and the sixth and seventh transistors are n-channel transistors.

[0020] In one aspect of the display device of the present invention, it is preferred that the back gate of the n-channel transistor is opposite to the gate of the n-channel transistor across the channel forming region of the n-channel transistor.

[0021] In one aspect of the display device of the present invention, preferably, the n-channel transistor includes a first semiconductor layer comprising indium oxide.

[0022] In one aspect of the display device of the present invention, it is preferred that the p-channel transistor includes a second semiconductor layer, and the second semiconductor layer comprises silicon.

[0023] In one aspect of the display device of the present invention, it is preferred that the high-level potential of the second control signal and the high-level potential of the fourth control signal are the same as the high-level potential of the first control signal and the high-level potential of the third control signal.

[0024] In one embodiment of the display device of the present invention, it is preferred that the channel length of the third transistor is longer than the channel lengths of the first transistor, the second transistor, the fourth transistor, and the fifth transistor.

[0025] Note that one aspect of the present invention includes a structure in which at least one of the gate, source, and drain of the transistor has no connection points or is connected to any node. Furthermore, one aspect of the present invention includes a structure in which the wiring connected to the transistor has no connection points or can be input with any signal or voltage.

[0026] Note that other aspects of the present invention are described in the following description and accompanying drawings.

[0027] Invention Effects

[0028] One aspect of the present invention can provide a display device with good display quality. Furthermore, one aspect of the present invention can provide a display device with good reliability. Additionally, one aspect of the present invention can provide a novel display device.

[0029] Note that the effects listed above do not preclude the existence of other effects. One embodiment of the invention does not necessarily require all of the effects listed above. Other effects besides those listed above can be understood and extracted from this specification, drawings, or claims. Attached Figure Description

[0030] Figure 1A and Figure 1B It is a block diagram and circuit diagram illustrating the display device.

[0031] Figure 2 This is a circuit diagram illustrating the display device.

[0032] Figures 3A to 3D It is a circuit diagram and waveform diagram illustrating the display device.

[0033] Figures 4A to 4D It is a circuit diagram and waveform diagram illustrating the display device.

[0034] Figure 5 This is a circuit diagram illustrating the display device.

[0035] Figure 6 This is a timing diagram illustrating the display device.

[0036] Figure 7A and Figure 7B It is a circuit diagram and timing diagram illustrating the operation of the display device.

[0037] Figure 8A and Figure 8B It is a circuit diagram and timing diagram illustrating the operation of the display device.

[0038] Figure 9A and Figure 9B It is a circuit diagram and timing diagram illustrating the operation of the display device.

[0039] Figure 10A and Figure 10B It is a circuit diagram and timing diagram illustrating the operation of the display device.

[0040] Figure 11A and Figure 11B It is a circuit diagram and timing diagram illustrating the operation of the display device.

[0041] Figure 12A and Figure 12B This is a circuit diagram illustrating the display device.

[0042] Figure 13A and Figure 13B This is a circuit diagram illustrating the display device.

[0043] Figure 14A and Figure 14B This is a circuit diagram illustrating the display device.

[0044] Figure 15 This is a circuit diagram illustrating the display device.

[0045] Figure 16 This is a circuit diagram illustrating the display device.

[0046] Figure 17A and Figure 17B This is a circuit diagram illustrating the display device.

[0047] Figure 18A and Figure 18B It is a circuit diagram and waveform diagram illustrating the display device.

[0048] Figure 19A and Figure 19B It is a circuit diagram and block diagram illustrating the display device.

[0049] Figure 20A and Figure 20B It is a block diagram and circuit diagram illustrating the display device.

[0050] Figure 21 This is a circuit diagram illustrating the display device.

[0051] Figure 22 This is a circuit diagram illustrating the display device.

[0052] Figure 23 This is a circuit diagram illustrating the display device.

[0053] Figure 24 This is a timing diagram illustrating the display device.

[0054] Figure 25A and Figure 25B It is a circuit diagram and timing diagram illustrating the operation of the display device.

[0055] Figure 26A and Figure 26B It is a circuit diagram and timing diagram illustrating the operation of the display device.

[0056] Figure 27A and Figure 27B It is a circuit diagram and timing diagram illustrating the operation of the display device.

[0057] Figure 28A and Figure 28B It is a circuit diagram and timing diagram illustrating the operation of the display device.

[0058] Figure 29A and Figure 29B It is a circuit diagram and timing diagram illustrating the operation of the display device.

[0059] Figure 30 This is a block diagram illustrating the display device.

[0060] Figure 31 This is a circuit diagram illustrating the display device.

[0061] Figures 32A to 32C It is a block diagram and waveform diagram illustrating the display device.

[0062] Figure 33 This is a circuit diagram illustrating the display device.

[0063] Figure 34 This is a circuit diagram illustrating the display device.

[0064] Figure 35 This is a timing diagram illustrating the display device.

[0065] Figure 36A and Figure 36B It is a circuit diagram illustrating how the display device works.

[0066] Figure 37 This is a timing diagram illustrating the display device.

[0067] Figure 38A and Figure 38B It is a circuit diagram and timing diagram illustrating the operation of the display device.

[0068] Figure 39A and Figure 39BIt is a circuit diagram and timing diagram illustrating the operation of the display device.

[0069] Figure 40A and Figure 40B It is a circuit diagram and timing diagram illustrating the operation of the display device.

[0070] Figure 41A and Figure 41B It is a circuit diagram and timing diagram illustrating the operation of the display device.

[0071] Figure 42A and Figure 42B It is a circuit diagram and timing diagram illustrating the operation of the display device.

[0072] Figure 43 This is a perspective view showing an example of the structure of a display device.

[0073] Figures 44A to 44C This is a cross-sectional view showing an example of the structure of a display device.

[0074] Figure 45A and Figure 45B This is a cross-sectional view showing an example of the structure of a display device.

[0075] Figure 46 This is a plan view showing an example of the structure of a display device.

[0076] Figures 47A to 47C This is a cross-sectional view showing an example of the structure of a display device.

[0077] Figure 48 This is a schematic diagram illustrating an example of the structure of a display device.

[0078] Figure 49 This is a plan view showing an example of the structure of a display device.

[0079] Figures 50A to 50C This is a cross-sectional view showing an example of the structure of a display device.

[0080] Figure 51 This is a plan view showing an example of the structure of a display device.

[0081] Figures 52A to 52C This is a cross-sectional view showing an example of the structure of a display device.

[0082] Figure 53A and Figure 53B This is a graph illustrating the carrier concentration dependence of Hall mobility. Figure 53C This is a cross-sectional view illustrating the indium oxide film.

[0083] Figure 54A and Figure 54B This is a diagram illustrating an example of an electronic device.

[0084] Figures 55A to 55D This is a diagram illustrating an example of an electronic device.

[0085] Figures 56A to 56G This is a diagram illustrating an example of an electronic device.

[0086] Figures 57A1 to 57A7 and Figures 57B1 to 57B6 It is a diagram illustrating electrical connections. Detailed Implementation

[0087] Hereinafter, embodiments will be described with reference to the accompanying drawings. Note that embodiments can be implemented in many different forms. Therefore, those skilled in the art will readily understand that the manner and details can be varied in many ways without departing from its spirit and scope. Thus, one aspect of the present invention should not be construed as being limited to the content described in the embodiments.

[0088] Furthermore, the structures shown in each embodiment in this specification and the like can be appropriately combined with the structures shown in other embodiments to constitute a mode of the present invention. Additionally, when multiple structures are shown in one embodiment, these structures can be appropriately combined to constitute a mode of the present invention.

[0089] Note that, regarding the accompanying drawings illustrating the embodiments, in the structure of the invention, the same symbols are sometimes used in different drawings to represent the same parts or parts having the same function, thereby omitting repeated descriptions. Furthermore, in the drawings, when parts having the same function are represented, the same shading lines are sometimes used, for example, without specifically adding additional symbols. For example, in perspective views or plan views (also called "top views"), for clarity, illustrations of some constituent elements are sometimes omitted. For example, descriptions of some hidden lines in the drawings are sometimes omitted. Furthermore, for example, descriptions of shading lines in the drawings are sometimes omitted.

[0090] In the accompanying drawings, sizes, layer thicknesses, or areas are sometimes exaggerated for clarity. Therefore, the drawings are not limited to the sizes or aspect ratios shown. Furthermore, ideal examples are schematically illustrated in the drawings, so the invention is not limited to the shapes or values ​​shown. For example, in actual manufacturing processes, layers or resist masks are sometimes unintentionally thinned due to processes such as etching, but this is sometimes not reflected in the drawings for ease of understanding. Additionally, in actual circuit operation, voltage or current non-uniformity is sometimes caused by noise or timing deviations, but these are sometimes not reflected in the drawings for ease of understanding.

[0091] In this specification and accompanying drawings, the constituent elements of the present invention are classified according to function and represented as independent constituent elements. However, it is difficult to classify the constituent elements according to function, as sometimes one constituent element relates to multiple functions or multiple constituent elements relate to one function. Therefore, the constituent elements shown in this specification and accompanying drawings are not limited to their description, and appropriate wording may be used.

[0092] In this specification and accompanying drawings, when multiple constituent elements use the same symbol and it is necessary to distinguish them, sometimes an identification symbol such as "A", "b", "_1", "[n]", or "[m,n]" is added to the symbol. Furthermore, when describing the common content among multiple constituent elements for which an identification symbol is added, or when it is not necessary to distinguish them, sometimes the identification symbol is not added and the description is presented.

[0093] (Implementation Method 1)

[0094] A display device according to one aspect of the present invention will be described with reference to the accompanying drawings. The display device described in this embodiment includes a display section having pixels whose operation is controlled by a gate line-side driving circuit and a data line-side driving circuit.

[0095] <Example 1 of the structure of a display device>

[0096] Figure 1A A block diagram illustrating one aspect of the present invention is shown. As an example, Figure 1A The display device 100 shown includes a display unit 20, a gate line-side driving circuit 30, a gate line-side driving circuit 31, a gate line-side driving circuit 32, and an integrated circuit 40, etc.

[0097] The display unit 20 includes a plurality of pixels 11 arranged in a matrix. Each pixel 11 includes sub-pixels 10_R, 10_G, and 10_B. Each sub-pixel 10_R, 10_G, and 10_B includes a light-emitting device used as a display device.

[0098] Pixel 11 is connected to wirings GI, GI_BG, GW, EM, GB, GC, GC_BG, DLR, DLG, and DLB. Wirings GI, GI_BG, GW, EM, GB, GC, and GC_BG are used as gate lines. Wirings DLR, DLG, and DLB are used as data lines.

[0099] Gate lines are wirings that supply control signals to control the on and off states of transistors used as switches. Gate lines are sometimes also called gate signal lines, scan lines, or wiring. Data lines are wirings that supply data voltages (also called video voltages or video data) based on image signals to pixels. Data lines are sometimes called data signal lines, source lines, or wiring.

[0100] The wiring DLR, wiring DLG, and wiring DLB are all connected to integrated circuit 40. Furthermore, the wiring DLR, wiring DLG, and wiring DLB are respectively connected to a plurality of sub-pixels 10_R, a plurality of sub-pixels 10_G, and a plurality of sub-pixels 10_B arranged in the column direction (the extension direction of the wiring DLR, wiring DLG, and wiring DLB). Integrated circuit 40 is used as a circuit that supplies data voltage to pixel 11 (also called a source line drive circuit, source line-side drive circuit, or source driver).

[0101] Wiring GW, wiring GC, and wiring GC_BG are connected to the gate line-side driving circuit 30. Wiring GW, wiring GC, and wiring GC_BG are all connected to sub-pixels 10_R, 10_G, and / or 10_B arranged in the row direction (the extension direction of wiring GI, wiring GI_BG, wiring GW, wiring EM, wiring GB, wiring GC, or wiring GC_BG). Wiring GI, wiring GI_BG, and wiring GB are all connected to the gate line-side driving circuit 31. Wiring GI, wiring GI_BG, and wiring GB are connected to sub-pixels 10_R, 10_G, and / or 10_B arranged in the row direction. Wiring EM is connected to the gate line-side driving circuit 32. Wiring EM is connected to sub-pixels 10_R, 10_G, and / or 10_B arranged in the row direction. Gate line-side drive circuits 30, 31 and 32 are all used as circuits to supply control signals to pixels (also known as gate line drive circuits, gate line-side drive circuits or gate drivers).

[0102] The sub-pixels 10_R, 10_G, and 10_B included in the display unit 20 all include OS transistors and LTPS transistors. The OS transistors and LTPS transistors can be thin film transistors (TFTs). Since thin film transistors can be formed on a light-transmitting substrate such as a glass substrate, it is possible to achieve large-scale and low-cost display devices 100.

[0103] Furthermore, the gate line-side driving circuits 30, 31, and 32 can be fabricated on the substrate using the thin-film transistors included in the display unit 20. This structure allows for narrow bezels and / or a reduction in the number of components such as external driving circuits. Similar to the integrated circuit 40 used as the source line-side driving circuit, the gate line-side driving circuits 30, 31, and 32 can also be disposed on the substrate as integrated circuits.

[0104] Figure 1B This is a diagram illustrating an example of a circuit diagram of a sub-pixel (hereinafter referred to as pixel 10) that can be used in the display device 100 described above, including sub-pixels 10_R, 10_G, and 10_B. Pixel 10 includes transistors M11, M12, M13, M14, M15, M16, and M17, a capacitor C1, and a light-emitting device 61.

[0105] Figure 1B Each transistor in pixel 10 shown is connected to wiring GI, wiring GI_BG, wiring GW, wiring EM, wiring GB, wiring GC, wiring GC_BG, wiring DL, wiring ELVDD, wiring ELVSS, and wiring INI. Wiring DL is, for example, a wiring used as any one of wiring DLR, wiring DLG, and wiring DLB.

[0106] Wiring ELVDD, wiring ELVSS, and wiring INI are, for example, wiring that supplies a fixed potential (constant potential) for controlling the light-emitting devices included in pixel 10. Wiring ELVDD is sometimes referred to as a current supply line. Wiring ELVSS is sometimes referred to as a common potential line or common electrode. Wiring INI is sometimes referred to as an initialization line.

[0107] Wiring ELVDD is supplied with a high power supply potential (VDD), and wiring ELVSS is supplied with a low power supply potential (VSS). That is, current flows from wiring ELVDD to wiring ELVSS through transistors M12, M13, and M14 through the light-emitting device 61. By adopting this structure, the light emission of the light-emitting device 61 can be controlled according to the drain current of transistor M13 during the light emission period (when transistors M12 and M14 are in the on state).

[0108] Wiring INI is supplied with potential V INI (also known as V) INI V INI This is the potential used to turn on transistor M13 by supplying it to the gate. When transistor M13 is a p-channel transistor, V... INI It can be a potential lower than the VSS supplied to the wiring ELVSS. Furthermore, by V... INI As the potential supply for the anode of the light-emitting device 61, V can be...INI Used as a potential to prevent the light-emitting device 61 from emitting light.

[0109] Transistors M11, M12, M14, M15, M16, and M17 are used as switches. Transistor M13 is used as a transistor to control the current flowing through the light-emitting device 61. Transistor M13 is also used as a driver transistor.

[0110] Transistors M11, M12, M14, M15, M16, and M17 have the function of setting the voltage of the gate (node ​​ND1) of the driving transistor used to allow current to flow through the light-emitting device 61 to a voltage corresponding to the data voltage. Transistors M16 and M17 have the function of maintaining the voltage corresponding to the data voltage held at node ND1.

[0111] In the circuit diagrams illustrated in this specification, symbols are sometimes added to nodes for ease of understanding. For example, in Figure 1B In the diagram, the node connected to the gate of transistor M13 is denoted as node ND1. Note that a node refers to a component that enables connections between elements constituting a circuit (e.g., wiring). Therefore, a "node connected to A" refers to a wiring connected to A and which can be considered to have the same potential as A.

[0112] The semiconductor layer comprising the channel formation region of transistors M11 to M15 contains silicon. Examples of silicon used for the semiconductor layer of transistors M11 to M15 include monocrystalline silicon, polycrystalline silicon, and amorphous silicon. In particular, LTPS transistors containing low-temperature polycrystalline silicon in the semiconductor layer are preferred. By using LTPS transistors as transistors M11 to M15, transistors with high field-effect mobility and good frequency characteristics can be realized. In particular, by using an LTPS transistor as transistor M13, which is used as a driving transistor, the current flowing through the light-emitting device can be increased.

[0113] Furthermore, as for transistors M11 to M15 that use LTPS transistors, p-channel transistors are preferred. Figure 1B In the above, transistors M11 to M15 included in pixel 10 are represented as p-channel transistors. When using organic electroluminescent elements as light-emitting devices, p-channel transistors are easier to use for circuit design compared to n-channel transistors.

[0114] Furthermore, the transistors M16 and M17 included in pixel 10 are n-channel OS transistors including a back gate. Figure 1B The circuit structure is shown when transistors including a back gate are used as transistors M16 and M17.

[0115] Pixel 10 can have a circuit structure where the OS transistor is an n-channel transistor and the LTPS transistor is a p-channel transistor. Pixel 10 can also have a complementary circuit structure. As a complementary circuit structure, for example in an inverter circuit, by supplying the gates of the two transistors with the same logic potential, one can be turned on and the other turned off. In this case, by placing both the n-channel and p-channel transistors between the power lines, the current flowing between the power lines can be reduced, thereby achieving low power consumption.

[0116] OS transistors include semiconductor layers with channel formation regions such as indium gallium zinc oxide (IGZO) and other oxide semiconductors (also known as metal oxides). Alternatively, OS transistors may include semiconductor layers with channel formation regions such as indium oxide (IO) and other highly mobile oxide semiconductors with excellent crystallinity. Highly mobile oxide semiconductors with excellent crystallinity are sometimes referred to as LTPI (Low Temperature Poly-Indium oxide). Because oxide semiconductors and LTPI have band gaps of 2 eV or higher, OS transistors exhibit extremely low off-state currents. At room temperature, an OS transistor with a channel width of 1 μm can have an off-state current of 1 × 10⁻⁶. -12 Below A, 1aA (1×10 -18 A) Below, 1zA (1×10 -21 A) or below or 1yA (1×10 -24 A) The following.

[0117] By turning off transistors M16 and M17, node ND1, connected to transistors M16 and M17, becomes electrically floating, thereby maintaining the charge corresponding to the potential. The drain current of transistor M13 depends on the potential of node ND1. Furthermore, the brightness of the light-emitting device 61 depends on the magnitude of the drain current of transistor M13. Therefore, by using OS transistors as M16 and M17 connected to node ND1, potential fluctuations at node ND1 can be suppressed, thereby improving the display quality of the display device. Furthermore, by using OS transistors as M16 and M17 connected to node ND1, the potential of node ND1 can be maintained even at extremely low frame rates (e.g., below 1 fps), thereby stopping integrated circuit 40 when displaying static images and reducing power consumption.

[0118] Furthermore, even at high temperatures, the off-state current of the OS transistor hardly increases. Specifically, even in environments above room temperature but below 200°C, the off-state current hardly increases. Moreover, even at high temperatures, the on-state current of the OS transistor does not easily decrease. Furthermore, even in environments above 125°C but below 150°C, the ratio of on-state current to off-state current of the OS transistor is large, thus ensuring good switching operation. Therefore, display devices using OS transistors operate stably and reliably even in high-temperature environments.

[0119] Furthermore, the OS transistor can be disposed in a different layer than the LTPS transistor. By employing this structure, the OS transistor and LTPS transistor processes can be performed in layers, thus reducing the impact of adding hydrogen to the semiconductor layer having the channel formation region during OS transistor fabrication. Furthermore, layers including LTPS transistors and layers including OS transistors can be stacked. With the above structure, the occupied area of ​​pixel 10 can be reduced. In particular, in display devices using organic EL elements, the number of transistors used to drive the pixels is greater than that in display devices using liquid crystal elements. In this case, it is particularly preferable to dispose of the OS transistor in a different layer than the LTPS transistor to reduce the occupied area of ​​pixel 10.

[0120] Furthermore, transistors with various structures can be used as OS transistors and LTPS transistors. For example, transistors with various structures such as planar, interleaved, FIN, TRI-GATE, top-gate, bottom-gate, or dual-gate (a structure in which gates are arranged on both sides (e.g., top and bottom) of the channel forming region) can be used.

[0121] Transistors M16 and M17 can also be transistors other than OS transistors. Any n-channel transistor whose voltage rating is higher than that of an LTPS transistor used as a p-channel transistor can be used in transistors M16 and M17. For example, in an n-channel LTPS transistor, increasing the voltage rating by increasing the channel length or the thickness of the gate insulating film allows it to be used as an n-channel transistor with a higher voltage rating than an LTPS transistor used as a p-channel transistor in transistors M16 and M17.

[0122] In one embodiment of the present invention, the OS transistors included in pixel 10, specifically, have their gates and back gates arranged opposite each other in a manner that separates them by a channel forming region through a semiconductor layer. Furthermore, the control signal supplied to the gate of the OS transistor and the control signal supplied to the back gate of the OS transistor are logically identical signals. Moreover, the potential supplied to the back gate (the low-level potential of the control signal) when the OS transistor is in a turned-off state is different from the low-level potential of the control signal supplied to the gate when the OS transistor is in a turned-off state. Note that sometimes the gate included in the OS transistor is referred to as the first gate, and the back gate included in the OS transistor is referred to as the second gate.

[0123] Furthermore, in one embodiment of the invention, the potential V of the wiring INI... INI The potential VSS is lower than the wiring ELVSS, and the potential supplied to the back gate (the low level of the control signal) when the OS transistor is turned off is the potential V. INI Hereinafter, the preferred potential V INI .

[0124] Furthermore, in one embodiment of the invention, the potential V of the wiring INI... INI The potential VSS below the wiring ELVSS and the data voltage V of the wiring DL DA And when the OS transistor is turned off, the potential supplied to the back gate (the low-level potential of the control signal) is the potential V of the wiring INI. INI Hereinafter, the preferred potential V INI .

[0125] By employing the above structure, the potential of the control signal supplied to the back gate of the OS transistor can be lower than the potential of the control signal supplied to the gate of the OS transistor (low-level potential). By making the potential supplied to the back gate of the OS transistor, which is an n-channel transistor, lower than the potential supplied to the gate of the OS transistor, which is an n-channel transistor (low-level potential), the threshold voltage can be shifted in the positive direction. Therefore, even when driving with a significantly reduced frame rate, the potential fluctuation of node ND1 can be suppressed, thereby enabling a display device with excellent display quality.

[0126] Furthermore, by employing the above structure, the low-level potential of the control signal supplied to the back gate of transistors M16 and M17 can be set below the source potential of transistors M16 and M17. The source potential of transistors M16 and M17 becomes a potential based on the data voltage or the potential V of the wiring INI. INITherefore, the voltage between the back gate and source of transistors M16 and M17 can be set to below 0V. This suppresses fluctuations in the threshold voltage of transistors M16 and M17, thereby improving their long-term reliability. Consequently, the reliability of display devices including these transistors can be improved.

[0127] By adopting the above structure, the potential V of the wiring INI can be used. INI The low-level potential serves as the control signal supplied to the back gates of transistors M16 and M17. Therefore, the number of potentials required to serve as the low-level control signal supplied to the back gates of transistors M16 and M17 does not need to be increased. Furthermore, potential V... INI It can be a few volts lower than the potential VSS (for example, equivalent to the variation in the threshold voltage of the transistor). Therefore, the low-level potential supplied to the back gate of transistors M16 and M17 will not become too low. Thus, the amplitude voltage of the control signal supplied to the back gate can be suppressed from becoming too large.

[0128] Furthermore, by employing the above structure, since the semiconductor layer with the channel formation region of the OS transistor is sandwiched between the gate and the back gate, the electric field generated outside the transistor is less likely to act on the channel formation region (also known as the "electric field shielding effect"). Therefore, by providing a back gate in the transistor, the transistor can operate stably. Moreover, by providing a back gate in the transistor, the characteristic non-uniformity between multiple transistors is reduced. By providing a back gate in the transistor, the reliability of the transistor can be improved. Therefore, the reliability of the display device including this transistor can be improved.

[0129] Furthermore, by employing the above structure, a light-shielding conductive material can be used on both the gate and back gate of the OS transistor. Additionally, when light is irradiated into the channel formation region of the transistor, the transistor's electrical characteristics sometimes change. Furthermore, when light is irradiated into the channel formation region while a voltage is applied to the transistor, the transistor's electrical characteristics sometimes deteriorate. In other words, the transistor's reliability sometimes decreases. By using a light-shielding conductive material on both the gate and back gate, the degradation of the transistor's electrical characteristics can be suppressed, thereby improving reliability.

[0130] Furthermore, with the above structure, when the transistor is turned on, the potential for the control signal that controls the transistor's on state can be supplied from both the gate and the back gate. For example, compared to supplying the potential to turn the transistor on to only one of the gate and the back gate, by supplying the potential to both the gate and the back gate, the on-state current can be further increased.

[0131] For example, the transistors included in pixel 10, such as Figure 1BAs shown, the transistors are connected to the wiring. One of the source and drain of transistor M11 is connected to wiring DL. The other of the source and drain of transistor M11 is connected to one of the source and drain of transistor M12 and one of the source and drain of transistor M13. The other of the source and drain of transistor M12 is connected to wiring ELVDD. The other of the source and drain of transistor M13 is connected to one of the source and drain of transistor M14 and one of the source and drain of transistor M16. The other of the source and drain of transistor M14 is connected to one of the source and drain of transistor M15 and the first terminal of light-emitting device 61. The second terminal of light-emitting device 61 is connected to wiring ELVSS.

[0132] One of the source and drain terminals of transistor M15 is connected to wiring INI. The other of the source and drain terminals of transistor M16 is connected to the gate of transistor M13, one electrode of capacitor C1, and one of the source and drain terminals of transistor M17. The other electrode of capacitor C1 is connected to wiring ELVDD. Furthermore, the other of the source and drain terminals of transistor M17 is connected to wiring INI.

[0133] The gate of transistor M11 is connected to wiring GW. The gate of transistor M12 is connected to wiring EM. The gate of transistor M14 is connected to wiring EM. The gate of transistor M15 is connected to wiring GB. The gate of transistor M16 is connected to wiring GC. The back gate of transistor M16 is connected to wiring GC_BG. The gate of transistor M17 is connected to wiring GI. The back gate of transistor M17 is connected to wiring GI_BG.

[0134] In pixel 10, the first terminal of the light-emitting element 61 is used as the anode, and the second terminal of the light-emitting element 61 is used as the cathode. The light-emitting element 61 can be an EL element (including organic and inorganic EL elements, organic EL elements, inorganic EL elements), LED (white LED, red LED, green LED, blue LED, etc.), Micro LED, QLED (Quantum-dot Light Emitting Diode), or an electron emission element, etc.

[0135] The control signal supplied to the wiring GW controls the on or off state of the transistor M11. For example, the control signal supplied to the wiring GW controls whether the data voltage supplied to the wiring DL is written to pixel 10. For example, the transistor M11, which is a p-channel transistor, is off when the control signal supplied to the wiring GW is at level H, and is on when the control signal supplied to the wiring GW is at level L.

[0136] The control signal supplied to the wiring EM controls the on or off state of transistors M12 and M14. For example, the control signal supplied to the wiring EM controls the current path flowing between wiring ELVDD and wiring ELVSS. For example, transistors M12 and M14, which are p-channel transistors, are in the off state when the control signal supplied to the wiring EM is at level H, and in the on state when the control signal supplied to the wiring EM is at level L.

[0137] The control signal supplied to the wiring GB controls the on or off state of transistor M15. For example, the control signal supplied to the wiring GB controls whether the potential of the first terminal of the light-emitting device 61, which serves as the anode, is set to potential V. INI For example, transistor M15, which is a p-channel transistor, is in the off state when the control signal supplied to the wiring GB is at level H, and in the on state when the control signal supplied to the wiring GB is at level L.

[0138] The control signals supplied to the wiring GC and the wiring GC_BG control the on or off state of transistor M16. For example, the control signals supplied to the wiring GC and the wiring GC_BG control whether the gate potential of transistor M13 is set to the potential of the other of the source and drain of transistor M13. For example, transistor M16, as an n-channel transistor, is in the on state when both the control signals supplied to the wiring GC and the wiring GC_BG are at level H, and in the off state when both the control signals supplied to the wiring GC and the wiring GC_BG are at level L.

[0139] The control signals supplied to wiring GI and wiring GI_BG are signals that control the on or off state of transistor M17. For example, the control signals supplied to wiring GI and wiring GI_BG control whether the gate potential of transistor M13 is set to potential V. INI For example, transistor M17, which is an n-channel transistor, is turned on when both the control signal supplied to wiring GI and the control signal supplied to wiring GI_BG are at level H, and is turned off when both the control signal supplied to wiring GI and the control signal supplied to wiring GI_BG are at level L.

[0140] Figure 2This is an example of a block diagram showing the control signals output to the gate line-side drive circuits 30 and 31 of the aforementioned wiring GI, wiring GI_BG, wiring GW, wiring GB, wiring GC, and wiring GC_BG. Gate line-side drive circuit 30 is connected to wiring GW, wiring GC, and wiring GC_BG and supplies control signals to pixel 10. Figure 1A The gate line-side drive circuit 31 shown is connected to wiring GI, wiring GB, and wiring GI_BG, and supplies control signals to pixel 10. Note that, although not shown, the gate line-side drive circuit 32 supplies control signals with timings different from those of the gate line-side drive circuits 30 and 31 to wiring EM.

[0141] In the gate line-side driving circuit 30, pulse output circuits PO_1 to PO_m are set according to the number of rows of pixels 10 provided in the display unit 20, for example, m rows (m is an integer greater than or equal to 2). Similarly, in the gate line-side driving circuit 31, pulse output circuits PO_1 to PO_m are also set according to the number of rows of pixels 10. The pulse output circuits PO_1 to PO_m output control signals that change the timing of the selected pixels according to the start pulse SP1 (or SP2) and the clock signal CLK through buffers BUF1 to BUF3 to the wiring of each row (wiring GI_1 to GI_m, wiring GI_BG_1 to GI_BG_m, wiring GW_1 to GW_m, wiring GB_1 to GB_m, wiring GC_1 to GC_m, and wiring GC_BG_1 to GC_BG_m).

[0142] The control signals output by the pulse output circuits PO_1 to PO_m included in the gate line-side drive circuits 30 and 31 are supplied to each wiring through buffers BUF1, BUF2, and BUF3. For example, the control signal output from the pulse output circuit PO_1 of the gate line-side drive circuit 30 is supplied to wiring GW_1 through buffer BUF1. Furthermore, the control signal output from the pulse output circuit PO_1 of the gate line-side drive circuit 30 is supplied to wiring GC_1 through buffer BUF2. Furthermore, the control signal output from the pulse output circuit PO_1 of the gate line-side drive circuit 30 is supplied to wiring GC_BG_1 through buffer BUF3. Furthermore, the control signal output from the pulse output circuit PO_1 of the gate line-side drive circuit 31 is supplied to wiring GB_1 through buffer BUF1. Furthermore, the control signal output from the pulse output circuit PO_1 of the gate line-side drive circuit 31 is supplied to wiring GI_1 through buffer BUF2. Furthermore, the control signal output from the pulse output circuit PO_1 of the gate line-side drive circuit 31 is supplied to wiring GI_BG_1 through buffer BUF3.

[0143] Similarly, the pulse output circuits PO_2 to PO_m also output the control signal through buffers BUF1 to BUF3 to the routing of each row (routing GI_2 to GI_m, routing GI_BG_2 to GI_BG_m, routing GW_2 to GW_m, routing GB_2 to GB_m, routing GC_2 to GC_m and routing GC_BG_2 to GC_BG_m).

[0144] Here, the amplitude voltage of the control signals output from buffers BUF1 to BUF3 is explained. Figure 3A From the middle, extract what can be used Figure 2 The pulse output circuits PO_1 to PO_m and buffers BUF1 to BUF3 are described in the description. The control signal output by the pulse output circuit PO is a low-active signal (a low-level potential signal is used as the selection state signal).

[0145] Buffers BUF1 to BUF3 are transistor-containing circuits positioned between the respective wirings of the input control signal and the wirings supplying the amplitude voltage of the control signal. For ease of understanding, buffers BUF1 to BUF3 and the pulse output circuit PO are shown as separate blocks, but a portion of the pulse output circuit PO can also be used as buffers BUF1 to BUF3. Although the wirings supplying the amplitude voltage of the control signal in buffers BUF1 to BUF3 are described as wirings supplying a constant potential, they could also be clock signal lines supplying the amplitude voltage of a clock signal.

[0146] Figure 3A The buffer BUF1 outputs the control signal via wiring GW or wiring GB to the gates of transistors M11 and M15, which are p-channel transistors. Buffer BUF1 outputs a low-active signal. For example... Figure 3A As shown, buffer BUF1 is supplied with potentials VH1 and VL1, which serve as the potentials for applying voltage level H and L, respectively. Potential VL1 is the potential at which the p-channel transistor is turned on when supplied to its gate. Potential VH1 is the potential at which the p-channel transistor is turned off when supplied to its gate. Note that in the following description, terms such as potential VH1 and VL1, representing potential or voltage, are sometimes abbreviated as VH1 and VL1.

[0147] Figure 3A The buffer BUF2 outputs the control signal via wiring GI or GC to the gates of transistors M16 and M17, which are n-channel transistors. Buffer BUF2 outputs a high-active-high signal (a signal that indicates a selected state with a high-level potential). For example... Figure 3AAs shown, buffer BUF2 is supplied with VH2 and VL2, which serve as the potentials for applying the H level and the L level, respectively. Potential VH2 is the potential at which the n-channel transistor is turned on when supplied to its gate. Potential VL2 is the potential at which the n-channel transistor is turned off when supplied to its gate.

[0148] In addition, regarding the supply to Figure 1A , Figure 1B The control signal for the wiring EM described herein is output as a low active signal through the shift register and buffer included in the gate line-side drive circuit 32, with a timing different from that of the gate line-side drive circuits 30 and 31. Buffer BUF1 can be used as the buffer included in the gate line-side drive circuit 32.

[0149] Figure 3A The buffer BUF3 outputs the control signal via wiring GI_BG or wiring GC_BG to the back gate of transistors M16 and M17, which are n-channel transistors. BUF3 outputs a high-active signal, the logic of which is the same as the control signal output to wiring GI or wiring GC. For example... Figure 3A As shown, buffer BUF3 is supplied with VH2 and V... INI , respectively, serve as the potentials for applying the H level and the L level.

[0150] like Figure 3B As shown in the waveform diagram, the control signal for wiring GW or wiring GB, corresponding to the selection signal of amplitude voltage of VH1 and VL1, is P during the selection period. SEL The medium is supplied to the gate of transistor M11 or M15. Furthermore, as... Figure 3C As shown in the waveform diagram, the control signal for wiring GI or wiring GC, corresponding to the selection signal of the amplitude voltage of VH2 and VL2, is P during the selection period. SEL The current is supplied to the gate of transistor M16 or M17. Figure 3B In this context, VL1 is a potential greater than VL2. Figure 3C In this configuration, VH1 is a potential greater than VH2. Using this structure, the amplitude voltage Am1 of the control signal for wiring GW or wiring GB is equal to the amplitude voltage Am2 of the control signal for wiring GI or wiring GC. By making the H and L levels supplied to buffer BUF1 different from the H and L levels supplied to buffer BUF2, the amplitude voltage can be reduced compared to the case where buffers BUF1 and BUF2 are supplied with a common potential.

[0151] like Figure 3D As shown in the waveform diagram, the control signals for routing GI_BG or GC_BG correspond to VH2 and V. INIThe amplitude voltage selection signal during the selection period P SEL It is supplied to the back gate of transistor M16 or M17. Figure 3D In this context, VH1 is a potential greater than VH2. By setting the H-level potential supplied to buffer BUF3 to the same potential as the H-level potential supplied to buffer BUF2, a common potential can be supplied to buffers BUF2 and BUF3, and the amplitude voltage Am3 can be reduced compared to the case where VH1 is supplied as an H-level potential.

[0152] like Figure 3D As shown, the low-level potential V of the control signal supplied to the back gate of transistor M16 or M17 INI The threshold voltage is lower than the low-level potential VL2 of the control signals supplied to the gates of transistors M16 and M17. Therefore, by making the potential supplied to the back gate lower than the potential supplied to the gate, the threshold voltage can be shifted in the positive direction. Thus, even when driving with a significantly reduced frame rate, the potential fluctuation of node ND1 can be suppressed, thereby enabling a highly reliable display device.

[0153] like Figure 3D As shown, the low-level potential V of the control signal supplied to the back gate of transistor M16 or M17 INI Less than the data voltage V DA V represents the maximum gray level. DA_H and V represents the smallest gray level DA_L By employing this structure, the voltage between the back gate and source of transistors M16 and M17 can be set below 0V. Therefore, fluctuations in the threshold voltage of transistors M16 and M17 can be suppressed, thereby improving the long-term reliability of the transistors. Consequently, the reliability of display devices including these transistors can be improved.

[0154] like Figure 3D As shown, the low-level potential V of the control signal supplied to the back gate of transistor M16 or M17 INI VSS is lower than the wiring ELVSS. By making VSS higher than V... INI The potential of the gate of transistor M13, which acts as the driving transistor, can be set to V. INI This ensures more reliable current flow through the drive transistor during initialization. Furthermore, the source potentials of M16 and M17 can be set to the potential of node ND1.

[0155] Furthermore, the amplitude voltage of the control signals output from buffers BUF1 to BUF3 can also be determined using the same method as... Figures 3A to 3D Different structures. In Figures 4A to 4D In the middle, explanation and Figures 3A to 3D Different structures. In Figures 4A to 4D In the explanation, regarding the relationship with Figures 3A to 3D Repeated descriptions of identical parts are omitted.

[0156] right Figure 4A The buffer BUF1 is supplied with VH and VL, which serve as the potentials for applying voltage H and voltage L, respectively. Furthermore, for... Figure 4A The buffer BUF2 is supplied with VH and VL, which serve as the potentials for applying a voltage level H and a voltage level L, respectively. VL is the potential at which the transistor is turned on when supplied to the gate of a p-channel transistor and turned off when supplied to the gate of an n-channel transistor. VH is the potential at which the transistor is turned off when supplied to the gate of a p-channel transistor and turned on when supplied to the gate of an n-channel transistor.

[0157] like Figure 4B and Figure 4C As shown in the waveform diagram, the control signals for wiring GW or wiring GB and wiring GI or wiring GC are supplied between buffers BUF1 and BUF2 at common voltages VH and VL, thus obtaining the same amplitude voltage Am3. By adopting a structure that supplies a common potential to buffers BUF1 and BUF2, the number of potentials required by the gate line-side drive circuits 30 and 31 can be reduced.

[0158] right Figure 4A The buffer BUF3 supplies VH and V INI , respectively, serve as the potentials for applying the H level and the L level.

[0159] like Figure 4D As shown in the waveform diagram, the control signals for routing GI_BG or GC_BG correspond to VH and V. INI The amplitude voltage selection signal during the selection period P SEL It is supplied to the back gate of transistor M16 or M17. Figure 4D In the middle, V INI The voltage is greater than VL. Therefore, the amplitude voltage Am4 of the control signal output from buffer BUF3 can be made smaller than the amplitude voltage Am3 of the control signals supplied from buffers BUF1 and BUF2. This allows for low power consumption. Furthermore, the transistor M16 or M17, which supplies the control signal output from buffer BUF2, is supplied with a voltage lower than VL. INI The VL value can cause the threshold voltage to drift in the positive direction. Therefore, even when driving with a significantly reduced frame rate, the potential variation of node ND1 can be suppressed, thereby enabling a display device with excellent display quality.

[0160] like Figure 4D As shown, the low-level potential V of the control signal supplied to the back gate of transistor M16 or M17INI Less than the data voltage V DA V represents the maximum gray level. DA_H and V represents the smallest gray level DA_L By employing this structure, the voltage between the back gate and source of transistors M16 and M17 can be set below 0V. Therefore, fluctuations in the threshold voltage of transistors M16 and M17 can be suppressed, thereby improving the long-term reliability of the transistors. Consequently, the reliability of display devices including these transistors can be improved.

[0161] like Figure 4D As shown, the low-level potential V of the control signal supplied to the back gate of transistor M16 or M17 INI VSS is lower than the wiring ELVSS. By making VSS higher than V... INI The potential of the gate of transistor M13, which acts as the driving transistor, can be set to V. INI This ensures more reliable current flow through the drive transistor during initialization. Furthermore, the source potentials of M16 and M17 can be set to the potential of node ND1.

[0162] As described above, the low-level potential of the control signal supplied to the back gate can be achieved using the V of the wiring INI. INI Therefore, as Figure 5 As shown, the wiring INI connected to pixel 10 can be used as a wiring connection to supply the low-level potential of buffer BUF3. As a result, the number of potentials required as low-level potentials for the control signals supplied to buffer BUF3 does not need to be increased. Furthermore, V INI It can be a potential several V lower than VSS. Therefore, the low-level potential supplied to the back gate will not become too low. Thus, the amplitude voltage of the control signal supplied to the back gate can be suppressed from becoming too large.

[0163] <Example 1 of a display device in operation>

[0164] Next, an example of the operation of the pixel 10 of a display device 100 that can be used in one aspect of the present invention will be described. Figure 6 This is a timing diagram illustrating a working example of pixel 10. Figure 6 The waveforms of the control signals supplied to wiring GI, wiring GI_BG, wiring GB, wiring GW, wiring GC, wiring GC_BG, and wiring EM connected to pixel 10 are shown, along with the potential changes at node ND1. Furthermore, in Figures 7A to 11B In the middle, side by side Figure 6 The diagram shown is a schematic and timing diagram illustrating the operation of pixel 10 during periods T11 to T15. Note that in Figures 7A to 11BIn the schematic diagram of pixel 10's operation, the circuit symbol for the transistor in the off state is crossed out. Furthermore, a thick dashed arrow indicates the current flowing through the transistor when it is in the on state.

[0165] Note that, for ease of understanding, the potentials of the control signals supplied to wiring GI, wiring GI_BG, wiring GB, wiring GW, wiring GC, wiring GC_BG, and wiring EM, respectively, and the potentials of the wiring supplied with constant potentials, can be represented as follows: Figures 3A to 3D The structure is illustrated below. For example, the diagram shows: amplitude voltages VH1 and VL1 are applied to the gate of a p-channel transistor, amplitude voltages VH2 and VL2 are applied to the gate of an n-channel transistor, and amplitude voltages VH2 and VL2 are applied to the back gate of the n-channel transistor. INI The amplitude voltage. Furthermore, in Figure 6 The timing diagram shown can also be used Figures 4A to 4D The amplitude voltage control signal is described in the text.

[0166] Note that, in the initial state, routing GI and GC are supplied with VL2, routing EM with VL1, and routing GB and GW with VH1. Therefore, transistors M11, M15, M16, and M17 are in the off state, and transistors M12 and M14 are in the on state. Furthermore, the potential of node ND1 is the data voltage V. DA +Vth, transistor M13 is in the ON state. Note that, due to Figure 1B The transistor M13 of pixel 10 shown is a p-channel transistor, so the Vth of transistor M13 is negative (lower than the reference voltage). Therefore, the data voltage V DA +Vth is below the data voltage V. DA The potential.

[0167] [Date T11]

[0168] During T11, wiring GI is supplied to VH2, wiring GI_BG is supplied to VH2, and wiring GB is supplied to VL1 (see reference). Figure 7A and Figure 7B When routing GI and routing GI_BG are supplied with VH2, transistor M17 becomes active, and node ND1 is supplied with VH2 for routing INI. INI .

[0169] Furthermore, when wiring GB is supplied with VL1, transistor M15 becomes active. Therefore, the path of the current flowing through the channel forming regions of each of transistors M11, M13, and M14 up to this point changes. Specifically, the current no longer flows through the light-emitting device 61, but instead flows through the channel forming region of transistor M15 to wiring INI. Consequently, the light emission from the light-emitting device 61 stops.

[0170] Furthermore, during period T11, VH2 can also be supplied to the wiring EM. By supplying VH2 to the wiring EM, transistors M12 and M14 become off. Therefore, the current flowing from wiring ELVDD through wiring INI is blocked, and power consumption is reduced. Moreover, since it becomes the same state as the subsequent period T12, period T12 can be omitted. Therefore, the operating speed of the display device including pixel 10 can be increased.

[0171] [Date T12]

[0172] During T12, the cabling EM is supplied to VH2 (see reference). Figure 8A and Figure 8B When wiring EM is supplied with VH2, transistors M12 and M14 are in the off state. Furthermore, transistor M15 is in the on state, so the first terminal of the light-emitting device 61 is supplied with VH2 from wiring INI. INI .

[0173] [Date T13]

[0174] During T13, wiring GI is supplied to VL2, and wiring GI_BG is supplied to V. INI Wiring GB is supplied by VH1 (refer to) Figure 9A and Figure 9B Therefore, transistors M17 and M15 are turned off. Furthermore, wiring GW is supplied with VL1, wiring GC is supplied with VH2, and wiring GC_BG is supplied with VH2.

[0175] Note that it is preferable to supply VL2 to wiring GI and VH1 to wiring GB, then supply VL1 to wiring GW, VH2 to wiring GC, and VH2 to wiring GC_BG. This prevents wiring DL and wiring INI from becoming conductive, thereby reducing the power consumption of the display device 100 including pixel 10.

[0176] When wiring GW is supplied with VL1, transistor M11 becomes on, and the data voltage V... DA The data is supplied from routing DL to node ND1. Additionally, when routing GC and GC_BG are supplied to VH2, transistor M16 becomes on. Because transistor M13 is also on, the data voltage V...DA It begins to be supplied to node ND1. As a result, the potential of node ND1 rises.

[0177] The potential of node ND1 continues to rise until it becomes the data voltage V at time t13a. DA Up to +Vth (refer to) Figure 6 When the potential of node ND1 becomes the data voltage V. DA When +Vth, transistor M13 becomes off, and the potential rise of node ND1 ends.

[0178] To shorten the time required for the potential of node ND1 in period T13 to rise, it is preferable to use a transistor with a large on-state current as transistor M16. This shortens the time required for transistor M13 to become off, thereby increasing the operating speed.

[0179] By increasing the operating speed, the period T13 for initializing the gate potential of transistor M13 can be performed multiple times. By performing multiple periods T13, the potential held at node ND1 is initialized multiple times, thus suppressing the hysteresis effect of changes in the electrical characteristics of transistor M13 based on the state of the potential held at node ND1. Since the hysteresis effect of transistor M13 is significant when a p-channel Si transistor is used, performing multiple periods T13 allows for the realization of a display device with superior display quality.

[0180] In one embodiment of the invention, indium oxide can be used as the semiconductor layer having the channel formation region for transistors M16 and M17, for example, as transistors with large on-state currents. Note that details regarding transistors containing indium oxide will be described later in Embodiment 3.

[0181] [Date T14]

[0182] During period T14, cabling GW is supplied with VH1, cabling GC is supplied with VL2, and cabling GC_BG is supplied with V. INI (Reference Figure 10A and Figure 10B When wiring GW is supplied with VH1, transistor M11 becomes off. Furthermore, when wiring GC is supplied with VL2 and wiring GC_BG is supplied with V... INI When this occurs, transistor M16 is turned off, and the potential of node ND1 is maintained (ND1 = V). DA +Vth). Thus, node ND1 maintains a connection to the data voltage V. DA Add the potential Vth of transistor M13. Note that when transistor M13, used as the driving transistor, is a p-channel transistor, the data voltage V... DA+Vth is a potential below Vth.

[0183] [Date T15]

[0184] During period T15, cabling EM is supplied to VL1 (refer to...). Figure 11A and Figure 11B When wiring EM is supplied with VL1, transistors M12 and M14 become active. Here, the data voltage maintained in node ND1 (ND1 = V) is... DA +Vth) is a potential below Vth, and VDD of the wiring ELVDD is a potential above the data voltage V. DA The +Vth potential is used to turn on transistor M13. Current then flows from wiring ELVDD through transistors M12, M13, M14 and light-emitting device 61 to wiring ELVSS. Furthermore, the current flowing from wiring ELVDD to wiring ELVSS depends on the potential of node ND1. Node ND1 of pixel 10 is maintained at a data voltage Vth corrected by transistor M13, which serves as the driving transistor. DA This allows the corresponding data voltage V to be... DA The accurate current value flows through the light-emitting device 61.

[0185] As shown in the above example, each pixel in the display device according to one aspect of the present invention can undergo Vth correction (also referred to as "internal correction") of the driving transistor. Therefore, the display device according to one aspect of the present invention can correct Vth non-uniformity of the driving transistors between pixels. Furthermore, the effects of hysteresis in the driving transistors can be suppressed. By using the display device according to one aspect of the present invention, the display quality of the display unit can be improved.

[0186] Furthermore, in pixel 10, data voltage V is simultaneously processed. DA The holding and driving transistor's Vth correction. Therefore, the driving transistor's Vth correction and the data voltage V are respectively performed. DA Compared to the number of pixels that can be preserved, it can operate at high speed.

[0187] In order to maintain the data voltage held by node ND1 during T15, it is preferable to use transistors with low off-state current for both transistors M16 and M17. This results in a stable luminous intensity.

[0188] In one embodiment of the invention, indium oxide can be used as the semiconductor layer having the channel formation region for transistors M16 and M17, for example, as transistors with extremely low off-state current. Note that details regarding transistors containing indium oxide will be described later in Embodiment 3.

[0189] <Example of pixel structure>

[0190] Next, an example of the structure of the pixels 10 included in a display device 100 that can be used in one aspect of the present invention will be described. Note that, as will be explained later... Figure 12A and Figure 19B In the description, sometimes the terms "and" are omitted. Figures 1A to 11B Repeated descriptions of the same parts.

[0191] Figure 1B Transistors M11, M12, M14, and M15 are used as switches. Therefore, as... Figure 12A As shown in pixel 10A, Figure 1B Pixel 10 can replace transistors M11, M12, M14, and M15 with switches SW11, SW12, SW14, and SW15, respectively. Figure 12A In a transistor, one of the source and drain terminals corresponds to the first terminal of a switch, and the other of the source and drain terminals corresponds to the second terminal of a switch.

[0192] Mechanical switches can also be used as switches SW11, SW12, SW14, and SW15. As an example of a mechanical switch, there is a switch utilizing MEMS (Micro-Electro-Mechanical Systems) technology. This switch has mechanically movable electrodes, and these electrodes actuate to select an on or off state.

[0193] Can Figure 12A In pixel 10A, each switch is replaced with a transistor. The transistor used as a switch is not limited to a p-channel transistor; an n-channel transistor can also be used. The field-effect mobility of an n-channel transistor is higher than that of a p-channel transistor, thus improving the operating speed of the display device including this pixel. For example, as... Figure 12B As shown in pixel 10B, in Figure 1B In pixel 10, transistor M15, described as a p-channel transistor, can be an n-channel transistor.

[0194] The on / off state of transistor M15 of pixel 10B can be controlled with the same timing as transistor M16. Therefore, transistor M15 can be an n-channel transistor with a gate and a back gate, the gate being connected to wiring GC and the back gate being connected to wiring GC_BG. By adopting this structure, wiring GB used to control the on / off state of transistor M15 can be omitted. As a result, the number of wirings connected to pixel 10B can be reduced, thereby improving one or both of the resolution and sharpness of the display device 100 using pixel 10B in the display unit 20.

[0195] In addition, for example, such as Figure 13A As shown in pixel 10C, in Figure 1B In pixel 10, transistor M11, which is described as a p-channel transistor, can be an n-channel transistor.

[0196] The on / off state of transistor M11 of pixel 10C can be controlled with the same timing as transistor M16. Therefore, transistor M11 can be an n-channel transistor with a gate and a back gate, the gate being connected to wiring GC and the back gate being connected to wiring GC_BG. By adopting this structure, wiring GW used to control the on / off state of transistor M11 can be omitted. As a result, the number of wirings connected to pixel 10C can be reduced, thereby improving one or both of the resolution and sharpness of the display device 100 using pixel 10C in the display unit 20.

[0197] Note that the structural example of pixel 10C can be combined with the structural example of pixel 10B described above. For example, as Figure 13B As shown in the pixel diagram of the 10D, in Figure 1B In pixel 10, transistors M11 and M15, described as p-channel transistors, can be n-channel transistors. By adopting this structure, the wiring GW for controlling the on / off state of transistor M11 and the wiring GB for controlling the on / off state of transistor M15 can be omitted. As a result, the number of wirings connected to pixel 10D can be reduced, thereby further improving one or both of the resolution and sharpness of the display device 100 using pixel 10D in the display unit 20.

[0198] Note that in Figures 12B to 13B In the example, a structure is shown where the transistor used as a switch is replaced with an n-channel transistor, including a structure with a gate and a back gate, but this is not a limitation. For example, such as Figure 14A As shown in pixel 10E, transistor M15 can be an n-channel transistor with a gate, which can be connected to wiring GC. This is because the electrical characteristic variations of transistor M15 do not significantly affect display quality as much as other n-channel transistors M16 and M17. By adopting this structure, wiring GB and the back gate of transistor M15, which control the on or off state of transistor M15, can be omitted. As a result, one or both of the resolution and sharpness of the display device 100 using pixel 10E in the display unit 20 can be improved. Note that the structure of transistor M15 in pixel 10E can also be used for transistor M11 in pixel 10C described above.

[0199] In addition, although Figures 12B to 13BThe diagram illustrates a structure in which the transistor used as a switch is replaced with an n-channel transistor, having a gate and a back gate, and different control signals are supplied to the gate and the back gate respectively, but it is not limited to this. For example, as... Figure 14B As shown in pixel 10F, both the gate and back gate of transistor M15 can be connected to wiring GC. By employing this structure, wiring GB, used to control the on or off state of transistor M15, can be omitted. As a result, one or both of the resolution and sharpness of the display device 100 using pixel 10F in the display unit 20 can be improved. Note that the structure of transistor M15 in pixel 10F can also be used for transistor M11 in pixel 10C as described above.

[0200] As Figure 1B The transistor described in pixel 10 can be a single-gate transistor with a gate between the source and drain. Alternatively, a dual-gate transistor can also be used. Figure 15 As shown in pixel 10G, a structure using the circuit symbol for a dual-gate transistor as in transistors M16 and M17 can be employed. Because a dual-gate transistor comprises multiple transistors connected in series, the insulation withstand voltage between the terminals used as the source or drain is high. Therefore, reliability is high. Furthermore, Figure 15 The dual-gate transistor shown can also be a triple-gate transistor. The insulation breakdown voltage between the terminals used as the source or drain in a triple-gate transistor is higher than that in a dual-gate transistor. Therefore, it has higher reliability.

[0201] also, Figure 15 The dual-gate transistor shown can also have a structure with more than four transistors connected in series. Note that, although Figure 15 An example of using a dual-gate structure for an n-channel transistor is shown, but a dual-gate structure can also be used for a p-channel transistor.

[0202] The aforementioned multi-gate transistors, including dual-gate or triple-gate types, are equivalent to transistors with long channel lengths. Therefore, compared to single-gate transistors, multi-gate transistors can reduce leakage current when in the off state. Thus, using multi-gate transistors is effective in improving the display quality of the display device 100.

[0203] Figure 1B The wiring INI described in pixel 10 can also be wiring that is not shared between transistors M15 and M17. For example, as Figure 16 As shown in pixel 10H, wiring INI_S and wiring INI can be set as wiring connected to transistor M15 and wiring connected to transistor M17, respectively.

[0204] By setting the routing INI and routing INI_S separately, the routing INI can be set to V.INI Set the routing INI_S to be the same as V INI A different potential. For example, the wiring INI_S can be set to a potential higher than VSS than the threshold voltage of the light-emitting device 61 (the voltage at which current begins to flow through the light-emitting device 61), thereby initializing the potential of the first terminal of the light-emitting device 61, which serves as the anode.

[0205] Furthermore, by setting two separate wiring INIs, wiring with different functions can be used; for example, one wiring can be used as a signal line, and the other as a line supplying a constant potential. The additional wiring INI_S can be used as a monitoring line that allows current to flow between the pixel 10H and the outside.

[0206] For example, when correcting the non-uniformity of the field-effect mobility and other electrical characteristics of transistor M13 included in pixel 10H among pixels, transistors M12, M13, M14, and M15 are turned on, while other transistors are turned off. The potential of wiring ELVSS is set to VDD (ELVSS=VDD), and the potential of wiring INI_S is set to VSS (INI_S=VSS) (see reference). Figure 17A ).like Figure 17A As shown, the current flowing through transistor M13 can flow through wiring INI_S. Using this structure, the current flowing through transistor M13 can be measured outside of pixel 10H. Based on the relationship between the potential of node ND1 and the current flowing through wiring INI_S at this time, the field-effect mobility isoelectric characteristics of transistor M13 can be obtained.

[0207] In addition, such as Figure 3B and Figure 4B As described above, in one embodiment of the invention, the VSS of the routing ELVSS is higher than the VSS of the routing INI_S. INI Therefore, the current flowing through transistor M13 can flow through wiring INI_S without switching the potential of wiring ELVSS to VDD. By adopting this structure, it is not necessary to switch the potential of wiring ELVSS to VDD, thereby achieving low power consumption.

[0208] Furthermore, for example, when the electrical characteristics of the light-emitting device 61 included in the correction pixel 10H are uneven among pixels, transistors other than transistor M15 are turned off, the potential of wiring ELVSS is set to VSS (ELVSS=VSS), and the potential of wiring INI_S is set to VDD (INI_S=VDD) (see reference). Figure 17B ).like Figure 17BAs shown, current can flow from the wiring INI_S through the light-emitting device 61. By employing this structure, the current flowing through the light-emitting device 61 can be measured outside the pixel 10H. Furthermore, since changes in the characteristics of the light-emitting device can be monitored, the characteristics of the light-emitting device can also be corrected.

[0209] For example, by converting the current obtained using wiring INI_S as a monitoring line into an analog voltage or a digital signal, it can be output to an external device. This external device can then use the analog voltage or the digital signal to generate a data voltage V. DA Correction (also known as external correction), etc.

[0210] By performing both internal and external calibrations, the display quality of the display device can be further improved. Note that internal calibration is preferably performed each time the image is rewritten. On the other hand, external calibration takes longer to process than internal calibration, so it is unnecessary to perform external calibration every time the image is rewritten. For example, external calibration can be performed only during a predetermined period.

[0211] exist Figure 3A and Figure 4A In the process, the potential supplied to the back gate (the low-level potential of the control signal) when the OS transistor is turned off is set to V. INI However, other structures can also be used. For example, the VSS of the ELVSS wiring can be used as the potential supplied to the back gate (the low-level potential of the control signal) when the OS transistor is turned off (see reference). Figure 18A ).

[0212] In this case, make the V of the wiring INI INI VSS higher than the wiring ELVSS (reference) Figure 18B In addition, V INI The voltage (potential difference) between VSS and the threshold voltage (V) of the light-emitting device 61 is set below the threshold voltage (the voltage at which current begins to flow through the light-emitting device 61). By employing this structure, it is possible to prevent the voltage difference between VSS and VSS from falling below VSS. INI Current flows through the light-emitting device 61.

[0213] In addition, Figure 3A and Figure 4A The diagram illustrates that the logic for the control signal supplied to the back gate when the OS transistor is turned off is the same as the structure for the control signal supplied to the gate of the OS transistor, but other structures can also be used. Alternatively, a V-shaped wiring INI can be supplied to the back gate of the OS transistor. INI The structure.

[0214] For example, in Figure 19A In the pixel 10I shown, Figure 1BIn pixel 10, the back gates of transistors M16 and M17 are connected to wiring INI. The V of wiring INI... INI Preferably, the VSS and data voltage V of the wiring DL are lower than the wiring ELVSS. DA With the help of this structure, although V is applied to the back gate even when it is in the ON state... INI However, the potential supplied to the back gate of the OS transistor can be set below the source potential of transistors M16 and M17. The source potentials of transistors M16 and M17 are based on the data voltage or the V of the wiring INI. INI Therefore, the voltage between the back gate and source of transistors M16 and M17 can be set to below 0V. This suppresses fluctuations in the threshold voltage of transistors M16 and M17, thereby improving the long-term reliability of the transistors. Consequently, the reliability of display devices including these transistors can be improved.

[0215] Note that when the structure of pixel 10I is used Figure 1A When the display device 100 is shown, the wiring GI_BG and GC_BG used to supply control signals to the back gate of the OS transistor can be omitted. Figure 19B The structure of the display device 100I with wiring GI_BG and GC_BG omitted is shown. Figure 19B As shown, by using pixel 10I for sub-pixels 10_R, 10_G, and 10_B included in pixel 11, the number of wirings in the display unit 20 can be reduced, thereby improving one or both of the resolution and clarity of the display device 100I.

[0216] <Example 2 of display device structure>

[0217] Next, a structural example different from the above-described display device will be described. Note that this will be explained later. Figures 20A to 29B In the description, sometimes the terms "and" are omitted. Figures 1A to 19B Repeated descriptions of the same parts.

[0218] Figure 20A This is a block diagram illustrating one aspect of the present invention: a display device. Figure 20A The display device 100A shown includes, for example, a display unit 20, a gate line-side driving circuit 33, a gate line-side driving circuit 32, and an integrated circuit 40.

[0219] Pixel 11 is connected to wiring GN_k-1, wiring GNBG_k-1, wiring GP_k-1, wiring EM_k, wiring GN_k, wiring GNBG_k, wiring GP_k, wiring DLR, wiring DLG, and wiring DLB. Wiring DLR, wiring DLG, and wiring DLB are used as data lines.

[0220] Routing GN_k, routing GNBG_k, routing GP_k, and routing EM_k are used as gate lines in the k-th row (k is an integer). Routing GN_k-1, routing GNBG_k-1, and routing GP_k-1 are used as gate lines in the (k-1)-th row. Therefore, in Figure 20A In the pixel 11, the pixel 11 in the k-th row is connected to the gate line of the k-th row and also connected to the gate line of the (k-1)-th row. The gate lines of the k-th row and the (k-1)-th row are respectively supplied with control signals from the gate line-side driving circuit 33 to change the timing of the selected pixel. Therefore, Figure 20A The display device can reduce the number of gate lines in the display section and the number of gate line-side driving circuits.

[0221] Figure 20B An example of a circuit diagram is shown for a sub-pixel (hereinafter referred to as pixel 10J) that can be used in the display device 100A described above, specifically for sub-pixels 10_R, 10_G, and 10_B. Figure 1B Similarly, pixel 10J, as described in the text, includes transistors M11 to M17, capacitor C1, and light-emitting device 61. Figure 20B The transistors in pixel 10J shown are connected to wiring GN_k-1, wiring GNBG_k-1, wiring GP_k-1, wiring EM_k, wiring GN_k, wiring GNBG_k, wiring GP_k, wiring DL, wiring ELVDD, wiring ELVSS and wiring INI.

[0222] In one embodiment of the invention, with Figure 1B Similar to pixel 10 described above, pixel 10J has the following features: the gates and back gates of transistors M16 and M17 are configured with channels formed across a semiconductor layer, etc. Therefore, with Figure 1B Similarly, the 10 pixels described herein can also enable a display device with excellent reliability.

[0223] The source and drain of each transistor included in pixel 10J and Figure 1B The same applies to pixel 10 as described in the text. Specifically, as... Figure 20B As shown, transistors M11 to M17 are connected. The capacitor C1 and the terminals in the light-emitting device 61 included in pixel 10J are connected to... Figure 1B The same applies to pixel 10 as described in the text. Specifically, as... Figure 20B As shown, capacitor C1 is connected to light-emitting device 61.

[0224] Pixel 10J includes transistor M11, whose gate is connected to wiring GP_k. Furthermore, transistor M12's gate is connected to wiring EM_k. Furthermore, transistor M14's gate is connected to wiring EM_k. Furthermore, transistor M15's gate is connected to wiring GP_k-1. Furthermore, transistor M16's gate is connected to wiring GN_k. Furthermore, transistor M16's back gate is connected to wiring GNBG_k. Furthermore, transistor M17's gate is connected to wiring GN_k-1. Furthermore, transistor M17's back gate is connected to wiring GNBG_k-1.

[0225] The control signal supplied to the routing GP_k in row k is a signal that controls the on or off state of transistor M11. For example, the control signal supplied to routing GP_k controls whether the data voltage supplied to routing DL is written to pixel 10. For example, transistor M11, which is a p-channel transistor, is off when the control signal supplied to routing GP_k is at level H, and is on when the control signal supplied to routing GW is at level L.

[0226] The control signal supplied to the wiring GP_k-1 in row k-1 is a signal that controls the on or off state of transistor M15. For example, by supplying the control signal to wiring GP_k-1, it controls whether the potential of the first terminal of the light-emitting device 61, which serves as the anode, is set to V. INI For example, transistor M15, which is a p-channel transistor, is in the off state when the control signal supplied to wiring GP_k-1 is at level H, and in the on state when the control signal supplied to wiring GB is at level L.

[0227] The control signal supplied to the wiring EM_k in row k is a signal that controls the on or off state of transistors M12 and M14. For example, the control signal supplied to the wiring EM controls the current path flowing between wiring ELVDD and wiring ELVSS. For example, transistors M12 and M14, which are p-channel transistors, are in the off state when the control signal supplied to the wiring EM is at level H, and in the on state when the control signal supplied to the wiring EM is at level L.

[0228] The control signals supplied to the wiring GN_k and GNBG_k in row k are signals that control the on or off state of transistor M16. For example, by controlling the control signals supplied to wiring GN_k and GNBG_k, it controls whether the gate potential of transistor M13 is set to the potential of the other of the source and drain of transistor M13. For example, transistor M16, as an n-channel transistor, is in the on state when both the control signals supplied to wiring GN_k and GNBG_k are at level H, and in the off state when both the control signals supplied to wiring GN_k and GNBG_k are at level L.

[0229] The control signals supplied to the (k-1)th row wiring GN_k-1 and GNBG_k-1 are signals that control the on or off state of transistor M17. For example, by supplying the control signals to wiring GN_k-1 and GNBG_K-1, the potential of the gate of transistor M13 can be controlled to be set to V. INI For example, transistor M17, which is an n-channel transistor, is turned on when both the control signals supplied to wiring GN_k-1 and wiring GNBG_k-1 are at level H, and is turned off when both the control signals supplied to wiring GN_k-1 and wiring GNBG_k-1 are at level L.

[0230] Figure 21 The diagram shows the wiring GN (GN_k-2 to GN_k), wiring GNBG (GNBG_k-2 to GNBG_k), wiring GP (GP_k-2 to GP_k), and wiring EM (EM_k-1 and EM_k) when pixel 10J is used as pixel 10J in row k-1 and pixel 10J_k is used as pixel 10J in row k.

[0231] like Figure 21 As shown, the wiring GP_k-1, GN_k-1, and GNBG_k-1 configured between pixel 10J and pixel 10J_k-1 are connected to the transistors on both sides of pixel 10J and pixel 10J_k-1. Therefore, with Figure 1B Compared to the structure of pixel 10 described in the diagram, the number of wirings can be reduced.

[0232] also, Figure 22shows the wiring GN (GN_k-2 to GN_k), wiring GNBG (GNBG_k-2 to GNBG_k), wiring GP (GP_k-2 to GP_k), wiring EM (EM_k-1 and EM_k), and the gate line side drive circuit 33 that outputs control signals to the wirings GN, GNBG, and GP, when the pixel 10J disposed in the (k-1)th row uses the pixel 10J_k-1 and the pixel 10J disposed in the k-th row uses the pixel 10J_k.

[0233] Note that as Figure 22 the gate line side drive circuit 33 in, there is shown a circuit diagram when a structural example of shift registers and buffers that output control signals to the wirings GN, GNBG, and GP of the (k-1)th and k-th rows adopts the structure described in Figure 3A . Figure 22 The gate line side drive circuit 33 in may also adopt the structure described in Figure 4A . In Figure 22 , there are shown the pulse output circuit PO_k-1 disposed in the (k-1)th row, the pulse output circuit PO_k disposed in the k-th row, and the buffers BUF1 to BUF3 disposed in each row.

[0234] Figure 22 The buffer BUF1 in outputs control signals with different timings to the gates of the transistors M11 and M15 which are p-channel transistors through the wiring GP_k and the wiring GP_k-1. As shown in Figure 22 , the potential VH1 and the potential VL1 (<VH1) are supplied to the buffer BUF1 as the potential for applying the H level and the potential for applying the L level, respectively.

[0235] Figure 22 The buffer BUF2 in outputs control signals with different timings to the gates of the transistors M16 and M17 which are n-channel transistors through the wiring GN_k and the wiring GC_k-1. As shown in Figure 22 , the potential VH2 and the potential VL2 (<VH2) are supplied to the buffer BUF2 as the potential for applying the H level and the potential for applying the L level, respectively.

[0236] Figure 22 The buffer BUF3 in outputs control signals with different timings to the back gates of the transistors M16 and M17 which are n-channel transistors through the wiring GNBG_k and the wiring GNBG_k-1. As shown in Figure 22 , the potential VH2 and the potential V

[0238] (<VH2) are supplied to the buffer BUF3 as the potential for applying the H level and the potential for applying the L level, respectively.

[0237] Note that Figure 22The supply of V to buffer BUF3 is shown. INI The wiring can be the wiring INI connected to pixel 10J. Figure 23 The wiring INI connecting pixels 10J_k-1 and 10J_k is shown as V supplying buffer BUF3. INI An example of the wiring structure. By adopting this structure, the number of potentials required to supply the low-level potential to buffer BUF3 can be increased without increasing the number of potentials needed. Furthermore, Figure 3B The V described in the text INI It can be a potential several volts lower than VSS. Therefore, the low-level potential supplied to the back gate of the OS transistors included in pixels 10J_k-1 and 10J_k will not become too low. Therefore, the amplitude voltage of the control signal supplied to the back gate can be suppressed from becoming too large.

[0238] As Figure 20B The pixel 10J described in the text and Figures 21 to 23 The pixels 10J_k-1 and 10J_k shown can be appropriately combined. Figure 12A and Figure 19B Examples of pixel deformation are illustrated below. For example, such as... Figure 15 As described in the 10G section, dual-gate transistors can be used as transistors M16 and M17. By adopting this structure, since multiple transistors are connected in series, the insulation withstand voltage between the terminals used as source or drain can be improved, thereby improving the reliability of the display device.

[0239] <Example 2 of a display device in operation>

[0240] Next, an example of the operation of the pixel 10J of the display device 100A, which can be used in one aspect of the present invention, will be described. Figure 24 This is a timing diagram illustrating a working example of pixel 10J. Figure 24 The waveforms of the control signals supplied to wirings GN_k-1, GNBG_k-1, GP_k-1, EM_k, GN_k, GNBG_k, and GP_k connected to pixel 10J are shown, along with the potential changes at node ND1. Furthermore, in Figures 25A to 29B In the middle, side by side Figure 24 The diagram shown is a schematic and timing diagram illustrating the operation of pixel 10J during periods T21 to T25. Note the following explanation... Figure 25A and Figure 29B In the explanation, sometimes the above-mentioned Figures 7A to 11B The description of the working example is a repetition of the same part.

[0241] Note that, for ease of understanding, the potentials of the control signals supplied to wiring GN_k-1, wiring GNBG_k-1, wiring GP_k-1, wiring EM_k, wiring GN_k, wiring GNBG_k, and wiring GP_k, respectively, and the potentials of the wiring supplied with constant potentials, can be represented as follows: Figure 3A and Figure 3B The structure is illustrated below. For example, the diagram shows: amplitude voltages VH1 and VL1 are applied to the gate of a p-channel transistor, amplitude voltages VH2 and VL2 are applied to the gate of an n-channel transistor, and amplitude voltages VH2 and VL2 are applied to the back gate of the n-channel transistor. INI The amplitude voltage. Furthermore, in Figure 24 The timing diagram shown can also be used Figure 4A and Figure 4B The amplitude voltage control signal is described in the text.

[0242] Note that, as an initial state, wiring GN_k and GN_k-1 are supplied with VL2, wiring EM_k is supplied with VL1, and wiring GP_k and GP_k-1 are supplied with VH1. Therefore, transistors M11, M15, M16, and M17 are in the off state, and transistors M12 and M14 are in the on state. Furthermore, the potential of node ND1 is the data voltage V. DA +Vth, transistor M13 is in the ON state. Note that, due to Figure 20B The transistor M13 in pixel 10J shown is a p-channel transistor, so the Vth of transistor M13 is negative (lower than the reference voltage). Therefore, the data voltage V DA +Vth is below the data voltage V. DA The potential.

[0243] [Date T21]

[0244] During period T21, wiring EM_k is supplied to VH1 (refer to...) Figure 25A and Figure 25B Therefore, transistors M11 to M17 are turned off. The current path flowing between wiring ELVDD and wiring ELVSS is blocked. Therefore, the light-emitting device 61 stops emitting light.

[0245] [Period T22]

[0246] During period T22, wiring GN_k-1 and wiring GNBG_k-1 are supplied to VH2, and wiring GP_k-1 is supplied to VL1 (see reference). Figure 26A and Figure 26B When wiring GN_k-1 and wiring GNBG_k-1 are supplied with VH2, transistor M17 becomes active, and node ND1 is supplied with VH2 from wiring INI. INI .

[0247] Furthermore, when wiring GP_k-1 is supplied with VL1, transistor M15 becomes active. The first terminal of the light-emitting device 61 is supplied with VL1 from wiring INI. INI .

[0248] [Date T23]

[0249] During period T23, wiring GN_k-1 is supplied to VL2, and wiring GNBG_k-1 is supplied to V. INI Wiring GP_k-1 is supplied to VH1 (refer to...) Figure 27A and Figure 27B Therefore, transistors M17 and M15 are turned off. Furthermore, wiring GP_k is supplied with VL1, wiring GN_k is supplied with VH2, and wiring GNBG_k is supplied with VH2.

[0250] When wiring GP_k is supplied with VL1, transistor M11 becomes on, and the data voltage V... DA The data is supplied from routing DL to node ND1. Additionally, when routing GN_k and GNBG_k are supplied with VH2, transistor M16 becomes on. Because transistor M13 is also on, the data voltage V... DA It begins to be supplied to node ND1. As a result, the potential of node ND1 rises.

[0251] The potential of node ND1 continues to rise until it becomes the data voltage V at time t23a. DA Up to +Vth (refer to) Figure 24 When the potential of node ND1 becomes the data voltage V. DA When +Vth, transistor M13 becomes off, and the potential rise of node ND1 ends.

[0252] [Date T24]

[0253] During period T24, wiring GP_k is supplied to VH1, wiring GN_k is supplied to VL2, and wiring GNBG_k is supplied to V INI (Reference Figure 28A and Figure 28B When wiring GP_k is supplied with VH1, transistor M11 becomes off. Furthermore, when wiring GN_k is supplied with VL2 and wiring GNBG_k is supplied with V... INI When this occurs, transistor M16 is turned off, and the potential of node ND1 is maintained (ND1 = V). DA +Vth). Thus, node ND1 maintains a connection to the data voltage V. DA Add the potential Vth of transistor M13. Note that when transistor M13, used as the driving transistor, is a p-channel transistor, the data voltage V...DA +Vth is a potential below Vth.

[0254] [During period T25]

[0255] During period T25, wiring EM_k is supplied to VL1 (refer to...) Figure 29A and Figure 29B When wiring EM is supplied with VL1, transistors M12 and M14 become active. Here, the data voltage maintained in node ND1 (ND1 = V) is... DA +Vth) is a potential below Vth, and VDD of wiring ELVDD is a potential higher than the data voltage, thus transistor M13 is turned on. In this way, current flows from wiring ELVDD through transistors M12, M13, M14 and light-emitting device 61 to wiring ELVSS. Furthermore, the value of the current flowing from wiring ELVDD to wiring ELVSS depends on the potential of node ND1. Node ND1 of pixel 10J_k is maintained at a data voltage Vth corrected to the Vth of transistor M13, which serves as the driving transistor. DA This allows the corresponding data voltage V to be... DA The accurate current value flows through the light-emitting device 61.

[0256] As shown in the above example, each pixel in the display device according to one aspect of the present invention can undergo Vth correction (also referred to as "internal correction") of the driving transistor. Therefore, the display device according to one aspect of the present invention can correct Vth non-uniformity of the driving transistors between pixels. Furthermore, the effects of hysteresis in the driving transistors can be suppressed. By using the display device according to one aspect of the present invention, the display quality of the display unit can be improved.

[0257] Furthermore, in pixel 10, data voltage V is simultaneously processed. DA The holding and driving transistor's Vth correction. Therefore, the driving transistor's Vth correction and the data voltage V are respectively performed. DA Compared to the number of pixels that can be preserved, it can operate at high speed.

[0258] <Example 3 of a display device structure>

[0259] Next, a structural example different from the above-described display device will be described. Note that this will be explained later. Figures 30 to 42B In the description, sometimes the terms "and" are omitted. Figures 1A to 29B Repeated descriptions of the same parts.

[0260] Figure 30 A block diagram illustrating one aspect of the present invention is shown. Figure 30The display device 100C shown includes, for example, a display unit 20, a gate line-side driving circuit 34, a gate line-side driving circuit 35, a gate line-side driving circuit 36, and an integrated circuit 40. The display unit 20 includes pixels 10P that serve as sub-pixels. The gate line-side driving circuit 34 includes a shift register 38 having multiple unit circuits 39.

[0261] also, Figure 31 Showing what can be used Figure 30 The circuit structure of pixel 10P is shown. Pixel 10P includes transistor M41, transistor M42, transistor M43, transistor M44, transistor M45, transistor M46, capacitor C41, and light-emitting device 61.

[0262] Pixel 10P is connected to wiring GI, wiring GI_BG, wiring GW, wiring EM1, wiring EM2, wiring DL, wiring ELVDD, wiring ELVSS and wiring INI2.

[0263] Wiring GI, wiring GI_BG, wiring GW, wiring EM1, and wiring EM2 are used as gate lines. Wiring DL is used as a data line. Wiring GI and wiring GI_BG are connected to the gate line-side drive circuit 34. Wiring GW is connected to the gate line-side drive circuit 35. Wiring EM1 and EM2 are connected to the gate line-side drive circuit 36.

[0264] Wiring ELVDD is supplied with VDD, and wiring ELVSS is supplied with VSS. That is, in pixel 10P, current flows from wiring ELVDD to wiring ELVSS through transistors M42, M43, and M44 through the light-emitting device 61. By adopting this structure, the light emission of the light-emitting device 61 can be controlled according to the drain current of transistor M43 during the light emission period (during the period when transistors M42 and M44 are in the on state).

[0265] Wiring INI2 is supplied with an initialization potential V INI2 (also known as V) INI2 V INI2 This is to maintain a constant potential supplied to the other electrode of capacitor C41 in order to keep the gate potential of transistor M43, which is connected to one electrode of capacitor C41, at a constant potential. Furthermore, by using V... INI2 As the potential supply for the anode of the light-emitting device 61, V can be... INI2 This is used as the potential to prevent the light-emitting device 61 from emitting light. Additionally, V INI2 It can be used as a potential to initialize the anode of the light-emitting device 61.

[0266] Transistors M41, M42, M44, M45, and M46 are used as switches. Transistor M43 is used as a driver transistor.

[0267] Transistors M41, M42, M44, M45, and M46 have the function of setting the potential of the gate (node ​​ND2) of transistor M43, which is used to allow current to flow through the light-emitting device 61, to a potential corresponding to the data voltage. Transistor M46 has the function of maintaining the potential corresponding to the data voltage held by node ND2 by becoming in the off state.

[0268] Transistors M41 to M45 are preferably LTPS transistors. Alternatively, transistors M41 to M45 are preferably LTPI transistors, which are high-mobility oxide semiconductors with excellent crystallinity. By using LTPS transistors or LTPI transistors as transistors M41 to M45, transistors with high field-effect mobility and good frequency characteristics can be realized.

[0269] Furthermore, transistors M41 to M45 can be n-channel transistors. N-channel transistors have higher field-effect mobility than p-channel transistors, making them preferred. Additionally, by employing a structure using n-channel transistors, the aforementioned LTPI transistor can be used. Note that, although not shown, transistors M41 to M45 can also have a back gate. This structure allows for the realization of transistors with good electrical characteristics in the saturation region (also known as "saturation characteristics"). The back gate included in transistors M41 to M45 can be supplied with the same signal as the gate or connected to one or the other of the source and drain. This structure enables the realization of transistors with excellent electrical characteristics, such as saturation characteristics.

[0270] Furthermore, the transistor M46 included in pixel 10P can be an n-channel OS transistor with a back gate. Alternatively, transistor M46 can be an LTPI transistor as an n-channel transistor with a back gate. Figure 31 The circuit structure is shown when a transistor with a back gate is used as transistor M46.

[0271] Pixel 10P can have a circuit structure in which all transistors are n-channel transistors. For example, transistors M41 to M46 can all be LTPS transistors, LTPI transistors, or OS transistors. In this case, compared to the case of using an LTPO structure that includes both LTPS transistors and OS transistors, the increase in the number of transistor manufacturing steps can be suppressed.

[0272] In one embodiment of the present invention, the gate and back gate of the transistor M46 included in the pixel 10P are arranged opposite each other in a manner that separates them by a channel forming region through a semiconductor layer. Furthermore, the control signal supplied to the gate of the transistor M46 and the control signal supplied to the back gate of the transistor M46 are logically identical signals. However, the potential applied to the back gate (the low-level potential of the control signal) when the transistor M46 is in a turned-off state is different from the low-level potential of the control signal supplied to the gate when the transistor M46 is in a turned-off state. Specifically, the potential V of the wiring INI2 is... INI2 The potential VSS below the wiring ELVSS and the data voltage V of the wiring DL DA The potential supplied to the back gate (the low-level potential of the control signal) when transistor M46 is turned off will be set to potential V. INI2 The following potentials are preferably potentials V. INI2 Note that sometimes the gate included in transistor M46 is called the first gate, and the back gate included in transistor M46 is called the second gate.

[0273] By employing this structure, the potential of the control signal supplied to the back gate of transistor M46 can be lower than the potential of the control signal supplied to the gate of transistor M46 (low-level potential). By making the potential supplied to the back gate of the OS transistor, which is an n-channel transistor, lower than the potential supplied to the gate of the OS transistor, which is also an n-channel transistor (low-level potential), the threshold voltage can be shifted in the positive direction. Therefore, even when driving at a significantly reduced frame rate, the potential fluctuation of the gate of transistor M46 can be suppressed, thereby enabling a display device with excellent display quality.

[0274] By adopting this structure, the potential V of the wiring INI2 connected to pixel 10P can be used. INI2 The low-level potential serves as the control signal supplied to the back gate of transistor M46. Therefore, the number of potentials required for the low-level control signal supplied to the back gate of transistor M46 does not need to be increased. Furthermore, potential V... INI2 It can be a few volts lower than the potential VSS (for example, equivalent to the threshold voltage of the light-emitting device 61 (the voltage at which current begins to flow through the light-emitting device 61)). Therefore, the low-level potential supplied to the back gate of transistor M46 will not become too low. Thus, the amplitude voltage of the control signal supplied to the back gate can be suppressed from becoming too large.

[0275] Furthermore, by employing this structure, since the semiconductor layer with the channel formation region of transistor M46 is sandwiched between the gate and the back gate, the electric field generated outside transistor M46 is less likely to act on the channel formation region. Therefore, by providing a back gate in transistor M46, transistor M46 can operate stably. Moreover, by providing a back gate in transistor M46, characteristic non-uniformity between multiple transistors is reduced. Probability is improved by providing a back gate in transistor M46. Therefore, the reliability of display devices including this transistor M46 can be improved.

[0276] Furthermore, by employing the above structure, a light-shielding conductive material can be used on both the gate and back gate of the transistor M46. Additionally, when light is irradiated onto the channel formation region of the transistor, the electrical characteristics of the transistor M46 sometimes change. Furthermore, when light is irradiated onto the channel formation region while a voltage is applied to the transistor M46, the electrical characteristics sometimes deteriorate. In other words, the reliability of the transistor M46 sometimes decreases. By using a light-shielding conductive material on both the gate and back gate, the degradation of the electrical characteristics of the transistor M46 can be suppressed, thereby improving reliability.

[0277] Furthermore, with the above structure, when transistor M46 is turned on, the potential for the control signal that controls the turn-on state of transistor M46 can be supplied from both the gate and the back gate. For example, compared to supplying the potential to turn on transistor M46 to only one of the gate and the back gate, by supplying the potential to both the gate and the back gate, the on-state current can be further increased.

[0278] like Figure 31 As shown, each transistor in pixel 10P is connected to a wiring. One of the source and drain of transistor M41 is connected to wiring DL. The other of the source and drain of transistor M41 is connected to one of the source and drain of transistor M43 and one of the source and drain of transistor M44. One of the source and drain of transistor M42 is connected to wiring ELVDD. The other of the source and drain of transistor M42 is connected to the other of the source and drain of transistor M43 and one of the source and drain of transistor M46. The other of the source and drain of transistor M44 is connected to one of the source and drain of transistor M45, one electrode of capacitor C41, and the first terminal of light-emitting device 61. The second terminal of light-emitting device 61 is connected to wiring ELVSS. The other of the source and drain of transistor M45 is connected to wiring INI2. The other of the source and drain of transistor M46 is connected to the gate of transistor M43 and the other electrode of capacitor C41.

[0279] The gate of transistor M41 is connected to wiring GW. The gate of transistor M42 is connected to wiring EM2. The gate of transistor M44 is connected to wiring EM1. The gate of transistor M45 is connected to wiring GI. The gate of transistor M46 is connected to wiring GI. The back gate of transistor M46 is connected to wiring GI_BG.

[0280] The control signal supplied to the wiring GW controls the on or off state of the transistor M41. For example, the control signal supplied to the wiring GW controls whether the data voltage supplied to the wiring DL is written to pixel 10P. For example, the transistor M41, which is an n-channel transistor, is turned on when the control signal is at level H and turned off when the control signal is at level L.

[0281] The control signal supplied to wiring EM1 controls the on / off state of transistor M44. The control signal supplied to wiring EM2 controls the on / off state of transistor M42. For example, the control signals supplied to wiring EM1 and wiring EM2 control the current path flowing between wiring ELVDD and wiring ELVSS. For example, transistors M42 and M44, as n-channel transistors, are turned on when the control signal is at level H and turned off when the control signal is at level L.

[0282] Furthermore, the control signal supplied to wiring EM2 is a signal that initializes the potential of node ND2. For example, while transistors M46 and M42 are in the ON state, the potential VDD of wiring ELVDD is supplied to node ND2 to initialize it. Through this initialization, a fixed voltage can be applied between the gate and source of transistor M46. Therefore, when the potential of the gate of transistor M46 varies between each pixel depending on the data voltage being written, the hysteresis effect of the electrical characteristics of transistor M43 changing due to the potential state maintained in node ND2 can be mitigated.

[0283] The control signals supplied to wiring GI and wiring GI_BG control the on / off state of transistor M46. For example, by controlling the control signals supplied to wiring GI and wiring GI_BG, the potential of the gate of transistor M46 is set to the potential of either the source or drain of transistor M46. As an n-channel transistor, transistor M46 is in the on state when both the control signals supplied to wiring GI and wiring GI_BG are at a high level (H), and in the off state when both the control signals supplied to wiring GI and wiring GI_BG are at a low level (L).

[0284] Figure 32AThis is an example of a block diagram of the unit circuit 39 included in the gate-side drive circuit 34 of the aforementioned wiring GI and wiring GI_BG, which outputs control signals. The unit circuit 39 includes a pulse output circuit PO and buffers BUF1 and BUF2.

[0285] In unit circuit 39, pulse output circuit PO outputs pulse signals based on clock signals, start pulses, etc. Buffer BUF1 outputs the output signal of pulse output circuit PO as a control signal for the amplitude voltage between potentials VH3 and VL3 to wiring GI. Buffer BUF2 outputs the output signal of pulse output circuit PO as a control signal for the amplitude voltage between potentials VH3 and VSS2 to wiring GI_BG.

[0286] VH3 is a potential equal to or higher than VDD of the wiring ELVDD supplied to pixel 10P. VL3 is a potential equal to or higher than VSS of the wiring ELVSS supplied to pixel 10P. VSS2 is a potential lower than VL3, preferably a potential V of the wiring INI2 supplied to pixel 10P. INI2 Hereinafter, the potential V of wiring INI2 is more preferably preferred. INI2 By employing this structure, the amplitude voltage of the control signal supplied from buffer BUF1 to wiring GI can be different from the amplitude voltage of the control signal supplied from buffer BUF2 to wiring GI_BG.

[0287] This describes the amplitude voltage of the control signals output from buffers BUF1 and BUF2.

[0288] Figure 32B This is an explanation Figure 32A The waveform of the amplitude voltage of the control signal output by buffer BUF1. The control signal output by buffer BUF1 is output to wiring GI. Figure 32A and Figure 32B As shown, buffer BUF1 is supplied with VH3 and VL3, which serve as the potentials for applying the H level and the L level, respectively. VH3 is the potential at which the n-channel transistor is turned on when supplied to its gate. VL3 is the potential at which the n-channel transistor is turned off when supplied to its gate.

[0289] Figure 32C This is an explanation Figure 32A The waveform of the amplitude voltage of the control signal output by buffer BUF2. The control signal output by buffer BUF2 is output to wiring GI_BG. Figure 32A and Figure 32CAs shown, buffer BUF2 is supplied with VH3 and VSS2, which serve as the potentials for applying the H level and L level, respectively. VH3 is the potential at which the n-channel transistor is turned on when supplied to its gate. Potential VSS2 is the potential at which the n-channel transistor is turned off when supplied to its gate, and is also a potential lower than VL3. By employing this structure, the potential V of wiring INI2 can be used. INI2 As VSS2. Potential V INI2 It can be a potential lower than the potential of the wiring ELVSS, and it does not require increasing the number of potentials used for VSS2, so it is preferred.

[0290] like Figure 32B As shown in the waveform diagram, the selection signal corresponding to the amplitude voltage Am4 of VH3 and VL3, which is the control signal for wiring GI, is P during the selection period. SEL The current is supplied to the gate of transistor M46. For example... Figure 32C As shown in the waveform diagram, the selection signal corresponding to the amplitude voltage Am5 of VH3 and VSS2, which is the control signal for wiring GI_BG, is P during the selection period. SEL The signal is supplied to the back gate of transistor M46. By employing this structure, control to turn on transistor M46 can be reliably performed without causing the amplitude voltage Am4 to exceed the amplitude voltage Am5. Furthermore, compared to using the control signal for wiring GI_BG as the control signal for wiring GI, the amplitude voltage Am4 of the control signal in wiring GI can be reduced.

[0291] Furthermore, the low-level potential of the control signal for wiring GI_BG is lower than that of VL3 and VSS. By employing this structure, the voltage between the back gate and source of transistor M46 can be set below 0V. Therefore, while allowing the threshold voltage of transistor M46 to drift in the positive direction, threshold voltage fluctuations can be suppressed, thereby improving the long-term reliability of the transistor.

[0292] Figure 33 This is a block diagram of the shift register 38 included in the gate line-side drive circuit 34 of the aforementioned display device 100C. Figure 33 The shift register 38 shown includes unit circuits 39_1 to 39_m (where m is an integer greater than 2) as a plurality of unit circuits 39. Unit circuits 39_1 to 39_m are all connected to wiring CKL1, wiring CKL2, power line VDL, power line VSL1, power line VSL2, wiring LIN1, wiring LIN2, wiring GI, wiring GI_BG, and wiring GO3.

[0293] Routing CKL1 is for transmitting the clock signal CK1 to the unit circuits 39_1 to 39_m in each row. Routing CKL2 is for transmitting the clock signal CK2 to the unit circuits 39_1 to 39_m in each row. Routing CKL1 and CKL2 are sometimes referred to as clock signal lines. Figure 33 In the unit circuits 39_1 to 39_m shown, the terminals connected to wirings CKL1 and CKL2 are represented as CK1 and CK2.

[0294] Power line VDL transmits power potentials, such as voltage VH3, to the unit circuits 39_1 to 39_m in each row. Power line VSL1 transmits power potentials, such as voltage VL3, to the unit circuits 39_1 to 39_m in each row. Power line VSL2 transmits power potentials, such as voltage VSS2, to the unit circuits 39_1 to 39_m in each row. Figure 33 In the unit circuits 39_1 to 39_m shown, the terminal connected to the power line VDL is denoted as VDD1, the terminal connected to the power line VSL1 is denoted as VSS1, and the terminal connected to the power line VSL2 is denoted as VSS2.

[0295] Routing LIN1 is the wiring that transmits control signals, such as the start pulse signal SP1, to the unit circuit 39_1 located in the first row. Routing LIN1 is sometimes referred to as a signal line. Figure 33 In the unit circuit 39_1 shown, the terminal connected to wiring LIN1 is designated SP1. Wiring LIN2 is the wiring that transmits control signals, such as the start pulse signal SP2, to the unit circuit 39_1 located in the first row. Wiring LIN2 is sometimes referred to as a signal line. Figure 33 In the unit circuit 39_1 shown, the terminal connected to wiring LIN2 is represented as SP2.

[0296] In addition, Figure 33 The setup shown is in the unit circuits 39_2 to 39_m in the second row and beyond. The signal output from the unit circuit 39 in the previous row is used as the start pulse signal. Therefore, the terminal connected to the wiring GO3_1 to GO3_m-1 in the previous row is denoted as SP1, and the terminal connected to the wiring GI_1 to GI_m-1 in the previous row is denoted as SP2.

[0297] Routing GI_1 to GI_m transmits the output signals from the unit circuits 39_1 to 39_m in each row. Routing GI_BG_1 to GI_BG_m transmits the output signals from the unit circuits 39_1 to 39_m in each row. Routing GO3_1 to GO3_m transmits the output signals from the unit circuits 39_1 to 39_m in each row. Routing GI_1 to GI_m, GI_BG_1 to GI_BG_m, and GO3_1 to GO3_m are sometimes referred to as output signal lines. Figure 33 In the unit circuits 39_1 to 39_m shown, the terminals connected to GI_BG_1 to GI_BG_m are represented as OUT1. Figure 33 In the unit circuits 39_1 to 39_m shown, the terminals connected to GI_1 to GI_m are designated as OUT2. Figure 33 In the unit circuits 39_1 to 39_m shown, the terminals connected to GO3_1 to GO3_m are represented as OUT3.

[0298] Figure 34 It can be applied to Figure 33 An example of the circuit diagram of unit circuit 39, from 39_1 to 39_m. Figure 35 This is an explanation of the reason. Figure 34 The circuit diagram shown represents the timing diagram of the operation of unit circuit 39.

[0299] Unit circuit 39 includes transistors M21 to M31 and capacitors C21 to C23. Unit circuit 39 and... Figure 33 The wiring diagram illustrates the connections CKL1, CKL2, power lines VDL, VSL1, VSL2, LIN1, LIN2, GI, GI_BG, and GO3. Transistors M21 to M31 are n-channel transistors. Transistors M21 to M31 can be LTPS transistors, LTPI transistors, or OS transistors.

[0300] In unit circuit 39, the aforementioned pulse output circuit PO corresponds to a circuit including transistors M25 to M31 and capacitor C23. Furthermore, buffer BUF1 corresponds to a circuit including transistors M21 and M22 and capacitor C21. Furthermore, buffer BUF2 corresponds to a circuit including transistors M23 and M24 and capacitor C22.

[0301] One of the source and drain of transistor M21 is connected to wiring CKL1. The other of the source and drain of transistor M21 is connected to one of the source and drain of transistor M22, one electrode of capacitor C21, and wiring GI. The gate of transistor M21 is connected to one of the source and drain of transistor M25, the gate of transistor M23, the other electrode of capacitor C21, and one electrode of capacitor C22. The other of the source and drain of transistor M22 is connected to power line VSL1. The gate of transistor M22 is connected to the gate of transistor M24, one of the source and drain of transistor M26, the gate of transistor M28, and one of the source and drain of transistor M29. One of the source and drain of transistor M23 is connected to wiring CKL1. The other of the source and drain of transistor M23 is connected to one of the source and drain of transistor M24, the other electrode of capacitor C22, and wiring GI_BG. The other of the source and drain of transistor M24 is connected to power line VSL2. The gate of transistor M25 is connected to power line VDL. The other of the source and drain of transistor M25 is connected to the gate of transistor M26, one of the source and drain of transistor M27, one of the source and drain of transistor M28, and wiring GO3. The other of the source and drain of transistor M26 is connected to power line VSL1. The other of the source and drain of transistor M27 is connected to power line VDL. The gate of transistor M27 is connected to wiring LIN1. The other of the source and drain of transistor M28 is connected to power line VSL1. The other of the source and drain of transistor M29 is connected to one electrode of capacitor C23 and wiring CKL2. The gate of transistor M29 is connected to one of the source and drain of transistor M30, one of the source and drain of transistor M31, and the other electrode of capacitor C23. The other of the source and drain of transistor M30 is connected to power line VSL1. The gate of transistor M30 is connected to wiring CKL1. The source or drain of transistor M31 is connected to power line VSL1. The gate of transistor M31 is connected to wiring LIN2.

[0302] Figure 35 The CKL1 shown is the clock signal supplied to the wiring CKL1. Figure 35 The CKL2 shown is the clock signal supplied to the wiring CKL2. Figure 35 The LIN1 shown is the control signal supplied to the wiring LIN1. Figure 35 The LIN2 shown is the control signal supplied to the wiring LIN2. Figure 35 The GI_BG shown is the control signal output to the wiring GI_BG. Figure 35 The GI shown is the control signal output to the wiring GI. Figure 35PO3 shown is the control signal output to wiring GO3. Furthermore, in Figure 35 For the purpose of explaining the work, periods T91 to T98 are attached.

[0303] Note that in the following description, the potentials of power lines VDL, VSL1, and VSL2 will be set as VH3, VL3, and VSS2, respectively. An n-channel transistor is in the ON state when the logic level of the signal applied to its gate is H, and in the OFF state when the logic level is L. Therefore, the logic level at which the transistor is ON is sometimes called the ON level, and the logic level at which the transistor is OFF is called the OFF level. Note that the H and L level potentials in clock signals, control signals, etc., are based on the potentials shown in the attached diagram.

[0304] During T91, the voltage level changes to H (high) through CKL2, and the gate of transistor M29 becomes H through capacitor C23, turning transistor M29 on. Therefore, transistors M22, M24, and M28 become on. Since transistor M28 is on, the gates of transistors M21 and M23 become L (low) through transistor M25. Therefore, GI, GI_BG, and GO3 become L.

[0305] During T92, CKL1 becomes high (H) level, turning transistor M30 on. The gate of transistor M29 becomes low (L) level, thus turning M29 off. Since LIN1 is low (L), transistor M27 is off, while the gates of transistors M22, M24, and M28 remain high (H). Therefore, transistors M22, M24, and M28 remain on. Furthermore, the gate of transistor M26 remains low (L), so transistor M26 remains off. Therefore, GI, GI_BG, and GO3 become low (L).

[0306] During T93, CKL1 becomes low (L) level, and transistor M30 becomes off. Although CKL2 becomes high (H) level, LIN2 is also high (H) level, so transistor M31 becomes on, and transistor M29 remains off. Because LIN1 becomes high (H) level, transistor M27 becomes on. The gate of transistor M26 becomes high (H) level, so transistor M26 becomes on. The gates of transistors M22, M24, and M28 become low (L) level. Therefore, transistors M22, M24, and M28 become off. Because transistor M27 becomes on (H), the gates of transistors M21 and M23 become high (H) level through transistor M25. Because CKL1 is low (L) level, GI and GI_BG become low (L) level, and GO3 becomes high (H).

[0307] During T94, CKL1 becomes high-level, turning transistor M30 on. The gate of transistor M29 becomes low-level, turning it off. LIN1 becomes low-level, turning transistor M27 off. The gate of transistor M26 remains high-level, so it remains on. The gates of transistors M22, M24, and M28 remain low-level, thus turning them off. Furthermore, the gates of transistors M21 and M23 remain high-level. Since CKL1 is high-level, GI, GI_BG, and GO3 also become high-level.

[0308] During T95, CKL1 becomes low (L) level, and transistor M30 becomes off. Although CKL2 becomes high (H) level, LIN2 is also high (H) level, so transistor M31 becomes on, and transistor M29 remains off. Because LIN1 becomes high (H) level, transistor M27 becomes on. The gate of transistor M26 becomes high (H) level, so transistor M26 becomes on. The gates of transistors M22, M24, and M28 become low (L) level. Therefore, transistors M22, M24, and M28 become off. Because transistor M27 becomes on (H), the gates of transistors M21 and M23 become high (H) level through transistor M25. Because CKL1 is low (L) level, GI and GI_BG become low (L) level, and GO3 becomes high (H).

[0309] During T96, CKL1 becomes high-level (H), turning transistor M30 on. The gate of transistor M29 becomes low-level (L), turning M29 off. LIN1 becomes low-level, turning transistor M27 off. The gate of transistor M26 remains high-level, so transistor M26 remains on. The gates of transistors M22, M24, and M28 remain low-level, therefore, transistors M22, M24, and M28 remain off. Furthermore, the gates of transistors M21 and M23 remain high-level. Since CKL1 is high-level, GI, GI_BG, and GO3 also become high-level.

[0310] During period T97, the voltage level changes to H (high) through CKL2, and the gate of transistor M29 becomes H through capacitor C23, turning transistor M29 on. Therefore, transistors M22, M24, and M28 become on. Since transistor M28 is on, the gates of transistors M21 and M23 become L (low) through transistor M25. Therefore, GI, GI_BG, and GO3 become L.

[0311] During T98, CKL1 becomes high (H) level, turning transistor M30 on. The gate of transistor M29 becomes low (L) level, thus turning M29 off. Since LIN1 is low (L), transistor M27 is off, while the gates of transistors M22, M24, and M28 remain high (H). Therefore, transistors M22, M24, and M28 remain on. Furthermore, the gate of transistor M26 remains low (L), so transistor M26 remains off. Therefore, GI, GI_BG, and GO3 become low (L).

[0312] The INI2 connected to pixel 10P can be used as a power line VSL2 connected to unit circuit 39. Specifically, as Figure 36A As shown, the power supply line connected to terminal VSS2 of unit circuit 39 can be the wiring INI2 connected to multiple pixels 10P. Wiring INI2 is supplied with a potential lower than VL3 of power supply line VSL1, i.e., V... INI2 Therefore, this potential is suitable for supplying the power supply line VSL2 to the potential VSS2. Thus, the low-level potential, which serves as the control signal supplied to the back gate of transistor M46, does not require increasing the number of potentials needed.

[0313] also, Figure 36B Show Figure 36A The detailed circuit diagram of the structure shown is as follows. Figure 36B As shown, the wiring INI2 connected to pixel 10P can be used as the power line VSL2 of unit circuit 39. By configuring the wiring INI2 in a direction parallel to wiring GI and wiring GI_BG, the connection between unit circuit 39 and pixel 10P can be configured efficiently row by row.

[0314] <Example 3 of a display device in operation>

[0315] Next, an example of the operation of a pixel 10P in a display device 100C that can be used in one aspect of the present invention will be described. Figure 37 This is an explanation Figure 31 The timing diagram illustrates a working example of a 10P pixel. Figure 37 The waveforms of the control signals supplied to wiring GI, wiring GI_BG, wiring GW, wiring EM1, and wiring EM2 connected to pixel 10P are shown, along with the potential changes at node ND2. Furthermore, in Figures 38A to 42B In the middle, side by side Figure 37 The diagram shown illustrates the operation of pixel 10P during periods T31 to T35, along with a timing diagram. Note the following explanation... Figures 38A to 42B In the explanation, sometimes the above-mentioned Figures 7A to 11B , Figure 25A and Figure 29B The description of the working example is a repetition of the same part.

[0316] Note that, for ease of understanding, the potentials of the control signals supplied to wiring GI, wiring GI_BG, wiring GW, wiring EM1, and wiring EM2, respectively, and the potentials of the wiring supplied with constant potentials, can be represented as follows: Figures 32A to 32C The structure described in the text.

[0317] Note that, as an initial state, routing GI and routing GW are supplied to VL3, and routing GI_BG is supplied to V. INI2 Wiring EM1 and EM2 are supplied with VH3. Therefore, transistors M41, M45, and M46 are in the off state, while transistors M42 and M44 are in the on state. Furthermore, the capacitor C41 located between the gate and source of transistor M43 maintains a voltage corresponding to the data voltage V. DA voltage V DA With +Vth+dV, transistor M43 is in the ON state.

[0318] [During period T31]

[0319] During T31, cabling GI and GI_BG are supplied with VH3, and cabling EM1 is supplied with VL3 (see reference). Figure 38A and Figure 38B Therefore, transistors M45 and M46 become active while transistor M44 becomes inactive. The current path between wiring ELVDD and wiring ELVSS is blocked. Consequently, the light-emitting device 61 stops emitting light. The potential of node ND2 at one electrode of capacitor C41 is initialized to VDD. Furthermore, the potential of the other electrode of capacitor C41 is initialized to VDD. INI2 Capacitor C41 holds the voltage VDD-V. INI2 The work performed by T31 during this period is also called initialization work.

[0320] [During period T32]

[0321] During T32, wiring GI is supplied to VL3, and wiring GI_BG is supplied to V. INI2 The cabling GW is supplied with VH3, and the cabling EM2 is supplied with VL3 (see reference). Figure 39A and Figure 39B Transistor M41 is turned on, while transistors M42, M45, and M46 are turned off. Capacitor C41 maintains the voltage VDD-V. INI2 Thus, the source potential of transistor M43 is released to the voltage V on which the previous row of data was written. DA The wiring DL. When current flows through transistor M43, a voltage stress is applied to transistor M43, thus mitigating the hysteresis effect of transistor M43. The operation of T32 during this period is also known as voltage stress application operation.

[0322] [During period T33]

[0323] During T33, wiring GI and GI_BG are supplied to VH3 (see reference). Figure 40A and Figure 40B At this point, transistors M45 and M46 are turned on. The potential of node ND2 is higher than the data voltage V. DA Therefore, the potential drops due to the discharge through transistor M43. The potential of node ND2 drops until it becomes the data voltage V at time t33a. DA Up to +Vth (refer to) Figure 37 When the potential of node ND2 becomes V DA When +Vth, transistor M43 becomes off, and the potential drop at node ND2 ends.

[0324] The potential at node ND2 is as follows: at one electrode of capacitor C41, it is V. INI In this state, the voltage between the gate and source of transistor M43 becomes the threshold voltage Vth. DA +Vth. Capacitor C41 maintains voltage V. DA +Vth-V INI2 Because the effects of T32 hysteresis are mitigated during this period, the unevenness of Vth between pixels is reduced. The work during T33 is also known as the data sampling work.

[0325] [During period T34]

[0326] During T34, wiring GI is supplied to VL3, and wiring GI_BG is supplied to V. INI2 The cabling GW is supplied with VH3 (refer to...) Figure 41A and Figure 41B Transistors M41, M42, M45, and M46 are turned off. With transistor M46 turned off, the potential of node ND2 is maintained (ND2 = V). DA +Vth). Thus, node ND2 maintains a connection to the data voltage V. DA Add the potential of Vth to transistor M43. The operation of T34 during this period is also known as the migration operation.

[0327] [During period T35]

[0328] During period T35, cabling EM1 and EM2 were supplied by VH3 (see reference). Figure 42A and Figure 42B When wirings EM1 and EM2 are supplied with VH3, transistors M42 and M44 become active. Here, VSS in wiring ELVSS is at a potential lower than VDD and remains at a potential in node ND2 (ND2 = VDD). DAWhen +Vth is greater than Vth, transistor M43 becomes active. Thus, current flows from wiring ELVDD through transistors M42, M43, M44 and light-emitting device 61 to wiring ELVSS. As current flows, the potential of the other electrode of capacitor C41 rises (e.g., +dV). One electrode of capacitor C41 on the ND2 side is electrically floating. Therefore, the potential of node ND2 rises to Vth. DA +Vth+dV. During this period, capacitor C41 maintains V. DA +Vth-V INI2 Therefore, it is possible to make the data voltage V... DA The accurate current value flows through the light-emitting device 61.

[0329] As shown in the above example, each pixel in the display device according to one aspect of the present invention can undergo Vth correction of the driving transistor. Therefore, the display device according to one aspect of the present invention can correct Vth non-uniformity of the driving transistors between pixels. Furthermore, the hysteresis effect of the driving transistors can be suppressed. By using the display device according to one aspect of the present invention, the display quality of the display unit can be improved.

[0330] Furthermore, in pixel 10P, data voltage V is simultaneously processed. DA The holding and driving transistor's Vth correction. Therefore, the driving transistor's Vth correction and the data voltage V are respectively performed. DA Compared to the number of pixels that can be preserved, it can operate at high speed.

[0331] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0332] (Implementation Method 2)

[0333] In this embodiment, refer to Figures 43 to 52C This invention describes a display device according to one aspect of the present invention.

[0334] <Perspective and cross-sectional view of the display device>

[0335] Figure 43 A perspective view of the display device 300A is shown. Figure 44A A cross-sectional view of the display device 300A is shown. Figure 44B and Figure 44C This is an explanation Figure 44A A cross-sectional view of a transistor structure example.

[0336] The display device 300A has a structure that bondes substrate 352 and substrate 351. Figure 43 In the image, substrate 352 is represented by a dashed line.

[0337] The display device 300A includes a display section 362, a connection section 340, a gate line-side driving circuit 364, and wiring 365, etc. Figure 43 An example is shown where an IC373 and an FPC372 are installed in a display device 300A. Therefore, it is also possible to... Figure 43 The structure shown is called a display module that includes display device 300A, IC (integrated circuit), and FPC.

[0338] The connecting portion 340 is disposed on the outer side of the display portion 362. The connecting portion 340 may be disposed along one or more sides of the display portion 362. The number of connecting portions 340 may also be one or more. Figure 43 An example is shown where the connecting portions 340 are arranged around the four sides of the display section. In the connecting portions 340, the common electrode of the light-emitting device is connected to the conductive layer, and a potential can be supplied to the common electrode.

[0339] The gate line-side driving circuit 364 is, for example, equivalent to the gate line-side driving circuits 30 to 33 described in Embodiment 1 above. By reducing the number or area of ​​the gate line-side driving circuits 364, the area of ​​the display portion 362 disposed between the substrate 351 and the substrate 352 can be increased.

[0340] Wiring 365 has the function of supplying signals and power to the display unit 362 and the gate line-side driving circuit 364. The signals and power are input to wiring 365 from the outside via FPC 372 or from IC 373.

[0341] Figure 43 An example is shown where IC 373 is mounted on substrate 351 using COG (Chip On Glass) or COF (Chip On Film) methods. IC 373 can be, for example, an IC including signal line drive circuitry. Note that the display device 300A and display module do not necessarily need to have an IC mounted on them. Furthermore, the IC can also be mounted on an FPC using COF or similar methods.

[0342] Figure 44A An example of a cross-section of a portion of the display device 300A including the FPC 372, a portion of the gate line-side drive circuit 364, a portion of the display portion 362, a portion of the connection portion 340, and a portion of the region including the end.

[0343] Figure 44A The display device 300A shown includes not only a layer 301 containing transistors 201A and 202, but also a light-emitting device 330 between substrates 351 and 352.

[0344] The light-emitting device 330 includes a conductive layer 311, a conductive layer 312 on the conductive layer 311, and a conductive layer 326 on the conductive layer 312. The conductive layers 311, 312, and 326 can all be referred to as pixel electrodes, or a portion of the conductive layers 311, 312, and 326 can be referred to as pixel electrodes. For example, self-emissive light-emitting devices such as LEDs (Light Emitting Diodes), organic EL (Electro Luminescence) devices (also known as OLEDs), inorganic EL devices, and semiconductor lasers can be used as the light-emitting device 330. Examples of LEDs include mini LEDs or micro LEDs. The following description explains the use of organic EL devices.

[0345] The conductive layer 311 is connected to the transistor 202 disposed in the display unit 362 through an opening provided in the insulating layer 324. For example, conductive layers 311 and 312 can be conductive layers used as reflective electrodes. For example, conductive layer 326 can be a conductive layer used as a transparent electrode.

[0346] A recess is formed in the conductive layer 311 to cover an opening in the insulating layer 324. For example, this recess is filled with layer 328. Layer 328 has the function of planarizing the recess in the conductive layer 311. A conductive layer 312 is provided on the conductive layer 311 and layer 328. The area overlapping the recess in the conductive layer 311 can also be used as a light-emitting area, thereby improving the aperture ratio of the pixel. When the planarity on the conductive layer 311 is sufficient, layer 328 can also be omitted.

[0347] Layer 328 can be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be appropriately used for layer 328. In particular, layer 328 is preferably formed using an insulating material.

[0348] Layer 328 may appropriately use an insulating layer containing organic materials. For example, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimide amide resin, silicone resin, benzocyclobutene resin, phenolic resin, and precursors of the above resins may be used as layer 328. Furthermore, a photosensitive resin may be used as layer 328. The photosensitive resin may be a positive or negative material.

[0349] By using a photosensitive resin, layer 328 can be manufactured through only exposure and development processes, which can reduce the impact on the surface of conductive layer 311 caused by dry etching or wet etching. In addition, by using a negative photosensitive resin to form layer 328, sometimes the same photomask forming layer 328 as the photomask (exposure mask) used to form the opening of insulating layer 324 can be used.

[0350] The top and side surfaces of conductive layer 312 and conductive layer 326 are covered by layer 313. Therefore, the entire area where conductive layer 312 is disposed can be used as the light-emitting area of ​​light-emitting device 330, thereby improving the aperture ratio of the pixel.

[0351] The sides of layer 313 are covered by insulating layers 325 and 327. A sacrificial layer 318 is located between layer 313 and insulating layer 325. A layer 314 is disposed on layer 313, insulating layer 325, and insulating layer 327. A common electrode 315 is disposed on layer 314. Both layer 314 and the common electrode 315 are continuous films shared by multiple light-emitting devices 330. Furthermore, a protective layer 331 is disposed on each light-emitting device 330.

[0352] The protective layer 331 and the substrate 352 are bonded together by the adhesive layer 342. The seal for the light-emitting device 330 can employ a solid sealing structure or a hollow sealing structure, etc. Figure 44A In this configuration, the space between substrates 352 and 351 is filled with adhesive layer 342, thus employing a solid sealing structure. Alternatively, a hollow sealing structure can be used, where the space is filled with an inactive gas (such as nitrogen or argon). In this case, adhesive layer 342 can also be positioned so as not to overlap with the light-emitting device. Furthermore, a resin different from that used for the frame-shaped adhesive layer 342 can be used to fill the space.

[0353] In the connection portion 340, a conductive layer 323 is provided on the insulating layer 324. An example is shown where the conductive layer 323 has a stacked structure of conductive films processed with the same conductive film as conductive layer 311, conductive films processed with the same conductive film as conductive layer 312, and conductive films processed with the same conductive film as conductive layer 326. The ends of the conductive layer 323 are covered by a sacrificial layer 318, an insulating layer 325, and an insulating layer 327. Furthermore, a layer 314 is provided on the conductive layer 323, and a common electrode 315 is provided on the layer 314. The conductive layer 323 and the common electrode 315 are connected through the layer 314. Alternatively, the connection portion 340 may not have a layer 314. In this case, the conductive layer 323 is in direct contact and connected to the common electrode 315.

[0354] The display device 300A is, for example, a top-emitting type. The light-emitting device emits light L onto one side of the substrate 352. The substrate 352 is preferably made of a material with high transmittance to visible light. The pixel electrode contains a material that reflects visible light, and the counter electrode (common electrode 315) contains a material that allows visible light to pass through. Alternatively, the display device can also be a bottom-emitting type.

[0355] Insulating layer 220 is provided in a manner that covers the transistor. Insulating layer 324 is provided in a manner that covers the transistor and is used as a planarization layer. Furthermore, there is no particular limitation on the number of insulating layers covering the transistor; there can be one or more.

[0356] Preferably, at least one of the insulating layers covering the transistor is made of a material that does not readily diffuse impurities such as water and hydrogen. This allows the insulating layer to function as a barrier insulating layer. By employing this structure, the diffusion of impurities from the outside into the transistor can be effectively suppressed, thereby improving the reliability of the display device.

[0357] As the insulating layer 220, an inorganic insulating film is preferably used. Examples of inorganic insulating films include silicon nitride films, silicon oxynitride films, silicon oxide films, silicon oxynitride films, aluminum oxide films, and aluminum nitride films. Additionally, hafnium oxide films, yttrium oxide films, zirconium oxide films, gallium oxide films, tantalum oxide films, magnesium oxide films, lanthanum oxide films, cerium oxide films, and neodymium oxide films can also be used. Furthermore, two or more of the above-mentioned insulating films can be laminated.

[0358] The insulating layer 324, used as the planarization layer, can appropriately use an organic insulating film. Examples of materials suitable for use in organic insulating films include acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimide amide resins, silicone resins, benzocyclobutene resins, phenolic resins, and precursors of these resins.

[0359] A connection portion 204 is provided in a region of substrate 351 that does not overlap with substrate 352. In the connection portion 204, wiring 365 is connected to FPC 372 via conductive layer 366 and connection layer 203. An example is shown where conductive layer 366 has a stacked structure of conductive films processed with the same conductive film as conductive layer 311, conductive films processed with the same conductive film as conductive layer 312, and conductive films processed with the same conductive film as conductive layer 326. Conductive layer 366 is exposed on the top surface of connection portion 204. Therefore, connection portion 204 can be connected to FPC 372 via connection layer 203.

[0360] Preferably, a light-shielding layer 317 is provided on the surface of the substrate 352 on the substrate 351 side. The light-shielding layer 317 can be provided between adjacent light-emitting devices 330, in the connection portion 340, and in the gate line-side driving circuit 364, etc. In addition, various optical components can be disposed on the outer side of the substrate 352. As optical components, polarizers, phase retardation plates, light diffusion layers (diffusion films, etc.), anti-reflection layers, and condensing films can be used. Furthermore, an antistatic film that inhibits dust adhesion, a water-repellent film that is not easily soiled, a hard coating film that inhibits damage during use, and an impact absorption layer can also be disposed on the outer side of the substrate 352.

[0361] By forming a protective layer 331 covering the light-emitting device 330, impurities such as water can be prevented from entering the light-emitting device 330, thereby improving the reliability of the light-emitting device.

[0362] Substrates 351 and 352 can be made of glass, quartz, ceramic, sapphire, resin, metal, alloy, semiconductor, etc. The substrate from which light from the light-emitting device is extracted uses a material that allows the light to pass through. By using a flexible material for substrates 351 and 352, the flexibility of the display device can be improved. Polarizers can also be used as substrates 351 or 352.

[0363] The following materials can be used as substrates 351 and 352: polyester resins such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resins, acrylic resins, polyimide resins, polymethyl methacrylate resins, polycarbonate (PC) resins, polyethersulfone (PES) resins, polyamide resins (nylon, aromatic polyamides, etc.), polysiloxane resins, cycloolefin resins, polystyrene resins, polyamide-imide resins, polyurethane resins, polyvinyl chloride resins, polyvinylidene chloride resins, polypropylene resins, polytetrafluoroethylene (PTFE) resins, ABS resins, and cellulose nanofibers, etc. Alternatively, one or both of substrates 351 and 352 can be made of glass with a flexible thickness.

[0364] When a circular polarizer is superimposed on a display device, it is preferable to use a substrate with high optical isotropy as the substrate included in the display device. A substrate with high optical isotropy has lower birefringence (or, in other words, less birefringence).

[0365] The adhesive layer 342 can use various curing adhesives such as UV-curing adhesives, reactive curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. In particular, materials with low moisture permeability, such as epoxy resins, are preferred. Furthermore, two-component mixed resins can also be used. Additionally, adhesive sheets can also be used.

[0366] The bonding layer 203 can use anisotropic conductive film (ACF) or anisotropic conductive paste (ACP).

[0367] A layer 301 including transistors is disposed between the substrate 351 and the insulating layer 220. Layer 301 includes transistors 201A and 202. Transistor 201A is, for example, an OS transistor with a gate and a back gate as described in Embodiment 1 above. Transistor 202 is an LTPS transistor as described in Embodiment 1 above. Transistors 201A and 202 are disposed on the substrate 351. Transistors 201A and 202 can be formed using the same material and the same process.

[0368] Figure 44B This is an enlarged view of a cross-section including transistor 201A. Figure 44C This is an enlarged view of the cross-section including transistor 202. Figure 44B The transistor 201A shown can be used as an OS transistor as an n-channel transistor. Figure 44C The transistor 202 shown can be an LTPS transistor that is a p-channel type transistor. Transistors 201A and 202 can be transistors included in the display unit 362. Furthermore, transistors 201A and 202 can be transistors not only included in the display unit 362, but also transistors included in the gate line-side drive circuit 364. The transistors included in the gate line-side drive circuit 364 can also be either transistor 201A or transistor 202.

[0369] Transistor 201A has insulating layer 211, conductive layer 212A, insulating layer 213, insulating layer 214, semiconductor layer 215, insulating layer 216, conductive layer 217, insulating layer 218, and conductive layers 219a and 219b sequentially stacked on substrate 351. A portion of insulating layers 213, 214, and 218 serves as the gate insulating layer of transistor 201A. Conductive layer 212A serves as the bottom gate electrode of transistor 201A. Conductive layer 217 serves as the top gate electrode of transistor 201A. Conductive layers 219a and 219b serve as source or drain electrodes.

[0370] Semiconductor layer 215 is, for example, a metal oxide containing indium oxide (called indium oxide). Conductive layers 219a and 219b are connected to the low-resistance region 215n included in semiconductor layer 215 through openings provided in insulating layers 216 and 218, respectively. Furthermore, the low-resistance region 215n can also be a region with low resistance compared to the channel formation region of transistor 201A, a region with high carrier concentration, a region with high oxygen vacancy density, a region with high impurity concentration, or a region exhibiting n-type characteristics. For example, the low-resistance region 215n is a region containing impurity elements. Examples of such impurity elements include, for example, hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, and rare gases. Typical examples of rare gases include helium, neon, argon, krypton, and xenon. The low-resistance region 215n is particularly preferably composed of boron or phosphorus. Furthermore, the low-resistance region 215n may also contain two or more of the above elements.

[0371] As a metal oxide that can be used for semiconductor layer 215, indium zinc oxide, indium tin oxide, indium titanium oxide, indium gallium oxide, indium gallium aluminum oxide, indium gallium tin oxide (also denoted as IGTO), gallium zinc oxide, aluminum zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium titanium zinc oxide, indium gallium zinc oxide (also denoted as IGZO), indium gallium tin zinc oxide, indium gallium aluminum zinc oxide, etc.

[0372] As a metal oxide that can be used in semiconductor layer 215, indium oxide (also denoted as IO) can be used, for example.

[0373] Transistor 202 has a semiconductor layer 210, an insulating layer 211, a conductive layer 212B, an insulating layer 213, an insulating layer 214, an insulating layer 216, an insulating layer 218, and conductive layers 219c and 219d sequentially stacked on substrate 351. A portion of insulating layer 211 is used as the gate insulating layer of transistor 202. Conductive layer 212B is used as the top gate electrode of transistor 202. Conductive layers 219c and 219d are used as source electrodes or drain electrodes.

[0374] Semiconductor layer 210 comprises silicon, such as low-temperature polycrystalline silicon. Conductive layers 219c and 219d are connected to the low-resistance region 210p included in semiconductor layer 210 through openings provided in insulating layers 211, 213, 214, 216, and 218, respectively. The low-resistance region 210p can also be described as a region with low resistance compared to the channel formation region of transistor 202, a region with high impurity concentration, or a p-type region. For example, the low-resistance region 210p is a region containing impurity elements used to form a p-channel transistor. In the case that transistor 202 is a p-channel transistor, boron and / or aluminum can be added to the low-resistance region 210p. Furthermore, in order to control the threshold voltage of transistor 202, the aforementioned impurities can also be added to the channel formation region of transistor 202.

[0375] The components of transistors 201A and 202 other than the semiconductor layer can be formed in the same process. Therefore, even if the two types of transistors are mixed and mounted, the increase in the number of processes can be suppressed.

[0376] Materials that can be used as conductive layers for gate electrodes, source electrodes, and drain electrodes of transistors, as well as for various wiring and electrodes constituting display devices, include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or alloys with the above metals as the main component. Single layers or stacks of films containing these materials can be used.

[0377] As a transparent conductive material, conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and gallium-containing zinc oxide, or graphene, can be used. Alternatively, metallic materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, or alloys containing such metallic materials, can be used. Alternatively, nitrides of the metallic materials (e.g., titanium nitride) can also be used. Furthermore, when using metallic or alloy materials (or their nitrides), it is preferable to form them thin enough to be transparent. In addition, a multilayer film of the above-mentioned materials can be used as a conductive layer. For example, by using a multilayer film of an alloy of silver and magnesium with indium tin oxide, conductivity can be improved, so it is preferred. The above-mentioned materials can also be used as conductive layers constituting various wirings and electrodes of display devices, as well as conductive layers included in light-emitting devices (conductive layers used as pixel electrodes or common electrodes).

[0378] Examples of insulating materials that can be used in various insulating layers include resins such as acrylic resin or epoxy resin, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, or aluminum oxide.

[0379] exist Figure 44B In this configuration, the conductive layer 212A, used as the bottom gate electrode, is preferably a conductive material with light-shielding properties. Furthermore, in... Figure 44BIn this process, the area of ​​the conductive layer 212A used as the bottom gate electrode that overlaps with the semiconductor layer 215 is preferably larger than the area of ​​the conductive layer 217 used as the top gate electrode that overlaps with the semiconductor layer 215.

[0380] For example, Figure 45A The cross-sectional schematic diagram of the display device 300A1 shown includes transistor 201B, wherein Figure 44B The conductive layer 212A used as the bottom gate electrode is a conductive layer 212C used as a light-shielding layer. Figure 45A The display device 300A1 shown is a modified example of the aforementioned display device 300A. Furthermore, Figure 45B Showing includes Figure 45A An enlarged cross-sectional view of the transistor 201B is shown. With the above structure, Figure 45A and Figure 45B The conductive layer 212C used as the bottom gate electrode can be a light-shielding layer that has the function of shielding stray light from the substrate 351 side to the semiconductor layer 215. Therefore, the electrical characteristic variation of the transistor caused by stray light from the substrate 351 side to the semiconductor layer 215 can be suppressed.

[0381] Furthermore, preferably, the area of ​​the conductive layer 212C used as the bottom gate electrode overlapping with the semiconductor layer 215 is not only larger than the area of ​​the conductive layer 217 used as the top gate electrode overlapping with the semiconductor layer 215, but also larger than the area of ​​the semiconductor layer 215 itself, for example, it is arranged to cover the semiconductor layer 215 when viewed from the substrate 351 side. By adopting the above structure, the flatness of the top surface of the insulating layers 213 and 214 on which the semiconductor layer 215 is disposed can be improved, thus obtaining good electrical characteristics of the transistor. In the detailed description of the display device 300A1 and the transistor 201B, with Figure 44A and Figure 44B The display device 300A and transistor 201A shown have many identical parts, so repeated explanations are omitted.

[0382] In addition, Figure 45A In the cross-sectional schematic shown, all transistors included in the gate line-side driving circuit 364, which serves as the driving pixel, are LTPS transistors such as transistor 202. The silicon used as the semiconductor layer for the LTPS transistors can be monocrystalline silicon, polycrystalline silicon, amorphous silicon, etc., in addition to low-temperature polycrystalline silicon. LTPS transistors have high field-effect mobility and good frequency characteristics, making them particularly preferred for the gate line-side driving circuit 364.

[0383] like Figure 44AAs shown in the cross-sectional schematic diagram, at least one of the transistors included in the gate line-side driving circuit 364, which serves as the driving pixel, can also be an OS transistor such as transistors 201A or 201B. Compared to transistors using amorphous silicon, OS transistors have a much higher field-effect mobility. Furthermore, OS transistors have extremely low off-state currents, allowing them to retain the charge stored in the capacitor connected in series with the transistor for extended periods.

[0384] <Picture planar and cross-sectional views>

[0385] Figure 46 It is Figures 44A to 45B The transistors 201B and 202 shown are used in the plan view of pixel 10 described in Embodiment 1. Figure 46 The circuit structure of the 10_X pixel planar diagram is just one example and is not limited to it. Figure 47A It is along Figure 46 The cross-sectional view of the thick dashed lines X1-X2 in the figure. Figure 47B It is along Figure 46 The cross-sectional view of the thick dashed line Y1-Y2 in the figure. Figure 47C It is along Figure 46 The cross-sectional view of the thick dashed lines Z1-Z2 in the figure. Figure 48 This is a schematic diagram showing the stacking sequence of layer 62, which contains transistors, etc.; layer 63, which contains wiring such as DL and ELVDD; layer 64, which contains conductive layer 311; and layer 64, which contains a common electrode 315 used as wiring ELVSS, etc. Figure 48 In the diagram, dashed arrows indicate connections between wirings in layer 63 and the semiconductor layers of wirings or transistors in layer 62.

[0386] Figure 46 Pixel 10_X shows the transistors M11 to M17 and capacitor C1 described in Embodiment 1 above. Furthermore, Figure 46 The wiring GI, wiring GI_BG, wiring GW, wiring EM, wiring GB, wiring GC, wiring GC_BG, and wiring DL described in Embodiment 1 above are shown. Furthermore, Figure 46 The diagram shows transistors M11 to M17, capacitor C1, wiring GI, wiring GI_BG, wiring GW, wiring EM, wiring GB, wiring GC, wiring GC_BG, conductive layers BG1 to BG7 (as components of wiring DL), conductive layers ME1 to ME6, conductive layers GE1 and GE2, semiconductor layers SI1 to SI5, semiconductor layers OI1 and OI2, contact holes CO1 to CO7, contact holes BC1 and BC2, and contact hole TC1.

[0387] Conductive layers BG1 to BG7 are disposed in conjunction with Figure 44B , Figure 44C and Figure 45B The conductive layers shown are in the same layer as conductive layers 212A, 212B, and 212C. Conductive layers ME1 to ME7 are disposed in the same layer as... Figure 44B and Figure 44C The conductive layers shown are the same as those in conductive layers 219a to 219d. Conductive layers GE1 and GE2 are disposed in the same layer as... Figure 44B and Figure 44C The conductive layer shown is the same as the conductive layer 217. Semiconductor layers SI1 to SI5 are disposed in the same layer as... Figure 44B and Figure 44C The semiconductor layers shown are in the same layer as semiconductor layer 210. Semiconductor layers OI1 and OI2 are disposed in the same layer as semiconductor layer 210. Figure 44B and Figure 44C The semiconductor layer shown is the same as semiconductor layer 215. Contact holes CO1 to CO7 are openings used to connect semiconductor layers SI1 to SI5 and semiconductor layers OI1 and OI2 to conductive layers ME1 to ME7. Contact holes BC1 and BC2 are openings used to connect conductive layers ME1 to ME6 to semiconductor layers BG1 to BG7. Contact hole TC1 is an opening used to connect conductive layer ME5 to conductive layer 311 (not shown), which is disposed in the upper layer and serves as a pixel electrode.

[0388] like Figure 46 and Figure 47A As shown, conductive layer BG1 is used as the gate for wiring GW and transistor M11. Figure 46 and Figure 47A As shown, conductive layer BG2 is used as the gate for wiring EM, the gate for transistor M12, and the gate for transistor M14. Figure 46 , Figure 47B and Figure 48 As shown, the conductive layer BG3 is used as the gate of transistor M13 and the first terminal of capacitor C1. Figure 46 As shown, conductive layer BG4 is used as the back gate for wiring GC_BG and transistor M16. Figure 46 As shown, conductive layer BG5 is used as the gate for wiring GB and transistor M15. Figure 46 and Figure 47C As shown, conductive layer BG6 is used as the back gate for wiring GI_BG and transistor M17. Figure 46 and Figure 48 As shown, the conductive layer BG7 is used as the wiring INI.

[0389] like Figure 46 , Figure 47A and Figure 48 As shown, the conductive layer ME1 is used as the first terminal for wiring DL and transistor M11. Figure 46 , Figure 47A and Figure 48As shown, the conductive layer ME2 is used as the second terminal of transistor M11, the first terminal of transistor M12, and the first terminal of transistor M13. Figure 46 , Figure 47A and Figure 48 As shown, conductive layer ME3 is used as the wiring ELVDD, the second terminal of transistor M12, and the second terminal of capacitor C1. Figure 46 , Figure 47B and Figure 48 As shown, conductive layer ME4 is used as the second terminal of transistor M13, the first terminal of transistor M14, and the first terminal of transistor M16. Figure 46 and Figure 48 As shown, conductive layer ME5 is used as the second terminal of transistor M14 and the first terminal of transistor M15. Figure 46 , Figure 47C and Figure 48 As shown, conductive layer ME6 is used as the second terminal of transistor M15 and the second terminal of transistor M17. Figure 46 , Figure 47C and Figure 48 As shown, the conductive layer ME7 is used as the second terminal of transistor M16 and the first terminal of transistor M17.

[0390] like Figure 46 As shown, conductive layer GE1 is used as the gate for wiring GC and transistor M16. Figure 46 , Figure 47C As shown, the conductive layer GE2 is used as the gate for wiring GI and transistor M17.

[0391] like Figure 46 and Figure 47A As shown, contact hole CO1 is used as an opening in the insulating layer to connect semiconductor layer SI1 with conductive layers ME1 and ME2. Figure 46 and Figure 47A As shown, the contact hole CO2 is used as an opening in the insulating layer to connect the semiconductor layer SI2 with the conductive layers ME2 and ME3. Figure 46 and Figure 47B As shown, contact hole CO3 is used as an opening in the insulating layer to connect semiconductor layer SI3 with conductive layers ME2 and ME4. Figure 46 As shown, contact hole CO4 is used as an opening in the insulating layer to connect semiconductor layer SI4 with conductive layers ME4 and ME5. Figure 46 As shown, contact hole CO5 is used as an opening in the insulating layer to connect semiconductor layer SI5 with conductive layers ME5 and ME6. Figure 46 As shown, contact hole CO6 is used as an opening in the insulating layer to connect the semiconductor layer OI1 with the conductive layers ME4 and ME7. Figure 46 and Figure 47C As shown, the contact hole CO7 is used as an opening in the insulating layer to connect the semiconductor layer OI2 with the conductive layers ME6 and ME7.

[0392] like Figure 46 As shown, contact hole BC1 is used as an opening in the insulating layer to connect conductive layer ME7 and conductive layer BG3. Figure 46 and Figure 47C As shown, contact hole BC2 is used as an opening in the insulating layer to connect conductive layer ME6 and conductive layer BG7. Figure 46 and Figure 48 As shown, the contact hole TC1 is used as an opening in the insulating layer to connect the conductive layer ME5 and the conductive layer 311.

[0393] Depend on Figure 46 The floor plan shown Figures 47A to 47C Cross-sectional view and Figure 48 As shown in the schematic diagram, in pixel 10_X, the line width of the conductive layer ME3, used as the wiring ELVDD, is larger than that of other wirings, such as wiring GI, wiring GI_BG, wiring GW, wiring EM, wiring GB, wiring GC, and wiring GC_BG. By adopting this structure, the resistance of the wiring ELVDD can be reduced. Therefore, by adopting this structure, the voltage drop caused by current flowing through the wiring ELVDD can be reduced.

[0394] Depend on Figure 46 The floor plan shown Figures 47A to 47C Cross-sectional view and Figure 48 As shown in the schematic diagram, in pixel 10_X, the conductive layer GE1 used for wiring GC overlaps with the conductive layer BG4 used for wiring GC_BG. Furthermore, the linewidth of the upper conductive layer GE1 is set to be smaller than the linewidth of the conductive layer BG4 used for wiring GC_BG. By adopting this structure, the resistance of the conductive layer BG4 can be made lower than the resistance of the conductive layer GE1. Compared to the conductive layer GE1, the conductive layer BG4 has a larger overlap area with other conductive layers or semiconductor layers, resulting in a larger parasitic capacitance. Therefore, by adopting this structure, the voltage drop caused by current flowing through wiring GC_BG can be made smaller than the voltage drop caused by current flowing through wiring GC.

[0395] Depend on Figure 46 The floor plan shown Figures 47A to 47C Cross-sectional view and Figure 48As shown in the schematic diagram, in pixel 10_X, conductive layers ME1 to ME7 disposed in layer 63 connect transistors M11 to M15, which are LTPS transistors, and transistors M16 and M17, which are OS transistors. Compared to a structure where conductive layers for connecting transistors are disposed across multiple layers, using conductive layers disposed in the same layer simplifies the process for transistors M11 to M17, thus potentially increasing the yield.

[0396] Depend on Figure 46 The floor plan shown Figures 47A to 47C Cross-sectional view and Figure 48 As shown in the schematic diagram, in pixel 10_X, the transistors are arranged in a manner that overlaps with a portion of the conductive layer branching off from the conductive layer that serves as the gate or back gate of transistors M11 to M17 in one direction. By adopting this structure, design freedom can be increased compared to structures where transistors are arranged on conductive layers extending in one direction.

[0397] Depend on Figure 46 The floor plan shown Figures 47A to 47C Cross-sectional view and Figure 48 As shown in the schematic diagram, in pixel 10_X, conductive layer BG7, used as wiring INI, and conductive layer ME3, used as wiring ELVDD, are disposed at the boundary of pixel 10_X. Conductive layer BG7 and conductive layer ME3 are used for wiring supplied with a constant potential. Therefore, by adopting this structure, noise caused by potential fluctuations in the wiring of adjacent pixels can be suppressed.

[0398] In addition to the effects mentioned above, it also... Figure 46 The floor plan shown Figures 47A to 47C Cross-sectional view and Figure 48 As can be seen from the schematic diagram, in pixel 10_X, for example, as a low-level potential for the control signal supplied to the back gate of M16 and M17, which are OS transistors, the V of the wiring INI can be used. INI The voltage between the back gate and source of transistors M16 and M17 can be set to a negative voltage. This can suppress fluctuations in the threshold voltage of transistors M16 and M17, thereby improving the long-term reliability of the transistors. This can improve the reliability of display devices including these transistors.

[0399] Figure 49 It has the same Figure 46 The diagram shown is a plan view of different structures of the pixels of pixel 10 that can be used in embodiment 1. Figure 50A It is along Figure 49 The cross-sectional view of the thick dashed lines X3-X4 in the figure. Figure 50B It is along Figure 49 The cross-sectional view of the thick dashed line Y3-Y4 in the figure. Figure 50CIt is along Figure 49 The cross-sectional view along the thick dashed lines Z3-Z4. Figure 49 The description of the floor plan shown omits... Figure 46 The plan shown repeatedly illustrates the same constituent elements. Figure 49 The description of each transistor included in pixel 10_Y and Figures 44A to 45B The descriptions of transistors 201A, 201B, and 202 shown are mostly the same, so their descriptions are omitted.

[0400] Note that in Figures 50A to 50C shown Figure 49 In the cross-sectional view of the specified part, it is shown that... Figures 47A to 47C shown Figure 46 The cross-sectional views of the specified parts are different from those of the specified parts. For example, in Figure 50A In the cross-sectional view, in addition to transistors M11 and M12, an opening MH1 disposed in the conductive layer ME3 is also shown. Furthermore, for example in... Figure 50B In the cross-sectional view, besides transistor M13, capacitor C1 is also shown, disposed between conductive layer BG3 and conductive layer ME3. Furthermore, for example in... Figure 50C In the cross-sectional view, in addition to transistor M17, an opening MH4 disposed in conductive layer ME3 is also shown.

[0401] Figure 49 and Figures 50A to 50C The structure shown in the plan view and cross-sectional view is similar to Figure 46 The difference in the structure of the planar diagram shown lies in the configuration of transistor M12. Furthermore, in Figure 49 The structure of the plan shown is Figure 46 The difference in the structure of the plan view shown is that: the area where the conductive layer ME3, which is used as the wiring ELVDD, overlaps with the conductive layers BG1, BG2, BG3, BE1, BG4, BG5, BG6, BE2 and BG7 includes openings MH1 to MH4.

[0402] By positioning transistor M12 close to transistor M11, the length of the conductive layer ME2 between transistors M11 and M13, and between transistors M12 and M13, can be shortened. The conductive layer ME2 intersects with the conductive layer BG2, which serves as the wiring EM for supplying control signals. Therefore, this structure reduces signal delay or waveform distortion transmitted to the conductive layer ME2. This structure is effective for wiring transistors connected to transistors M13 and M14, M15 and M17, etc., that intersect with other conductive layers BG1 to BG7.

[0403] By including openings MH1 to MH4 in the region of conductive layer ME3 that overlaps with conductive layers BG1, BG2, BG3, BE1, BG4, BG5, BG6, BE2, and BG7, the cross capacitance between the wiring GI, wiring GI_BG, wiring GW, wiring EM, wiring GB, wiring GC, wiring GC_BG transmitting various control signals and the wiring ELVDD transmitting VDD can be reduced. For example, by... Figure 50A As shown, the opening MH1 is set in such a way that the conductive layer ME3 on the conductive layer BG1 used as the wiring GW is removed, and as shown... Figure 50C By setting the opening MH4 in such a way as shown, by removing the conductive layer ME3 on the conductive layer GE2 used for wiring GI and the conductive layer BG6 used for wiring GI_BG, parasitic capacitance caused by wiring crossings can be reduced. Therefore, by adopting this structure, noise, signal delay, or waveform distortion introduced into the transmitted control signals can be reduced.

[0404] Figure 50B The capacitor C1, which is formed by overlapping the conductive layer ME3 and the conductive layer BG3, can also be configured in multiple parts as needed. Furthermore, by employing a structure that increases the parasitic capacitance of the conductive layer ME3, the capacitor C1 can be omitted. Additionally, although in Figure 49 and Figure 50B In one configuration, capacitor C1 is constructed by stacking conductive layers ME3 and BG3. However, capacitor C1 can also be constructed by placing other conductive layers, such as those in the same layers as wirings GE1 and GE2, at a position overlapping conductive layer BG3. By employing this structure, the thickness of the insulating layer between the conductive layers can be reduced, thereby enabling the construction of capacitors with large capacitance values.

[0405] Note, refer to Figure 49 floor plan Figures 50A to 50C The cross-sectional view illustrates that pixel 10_Y has the same features as pixel 10_X. Therefore, in addition to the effects described above, it can also have the effects illustrated in Figure 10_X. Furthermore, the structures of pixel 10_Y can be combined with the structures of pixel 10_X.

[0406] Figure 51 It has the same Figure 46 and Figure 49 The plan view of the pixel 10 in Embodiment 1 is described in the figure, showing different structures of the pixel plan view. Figure 52A It is along Figure 51 The cross-sectional view of the thick dashed lines X5-X6 in the figure. Figure 52B It is along Figure 51 The cross-sectional view of the thick dashed lines Y5-Y6 in the figure. Figure 52C It is along Figure 51 The cross-sectional view of the thick dashed lines Z5-Z6 in the diagram. Figure 51 The description of the floor plan shown omits... Figure 46 and Figure 49 The plan shown repeatedly illustrates the same constituent elements. Figure 51 The description of each transistor included in pixel 10_Z and Figures 44A to 45B The descriptions of transistors 201A, 201B, and 202 shown are mostly the same, so their descriptions are omitted.

[0407] Note that in Figures 52A to 52C shown Figure 51 In the cross-sectional view of the specified part, it is shown that... Figures 47A to 47C shown Figure 46 Cross-sectional view of the specified part and Figures 50A to 50C shown Figure 49 The cross-sectional views of the specified parts are different from those of the specified parts. For example, in Figure 52A The cross-sectional view shows transistors M11 and M14. Furthermore, for example, in... Figure 52B The cross-sectional view shows a structure with... Figure 46 and Figure 49 Cross-sectional views of transistor M13 with different structures. Furthermore, for example, in... Figure 52C The cross-sectional view of transistor M15 is shown instead of that of transistor M17.

[0408] Figure 51 and Figures 52A to 52C The structure shown in the plan view and cross-sectional view is similar to Figure 46 and Figure 49 The difference in the planar diagram shown lies in the shape of the semiconductor layer SI3 of transistor M13. For example... Figure 51 and Figure 52B As shown, transistor M13 has a structure in which the semiconductor layer SI3 is bent between the source and drain. By employing this structure, the channel length of transistor M13 can be greater than that of other transistors, such as transistors M11, M12, M14, or M15. Transistor M13, used as a driving transistor, is preferably a transistor capable of allowing current corresponding to the data voltage to flow through it. Therefore, transistor M13 preferably has good electrical characteristics (also called "saturation characteristics") in the saturation region. By employing transistor M13 with a long channel length, a transistor with good saturation characteristics can be realized. The channel length can be determined from the region where the semiconductor layer and the conductive layer overlap.

[0409] In addition, Figure 51 and Figures 52A to 52CIn the plan and cross-sectional views shown, the area where the conductive layer BG3, used as the gate of transistor M13, overlaps with the semiconductor layer SI3 is preferably larger than the area where the conductive layer BG1, used as the gate of transistor M11, overlaps with the semiconductor layer SI1. By employing this structure, the channel width of the transistor can be increased, and the amount of current flowing through transistor M13 can be increased. The channel width can be determined from the area where the semiconductor layer and the conductive layer overlap.

[0410] Note, refer to Figure 51 The floor plan shown and Figures 52A to 52C The cross-sectional view illustrates that pixel 10_Z has the same features as pixel 10_X or pixel 10_Y. Therefore, in addition to the effects described above, it can also have the effects illustrated in FIG10_X or pixel 10_Y. Furthermore, the structures of pixel 10_Z can be combined with the structures of pixel 10_X or pixel 10_Y.

[0411] This implementation method can be appropriately combined with other implementation methods.

[0412] (Implementation Method 3)

[0413] In this embodiment, the indium oxide film of the semiconductor layer of the transistor included in a display device that can be used in one aspect of the present invention will be described.

[0414] Note that in this specification, etc., indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). For example, monocrystalline indium oxide, polycrystalline indium oxide, microcrystalline indium oxide, etc. can be cited as crystal IO or crystalline IO.

[0415] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also known as IGZO) and zinc oxide.

[0416] The carrier concentration dependence of Hall mobility for indium oxide, silicon, and IGZO is explained. Figure 53A It concerns silicon (Si) and indium oxide (InO). X A schematic diagram illustrating the carrier concentration dependence of Hall mobility. Figure 53B This is a schematic diagram showing the carrier concentration dependence of Hall mobility in IGZO.

[0417] First, such as Figure 53B As indicated by the arrows, IGZO tends to exhibit higher Hall mobility with higher carrier concentrations. On the other hand, as... Figure 53AAs indicated by the arrows, indium oxide (INO) tends to exhibit higher Hall mobility with lower carrier concentrations (see Non-Patent Literature 1). This tendency is similar to that of silicon; the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs, and the higher the Hall mobility. In other words, in INO, higher purity and more intrinsic properties result in higher Hall mobility. From this result, it can be concluded that, unlike IGZO, INO possesses properties close to those of silicon. Note that... Figure 53A The properties of indium oxide shown are those assuming a single crystal. Therefore, when indium oxide is not a single crystal (e.g., polycrystalline), its properties may differ. Figure 53A The characteristics shown are different.

[0418] exist Figure 53A In this context, the range R1, characterized by low carrier concentration, represents a range with extremely high Hall mobility. Therefore, it can be considered, for example, a suitable range of carrier concentrations for use in the channel formation region of a transistor. For instance, in indium oxide, the range R1 includes carrier concentrations of 1 × 10⁻⁶. 15 cm -3 The range, for example, is 1×10 14 cm -3 Above and 1×10 18 cm -3 The following range. By sufficiently reducing the carrier concentration, it is expected that the Hall mobility value can be increased to 270 cm⁻¹. 2 / (V) (s) around.

[0419] Furthermore, in indium oxide, the region with a carrier concentration in the range R1 can contain elements that reduce the carrier concentration. Examples of elements that reduce carrier concentration include magnesium, calcium, zinc, cadmium, and copper. Replacing indium with these elements reduces the carrier concentration. Other examples of elements that reduce carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, replacing oxygen with nitrogen, phosphorus, arsenic, or antimony reduces the carrier concentration.

[0420] On the other hand, the range of high carrier concentration R2 is the range of low resistance; for example, it can be said to be the range of carrier concentrations suitable for use in the source and drain regions of transistors, resistive bodies, or transparent conductive films. The range R2 includes carrier concentrations of 1 × 10⁻⁶. 20 cm -3 The range, for example, is 1×10 19 cm -3 Above and 1×10 22 cm -3 The following range. By significantly increasing the carrier concentration, it is expected that the resistivity can be reduced to 1 × 10⁻⁶. -4 Ω Less than cm.

[0421] Furthermore, in indium oxide, the region with a carrier concentration in the range R2 can contain elements that increase the carrier concentration. For example, it is preferable to include the same elements as the source and drain electrodes of the transistor. Examples of such elements include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements whose oxides have conductive or semiconductor properties.

[0422] Thus, in indium oxide (IO), regions with low carrier concentration are used for the channel formation region of the transistor, while regions with high carrier concentration are used for the source and drain regions. In other words, IO can also be considered an oxide capable of controlling valence electrons. Note that in IGZO, strain sometimes forms in the source and drain regions due to the stress of the electrodes in contact with the IGZO, resulting in n-type regions. On the other hand, unlike IGZO, IO can control valence electrons, so strain can be formed in the film as little as in IGZO. When the strain in the film is low, improved reliability can be expected. For example, by forming carrier concentrations of [missing information] in the IO film... Figure 53A The regions R1 and R2 shown can form a so-called nin junction (a combination of n-type, i-type, and n-type regions). Note that valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technical concept that is not usually considered.

[0423] By utilizing the above-described technical concept, the indium oxide-containing transistor in this specification, etc., has two or more of the following features (1) to (5), preferably three or more, more preferably four or more, and most preferably five. (1) High on-state current (in other words, high mobility). (2) Low off-state current. (3) Can be normally off. (4) Has high reliability. (5) High cutoff frequency (fT). For example, the indium oxide-containing transistor in this specification, etc., has high mobility and low off-state current and can be normally off. This transistor is different from a transistor with high mobility that is normally on.

[0424] Next, an indium oxide film for transistors will be described. The indium oxide film preferably has crystalline properties (i.e., contains grains). Examples of grain-containing films include monocrystalline films, polycrystalline films, and amorphous films containing grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a monocrystalline film. Monocrystalline films do not have grain boundaries (also called grain boundaries). Impurities that impede carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at grain boundaries. By using a monocrystalline film, carrier scattering at grain boundaries can be suppressed, thereby enabling transistors with high field-effect mobility. Furthermore, it exhibits excellent effects such as suppressing non-uniformity in transistor characteristics caused by these grain boundaries.

[0425] Furthermore, compared to microcrystalline or amorphous films, polycrystalline films can reduce carrier scattering and exhibit high field-effect mobility, making them preferred. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. Note that in transistors using polycrystalline indium oxide films, if there are no grain boundaries or no grain boundaries are observed in the channel formation region, since the channel formation region is located within the single-crystal region contained in the polycrystalline film, it can be considered as a transistor using single-crystal indium oxide.

[0426] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods can be used for analysis.

[0427] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is included in a single grain, or a semiconductor layer in which the crystal axis orientation is the same in at least two regions of the channel formation region, may be referred to as a single crystal film. Additionally, a semiconductor layer in which the orientation of other crystal axes continuously changes within a single grain in the channel formation region, with a certain crystal axis or a certain crystal orientation as the axis of rotation, may also be referred to as a single crystal film.

[0428] Note that the channel formation region refers to the area in the semiconductor layer that overlaps (or is opposite) to the gate electrode across the gate insulating layer, and specifically the region located between the area contacting the source electrode and the area contacting the drain electrode. The current path in the channel formation region is the shortest distance between the source and drain electrodes. Therefore, in cross-sectional observation including the semiconductor layer, source electrode, and drain electrode, grains, grain boundaries, grain axes, crystal orientations, etc., can be identified in the channel formation region.

[0429] The lower the impurity concentration of the indium oxide film in the channel formation region, the better. Impurities in the indium oxide film in the channel formation region can act as sources of carrier scattering, thus potentially reducing the field-effect mobility. Furthermore, these impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that carbon, hydrogen, etc., are elements that may be contained in the deposition gas or precursors during deposition; sometimes, the amount of carbon, hydrogen, etc., remaining in the indium oxide film is greater than that of the aforementioned impurities.

[0430] By using this indium oxide film in transistors, the field-effect mobility of the transistor can be increased to 50 cm⁻¹. 2 / (V) s) or more, preferably 100cm 2 / (V) s) or more, more preferably 150cm 2 / (V) s) or above, more preferably 200cm 2 / (V) s) and above, and even more preferably 250cm 2 / (V) s) and above.

[0431] One characteristic of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example... Figure 53C As shown, diffusion occurs into the indium oxide film (referred to as InO). X Oxygen (O) permeates through the indium oxide membrane and is released as oxygen molecules (O2). Additionally, it is sometimes released as water molecules (H2O) by reacting with hydrogen contained in the membrane. Furthermore, when oxygen vacancies (V) are present in the membrane... o When oxygen diffuses, it fills the oxygen vacancies. Because oxygen diffuses easily, indium oxide films can be said to fill oxygen vacancies more easily than IGZO films.

[0432] Thus, compared to IGZO films, indium oxide films are easier to reduce oxygen vacancies in the film. Therefore, by using this indium oxide film in transistors, transistors with extremely high reliability can be realized.

[0433] In addition, such as Figure 53C As shown, hydrogen diffuses through the indium oxide membrane. Hydrogen diffuses from the outside into the indium oxide membrane and is released as hydrogen molecules (H2) through the membrane. Alternatively, the hydrogen reacts with oxygen contained in the membrane and is released as water molecules.

[0434] Transistors using indium oxide (IO) films are accumulation-type transistors where electrons are the majority carriers. Assuming a fixed relaxation time for the carriers, the smaller the effective mass of the electrons (charge carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective electron mass, in transistors, the on-state current or field-effect mobility of the transistor can be improved.

[0435] Table 1 shows the effective mass of single-crystal indium oxide (In₂O₃) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Furthermore, indium oxide also has the characteristic that the effective mass of electrons is almost independent of crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also known as f-characteristics) can be realized. Moreover, due to the large effective mass of holes, transistors with extremely low off-state currents can be realized. For example, by using an indium oxide film in a vertical transistor, the off-state current per channel width of 1 μm can be 1 fA (1 × 10⁻⁶) at 125°C. -15 A) or below or 1aA (1×10 -18 A) Below this, at room temperature (25°C), the off-state current per channel width of 1 μm can be 1 A (1 × 10⁻⁶). -18 A) or below or 1zA (1×10 -21 A) Below. Furthermore, as shown in Table 1, compared to silicon, indium oxide has a smaller effective electron mass and a larger effective hole mass, making it possible to realize transistors with higher field-effect mobility and lower off-state current compared to Si transistors.

[0436] [Table 1]

[0437] As a layer in contact with at least a portion of the crystalline indium oxide film (hereinafter referred to as the seed layer), it is preferable to use a material containing crystals with a small difference (also referred to as lattice mismatch) from the lattice constant of indium oxide. This improves the crystallinity of the indium oxide film. Furthermore, a substrate (e.g., a single-crystal substrate) may also be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0438] One method for evaluating lattice mismatch is to use the lattice mismatch value shown below. The lattice mismatch Δa[%] of the crystals contained in the formed film (in this case, an indium oxide film) relative to the crystals contained in the seed layer is calculated as Δa = ((L1-L2) / L2) × 100. Here, L1 represents the length of the cell vector or lattice constant of the crystals contained in the formed film, and L2 represents the length of the cell vector or lattice constant of the crystals contained in the seed layer.

[0439] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the better, and most preferably 0. For example, Δa can be -5% or more and less than 5%, preferably -4% or more and less than 4%, more preferably -3% or more and less than 3%, and even more preferably -2% or more and less than 2%.

[0440] Here, indium oxide crystals exhibit a cubic crystal structure (manganese ferrophosphate type). For example, yttrium-stabilized zirconia (YSZ) crystals can exhibit a cubic crystal structure (fluorite type). Compared to YSZ crystals with a cubic crystal structure, indium oxide has a lattice mismatch in the range of -2% to 2%, allowing for the epitaxial growth of single-crystal indium oxide films on YSZ substrates.

[0441] Note that the crystal system or crystal orientation of the seed layer and the indium oxide film can also be different. For example, a film containing crystals with a hexagonal or trigonal crystal structure can be used under an indium oxide film containing crystals with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the bottom surface of the indium oxide film to

[111] , the crystal orientation requirements for epitaxial growth can be met. Examples of hexagonal or trigonal crystal systems include wurtzite-type structures, YbFe2O4-type structures, Yb2Fe3O7-type structures, and their variants. IGZO is an example of a crystal with a YbFe2O4-type structure or a Yb2Fe3O7-type structure.

[0442] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0443] (Implementation Method 4)

[0444] In this embodiment, an electronic device according to one aspect of the present invention will be described with reference to FIGS. 54 to 56. The electronic device of this embodiment includes a display device according to one aspect of the present invention in its display unit. The display device according to one aspect of the present invention is easily made to achieve high definition and high resolution. Therefore, it can be used in the display units of various electronic devices.

[0445] As electronic devices, in addition to large-screen electronic devices such as television sets, desktop or laptop personal computers, monitors for computers, digital signage, and large game machines such as pinball machines, other examples include digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices.

[0446] Figure 54A The electronic device 6500 shown is a portable information terminal device that can be used as a smartphone.

[0447] Electronic device 6500 includes a frame 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508, etc. The display unit 6502 has a touch panel function.

[0448] The display unit 6502 can use a display device according to one aspect of the present invention.

[0449] Figure 54B It is a cross-sectional schematic diagram of one end of the microphone 6506, including the frame 6501.

[0450] A light-transmitting protective component 6510 is provided on one side of the display surface of the frame 6501. The space surrounded by the frame 6501 and the protective component 6510 contains a display panel 6511, an optical component 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc.

[0451] The display panel 6511, optical component 6512, and touch sensor panel 6513 are fixed to the protective component 6510 using an adhesive layer (not shown).

[0452] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back, and this folded portion is connected to an FPC 6515. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to terminals disposed on a printed circuit board 6517.

[0453] The display panel 6511 can be a flexible display. This allows for the realization of extremely lightweight electronic devices. Furthermore, because the display panel 6511 is extremely thin, a large-capacity battery 6518 can be installed while minimizing the thickness of the electronic device. Additionally, by folding back a portion of the display panel 6511 to provide a connection to the FPC 6515 on the back of the pixel section, a narrow-bezel electronic device can be achieved.

[0454] Figure 55A An example of a television device is shown. In the television device 7100, a display unit 7000 is assembled in a frame 7101. Here is shown the structure in which the frame 7101 is supported by a bracket 7103.

[0455] A display device according to one aspect of the present invention can be applied to the display unit 7000.

[0456] It can be operated using the operating switches provided in the housing 7101 and the separately provided remote control 7111. Figure 55A The operation of the television device 7100 shown is illustrated. Alternatively, a touch sensor may be included in the display unit 7000, allowing operation of the television device 7100 by touching the display unit 7000 with a finger or similar object. Furthermore, a display unit for displaying information output from the remote control 7111 may be included in the remote control 7111. Channel and volume adjustments can be made using the operation keys or touch panel provided in the remote control 7111, and the images displayed on the display unit 7000 can also be manipulated.

[0457] Furthermore, the television device 7100 includes a receiver and a modem. It can receive general television broadcasts using the receiver. Moreover, it can connect to a wired or wireless communication network via the modem, enabling one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0458] Figure 55B An example of a notebook computer is shown. The notebook computer 7200 includes a chassis 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. A display unit 7000 is assembled in the chassis 7211.

[0459] A display device according to one aspect of the present invention can be applied to the display unit 7000.

[0460] Figure 55C and Figure 55D Here is an example of digital signage.

[0461] Figure 55C The digital sign 7300 shown includes a frame 7301, a display unit 7000, and a speaker 7303. It may also include LEDs, operation buttons (including a power switch or operation switch), connection terminals, various sensors, a microphone, etc.

[0462] Figure 55D A digital sign 7400 is shown mounted on a cylindrical column 7401. The digital sign 7400 includes a display section 7000 disposed along the curved surface of the column 7401.

[0463] exist Figure 55C and Figure 55D In this embodiment, a display device according to one aspect of the present invention can be used in the display unit 7000.

[0464] The larger the display unit 7000, the more information it can provide at once. Furthermore, a larger display unit 7000 is more likely to attract attention, thus improving the effectiveness of advertising.

[0465] By using a touch panel in the display unit 7000, not only can static or dynamic images be displayed on the display unit 7000, but users can also operate it intuitively, making it preferable. Furthermore, when used to provide information such as route information or traffic information, intuitive operation enhances ease of use.

[0466] like Figure 55C and Figure 55DAs shown, digital signage 7300 or digital signage 7400 preferably connects wirelessly with information terminal devices 7311 or 7411, such as smartphones carried by the user. For example, advertising information displayed on display unit 7000 can be displayed on the screen of information terminal device 7311 or information terminal device 7411. Furthermore, the display on display unit 7000 can be switched by operating information terminal device 7311 or information terminal device 7411.

[0467] The game can be executed on the digital signage 7300 or 7400 using the screen of information terminal device 7311 or 7411 as the operating unit (controller). Thus, multiple users can participate in the game simultaneously and enjoy the experience.

[0468] Figures 56A to 56G The electronic device shown includes a frame 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), a connection terminal 9006, a sensor 9007 (which has the function of measuring the following factors: force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation), a microphone 9008, etc.

[0469] Figures 56A to 56G The electronic device shown has various functions. For example, it may have the following functions: displaying various information (still images, moving images, text images, etc.) on a display unit; a touch panel function; displaying a calendar, date, or time; controlling processing using various software (programs); wireless communication function; reading and processing programs or data stored in a storage medium; etc. Note that the functions of the electronic device are not limited to the above functions, but can have various functions. The electronic device may also include multiple display units. In addition, a camera or the like may be installed in the electronic device to give it the following functions: capturing still or moving images and storing the captured images in a storage medium (external storage medium or storage medium built into the camera); displaying the captured images on a display unit; etc.

[0470] The following is an explanation Figures 56A to 56G Details of the electronic device shown.

[0471] Figure 56AThis is a perspective view showing a portable information terminal 9101. For example, the portable information terminal 9101 can be used as a smartphone. Note that a speaker 9003, a connection terminal 9006, a sensor 9007, etc., may also be included in the portable information terminal 9101. Furthermore, as a portable information terminal 9101, text or image information can be displayed on multiple surfaces. Figure 56A The image shows an example displaying three icons 9050. Furthermore, information 9051, shown as a dashed rectangle, can be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of incoming emails, SNS messages, or phone calls; the subject of the email or SNS message; the sender's name; the date; the time; remaining battery level; and radio wave strength. Alternatively, icons 9050 can be displayed in the same location where information 9051 is displayed.

[0472] Figure 56B This is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has the function of displaying information on three or more surfaces of the display unit 9001. Here, examples are shown where information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, when the portable information terminal 9102 is placed in a jacket pocket, the user can check the information 9053 displayed in a position seen from above the portable information terminal 9102. For example, the user can check this display without taking the portable information terminal 9102 out of their pocket, thereby determining whether to answer a phone call.

[0473] Figure 56C This is a perspective view of a tablet terminal 9103. The tablet terminal 9103 can, for example, execute various application software such as mobile phone, email, and article reading and editing, music playback, network communication, and computer games. The tablet terminal 9103 includes a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of the frame 9000; operation keys 9005 used as buttons for operation are included on the left side of the frame 9000; and a connection terminal 9006 is included on the bottom surface.

[0474] Figure 56D This is a perspective view showing a watch-type portable information terminal 9200. For example, the portable information terminal 9200 can be used as a smartwatch (registered trademark). Furthermore, the display surface of the display unit 9001 is curved, allowing display along its curved surface. Additionally, the portable information terminal 9200 can perform hands-free calls, for example, by communicating with a headset capable of wireless communication. Furthermore, by utilizing the connection terminal 9006, the portable information terminal 9200 can transmit data or charge with other information terminals. Furthermore, charging can also be performed wirelessly.

[0475] Figures 56E to 56G This is a perspective view showing the foldable portable information terminal 9201. Furthermore, Figure 56E This is a 3D diagram showing the 9201 portable information terminal unfolded. Figure 56G It is a 3D image of the folded state. Figure 56F From Figure 56E status and Figure 56G This is a three-dimensional view of the state transitioning from one state to another. The portable information terminal 9201 is highly portable in its folded state, and offers excellent browsing capabilities in its unfolded state due to its large, seamlessly integrated display area. The display unit 9001 included in the portable information terminal 9201 is supported by three frames 9000 connected by hinges 9055. For example, the display unit 9001 can be bent within a radius of curvature of 0.1 mm or more and 150 mm or less.

[0476] This implementation method can be appropriately combined with other implementation methods.

[0477] (Notes regarding the contents of this instruction manual, etc.)

[0478] Below, additional notes are added to the descriptions of the above embodiments and the structures in those embodiments.

[0479] The structures shown in each embodiment can be appropriately combined with the structures shown in other embodiments to constitute a mode of the present invention. Furthermore, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0480] Furthermore, the content (or a portion thereof) described in one embodiment may be applied, combined, or replaced with other content (or a portion thereof) described in that embodiment and / or content (or a portion thereof) described in one or more other embodiments.

[0481] The content described in the embodiments refers to the content described in each embodiment using various accompanying drawings or the content described in the instruction manual.

[0482] Furthermore, more figures can be formed by combining the figures (or portions thereof) shown in one embodiment with other portions of the figures, other figures (or portions thereof) shown in that embodiment, and / or figures (or portions thereof) shown in one or more other embodiments.

[0483] In this specification, components are categorized according to function and represented by independent boxes in block diagrams. However, in actual circuits, it is difficult to categorize components according to function; sometimes a circuit involves multiple functions or multiple circuits involve a single function. Therefore, the division of boxes in block diagrams is not limited to the components described in the specification and can vary appropriately.

[0484] In the accompanying drawings, sizes, layer thicknesses, or areas are sometimes exaggerated for clarity. Therefore, the invention is not limited to the dimensions shown in the drawings. The drawings are shown in arbitrary sizes for clarity and are not limited to the shapes or values ​​shown. For example, they may include non-uniformity in signals, voltages, or currents caused by noise or timing deviations.

[0485] In this specification and other materials, when describing the connection relationship of transistors, the terms "one of the source and drain" (first electrode or first terminal) and "the other of the source and drain" (second electrode or second terminal) are used. This is because the source and drain of a transistor are interchangeable depending on the transistor's structure or operating conditions. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminals or source (drain) electrodes, etc.

[0486] Furthermore, in this specification and other documents, "electrode" and "wiring" do not functionally limit their constituent elements. For example, sometimes an "electrode" is used as part of a "wiring," and vice versa. Moreover, "electrode" and "wiring" also include cases where multiple "electrodes" and "wiring" are formed as a single unit.

[0487] Furthermore, voltage and potential can be interchanged appropriately in this instruction manual and other documents. Voltage refers to the potential difference between the voltage and a reference potential. For example, when the reference potential is ground voltage (ground voltage), voltage can be replaced with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential supplied to wiring, etc., sometimes varies according to the reference potential.

[0488] In this specification and other materials, terms such as "film" and "layer" are interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Or, "insulating film" may sometimes be replaced with "insulating layer."

[0489] In this specification and the like, a switch refers to a component that controls whether current flows by changing to a conducting state (on state) or a non-conducting state (off state). Alternatively, a switch refers to a component that selects and switches current paths.

[0490] In this specification, for example, channel length refers to the distance between the source and drain in the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on-state) and gate overlap or in the region forming the channel in a plan view of the transistor.

[0491] In this specification, for example, the channel width refers to the length of the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on state) and the gate electrode overlap, or the length of the portion of the region in which the source and drain electrodes of the channel are opposite each other.

[0492] In this specification, the "on state" of a transistor refers, for example, to a state in which the source and drain of the transistor are short-circuited. For example, the following states are sometimes referred to as the "on state": in an n-channel transistor, the voltage between the gate and source is higher than the threshold voltage; or in a p-channel transistor, the voltage between the gate and source is lower than the threshold voltage, etc. Note that the "on state" of a transistor refers to a state that allows current to flow between the source and drain. Therefore, sometimes a transistor being in the "on state" is referred to as a transistor being in the "conduction state."

[0493] In this specification and other materials, the "off state" of a transistor refers to a state in which the source and drain of the transistor are disconnected. For example, the following states are sometimes referred to as the "off state": in an n-channel transistor, the voltage between the gate and source is lower than the threshold voltage; or in a p-channel transistor, the voltage between the gate and source is higher than the threshold voltage, etc. Furthermore, sometimes the transistor being in the "off state" is referred to as the transistor being in the "non-conducting state".

[0494] In this specification and other materials, the voltage between the gate and the source (gate-source) is sometimes referred to as the "gate voltage," the voltage between the drain and the source (drain-source) is sometimes referred to as the "drain voltage," and the voltage between the back gate and the source (back gate-source) is sometimes referred to as the "back gate voltage." In addition, the current flowing from the drain to the source is sometimes referred to as the "drain current."

[0495] In this specification, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in the off state. Note that in this specification, the off-state current and the current flowing from the gate to the source and drain (also called gate leakage current) are sometimes referred to as leakage current.

[0496] In this specification, the term "connection" includes, for example, "electrical connection." When "electrical connection" is used to describe the connection relationship of circuit elements as an object, it includes, for example, "direct connection" and "indirect connection." "A and B directly connected" means, for example, that A and B are connected without being connected by circuit elements (e.g., transistors or switches, rather than wiring). On the other hand, "A and B indirectly connected" means, for example, that A and B are connected through more than one circuit element.

[0497] Here, the term "indirectly connected between A and B" refers to a connection relationship in the following ways: That is, when it is assumed that the circuit is operating, and there is a sequence of events such as the exchange of electrical signals or the interaction of potentials between A and B during the circuit's operation, such a circuit can be defined as an object "indirectly connected between A and B." Furthermore, even if there is no sequence of events where there is an exchange of electrical signals or the interaction of potentials between A and B, but there is still a sequence of events where there is an exchange of electrical signals or the interaction of potentials between A and B during the circuit's operation, it can still be defined as "indirectly connected between A and B." Note that the expression "indirectly connected between A and B" defines the connection relationship of circuit elements as an object. Therefore, for example, even if the circuit is not operating because it is not supplied with a power supply voltage, the circuit can still be defined as an object "indirectly connected between A and B" (however, this is limited, for example, to the case where, when the circuit is operating because it is supplied with a power supply voltage, there is an exchange of electrical signals or the interaction of potentials between A and B during the circuit's operation).

[0498] The following are specific examples of "indirect connection". First, as an example of "A and B being indirectly connected", there is... Figure 57A1 and Figure 57A2Examples of indirect A-B connections include those where A and B are connected via the source and drain of one or more transistors. Other examples of indirect A-B connections include those where A and B are connected via one or more switches. In the case of indirect A-B connections, assuming the circuit is operational, at least one transistor between A and B must be in an on-state, a conducting state, or a state where current can flow at least once. Furthermore, in the case of indirect A-B connections, there are also cases where one transistor between A and B must be in a off-state or a non-conducting state. In the case of indirect A-B connections, if multiple transistors are connected between A and B, assuming the circuit is operational, each of the multiple transistors between A and B must be in an on-state, a conducting state, or a state where current can flow at least once. In other words, in the case of indirect A-B connections, multiple transistors do not necessarily need to be in an on-state, a conducting state, or a state where current can flow simultaneously. Therefore, in the case of "A and B being indirectly connected," this includes situations where multiple transistors between A and B simultaneously or at different times become off or non-conducting. As another example, such as... Figure 57A3 As shown, when A and C are connected through the source and drain of transistor TrP and B and C are connected through the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected", "B and C are indirectly connected", or "A and B are indirectly connected". Note that, as described below, when a fixed potential V is supplied to C from the power supply or GND, etc., although it can be said that "A and C are indirectly connected" or "B and C are indirectly connected", it is not possible to say that "A and B are indirectly connected".

[0499] The above examples illustrate situations where "indirect connection" can or cannot be described. However, the following examples show situations where "indirect connection" cannot be described. Even when electrical signals are exchanged or potentials interact between A and B during circuit operation, there are exceptions where "A and B are indirectly connected" cannot be described. An example of this exception is when A and B are connected through an insulator. That is, when A and B are connected through an insulator, "A and B are indirectly connected" cannot be described. Specific examples of A and B being connected through an insulator include... Figure 57A4 The case shown illustrates a capacitor connected between A and B. Other examples of A and B being connected via an insulator include... Figure 57A5 This refers to a situation where a gate insulating film of a transistor is sandwiched between A and B, as shown. In this case, it is not permissible to say that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected".

[0500] As another example where it's inappropriate to say "A and B are indirectly connected," cases where there is no exchange of electrical signals or interaction of electrical potentials between A and B can be cited. For example, the following situations exist: Figure 57A6 and Figure 57A7 As shown, along the path from A to B, multiple transistors are connected through their source and drain terminals, and a fixed potential V is supplied from the power supply or GND at the nodes between the transistors. In this case, although it cannot be said that "A and B are indirectly connected," it is possible to say that "A is indirectly connected to V" or "B is indirectly connected to V." Figure 57A3 In the case where A and C are connected through the source and drain of transistor TrP, and B and C are connected through the source and drain of transistor TrQ, and a fixed potential V is supplied to C from the power supply or GND, etc., it has the same characteristics as... Figure 57A6 and Figure 57A7 Since they have the same connection relationship, we cannot say "A is indirectly connected to B" but we can say "A is indirectly connected to C" or "B is indirectly connected to C".

[0501] Although the above examples of "indirect connection" are shown, the provisions of "indirect connection" are included in the provisions of "electrical connection", so in the case of "A and B are indirectly connected", it can be said that "A and B are electrically connected".

[0502] The following shows specific examples of the "direct connection" case. For example, in the case of "A and B are directly connected,"... Figure 57B1 , Figure 57B2 and Figure 57B3 As shown, there are cases where A and B are not connected through circuit components. Furthermore, as... Figure 57B4 and Figure 57B5 As shown, when A and B are not connected to a power supply with a fixed potential V or GND via circuit components, it can be said that "A and B are directly connected", "A is directly connected to V", or "B is directly connected to V". Furthermore, as... Figure 57B6 As shown, even when A (or B) is connected to a fixed potential V through the source and drain of a transistor, it can be said that "A and B are directly connected". However, since A and V, or B and V, are connected through the source and drain of a transistor, it cannot be said that they are directly connected; instead, it can be said that "A and V are indirectly connected" or "B and V are indirectly connected".

[0503] Although the above examples show "direct connection", the definition of "direct connection" is included in the definition of "electrical connection", so in the case of "A and B are directly connected", it can be said that "A and B are electrically connected".

[0504] [Symbol Explanation]

[0505] DL: Wiring, ELVDD: Wiring, ELVSS: Wiring, EM: Wiring, GB: Wiring, GC: Wiring, GI: Wiring, GN: Wiring, GNBG: Wiring, GW: Wiring, INI: Wiring, M11: Transistor, M12: Transistor, M13: Transistor, M14: Transistor, M15: Transistor, M16: Transistor, M17: Transistor, ND1: Node, 10: Pixel, 20: Display Unit, 30: Gate Line-Side Driving Circuit, 31: Gate Line-Side Driving Circuit, 32: Gate Line-Side Driving Circuit, 33: Gate Line-Side Driving Circuit, 40: Integrated Circuit, 61: Light Emitting Device, 100: Display Device

Claims

1. A display device, comprising: First to seventh transistors; Capacitor; as well as Light-emitting devices The first to fifth transistors each include a gate, a first terminal, and a second terminal. Both the sixth and seventh transistors include a gate, a back gate, a first terminal, and a second terminal. The first terminal of the first transistor is electrically connected to the first terminal of the second transistor and the first terminal of the third transistor. The second terminal of the third transistor is electrically connected to the first terminal of the fourth transistor and the first terminal of the sixth transistor. The second terminal of the fourth transistor is electrically connected to the first terminal of the light-emitting device and the first terminal of the fifth transistor. The second terminal of the light-emitting device is electrically connected to a common potential line. The gate of the third transistor is electrically connected to the second terminal of the sixth transistor, the first terminal of the seventh transistor, and the first terminal of the capacitor. The second terminal of the fifth transistor and the second terminal of the seventh transistor are both electrically connected to the initialization line. The gate of the sixth transistor is electrically connected to the first gate line to which the first control signal is supplied. The back gate of the sixth transistor is electrically connected to the second gate line to which the second control signal is supplied. The gate of the seventh transistor is electrically connected to the third gate line to which the third control signal is supplied. The back gate of the seventh transistor is electrically connected to the fourth gate line to which the fourth control signal is supplied. The first control signal and the second control signal are logically identical signals. The third control signal and the fourth control signal are logically identical. Furthermore, the low-level potential of the second control signal and the low-level potential of the fourth control signal are different from the low-level potential of the first control signal and the low-level potential of the third control signal.

2. A display device, comprising: First to seventh transistors; Capacitor; as well as Light-emitting devices The first to fifth transistors each include a gate, a first terminal, and a second terminal. Both the sixth and seventh transistors include a gate, a back gate, a first terminal, and a second terminal. The first terminal of the first transistor is electrically connected to the data line. The second terminal of the first transistor is electrically connected to the first terminal of the second transistor and the first terminal of the third transistor. The second terminal of the second transistor is electrically connected to the current supply line. The second terminal of the third transistor is electrically connected to the first terminal of the fourth transistor and the first terminal of the sixth transistor. The second terminal of the fourth transistor is electrically connected to the first terminal of the light-emitting device and the first terminal of the fifth transistor. The second terminal of the fifth transistor is electrically connected to the initialization line. The second terminal of the light-emitting device is electrically connected to a common potential line. The gate of the third transistor is electrically connected to the second terminal of the sixth transistor, the first terminal of the seventh transistor, and the first terminal of the capacitor. The second terminal of the capacitor is electrically connected to the current supply line. The second terminal of the seventh transistor is electrically connected to the initialization line. The gate of the sixth transistor is electrically connected to the first gate line to which the first control signal is supplied. The back gate of the sixth transistor is electrically connected to the second gate line to which the second control signal is supplied. The gate of the seventh transistor is electrically connected to the third gate line to which the third control signal is supplied. The back gate of the seventh transistor is electrically connected to the fourth gate line to which the fourth control signal is supplied. The first control signal and the second control signal are logically identical signals. The third control signal and the fourth control signal are logically identical. The potential of the initialization line is lower than the potential of the common potential line. Furthermore, the low-level potential of the second control signal and the low-level potential of the fourth control signal are below the potential of the initialization line.

3. A display device, comprising: First to seventh transistors; Capacitor; as well as Light-emitting devices The first to fifth transistors each include a gate, a first terminal, and a second terminal. Both the sixth and seventh transistors include a gate, a back gate, a first terminal, and a second terminal. The first terminal of the first transistor is electrically connected to the data line. The second terminal of the first transistor is electrically connected to the first terminal of the second transistor and the first terminal of the third transistor. The second terminal of the second transistor is electrically connected to the current supply line. The second terminal of the third transistor is electrically connected to the first terminal of the fourth transistor and the first terminal of the sixth transistor. The second terminal of the fourth transistor is electrically connected to the first terminal of the light-emitting device and the first terminal of the fifth transistor. The second terminal of the fifth transistor is electrically connected to the initialization line. The second terminal of the light-emitting device is electrically connected to a common potential line. The gate of the third transistor is electrically connected to the second terminal of the sixth transistor, the first terminal of the seventh transistor, and the first terminal of the capacitor. The second terminal of the capacitor is electrically connected to the current supply line. The second terminal of the seventh transistor is electrically connected to the initialization line. The gate of the sixth transistor is electrically connected to the first gate line to which the first control signal is supplied. The back gate of the sixth transistor is electrically connected to the second gate line to which the second control signal is supplied. The gate of the seventh transistor is electrically connected to the third gate line to which the third control signal is supplied. The back gate of the seventh transistor is electrically connected to the fourth gate line to which the fourth control signal is supplied. The first control signal and the second control signal are logically identical signals. The third control signal and the fourth control signal are logically identical. The potential of the initialization line is lower than the potential of the common potential line. The potential of the initialization line is lower than the potential of the data line. Furthermore, the low-level potential of the second control signal and the low-level potential of the fourth control signal are below the potential of the initialization line.

4. The display device according to any one of claims 1 to 3, The first to fifth transistors are all p-channel transistors. Furthermore, both the sixth and seventh transistors are n-channel transistors.

5. The display device according to claim 4, The back gate of the n-channel transistor is opposite to the gate of the n-channel transistor across the channel forming region of the n-channel transistor.

6. The display device according to claim 4, The n-channel transistor includes a first semiconductor layer. Furthermore, the first semiconductor layer contains indium oxide.

7. The display device according to claim 4, The p-channel transistor includes a second semiconductor layer. The second semiconductor layer contains silicon.

8. The display device according to any one of claims 1 to 3, The high-level potential of the second control signal and the high-level potential of the fourth control signal are the same as the high-level potential of the first control signal and the high-level potential of the third control signal.

9. The display device according to any one of claims 1 to 3, The channel length of the third transistor is longer than that of the first transistor, the second transistor, the fourth transistor, and the fifth transistor.

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