Display substrate and display device

Abstract

The application discloses a display substrate and a display device, and relates to the technical field of display. The display substrate comprises a display area and a non-display area arranged at the periphery of the display area. The display substrate comprises a substrate, a first signal line, a second signal line, a first cross line and a first driving circuit arranged on one side of the substrate, and the first cross line is used for connecting the first signal line and the first driving circuit. The second signal line comprises a first line segment and a second line segment which are connected with each other. The first line segment is located between the first signal line and the first driving circuit, and the first line segment and the first cross line cross each other and are insulated from each other. A plurality of insulating layers are arranged between the first line segment and the first cross line in the normal direction of the substrate. The number of the second signal lines arranged on the same side of the display area is one or more. The number of the first cross lines crossing each of the plurality of second signal lines is the same.

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) still dominate the current flat panel display market due to their small size, low power consumption, and lack of radiation. In driving an LCD to display data, the gate voltage controls the opening and closing of the thin-film transistor (TFT). When the TFT is on, the data line voltage is written to the pixel electrode, which in turn drives the liquid crystal molecules to deflect, thus achieving different brightness levels.

[0003] Overview

[0004] This disclosure provides a display substrate, including a display area and a non-display area disposed around the display area, the display substrate comprising:

[0005] A substrate, and a first signal line, a second signal line, a first jumper wire, and a first driving circuit disposed on one side of the substrate, wherein the first signal line, the second signal line, the first jumper wire, and the first driving circuit are all located in the non-display area, and the first jumper wire is used to connect the first signal line and the first driving circuit;

[0006] The second signal line includes a first segment and a second segment connected to each other. The first segment is located between the first signal line and the first driving circuit. The first segment intersects with and is insulated from the first jumper wire. Multiple insulating layers are spaced apart between the first segment and the first jumper wire in the normal direction of the substrate.

[0007] The number of second signal lines located on the same side of the display area is one or more, and the number of first jumpers that cross each of the multiple second signal lines is the same.

[0008] In some embodiments, the non-display area further includes:

[0009] The third signal line is connected to the end of the first jumper wire away from the first signal line. The third signal line is used to connect the first jumper wire and the first drive circuit. The third signal line is arranged on the same layer as the first signal line.

[0010] In some embodiments, the first signal line includes a first voltage fan-out line, the first jumper includes a first voltage jumper, the third signal line includes a first voltage transmission line, the first voltage transmission line is connected to the first voltage input terminal of the first driving circuit, the first voltage fan-out line, the first voltage jumper and the first voltage transmission line are used to provide a first voltage signal to the first driving circuit, and the second signal line is not connected to the first driving circuit.

[0011] In some embodiments, the first driving circuit is a gate driving circuit, and the output terminal of the gate driving circuit is connected to the scan line of the display area;

[0012] The second signal line includes a gating signal line, and the non-display area further includes a gating circuit. The control terminal of the gating circuit is connected to the gating signal line, the gating signal line is used to provide a control signal to the gating circuit, and the output terminal of the gating circuit is connected to the data line of the display area.

[0013] In some embodiments, the first signal line includes an output voltage signal line, the first jumper wire includes an output voltage jumper wire, the third signal line includes an output voltage transmission line, the output voltage transmission line is connected to the output terminal of the first driving circuit, and the first driving circuit is used to output signals to the output voltage transmission line, the output voltage jumper wire, and the output voltage signal line.

[0014] The second signal line includes a second voltage transmission line, which is connected to the second voltage input terminal of the first driving circuit. The second voltage transmission line is used to provide a second voltage signal to the first driving circuit.

[0015] In some embodiments, the output voltage signal line is connected to the scan line of the display area, and the first driving circuit is a gate driving circuit.

[0016] In some implementations, the first line segment is located on the side of the first driving circuit closer to the display area.

[0017] In some embodiments, the first signal line includes a first voltage fan-out line, and the non-display area further includes a bonding area, wherein the first voltage fan-out line is connected to the bonding area and is located between the bonding area and the display area;

[0018] In the orthographic projection of the first driving circuit in the direction pointing to the display area, the first line segment does not overlap with the display area, and the first line segment is located on the side of the display area closer to the binding area.

[0019] In some embodiments, the first line segment includes a first end and a second end, the second line segment connected to the first end is located between the first voltage fan-out line and the display area, and the second line segment connected to the second end is located between the first voltage fan-out line and the bonding area.

[0020] In some embodiments, the first jumper wire includes a first voltage jumper wire, and the non-display area further includes:

[0021] A common voltage fan-out line, a common voltage jumper wire, and a common voltage transmission line are connected in sequence. The common voltage fan-out line is also connected to the bonding area, and the common voltage transmission line is also connected to the display area. The first line segment is located between the common voltage fan-out line and the common voltage transmission line. The common voltage jumper wire and the first line segment intersect and are insulated from each other. The common voltage jumper wire and the first voltage jumper wire are arranged on the same layer. The common voltage fan-out line, the common voltage transmission line, and the first voltage fan-out line are arranged on the same layer.

[0022] In some embodiments, the second signal line includes a gating signal line, in which a first segment intersecting the first voltage jumper and a first segment intersecting the common voltage jumper are interconnected.

[0023] In some embodiments, the first signal line includes an output voltage signal line connected to the display area, and in the orthographic projection of the first driving circuit in the direction pointing to the display area, the first line segment at least partially overlaps with the display area.

[0024] In some embodiments, the second signal line includes a second voltage transmission line, the first jumper includes an output voltage jumper, and the non-display area further includes:

[0025] The fourth signal line is located between the first driving circuit and the first segment of the second voltage transmission line, and / or between the first segment of the second voltage transmission line and the display area. The fourth signal line and the output voltage jumper intersect each other and are insulated from each other. The fourth signal line and the second segment are arranged on the same layer. The thickness of the insulation layer between the fourth signal line and the output voltage jumper is less than or equal to the thickness of the insulation layer between the first segment of the second voltage transmission line and the output voltage jumper.

[0026] In some embodiments, the display area includes multiple scan lines arranged along the column direction, the second signal line includes a second voltage transmission line, the first jumper includes an output voltage jumper, the second voltage transmission line intersects with the multiple output voltage jumpers, and in the column direction, the spacing between two adjacent output voltage jumpers is approximately an integer multiple of the spacing between two adjacent scan lines.

[0027] In some embodiments, the second signal line includes a second voltage transmission line, the first jumper includes an output voltage jumper, the second voltage transmission line intersects with multiple output voltage jumpers, and in the same second voltage transmission line, the first segments intersecting with different output voltage jumpers are separated from each other, and two adjacent first segments are connected by the second segment.

[0028] In some embodiments, the second signal line includes a second voltage transmission line, the first jumper includes an output voltage jumper, the second voltage transmission line intersects with multiple output voltage jumpers, and the first segments intersecting with different output voltage jumpers on the same second voltage transmission line are interconnected.

[0029] In some embodiments, the second line segment is a single-layer trace, which is a trace located in a single film layer.

[0030] In some embodiments, the second line segment includes a first layer of traces and a second layer of traces, which are stacked in the normal direction of the substrate. The first layer of traces is disposed on the same layer as the first line segment and is interconnected with it, while the second layer of traces is disposed on a different layer from the first line segment and is connected through vias.

[0031] In some embodiments, the display substrate includes:

[0032] A first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, and a fifth conductive layer are sequentially stacked along the normal direction of the substrate, with the first conductive layer disposed close to the substrate;

[0033] The plurality of insulating layers located between the first line segment and the first jumper wire include at least two adjacent insulating layers among the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer.

[0034] In some embodiments, the first jumper is located in the first conductive layer, and the first line segment is located in the second conductive layer, the third conductive layer, the fourth conductive layer, or the fifth conductive layer; or

[0035] The first jumper is located in the second conductive layer, and the first line segment is located in the first conductive layer, the fourth conductive layer, or the fifth conductive layer; or

[0036] The first jumper wire is located in the third conductive layer, and the first line segment is located in the first conductive layer, the fourth conductive layer, or the fifth conductive layer; or

[0037] The first jumper is located in the fourth conductive layer, and the first line segment is located in the first conductive layer, the second conductive layer, or the third conductive layer; or

[0038] The first jumper is located in the fifth conductive layer, and the first line segment is located in the first conductive layer, the second conductive layer, or the third conductive layer.

[0039] This disclosure provides a display device, including: a display substrate as described in any one of the claims; and a driving circuit connected to a non-display area of ​​the display substrate for driving the display substrate to perform a display.

[0040] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below.

[0041] Brief description of the attached diagram

[0042] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the scale in the drawings is for illustration only and does not represent the actual scale.

[0043] Figure 1 illustrates a schematic diagram of a gate drive circuit;

[0044] Figure 2 shows a schematic diagram of the structure of a display substrate in a first position in the related art;

[0045] Figure 3 shows a schematic diagram of the structure of a display substrate in a second position in the related art;

[0046] Figure 4 illustrates, by way of example, a schematic diagram of the structure of a display substrate provided in this disclosure;

[0047] Figure 5 illustrates, by way of example, a schematic diagram of the structure of the first type of display substrate provided in this disclosure;

[0048] Figure 6 illustrates, by way of example, a schematic diagram of the structure of the second type of display substrate provided in this disclosure;

[0049] Figure 7 illustrates, by way of example, a structural schematic diagram of the third type of display substrate provided in this disclosure;

[0050] Figure 8 illustrates, by way of example, a structural schematic diagram of the fourth type of display substrate provided in this disclosure;

[0051] Figure 9 illustrates, by way of example, a structural schematic diagram of the fifth type of display substrate provided in this disclosure;

[0052] Figure 10 illustrates, by way of example, a schematic diagram of the structure of the sixth type of display substrate provided in this disclosure;

[0053] Figure 11 illustrates, by way of example, a structural schematic diagram of the seventh type of display substrate provided in this disclosure;

[0054] Figure 12 illustrates, by way of example, a structural schematic diagram of the eighth type of display substrate provided in this disclosure;

[0055] Figure 13 illustrates, by way of example, a structural schematic diagram of the ninth type of display substrate provided in this disclosure;

[0056] Figure 14 illustrates, by way of example, a structural schematic diagram of the tenth type of display substrate provided in this disclosure;

[0057] Figure 15 exemplarily illustrates a design layout of the first type of display substrate provided in this disclosure;

[0058] Figure 16 illustrates, exemplarily, a design layout of the ninth type of display substrate provided in this disclosure;

[0059] Figure 17 illustrates a schematic cross-sectional structure of a top-gate thin-film transistor;

[0060] Figure 18 illustrates a schematic cross-sectional view of a bottom-gate thin-film transistor.

[0061] Detailed description

[0062] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0063] In related technologies, the display substrate adopts the gate driving circuit shown in Figure 1. The gate driving circuit includes a first transistor M0, which is used to enhance the potential stability of the pull-up node PU. The source of the first transistor M0 is connected to the VGH signal line.

[0064] Referring to Figure 2, a schematic diagram of the structure at the intersection of the VGH signal line and the MUX signal line is shown. Figure a shows a planar structural diagram of the intersection, and Figure b shows a cross-sectional structural diagram of the intersection. As shown in Figure b of Figure 2, at the intersection, the VGH signal line is located on the SD layer, and the MUX signal line is located on the Gate layer. An interlayer dielectric (ILD) is disposed between the VGH signal line and the MUX signal line. The inventors have discovered that ESD is prone to occur at the intersection of the VGH signal line and the MUX signal line during the manufacturing process, as shown in Figure c of Figure 2.

[0065] Figure 3 illustrates the structural diagram of the VGH and Gout signal lines at their intersection. Figure a shows a planar structural diagram of the intersection, and Figure b shows a cross-sectional structural diagram of the intersection. As shown in Figure b of Figure 3, at the intersection, the VGH signal line is located on the SD layer, and the Gout signal line is located on the Gate layer. An interlayer dielectric (ILD) is placed between the VGH and Gout signal lines. The inventors discovered that during high-temperature and high-humidity reliability testing, a short circuit easily occurs at the intersection of the VGH and Gout signal lines, as shown in Figure c of Figure 3. Analysis of the cause of the short circuit revealed that because the signal in the VGH signal line is consistently at a high potential (e.g., 17-18V), while the signal in the Gout signal line is mostly at a low potential (e.g., -12 to -13V), the large voltage difference and long interaction time between the VGH and Gout signal lines make copper diffusion prone to occur at their intersection, leading to a short circuit. In severe cases, this can burn out the TFT in the gate drive circuit, causing display abnormalities.

[0066] To address the aforementioned problems, this disclosure provides a display substrate, including a display area AA and a non-display area NA disposed around the periphery of the display area AA. As shown in FIG4, the display area AA includes multiple scan lines GL arranged along the column direction f2 and multiple data lines DL arranged along the row direction f1. The scan lines GL and data lines DL intersect to form multiple sub-pixels PX. Each sub-pixel PX includes a switching transistor T1. The gate of the switching transistor T1 is connected to the scan line GL, the source S is connected to the data line DL, and the drain D is connected to the pixel electrode Ep. The pixel electrode Ep and the common electrode Ec constitute a storage capacitor.

[0067] As shown in Figures 5 to 14, the display substrate includes: a substrate 10, and a first signal line 11, a second signal line 12, a first jumper 13 and a first driving circuit DRC1 disposed on one side of the substrate 10. The first signal line 11, the second signal line 12, the first jumper 13 and the first driving circuit DRC1 are all located in the non-display area NA. The first jumper 13 is used to connect the first signal line 11 and the first driving circuit DRC1.

[0068] The second signal line 12 includes a first line segment 121 and a second line segment 122 that are connected to each other. The first line segment 121 is located between the first signal line 11 and the first driving circuit DRC1. The first line segment 121 and the first jumper 13 intersect each other and are insulated from each other. In the normal direction of the substrate 10, a plurality of insulating layers are provided between the first line segment 121 and the first jumper 13.

[0069] As shown in Figure 5 or Figure 10, the insulating layer between the first segment 121 and the first jumper 13 includes a first insulating layer buffer, a second insulating layer GI, and a third insulating layer ILD. As shown in Figure 6 or Figure 11, the insulating layer between the first segment 121 and the first jumper 13 includes a third insulating layer ILD, a fourth insulating layer PVX1, a fifth insulating layer ORG, and a sixth insulating layer PVX2. As shown in Figure 7 or Figure 12, the insulating layer between the first segment 121 and the first jumper 13 includes a fourth insulating layer PVX1, a fifth insulating layer ORG, and a sixth insulating layer PVX2. As shown in Figures 8, 9, 12, or 13, the insulating layer between the first segment 121 and the first jumper 13 includes a first insulating layer buffer, a second insulating layer GI, and a third insulating layer ILD.

[0070] In the second signal line 12, the segment that intersects with the first jumper 13 is the first segment 121. By providing multiple insulating layers between the first segment 121 and the first jumper 13, the thickness of the insulating layer between the first segment 121 and the first jumper 13 can be increased, thereby reducing the risk of ESD or short circuit at the intersection of the first jumper 13 and the second signal line 12 and improving the reliability of the display substrate.

[0071] As shown in Figures 5 to 14, the number of second signal lines 12 located on the same side of the display area AA is one or more, and the number of first jumper wires 13 that cross each of the multiple second signal lines 12 is the same.

[0072] As shown in Figures 5 to 9, there are multiple second signal lines 12 located on the same side of the display area AA, and the number of first jumpers 13 that cross each of the multiple second signal lines 12 is the same, for example, one for each. As shown in Figures 10 to 14, there is only one second signal line 12 located on the same side of the display area AA.

[0073] Since the number of first jumpers 13 that intersect with each of the multiple second signal lines 12 is the same, the area of ​​the overlapping region between each second signal line 12 and the first jumper 13 is approximately the same. This can reduce the parasitic capacitance difference between different second signal lines 12 and help improve display uniformity.

[0074] For example, in the orthographic projection on the substrate 10, the first line segment 121 and the first jumper 13 overlap at the intersection, while the second line segment 122 does not overlap with the first jumper 13 and is not connected to each other. The orthographic projections of the first line segment 121 and the second line segment 122 on the substrate 10 are, for example, alternately arranged.

[0075] For example, the second line segment 122 and the first signal line 11 can be disposed on the same layer, as shown in Figures 5 to 9, where both the second line segment 122 and the first signal line 11 are located on the second conductive layer gate. Alternatively, the second line segment 122 and the first signal line 11 can be disposed on different layers, as shown in Figures 10 to 14, where the second line segment 122 is located on the second conductive layer gate, and the first signal line 11 is located on the third conductive layer SD.

[0076] For example, the first signal line 11 or the second signal line 12 is used to transmit a DC signal, such as an enable voltage signal VGH, which is used to turn on the switching transistor T1.

[0077] In some embodiments, as shown in Figures 5 to 14, the non-display area NA further includes: a third signal line 14, which is connected to the end of the first jumper 13 away from the first signal line 11. The third signal line 14 is used to connect the first jumper 13 and the first drive circuit DRC1. The third signal line 14 is disposed on the same layer as the first signal line 11.

[0078] In some embodiments, as shown in Figures 5 to 9, the first signal line 11 includes a first voltage fan-out line VGH1, the first jumper wire 13 includes a first voltage jumper wire VGH2, and the third signal line 14 includes a first voltage transmission line VGH3. The first voltage transmission line VGH3 is connected to the first voltage input terminal Vin1 of the first driving circuit DRC1. The first voltage fan-out line VGH1, the first voltage jumper wire VGH2, and the first voltage transmission line VGH3 are used to provide a first voltage signal to the first driving circuit DRC1. The second signal line 12 is not connected to the first driving circuit DRC1.

[0079] For example, as shown in FIG4, the non-display area NA also includes a bonding area BD, and one end of the first voltage fan-out line VGH1 away from the first voltage jumper line VGH2 is connected to the bonding area BD.

[0080] For example, the first voltage signal is a DC signal, such as the turn-on voltage signal VGH.

[0081] For example, as shown in Figures 5 to 9, the first driving circuit DRC1 is a gate driving circuit GOA, and the output terminal of the gate driving circuit GOA is connected to the scan line GL of the display area AA.

[0082] For example, the gate drive circuit GOA includes a plurality of first voltage input terminals Vin1, which are connected, for example, to the same first voltage transmission line VGH3.

[0083] In some embodiments, as shown in Figures 5 to 9, the second signal line 12 includes a gating signal line ML. Referring also to Figure 4, the non-display area NA further includes a gating circuit MUX. The control terminal CTR of the gating circuit MUX is connected to the gating signal line ML, which provides a control signal to the gating circuit MUX. The output terminal of the gating circuit MUX is connected to the data line DL of the display area AA. The gating circuit MUX is turned on under the control signal provided by the gating signal line ML and provides a data signal to the data line DL. By including the gating circuit MUX, the number of source driver chips or channels can be reduced.

[0084] In some embodiments, as shown in Figures 10 to 14, the first signal line 11 includes an output voltage signal line Gout3, the first jumper wire 13 includes an output voltage jumper wire Gout2, and the third signal line 14 includes an output voltage transmission line Gout1. The output voltage transmission line Gout1 is connected to the output terminal OUT of the first driving circuit DRC1. The first driving circuit DRC1 is used to output signals to the output voltage transmission line Gout1, the output voltage jumper wire Gout2, and the output voltage signal line Gout3.

[0085] For example, the output voltage signal line Gout3 is connected to the scan line GL of the display area AA, and the first driving circuit DRC1 is the gate driving circuit GOA.

[0086] In some embodiments, as shown in Figures 10 to 14, the second signal line 12 includes a second voltage transmission line VL2, which is connected to the second voltage input terminal Vin2 of the first driving circuit DRC1. The second voltage transmission line VL2 is used to provide a second voltage signal to the first driving circuit DRC1.

[0087] For example, the gate drive circuit GOA includes a plurality of second voltage input terminals Vin2, which are connected, for example, to the same second voltage transmission line VL2.

[0088] For example, the second voltage signal is a DC signal, such as the turn-on voltage signal VGH.

[0089] For example, the second voltage transmission line VL2 and the first voltage transmission line VGH3 are the same signal line.

[0090] In some embodiments, as shown in FIG15 or FIG16, the first line segment 121 is located on the side of the first driving circuit DRC1 near the display area AA.

[0091] In some embodiments, as shown in FIG15, the first signal line 11 includes a first voltage fan-out line VGH1, which is located between the bonding area BD and the display area AA.

[0092] In some embodiments, as shown in FIG15, in the orthographic projection of the first driving circuit DRC1 onto the direction f3 pointing to the display area AA, the first line segment 121 does not overlap with the display area AA, and the first line segment 121 is located on the side of the display area AA closer to the bonding area BD. As shown in FIG15, the first line segment 121 does not overlap with the display area AA along the lateral extension area.

[0093] As shown in Figure 4, the non-display area NA includes a first non-display area NA1 and a second non-display area NA2. The first non-display area NA1 and the second non-display area NA2 are located on two adjacent sides of the display area AA. The first driving circuit DRC1 is located in the first non-display area NA1, and the bonding area BD is located in the second non-display area NA2.

[0094] For example, the first line segment 121 is located in the overlapping area of ​​the first non-display area NA1 and the second non-display area NA2. For instance, in Figure 4, the first non-display area NA1 is located to the left of the display area AA, the second non-display area NA2 is located below the display area AA, and the first line segment 121 is located in the lower left corner of the overlapping area of ​​the first non-display area NA1 and the second non-display area NA2. The first non-display area NA1 can also be located to the right of the display area AA, and the second non-display area NA2 can be located below the display area AA. In this case, the first line segment 121 is located in the lower right corner.

[0095] In some embodiments, as shown in FIG15, the first line segment 121 includes a first end D1 and a second end D2. The second line segment 122 connected to the first end D1 is located between the first voltage fan-out line VGH1 and the display area AA. The second line segment 122 connected to the second end D2 is located between the first voltage fan-out line VGH1 and the bonding area BD. The second line segment 122 connected to the second end D2 is connected to the bonding area BD, for example.

[0096] For example, as shown in FIG15, the first ends D1 of a plurality of first line segments 121 are arranged and approximately aligned along the column direction f2, and the second ends D2 of a plurality of first line segments 121 are arranged and approximately aligned along the column direction f2.

[0097] For example, as shown in FIG15, in the direction f3 of the first driving circuit DRC1 pointing to the display area AA, the length of multiple first line segments 121 gradually shortens.

[0098] For example, as shown in FIG15, the third signal line 14 includes a bent segment WZ1 and an extended segment YS. The bent segment WZ1 is located on the side of the first driving circuit DRC1 near the bonding area BD, and on the side of the first line segment 121 away from the first signal line 11, that is, the bent segment WZ1 is located in the overlapping area of ​​the first non-display area NA1 and the second non-display area NA2. The extended segment YS is located in the first non-display area NA1, and is located between the first driving circuit DRC1 and the display area AA. Among them, the bent segment WZ1 bends towards the side away from the first line segment 121.

[0099] In some embodiments, as shown in FIG15, the first jumper wire 13 includes a first voltage jumper wire VGH2, and the non-display area NA further includes: a common voltage fan-out line COM1, a common voltage jumper wire COM2, and a common voltage transmission line COM3 connected in sequence. The common voltage fan-out line COM1 is also connected to the bonding area BD, and the common voltage transmission line COM3 is also connected to the display area AA. The first line segment 121 is located between the common voltage fan-out line COM1 and the common voltage transmission line COM3. The common voltage jumper wire COM2 and the first line segment 121 cross each other and are insulated from each other. The common voltage jumper wire COM2 and the first voltage jumper wire VGH2 are arranged on the same layer. The common voltage fan-out line COM1, the common voltage transmission line COM3, and the first voltage fan-out line VGH1 are arranged on the same layer.

[0100] For example, as shown in FIG15, the common voltage fan-out line COM1 is located between the first signal line 11 and the second line segment 122 connected to the first end D1, and the common voltage transmission line COM3 is located between the extension line segment YS and the display area AA.

[0101] For example, as shown in FIG15, the common voltage jumper COM2 is located on the side of the first jumper 13 near the display area AA.

[0102] In some embodiments, as shown in FIG15, the second signal line 12 includes a gating signal line ML, in which a first segment 121 intersecting the first voltage jumper line VGH2 and a first segment 121 intersecting the common voltage jumper line COM2 are interconnected.

[0103] In some embodiments, as shown in FIG16, the first signal line 11 includes an output voltage signal line Gout3, which is connected to the display area AA. In the orthographic projection of the first driving circuit DRC1 in the direction f3 pointing to the display area AA, the first line segment 121 at least partially overlaps with the display area AA. As shown in FIG16, the first line segment 121 overlaps with the display area AA along the lateral extension region.

[0104] As shown in Figure 16, the first line segment 121 and the second line segment 122 are both located between the first driving circuit DRC1 and the display area AA.

[0105] In some embodiments, as shown in FIG16, the non-display area NA further includes: a fourth signal line 15, located between the first driving circuit DRC1 and the first segment 121 of the second voltage transmission line VL2, and / or between the first segment 121 of the second voltage transmission line VL2 and the display area AA, the fourth signal line 15 and the output voltage jumper line Gout2 intersect each other and are insulated from each other, the fourth signal line 15 and the second segment 122 are disposed on the same layer, and the thickness of the insulating layer between the fourth signal line 15 and the output voltage jumper line Gout2 is less than or equal to the thickness of the insulating layer between the first segment 121 of the second voltage transmission line VL2 and the output voltage jumper line Gout2.

[0106] For example, as shown in FIG16, the third signal line 14 includes a frame start signal line STV, and may also include a shutdown voltage signal line VGL, and may also include a common voltage transmission line COM3. The frame start signal line STV and the shutdown voltage signal line VGL are located, for example, between the first driving circuit DRC1 and the first segment 121 of the second voltage transmission line VL2, and the common voltage signal line COM is located, for example, between the first segment 121 of the second voltage transmission line VL2 and the display area AA.

[0107] In some embodiments, as shown in FIG16, the display area AA includes multiple scan lines GL arranged along the column direction f2, the second signal line 12 includes a second voltage transmission line VL2, the first jumper line 13 includes an output voltage jumper line Gout2, the second voltage transmission line VL2 intersects with the multiple output voltage jumper lines Gout2, and in the column direction f2, the spacing between two adjacent output voltage jumper lines Gout2 is approximately equal to an integer multiple of the spacing between two adjacent scan lines GL, such as one, two, or three times.

[0108] For example, as shown in Figure 16, multiple output voltage jumpers Gout2 are arranged at equal intervals in the column direction f2.

[0109] In some embodiments, as shown in FIG16, the second signal line 12 includes a second voltage transmission line VL2, the first jumper 13 includes an output voltage jumper Gout2, the second voltage transmission line VL2 intersects with multiple output voltage jumpers Gout2, and in the same second voltage transmission line VL2, the first segments 121 that intersect with different output voltage jumpers Gout2 are separated from each other, and two adjacent first segments 121 are connected by a second segment 122.

[0110] As shown in Figure 16, the first line segment 121 and the output voltage jumper Gout2 are set in a one-to-one correspondence. In the column direction f2, the output voltage jumper Gout2 is set approximately in the center relative to the first line segment 121.

[0111] In some embodiments, as shown in any one of Figures 10 to 12, the second signal line 12 includes a second voltage transmission line VL2, the first jumper 13 includes an output voltage jumper Gout2, the second voltage transmission line VL2 intersects with multiple output voltage jumpers Gout2, and the first segments 121 that intersect with different output voltage jumpers Gout2 in the same second voltage transmission line VL2 are interconnected.

[0112] For example, multiple output voltage jumpers Gout2 intersect at different locations on the same first line segment 121.

[0113] For example, in the orthographic projection on the substrate 10, along the extension direction f4 of the first line segment 121, the boundary of the first line segment 121 extends outward by a first distance relative to the boundary of the first crossover line 13, the first distance being greater than or equal to 3 micrometers and less than or equal to 10 micrometers.

[0114] In some embodiments, as shown in Figures 5 to 8 and Figures 10 to 13, the second line segment 122 is a single-layer trace, which is a trace located in a single film layer. The second line segment 122 and the first line segment 121 can be disposed in the same layer or in different layers.

[0115] As shown in Figure 5 or Figure 10, the first line segment 121 is located in the third conductive layer SD, and the second line segment 122 is located in the second conductive layer gate. As shown in Figure 6 or Figure 11, both the first line segment 121 and the second line segment 122 are located in the second conductive layer gate. As shown in Figure 7 or Figure 12, the first line segment 121 is located in the third conductive layer SD, and the second line segment 122 is located in the second conductive layer gate. As shown in Figure 8 or Figure 13, the first line segment 121 is located in the first conductive layer LS, and the second line segment 122 is located in the second conductive layer gate.

[0116] In some embodiments, as shown in FIG9 or FIG14, the second line segment 122 includes a first layer trace ZX1 and a second layer trace ZX2. The first layer trace ZX1 and the second layer trace ZX2 are stacked in the normal direction of the substrate 10. The first layer trace ZX1 is disposed in the same layer as the first line segment 121 and is interconnected with it. The second layer trace ZX2 is disposed in a different layer from the first line segment 121 and is connected through a via.

[0117] For example, as shown in Figure 9 or Figure 14, the first layer trace ZX1 and the first line segment 121 are both located in the first conductive layer LS, and the second layer trace ZX2 is located in the second conductive layer gate.

[0118] By setting up multi-layer routing (such as double-layer routing), the routing resistance of the second segment 122 or the second signal line 12 can be reduced.

[0119] For example, in the orthographic projection on the substrate 10, the first layer trace ZX1 and the second layer trace ZX2 at least partially overlap. The second layer trace ZX2 is disposed on the same layer as the first signal line 11, for example.

[0120] For example, the thin-film transistor in the first driving circuit DRC1 is a top-gate structure, as shown in FIG17. In some embodiments, as shown in FIG17, the display substrate includes: a first conductive layer LS, a first insulating layer buffer, a semiconductor layer ACT, a second insulating layer GI, a second conductive layer gate, a third insulating layer ILD, a third conductive layer SD, a fourth insulating layer PVX1, a fifth insulating layer ORG, a fourth conductive layer ITO1, a sixth insulating layer PVX2, and a fifth conductive layer ITO2, which are sequentially stacked along the normal direction of the substrate 10, with the first conductive layer LS disposed close to the substrate 10.

[0121] Exemplarily, the first conductive layer LS includes a masking pattern whose orthogonal projection onto the substrate 10 covers the channel region CH of the thin-film transistor. The gate G of the thin-film transistor is located in the second conductive layer gate, the channel region CH is located in the semiconductor layer ACT, and the source S and drain D are located in the third conductive layer SD. The fourth conductive layer ITO1 includes a common electrode Ec (or a pixel electrode Ep), and the fifth conductive layer ITO2 includes a pixel electrode Ep (or a common electrode Ec).

[0122] For example, the plurality of insulating layers located between the first line segment 121 and the first jumper 13 include at least two adjacent insulating layers among the first insulating layer buffer, the second insulating layer GI, the third insulating layer ILD, the fourth insulating layer PVX1, the fifth insulating layer ORG, and the sixth insulating layer PVX2.

[0123] For example, the first jumper 13 is located in the first conductive layer LS, and the first line segment 121 is located in the second conductive layer gate, the third conductive layer SD, the fourth conductive layer ITO1, or the fifth conductive layer ITO2.

[0124] As shown in Figure 5 or Figure 10, the first jumper 13 is located in the first conductive layer LS, and the first line segment 121 is located in the third conductive layer SD. The insulating layer between the first line segment 121 and the first jumper 13 includes a first insulating layer buffer, a second insulating layer GI, and a third insulating layer ILD. The thickness of the insulating layer between the first line segment 121 and the first jumper 13 is 7000 angstroms to 13000 angstroms.

[0125] As shown in Figure 5, the first signal line 11 and the third signal line 14 are located in the second conductive layer (gate), and the first jumper 13 is located in the first conductive layer (LS). The first signal line 11 and the third signal line 14 are connected to the first jumper 13 via vias. Specifically, the first signal line 11 and the first jumper 13 are connected via a first adapter pattern ZJ1 located in the third conductive layer (SD), and the first signal line 11 and the first adapter pattern ZJ1 are connected via vias located in the third insulating layer (ILD). The first jumper 13 and the first adapter pattern ZJ1 are connected via vias located in the third insulating layer (ILD) and the first insulating layer (buffer). The third signal line 14 and the first jumper 13 are connected via a second adapter pattern ZJ2 located in the third conductive layer (SD), and the third signal line 14 and the second adapter pattern ZJ2 are connected via vias located in the third insulating layer (ILD). The first jumper 13 and the second adapter pattern ZJ2 are connected via vias located in the third insulating layer (ILD) and the first insulating layer (buffer). The first segment 121 of the second signal line 12 is located in the third conductive layer SD, and the second segment 122 is located in the second conductive layer gate. The first segment 121 and the second segment 122 are connected by a via provided in the third insulating layer ILD.

[0126] As shown in Figure 10, the first signal line 11 and the third signal line 14 are located in the third conductive layer SD, and the first jumper 13 is located in the first conductive layer LS. The first signal line 11 and the third signal line 14 are connected to the first jumper 13 through vias provided in the third insulating layer ILD and the first insulating layer buffer, respectively. The first segment 121 of the second signal line 12 is located in the third conductive layer SD, and the second segment 122 is located in the second conductive layer gate. The first segment 121 and the second segment 122 are connected through vias provided in the third insulating layer ILD.

[0127] For example, the first jumper 13 is located in the second conductive layer gate, and the first line segment 121 is located in the first conductive layer LS, the fourth conductive layer ITO1, or the fifth conductive layer ITO2.

[0128] For example, the first jumper 13 is located in the third conductive layer SD, and the first line segment 121 is located in the first conductive layer LS, the fourth conductive layer ITO1, or the fifth conductive layer ITO2.

[0129] As shown in Figures 8, 9, 13, or 14, the first jumper 13 is located on the third conductive layer SD, and the first line segment 121 is located on the first conductive layer LS. The insulating layer between the first line segment 121 and the first jumper 13 includes a first insulating layer buffer, a second insulating layer GI, and a third insulating layer ILD. The thickness of the insulating layer between the first line segment 121 and the first jumper 13 is 7000 angstroms to 13000 angstroms.

[0130] As shown in Figure 8, the first signal line 11 and the third signal line 14 are located in the second conductive layer gate, and the first jumper wire 13 is located in the third conductive layer SD. The first signal line 11 and the third signal line 14 are connected to the first jumper wire 13 through vias located in the third insulating layer ILD. The first segment 121 of the second signal line 12 is located in the first conductive layer LS, and the second segment 122 is located in the second conductive layer gate. The first segment 121 and the second segment 122 are connected through the third transition pattern ZJ3 located in the third conductive layer SD. The second segment 122 and the third transition pattern ZJ3 are connected through vias located in the third insulating layer ILD. The first segment 121 and the third transition pattern ZJ3 are connected through vias located in the third insulating layer ILD and the first insulating layer buffer.

[0131] As shown in Figure 9, the first signal line 11 and the third signal line 14 are located in the second conductive layer gate, and the first jumper 13 is located in the third conductive layer SD. The first signal line 11 and the third signal line 14 are connected to the first jumper 13 through vias located in the third insulating layer ILD. The first segment 121 of the second signal line 12 is located in the first conductive layer LS, the first layer trace ZX1 of the second segment 122 is located in the first conductive layer LS, and the second layer trace ZX2 is located in the second conductive layer gate. The second layer trace ZX2 is connected to the first segment 121 through the third transition pattern ZJ3 located in the third conductive layer SD. The second layer trace ZX2 and the third transition pattern ZJ3 are connected through vias located in the third insulating layer ILD. The first segment 121 and the third transition pattern ZJ3 are connected through vias located in the third insulating layer ILD and the first insulating layer buffer.

[0132] As shown in Figure 13, the first signal line 11 and the third signal line 14 are located on the third conductive layer SD, and the first jumper 13 is also located on the third conductive layer SD. The first signal line 11 and the third signal line 14 are connected to the first jumper 13 on the same layer. The first segment 121 of the second signal line 12 is located on the first conductive layer LS, and the second segment 122 is located on the second conductive layer gate. The first segment 121 and the second segment 122 are connected through the fourth transition pattern ZJ4 located on the third conductive layer SD. The second segment 122 and the fourth transition pattern ZJ4 are connected through vias located on the third insulating layer ILD. The first segment 121 and the fourth transition pattern ZJ4 are connected through vias located on the third insulating layer ILD and the first insulating layer buffer.

[0133] As shown in Figure 14, the first signal line 11 and the third signal line 14 are located on the third conductive layer SD, and the first jumper 13 is located on the third conductive layer SD. The first signal line 11 and the third signal line 14 are connected to the first jumper 13 on the same layer. The first segment 121 of the second signal line 12 is located on the first conductive layer LS. The first layer trace ZX1 of the second segment 122 is located on the first conductive layer LS, and the second layer trace ZX2 is located on the second conductive layer gate. The second layer trace ZX2 is connected to the first segment 121 through the fourth transition pattern ZJ4 located on the third conductive layer SD. The second layer trace ZX2 and the fourth transition pattern ZJ4 are connected through vias located on the third insulating layer ILD. The first segment 121 and the fourth transition pattern ZJ4 are connected through vias located on the third insulating layer ILD and the first insulating layer buffer.

[0134] For example, the first jumper 13 is located in the fourth conductive layer ITO1, and the first line segment 121 is located in the first conductive layer LS, the second conductive layer gate, or the third conductive layer SD.

[0135] For example, the first jumper 13 is located in the fifth conductive layer ITO2, and the first line segment 121 is located in the first conductive layer LS, the second conductive layer gate, or the third conductive layer SD.

[0136] As shown in Figure 6 or Figure 11, the first jumper 13 is located in the fifth conductive layer ITO2, and the first line segment 121 is located in the second conductive layer gate. The insulating layer between the first line segment 121 and the first jumper 13 includes the third insulating layer ILD, the fourth insulating layer PVX1, the fifth insulating layer ORG, and the sixth insulating layer PVX2. The thickness of the insulating layer between the first line segment 121 and the first jumper 13 is 25,000 angstroms to 41,000 angstroms.

[0137] As shown in Figure 6, the first signal line 11 and the third signal line 14 are located in the second conductive layer gate, and the first jumper 13 is located in the fifth conductive layer ITO2. The first signal line 11 and the third signal line 14 are connected to the first jumper 13 through vias located in the third insulating layer ILD, the fourth insulating layer PVX1, the fifth insulating layer ORG, and the sixth insulating layer PVX2, respectively. The first segment 121 and the second segment 122 of the second signal line 12 are both located in the second conductive layer gate and are connected in the same layer.

[0138] As shown in Figure 11, the first signal line 11 and the third signal line 14 are located on the third conductive layer SD, and the first jumper 13 is located on the fifth conductive layer ITO2. The first signal line 11 and the third signal line 14 are connected to the first jumper 13 through vias located on the fourth insulating layer PVX1, the fifth insulating layer ORG, and the sixth insulating layer PVX2, respectively. The first segment 121 and the second segment 122 of the second signal line 12 are both located on the second conductive layer gate, and the two are connected on the same layer.

[0139] As shown in Figure 7 or Figure 12, the first jumper 13 is located in the fifth conductive layer ITO2, and the first line segment 121 is located in the third conductive layer SD. The insulating layer between the first line segment 121 and the first jumper 13 includes the fourth insulating layer PVX1, the fifth insulating layer ORG, and the sixth insulating layer PVX2. The thickness of the insulating layer between the first line segment 121 and the first jumper 13 is 22,000 angstroms to 36,000 angstroms.

[0140] As shown in Figure 7, the first signal line 11 and the third signal line 14 are located in the second conductive layer gate, and the first jumper 13 is located in the fifth conductive layer ITO2. The first signal line 11 and the third signal line 14 are connected to the first jumper 13 through vias located in the third insulating layer ILD, the fourth insulating layer PVX1, the fifth insulating layer ORG, and the sixth insulating layer PVX2, respectively. The first segment 121 of the second signal line 12 is located in the third conductive layer SD, and the second segment 122 is located in the second conductive layer gate. The first segment 121 and the second segment 122 are connected through vias provided in the third insulating layer ILD.

[0141] As shown in Figure 12, the first signal line 11 and the third signal line 14 are located on the third conductive layer SD, and the first jumper 13 is located on the fifth conductive layer ITO2. The first signal line 11 and the third signal line 14 are connected to the first jumper 13 through vias located on the fourth insulating layer PVX1, the fifth insulating layer ORG, and the sixth insulating layer PVX2, respectively. The first segment 121 of the second signal line 12 is located on the third conductive layer SD, and the second segment 122 is located on the second conductive layer gate. The first segment 121 and the second segment 122 are connected through vias provided on the third insulating layer ILD.

[0142] In this disclosure, the first crossover line 13 and the first line segment 121 can be formed on the same layer as other structures in the substrate, eliminating the need for an additional mask and simplifying the process.

[0143] For example, the first conductive layer LS, the second conductive layer gate, the third conductive layer SD, the fourth conductive layer ITO1, and the fifth conductive layer ITO2 can each be independently made of metal materials such as aluminum and copper, or transparent conductive materials such as metal oxides such as ITO, IZO, IGZO, IGO, and ZTO.

[0144] In some embodiments, the first conductive layer LS is made of a metal material such as aluminum or copper, with a thickness of 1000 angstroms to 2000 angstroms; the first insulating layer buffer is made of SiNx and / or SiOx, with a thickness of 3000 angstroms to 5000 angstroms; the semiconductor layer ACT is made of IGZO, with a thickness of 300 angstroms to 1000 angstroms; the second insulating layer GI is made of SiOx, with a thickness of 1000 angstroms to 3000 angstroms; and the second conductive layer gate can be made of a metal material such as aluminum or copper, with a thickness of 3000 angstroms to 5000 angstroms. The third insulating layer, ILD, is made of SiNx and / or SiOx, with a thickness of 3000 Å to 5000 Å. The third conductive layer, SD, can be made of metals such as aluminum or copper, with a thickness of 3000 Å to 5000 Å. The fourth insulating layer, PVX1, can be made of SiNx, with a thickness of 1000 Å to 3000 Å. The fifth insulating layer, ORG, is made of organic materials, with a thickness of 20000 Å to 30000 Å. The sixth insulating layer, PVX2, can be made of SiNx, with a thickness of 1000 Å to 3000 Å. The fourth conductive layer, ITO1, and the fifth conductive layer, ITO2, are made of transparent conductive materials such as ITO, with a thickness of 500 Å to 1000 Å.

[0145] For example, as shown in FIG17, the display substrate with the top gate structure can be formed by 10 mask plate processes, which are in sequence: first conductive layer LS → semiconductor layer ACT → second conductive layer gate → third insulating layer ILD → third conductive layer SD → fifth insulating layer ORG → fourth conductive layer ITO1 → touch electrode layer (not shown in FIG17) → sixth insulating layer PVX2 → fifth conductive layer ITO2.

[0146] For example, in the same display substrate, the first line segment 121 at different locations can be located in the same layer or different layers, and the first bridge line 13 at different locations can be located in the same layer or different layers. Referring to Figures 15 and 16, the wiring structure of the lower left (or lower right) corner and left (or right) side of the display substrate is shown respectively. At the lower left or lower right corner of the display substrate, as shown in Figure 15, the first bridge line 13 is the first voltage bridge line VGH2, the second signal line 12 is the gating signal line ML, the first line segment 121 of the gating signal line ML is located in the third conductive layer SD, and the first voltage bridge line VGH2 is located in the first conductive layer LS. On the left or right side of the display substrate, as shown in Figure 16, the first bridge line 13 is the output voltage bridge line Gout2, the second signal line 12 is the second voltage transmission line VL2, the first line segment 121 of the second voltage signal line is located in the first conductive layer LS, and the output voltage bridge line Gout2 is located in the third conductive layer SD.

[0147] In specific implementations, the thin-film transistor in the first driving circuit DRC1 can also be a bottom-gate structure as shown in Figure 18, and this disclosure does not limit it.

[0148] For example, the gate drive circuit GOA includes multiple cascaded shift registers, each shift register adopting the 24T1C structure shown in Figure 1.

[0149] In this disclosure, a thin-film transistor (TFT) refers to a device comprising at least three terminals: a gate (G), a drain (D), and a source (S). The TFT has a channel region CH between the drain (D) (drain terminal, drain region, or drain) and the source (S) (source terminal, source region, or source), and current can flow through the drain (D), the channel region CH, and the source (S). In this disclosure, the channel region CH refers to the region through which current primarily flows.

[0150] In this disclosure, when using thin-film transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source S" and "drain D" are sometimes interchanged. Therefore, in this disclosure, the "source S" and "drain D" can be interchanged.

[0151] For example, the material of the channel region CH includes oxide semiconductor materials such as IGZO, and may also include materials such as amorphous silicon or low-temperature polycrystalline silicon, which are not limited in this disclosure.

[0152] The ratio of the on-state current Ion to the leakage current Ioff of a thin-film transistor during conduction, i.e., the on / off ratio Ion / Ioff ≥ 10. 6 The on-state current Ion can be in the microampere range, and the leakage current Ioff can be in the picoampere range. Due to the high mobility of oxide materials, transistors using oxide materials have relatively large switching capabilities.

[0153] In some embodiments, the channel region CH comprises a semiconductor material M1OaNb, where M1 is a single metal or a combination of multiple metals, a > 0, and b ≥ 0, O represents oxygen, and N represents nitrogen. That is, the semiconductor material is a metal oxide material or a metal oxide-nitrogen material. Suitable metal oxide materials include, but are not limited to, one or more of the following: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxides (In-free OS), rare earth-doped oxides (Ln-OS, such as rare earth element-doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. The material of CH in the channel region can be amorphous, partially crystalline, single-crystal or polycrystalline, and can also be a single-layer or multi-layer structure.

[0154] Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. In one example, the material of the channel region CH includes indium gallium zinc oxide (IGZO).

[0155] This disclosure provides a display device, which includes: a display substrate as provided in any embodiment; and a driving circuit connected to the non-display area of ​​the display substrate for driving the display substrate to perform display.

[0156] Those skilled in the art will understand that the display device provided in this disclosure has the advantages of the aforementioned display substrate.

[0157] The display device disclosed herein can be any product or component with display function, such as a display module, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, in-vehicle display device, smartwatch, fitness wristband, personal digital assistant, etc.

[0158] In this disclosure, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this disclosure.

[0159] In this disclosure, relational terms such as first and second are used merely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0160] In this specification, "electrical connection" and "coupling" include situations where components are connected together by elements that have some electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0161] In this disclosure, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly specified. "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C," both including the following combinations of A, B, and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C. "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0162] The use of “for” or “configured to” in this disclosure implies an open and inclusive language that does not preclude applicability to or configuration to devices for performing additional tasks or steps.

[0163] As used in this disclosure, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0164] As used in this disclosure, "parallel," "perpendicular," "equal," and "flush" include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein an acceptable deviation range for approximate parallelism may be, for example, within 10° or 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein an acceptable deviation range for approximate perpendicularity may also be, for example, within 10° or 5°. "Equal" includes absolute equality and approximate equality, wherein an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one. "Flush" includes absolute flush and approximate flush, wherein an acceptable deviation range for approximate flush may be, for example, a distance between the flushes being less than or equal to 5% of either one's dimension.

[0165] It should be understood that when a layer or element is referred to as being disposed on one side of another layer or substrate, it may be that the layer or element is directly disposed on the other layer or substrate, or it may be that there is an intermediate layer between the layer or element and the other layer or substrate.

[0166] This disclosure describes exemplary embodiments with reference to cross-sectional views and / or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown in this disclosure, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0167] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

A display substrate includes a display area and a non-display area disposed around the display area, the display substrate comprising: A substrate, and a first signal line, a second signal line, a first jumper wire, and a first driving circuit disposed on one side of the substrate, wherein the first signal line, the second signal line, the first jumper wire, and the first driving circuit are all located in the non-display area, and the first jumper wire is used to connect the first signal line and the first driving circuit; The second signal line includes a first segment and a second segment connected to each other. The first segment is located between the first signal line and the first driving circuit. The first segment intersects with and is insulated from the first jumper wire. Multiple insulating layers are spaced apart between the first segment and the first jumper wire in the normal direction of the substrate. The number of second signal lines located on the same side of the display area is one or more, and the number of first jumpers that cross each of the multiple second signal lines is the same. The display substrate according to claim 1, wherein, The non-display area also includes: The third signal line is connected to the end of the first jumper wire away from the first signal line. The third signal line is used to connect the first jumper wire and the first drive circuit. The third signal line is arranged on the same layer as the first signal line. The display substrate according to claim 2, wherein, The first signal line includes a first voltage fan-out line, the first jumper wire includes a first voltage jumper wire, the third signal line includes a first voltage transmission line, the first voltage transmission line is connected to the first voltage input terminal of the first driving circuit, the first voltage fan-out line, the first voltage jumper wire and the first voltage transmission line are used to provide a first voltage signal to the first driving circuit, and the second signal line is not connected to the first driving circuit. The display substrate according to claim 3, wherein, The first driving circuit is a gate driving circuit, and the output terminal of the gate driving circuit is connected to the scan line of the display area; The second signal line includes a gating signal line, and the non-display area further includes a gating circuit. The control terminal of the gating circuit is connected to the gating signal line, the gating signal line is used to provide a control signal to the gating circuit, and the output terminal of the gating circuit is connected to the data line of the display area. The display substrate according to claim 2, wherein, The first signal line includes an output voltage signal line, the first jumper wire includes an output voltage jumper wire, the third signal line includes an output voltage transmission line, the output voltage transmission line is connected to the output terminal of the first driving circuit, and the first driving circuit is used to output signals to the output voltage transmission line, the output voltage jumper wire, and the output voltage signal line. The second signal line includes a second voltage transmission line, which is connected to the second voltage input terminal of the first driving circuit. The second voltage transmission line is used to provide a second voltage signal to the first driving circuit. According to claim 5, the display substrate, wherein, The output voltage signal line is connected to the scan line of the display area, and the first driving circuit is a gate driving circuit. The display substrate according to claim 1, wherein, The first line segment is located on the side of the first driving circuit closer to the display area. The display substrate according to claim 7, wherein, The first signal line includes a first voltage fan-out line, and the non-display area further includes a bonding area. The first voltage fan-out line is connected to the bonding area and is located between the bonding area and the display area. In the orthographic projection of the first driving circuit in the direction pointing to the display area, the first line segment does not overlap with the display area, and the first line segment is located on the side of the display area closer to the binding area. The display substrate according to claim 8, wherein, The first line segment includes a first end and a second end. The second line segment connected to the first end is located between the first voltage fan-out line and the display area, and the second line segment connected to the second end is located between the first voltage fan-out line and the bonding area. The display substrate according to claim 8, wherein, The first jumper wire includes a first voltage jumper wire, and the non-display area further includes: A common voltage fan-out line, a common voltage jumper wire, and a common voltage transmission line are connected in sequence. The common voltage fan-out line is also connected to the bonding area, and the common voltage transmission line is also connected to the display area. The first line segment is located between the common voltage fan-out line and the common voltage transmission line. The common voltage jumper wire and the first line segment intersect and are insulated from each other. The common voltage jumper wire and the first voltage jumper wire are arranged on the same layer. The common voltage fan-out line, the common voltage transmission line, and the first voltage fan-out line are arranged on the same layer. The display substrate according to claim 10, wherein, The second signal line includes a gating signal line, in which a first segment intersecting the first voltage jumper and a first segment intersecting the common voltage jumper are interconnected. The display substrate according to claim 7, wherein, The first signal line includes an output voltage signal line, which is connected to the display area, and in the orthographic projection of the first driving circuit in the direction pointing to the display area, the first line segment at least partially overlaps with the display area. The display substrate according to claim 12, wherein, The second signal line includes a second voltage transmission line, the first jumper includes an output voltage jumper, and the non-display area further includes: The fourth signal line is located between the first driving circuit and the first segment of the second voltage transmission line, and / or between the first segment of the second voltage transmission line and the display area. The fourth signal line and the output voltage jumper intersect each other and are insulated from each other. The fourth signal line and the second segment are arranged on the same layer. The thickness of the insulation layer between the fourth signal line and the output voltage jumper is less than or equal to the thickness of the insulation layer between the first segment of the second voltage transmission line and the output voltage jumper. The display substrate according to claim 12, wherein, The display area includes multiple scan lines arranged along the column direction. The second signal line includes a second voltage transmission line. The first jumper includes an output voltage jumper. The second voltage transmission line intersects with the multiple output voltage jumpers. In the column direction, the spacing between two adjacent output voltage jumpers is approximately an integer multiple of the spacing between two adjacent scan lines. The display substrate according to claim 12, wherein, The second signal line includes a second voltage transmission line, the first jumper includes an output voltage jumper, the second voltage transmission line intersects with multiple output voltage jumpers, and the first segments that intersect with different output voltage jumpers in the same second voltage transmission line are separated from each other, and two adjacent first segments are connected by the second segment. The display substrate according to claim 12, wherein, The second signal line includes a second voltage transmission line, the first jumper includes an output voltage jumper, the second voltage transmission line intersects with multiple output voltage jumpers, and the first segments that intersect with different output voltage jumpers on the same second voltage transmission line are interconnected. The display substrate according to claim 1, wherein, The second line segment is a single-layer trace, which is a trace located in a single film layer. The display substrate according to claim 1, wherein, The second line segment includes a first layer of traces and a second layer of traces. The first layer of traces and the second layer of traces are stacked in the normal direction of the substrate. The first layer of traces is disposed in the same layer as the first line segment and is interconnected with it. The second layer of traces is disposed in a different layer from the first line segment and is connected through vias. The display substrate according to any one of claims 1 to 18, wherein, The display substrate includes: A first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, and a fifth conductive layer are sequentially stacked along the normal direction of the substrate, with the first conductive layer disposed close to the substrate; The plurality of insulating layers located between the first line segment and the first jumper wire include at least two adjacent insulating layers among the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer. The display substrate according to claim 19, wherein, The first jumper is located in the first conductive layer, and the first line segment is located in the second conductive layer, the third conductive layer, the fourth conductive layer, or the fifth conductive layer; or The first jumper is located in the second conductive layer, and the first line segment is located in the first conductive layer, the fourth conductive layer, or the fifth conductive layer; or The first jumper wire is located in the third conductive layer, and the first line segment is located in the first conductive layer, the fourth conductive layer, or the fifth conductive layer; or The first jumper is located in the fourth conductive layer, and the first line segment is located in the first conductive layer, the second conductive layer, or the third conductive layer; or The first jumper is located in the fifth conductive layer, and the first line segment is located in the first conductive layer, the second conductive layer, or the third conductive layer. A display device, comprising: The display substrate as described in any one of claims 1 to 20; as well as A driving circuit is connected to the non-display area of ​​the display substrate and is used to drive the display substrate to perform display.

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