Independent refresh of memory dies based on temperature information

Abstract

A memory system includes a first memory die, a second memory die, and a memory controller. A memory controller circuit is coupled to the first memory die and the second memory die. The memory controller circuit receives first temperature information corresponding to a temperature of the first memory die and second temperature information corresponding to a temperature of the second memory die. The memory controller also determines a first refresh rate for the first memory die based on the first temperature information and a second refresh rate for the second memory die based on the second temperature information. The second refresh rate is different than the first refresh rate.

Description

Technical Field

[0001] The examples disclosed herein generally relate to independently determining the refresh rate of a memory integrated circuit die based on temperature information of the memory integrated circuit die. Background Technology

[0002] Memory devices comprise multiple memory integrated circuit (IC) dies. Memory IC dies or memory dies are interconnected. A memory controller is coupled to the memory IC die via a channel. The memory controller transmits read / write command signals and refresh signals to the memory IC die via the channel. The refresh signal instructs the memory IC die to perform a memory refresh process. The refresh signal controls the frequency at which the memory refresh process is performed. The memory refresh process involves periodically reading information from regions of the memory IC die and rewriting information to the same regions. The process of reading and writing data preserves the data. In a memory IC die, each bit of memory data is stored as the presence or absence of charge on a capacitive element. Over time, the charge decreases (e.g., leakage). The charge may decrease to the point where the stored data is lost. Refreshing the data restores the charge, thus preserving the data. A memory refresh cycle is used to repeatedly perform the refresh process. Summary of the Invention

[0003] In one example, a memory system includes a first memory die, a second memory die, and a memory controller. The memory controller circuitry is coupled to the first and second memory dies. The memory controller circuitry receives first temperature information corresponding to the temperature of the first memory die and second temperature information corresponding to the temperature of the second memory die. The memory controller further determines a first refresh rate for the first memory die based on the first temperature information and determines a second refresh rate for the second memory die based on the second temperature information. The second refresh rate differs from the first refresh rate.

[0004] In one example, the memory controller receives first temperature information corresponding to the temperature of a first memory die and second temperature information corresponding to the temperature of a second memory die. Furthermore, the memory controller determines a first refresh rate for the first memory die based on the first temperature information and a second refresh rate for the second memory die based on the second temperature information. The second refresh rate differs from the first refresh rate.

[0005] In one example, a method includes: receiving, at a memory controller, first temperature information corresponding to the temperature of a first memory die; and receiving, at a memory controller, second temperature information corresponding to the temperature of a second memory die. The method further includes: at a memory controller, determining, based on the first temperature information, a first refresh rate of the first memory die; and at a memory controller, determining, based on the second temperature information, a second refresh rate of the second memory die. The second refresh rate differs from the first refresh rate.

[0006] These and other aspects can be understood by referring to the following detailed description. Attached Figure Description

[0007] To gain a more detailed understanding of the features described above, a more specific description of the brief summary can be obtained by referring to the exemplary embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical exemplary embodiments and should not be considered as limiting the scope of the description.

[0008] Figure 1 A block diagram of a memory system is shown.

[0009] Figure 2 A block diagram of a memory device is shown.

[0010] Figure 3 A flowchart illustrating a method for controlling the refresh of a memory device is provided.

[0011] Figure 4 A timing diagram for the refresh signal used in a memory die is shown.

[0012] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures. It is conceivable that elements of one example can be advantageously incorporated into other examples. Detailed Implementation

[0013] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may be drawn to scale or not, and elements with similar structures or functions are indicated by similar reference numerals in all the drawings. It should be noted that the drawings are intended only to facilitate the description of the features. They are not intended as an exhaustive description of the features, nor as a limitation on the scope of the claims. Furthermore, the illustrated examples do not necessarily possess all the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example even if not so illustrated or so explicitly described.

[0014] A memory device comprises multiple memory integrated circuit (IC) dies or chips. A memory IC die may be referred to as a memory die. Each memory IC die includes one or more memory cells (e.g., bit cells) that store bit values. The memory device is coupled to a memory controller (memory controller circuitry). The memory controller controls the writing of data to the memory IC die, the reading of data from the memory IC die, and the refreshing of the memory IC die.

[0015] Memory cells in a memory IC die store bit values ​​as the presence or absence of charge. For example, a memory cell includes one (or more) capacitor elements, and the bit value is stored as the presence or absence of charge within the capacitor elements. A memory cell is refreshed by reading data from the memory cell and writing data back to the memory cell. Over time, the capacitor elements in the memory cell leak charge, thus reducing the charge stored by the capacitor elements. The memory refresh process refreshes the data stored within the memory cell.

[0016] The memory refresh process is performed periodically during the memory refresh cycle. Each memory refresh cycle refreshes a region (e.g., a portion) of the memory IC die. The memory refresh process is a background process. Furthermore, while the memory refresh process is being performed, the corresponding memory IC die cannot be used for read and write operations.

[0017] The memory refresh rate corresponds to the frequency at which the memory refresh process is performed. In one or more examples, the memory refresh rate corresponds to the temperature of the memory IC die in the memory device. For example, as the temperature increases, the amount of charge leaking from the memory cells of the memory IC die increases. Therefore, the memory refresh rate increases. In many memory devices, a common memory refresh rate is used for all memory IC dies of the memory device.

[0018] The memory refresh process described herein allows two or more memory IC dies to be controlled independently, with corresponding and sometimes different memory refresh rates. In one example, the memory controller receives a first temperature signal from a first memory IC die and a second temperature signal from a second memory IC device. The memory controller determines the refresh rate of the first memory IC die based on the first temperature signal, and also determines the refresh rate of the second memory IC die based on the first temperature signal. Therefore, the refresh rate of the second memory IC die is determined independently of the refresh rate of the first memory IC die. The refresh rate of the first memory IC die may differ from the refresh rate of the second IC die and depends on the temperatures of both the first and second memory IC dies. In examples where the temperature of the first memory IC die is greater than that of the second memory IC die, the refresh rate of the first memory IC die is increased to be greater than that of the second memory IC die.

[0019] When a memory IC die is refreshed, it cannot be used for read and write commands. Therefore, a higher memory refresh rate reduces the amount of time a memory IC die can be used to perform read and write operations, thus degrading its performance. In memory devices where each memory IC die uses a common memory refresh rate, as the temperature of one memory IC die increases, the refresh rates of all other memory IC dies also increase. However, the temperature of one or more memory IC dies may not necessarily require an increase in the corresponding memory refresh rate. The memory refresh process described below allows the memory refresh rates of two or more memory IC dies to be controlled independently of each other. Therefore, the performance of the corresponding memory device is improved compared to a memory device where all memory IC dies have the same refresh rate. In memory devices as described herein, the refresh rate of one or more memory IC dies can be maintained at a lower rate compared to another memory IC die, thereby increasing the availability and corresponding bandwidth of that one or more memory IC dies.

[0020] Figure 1 An IC system 100 is illustrated. The IC system 100 includes an IC device 110, a substrate 120, and a memory device 130. The IC device 110 is coupled to the memory device 130 through vias and traces disposed in one or more metal layers within the substrate 120.

[0021] IC system 100 may be referred to as a package device. In one or more examples, IC system 100 may be referred to as a memory system. In one example, IC system 100 is coupled to another substrate (e.g., a package substrate) and / or other devices (e.g., a processor and / or a memory device).

[0022] In one example, IC device 110 is one or more processing devices. In one or more examples, IC device 110 represents one or more processing devices. The one or more processing devices may be microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. In one example, IC device 110 may be a processing device that is one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. IC device 110 may be configured to execute instructions for performing the operations and steps described herein.

[0023] In one example, IC device 110 includes memory controller circuitry 112. Memory controller circuitry 112 generates and outputs control signals for memory device 130. For example, memory controller circuitry 112 receives data signals and / or other signals, and generates command signals (e.g., read command signals and / or write command signals) and / or control signals (e.g., refresh signals) from the data signals. The command signals and control signals are output to memory device 130.

[0024] Substrate 120 includes one or more metal layers and dielectric layers. The metal layers are disposed between alternating dielectric layers. In one example, substrate 120 is an interposer. In another example, substrate 120 is a package substrate. Substrate 120 may be coupled to another substrate. In one or more examples, one or more additional processor devices and / or memory devices are disposed on and / or coupled to substrate 120.

[0025] Memory device 130 includes logic die 132 and memory die 134. Memory dies 134 are interconnected with each other and with logic die 132. In one example, memory dies 134 are vertically stacked on top of logic die 132.

[0026] A logic die 132 is disposed on a substrate 120. The logic die 132 is communicatively coupled to an IC device 110. In one example, the logic die 132 receives commands from the IC device 110 and transmits the commands to a memory die 134. In one example, the logic die 132 includes memory controller circuitry that at least partially controls the memory die 134 (e.g., generates read command signals, write command signals, and / or other control signals for the memory die 134). For example, memory controller circuitry 112 is included within the logic die 132.

[0027] Memory die 134 can be non-volatile memory. For example, memory die 134 can be random access memory (RAM). In one example, memory die 134 is dynamic RAM (DRAM). In another example, memory die 134 can be other types of RAM (e.g., field-effect transistor memory or magnetoresistive memory, etc.). In one example, memory die is high-bandwidth memory (HBM).

[0028] Memory die 134 can be grouped into memory die groups 140, 142, 144, and 146. Each memory die group is identified by an identifier or stack identifier (SID). For example, memory die group 140 is assigned SID0, memory die group 142 is assigned SID1, memory die group 144 is assigned SID2, and memory die group 146 is assigned SID3. The SID can be referred to as the "rank" of the memory die and is used to identify a specific memory die group when communicating with memory die 134.

[0029] Memory die 134 is coupled to IC device 110 via one or more channels. These channels are used to transmit data signals and control signals (e.g., read command signals, write command signals, and refresh signals) from memory controller circuitry 112 to memory die 134. In one example, memory die 134 is coupled to IC device 110 via N channels. N is a number of two or greater. In one example, N is 16. In other examples, N is greater than or less than 16.

[0030] In one example, the one or more channels are used by each memory die in each group 140, 142, 144, and 146 of memory die 134 to couple with the memory controller circuitry 112 of IC device 110. For example, each memory die in each group 140, 142, 144, and 146 of memory die 134 is coupled to IC device 110 via one or more different channels. Each memory die within each group 140, 142, 144, and 146 is assigned a SID and one or more channels. The SID and channels are used to transmit signals from memory controller circuitry 112 to the corresponding memory die.

[0031] refer to Figure 2 The memory die 134 of the memory device 130 includes 16 memory dies 1401 to 1464 grouped into memory die groups 140 to 146. Each memory die group 140 to 146 has four memory dies. In other examples, more or fewer groups may be used, and / or each group may have more or fewer memory dies 1401 to 1464.

[0032] The memory die group 140 includes memory dies 1401 to 1404. The memory die group 140 is assigned SID0. In addition, memory die 1401 is assigned channels 1 to 4, memory die 1402 is assigned channels 5 to 8, memory die 1403 is assigned channels 9 to 12, and memory die 1404 is assigned channels 13 to 16.

[0033] The memory die group 142 includes memory dies 1421 to 1424. The memory die group 142 is assigned SID1. In addition, memory die 1421 is assigned channels 1 to 4, memory die 1422 is assigned channels 5 to 8, memory die 1423 is assigned channels 9 to 12, and memory die 1424 is assigned channels 13 to 16.

[0034] The memory die group 144 includes memory dies 1441 to 1444. The memory die group 144 is assigned SID2. In addition, memory die 1441 is assigned channels 1 to 4, memory die 1442 is assigned channels 5 to 8, memory die 1443 is assigned channels 9 to 12, and memory die 1444 is assigned channels 13 to 16.

[0035] The memory die group 146 includes memory dies 1461 to 1464. The memory die group 146 is assigned SID3. In addition, memory die 1461 is assigned channels 1 to 4, memory die 1462 is assigned channels 5 to 8, memory die 1463 is assigned channels 9 to 12, and memory die 1464 is assigned channels 13 to 16.

[0036] The memory dies in each group 140 to 146 are assigned one or more common channels. Therefore, in order to communicate with a specific memory die, a SID (or rank) and one (or more) channels are used. For example, SID0 and one or more channels 1 to 4 are used to communicate with memory die 1401, and SID1 and one or more channels 1 to 4 are used to communicate with memory die 1421.

[0037] Each memory die 1401 to 1464 is associated with a temperature sensor 2001 to 2064. Temperature sensors 2001 to 2064 may be located inside or outside the corresponding memory die 1401 to 1464. In one example, one or more of the temperature sensors 2001 to 2064 are located outside the memory die 134 or memory device 130. Temperature sensors 2001 to 2064 measure the temperature of the corresponding memory die 1401 to 1464. Temperature sensors 2001 to 2064 output the temperature information of the corresponding memory die 1401 to 1464 to IC device 110. In one example, the temperature information is output to logic die 132 and from logic die 132 to memory controller circuitry 112. Therefore, temperature sensors 2001 to 2064 output temperature information from the corresponding memory dies 1401 to 1464 to memory controller circuitry 112.

[0038] Temperature information includes the temperatures of the corresponding memory dies 1401 to 1464, the temperature variations of the corresponding memory dies 1401 to 1464, or values ​​relative to a temperature threshold or threshold value. Temperatures are expressed in degrees Celsius, Fahrenheit, or another unit of temperature measurement.

[0039] In one example, memory controller circuitry 112 transmits a request for temperature information for one or more memory dies 1401 to 1464. For example, memory controller circuitry 112 transmits a request for temperature information from each of the memory dies 1401 to 1404. In one example, memory controller circuitry 112 transmits a request for temperature information for each channel (e.g., channels 1 to 16) of each SID (e.g., SID0, SID1, SID2, and SID3). Memory controller circuitry 112 determines the temperature of each memory die 1401 to 1464 based on the temperature information for each channel and each SID. In one example, memory controller circuitry 112 has a mapping indicating which channel(s) and which SID correspond to which memory die among memory dies 1401 to 1464. Memory controller circuitry 112 uses the mapping to associate temperature information with specific memory dies 1401 to 1404.

[0040] As described in more detail below, the memory controller circuit 112 updates the refresh rate of the SID memory die groups 140 to 146 or memory dies 1401 to 1464 based on corresponding temperature information. For example, Figure 3A flowchart illustrating a method 300 for updating the refresh rate of a memory die is provided. While method 300 is described with respect to the memory controller circuitry 112 of IC device 110, in other examples, method 300 may be performed by the memory controller circuitry of logic die 132 and / or other memory controller circuitry coupled to memory device 130.

[0041] At 310 of method 300, a request for temperature information is output from the memory controller circuitry to the memory die. For example, memory controller circuitry 112 generates a request for temperature information and outputs it to memory dies 1401 through 1464. In one example, memory controller circuitry 112 is coupled to memory dies 1401 through 1464 via a core test interface. The interface enables communication via a test multiplexing and integration interface for embedded cores (e.g., memory dies) and associated circuitry. An example of a test interface is an IEEE 1500 interface. In other examples, other interfaces that allow temperature information to be communicated from each memory die 1401 through 1464 to memory controller circuitry 112 may be used.

[0042] Temperature information requests are transmitted via the channel used for each SID. (Reference) Figure 2 Temperature information requests are transmitted for SID0 and channels 1-16, SID1 and channels 1-16, SID2 and channels 1-16, and SID3 and channels 1-16. In one example, the temperature information request is set via a bit stream, where the first bit corresponds to SID0 (e.g., memory die group 140) and channels 1-16, the second bit corresponds to SID1 (e.g., memory die group 142) and channels 1-16, the third bit corresponds to SID2 (e.g., memory die group 144) and channels 1-16, and the fourth bit corresponds to SID3 (e.g., memory die group 148) and channels 1-16. In other examples, different bit stream configurations may be used. The bit stream is transmitted from memory controller circuitry 112 to memory dies 1401-1464.

[0043] At 320 of method 300, the memory controller receives temperature information from the memory dies. For example, memory controller circuitry 112 receives temperature information from memory dies 1401 through 1464. In one example, temperature information is provided for each memory die in each of the memory die groups 140 through 146. In another example, temperature information is provided for one memory die in each of the memory die groups 140 through 146. In one or more examples, temperature information is provided for one or more memory dies in each of the memory die groups 140 through 146.

[0044] Temperature information can be conveyed via a bit stream, which includes a first bit corresponding to the temperature information of SID0 (e.g., memory die group 140) and channels 1 to 16, a second bit corresponding to the temperature information of SID1 (e.g., memory die group 142) and channels 1 to 16, a third bit corresponding to the temperature information of SID2 (e.g., memory die group 144) and channels 1 to 16, and a fourth bit corresponding to the temperature information of SID3 (e.g., memory die group 146) and channels 1 to 16. Other bit stream configurations may be used in other examples.

[0045] At 330 of method 300, the refresh rate of the first memory die group is determined based on temperature information. For example, memory controller circuit 112 determines the refresh rate of one or more memory dies 1401 to 1404 of memory die group 140 based on the corresponding temperature information. Memory controller circuit 112 receives temperature information for each SID (e.g., memory die group) and each channel, and associates the temperature information with the corresponding memory dies 1401 to 1404. For example, memory die group 140 corresponds to SID0, memory die 1401 corresponds to channels 1 to 4, memory die 1402 corresponds to channels 5 to 8, memory die 1403 corresponds to channels 9 to 14, and memory die 1404 corresponds to channels 15 to 16. Memory controller circuit 112 determines the temperature information (e.g., bits of the bit stream) associated with SID0 and each corresponding memory die 1401 to 1404. Memory controller circuitry 112 compares temperature information with one or more temperature thresholds to determine the refresh rate of SID0 (e.g., memory die group 140) and / or each memory die 1401 to 1404. In one example, one or more temperature thresholds are used. The number of temperature thresholds may correspond to the number of different refresh rates. In one example, a first temperature threshold indicates a first refresh rate, and a second temperature threshold indicates a second refresh rate. Temperatures below the first temperature threshold correspond to the first refresh rate, temperatures above the first temperature threshold and below the second temperature threshold correspond to the second refresh rate, and temperatures above the second temperature threshold correspond to a third refresh rate. The second refresh rate is greater than the first refresh rate, and the third refresh rate is greater than the second refresh rate. In this example, memory controller circuitry 112 compares temperature information with thresholds to determine the refresh rate of memory die group 140.

[0046] In one or more examples, a lookup table is used to determine the refresh rate based on temperature information. For example, the lookup table includes temperature ranges associated with different refresh rates. In this example, memory controller circuitry 112 compares the temperature information with the temperature ranges within the lookup table to determine the refresh rate of the memory die set 140.

[0047] In one example, memory controller circuitry 112 determines the highest temperature of each memory die group 140 to 146 and uses the highest temperature to determine the refresh rate of memory die group 140, as described above. In another example, an average temperature is determined based on the memory dies in each memory die group 140 to 146, and the average temperature is used to determine the refresh rate, as described above. In an example where memory dies 1401 to 1464 are vertically stacked, the temperature of the top (e.g., the most vertical) memory die in each memory die group 140 to 146 is used to determine the refresh rate, as described above. In another example, the refresh rate of each memory die in memory die groups 140 to 146 is determined based on the corresponding temperature information. Each memory die can be updated at a different corresponding refresh rate; the highest refresh rate of the memory dies in a memory die group can be used as the refresh rate of the corresponding memory die group, or the average refresh rate of the memory dies in a memory die group can be used as the refresh rate of the corresponding memory die group.

[0048] In one example, memory controller circuitry 112 determines the refresh rate of memory dies 1401 to 1404 of memory die group 140 based on temperature information as described above. In another example, memory controller circuitry 112 determines different refresh rates for two or more memory dies among memory dies 1401 to 1404 of memory die group 140 based on temperature information as described above.

[0049] At 340 of method 300, the refresh rate of the second memory die group is determined based on temperature information. For example, memory controller circuit 112 determines the refresh rate of one or more memory dies 1421 to 1424 of memory die group 142 based on the corresponding temperature information, as described above with respect to memory die group 140.

[0050] The memory controller circuit 112 can also determine the refresh rates of memory die groups 144 and 146 (e.g., SID2 and SID3), as described above in 330 and 340 of method 300.

[0051] As can be seen from the above, the memory controller circuit 112 independently determines the refresh rate of each memory die group 140 to 146. For example, memory die group 140 may be associated with a higher temperature than memory die group 142, and therefore, the refresh rate of memory die group 140 is greater than that of memory die group 142. In one or more examples, additionally or alternatively, the memory controller circuit 112 independently determines the refresh rate of each memory die 1401 to 1464 of each memory die group 140 to 146.

[0052] At 350 of method 300, a first refresh control signal is output to a first memory die and a second refresh control signal is output to a second memory die. In one example, memory controller circuit 112 outputs the first refresh control signal to first memory dies 1401 to 1464 and the second refresh control signal to second memory dies 1401 to 1464. In one or more examples, the first refresh signal corresponds to a refresh rate that is greater than or less than the refresh rate of the second refresh signal.

[0053] In one example, the first memory die is one of memory dies 1401 to 1404 in memory die group 140, and the second memory die is one of memory dies 1421 to 1424 in memory die group 142. A refresh control signal is generated based on the refresh rate determined at 330 and 340 of method 300. The refresh control signal is used to independently control the refresh of memory die groups 140 to 144. For example, different refresh control signals are used for each memory die group 140 to 144. The refresh control signal is based on a refresh rate independently determined for each memory die group 140 to 146. Therefore, the refresh control signal independently controls the refresh rate of each memory die group 140 to 146.

[0054] In another example, the refresh rate of each memory die in each memory die group 140 to 146 is independently controlled based on the corresponding refresh control signal.

[0055] The memory controller circuit 112 transmits refresh control signals to the memory device 130. For example, the memory controller circuit 112 transmits refresh control signals to the logic die 132, and the logic die routes the refresh control signals to each of the memory dies 1401 to 1464.

[0056] Refresh control signals can be transmitted to memory dies 1401 to 1464 via corresponding channels and SIDs. For example, in order to output refresh control signals to memory die 1401, channels 1 to 4 and SID0 are used as indicators to route refresh control signals to memory die 1401.

[0057] Multiple memory dies can share a common channel. In this example, the corresponding SID is used to route refresh control signals to the correct memory die. Figure 4 Waveform 400 is illustrated. Waveform 400 indicates refresh control signal 410 for memory die 1401 and refresh control signal 420 for memory die 1421. Memory dies 1401 and 1421 share a common channel (e.g., channel 1). Therefore, control signals 410 and 420 in Figure 4The symbols are illustrated as interleaved. Control signals 410 and 420 are transmitted during refresh cycle 402.

[0058] The memory refresh process described in method 300 allows for independent control of the refresh process of memory die groups 140 to 146 and / or memory dies 1401 to 1464. Memory die groups 140 to 146 and / or memory dies 1401 to 1464 have corresponding memory refresh rates. Independently controlling the refresh rate allows memory dies with lower temperatures to have lower refresh rates than memory dies with higher temperatures. Memory dies with lower refresh rates have greater availability than memory dies with higher refresh rates. Therefore, independently controlling the refresh rate of different memory dies based on temperature improves the performance of the corresponding memory devices.

[0059] The techniques disclosed above can be expressed in the following non-limiting embodiments.

[0060] Example 1. A memory system comprising: a first memory die; a second memory die; and a memory controller circuit coupled to the first memory die and the second memory die, wherein the memory controller circuit is configured to: receive first temperature information corresponding to the temperature of the first memory die; receive second temperature information corresponding to the temperature of the second memory die; determine a first refresh rate of the first memory die based on the first temperature information; and determine a second refresh rate of the second memory die based on the second temperature information, wherein the second refresh rate is different from the first refresh rate.

[0061] Example 2. According to the memory system of Example 1, the memory system further includes: a third memory die, wherein: the first memory die and the third memory die are associated with a first identifier; the second memory die is associated with a second identifier; the first memory die and the second memory die are coupled to the memory controller circuit via a first channel; and the third memory die is coupled to the memory controller circuit via a second controller.

[0062] Example 3. The memory system according to Example 2, wherein the memory controller circuit is further configured to receive third temperature information corresponding to the temperature of the third memory die, wherein the first refresh rate is determined based on the third temperature information, and wherein the first refresh rate is also used for the third memory die.

[0063] Example 4. The memory system according to Example 3, wherein the memory controller circuit is further configured to: output a first refresh signal to the first memory die and the third memory die based on the first refresh rate; and output a second refresh signal to the second memory die based on the second refresh rate.

[0064] Example 5. The memory system according to Example 2, wherein the memory controller circuit is further configured to: receive third temperature information from the third memory die; and determine a third refresh rate of the third memory die based on the third temperature information.

[0065] Example 6. The memory system according to Example 5, wherein the memory controller circuit is further configured to: output a first refresh signal to the first memory die based on the first refresh rate; output a second refresh signal to the second memory die based on the second refresh rate; and output a third refresh signal to the third memory die based on the third refresh rate.

[0066] Example 7. The memory system according to Example 1, wherein the temperature of the first memory die is greater than the temperature of the second memory die, and wherein the first refresh rate is greater than the second refresh rate.

[0067] Example 8. The memory system according to Example 1, wherein the first memory die and the second memory die are stacked vertically on top of each other.

[0068] Example 9. A memory controller, the memory controller being configured to: receive first temperature information corresponding to the temperature of a first memory die; receive second temperature information corresponding to the temperature of a second memory die; determine a first refresh rate of the first memory die based on the first temperature information; and determine a second refresh rate of the second memory die based on the second temperature information, wherein the second refresh rate is different from the first refresh rate.

[0069] Example 10. A memory controller according to Example 9, wherein the memory controller is coupled to the first memory die and the second memory die via a first channel and to the third memory die via a second channel, wherein the first memory die and the third memory die are associated with a first identifier, and wherein the second memory die is associated with a second identifier.

[0070] Example 11. According to the memory controller of Example 10, the memory controller is further configured to receive third temperature information corresponding to the temperature of the third memory die, wherein the first refresh rate is determined based on the third temperature information, and wherein the first refresh rate is also used for the third memory die.

[0071] Example 12. According to the memory controller of Example 11, the memory controller is further configured to: output a first refresh signal to the first memory die and the third memory die based on the first refresh rate; and output a second refresh signal to the second memory die based on the second refresh rate.

[0072] Example 13. According to the memory controller of Example 10, the memory controller is further configured to: receive third temperature information from the third memory die; and determine a third refresh rate of the third memory die based on the third temperature information.

[0073] Example 14. According to the memory controller of Example 13, the memory controller is further configured to: output a first refresh signal to the first memory die based on the first refresh rate; output a second refresh signal to the second memory die based on the second refresh rate; and output a third refresh signal to the third memory die based on the third refresh rate.

[0074] Example 15. The memory controller according to Example 9, wherein the temperature of the first memory die is greater than the temperature of the second memory die, and wherein the first refresh rate is greater than the second refresh rate.

[0075] Example 16. The memory controller according to Example 9, wherein the first memory die and the second memory die are stacked vertically on top of each other.

[0076] Example 17. A method comprising: receiving at a memory controller first temperature information corresponding to the temperature of a first memory die; receiving at the memory controller second temperature information corresponding to the temperature of a second memory die; determining at the memory controller a first refresh rate of the first memory die based on the first temperature information; and determining at the memory controller a second refresh rate of the second memory die based on the second temperature information, wherein the second refresh rate is different from the first refresh rate.

[0077] Example 18. According to the method of Example 17, the method further includes: receiving third temperature information corresponding to the temperature of the third memory die, wherein the first refresh rate is determined based on the third temperature information, and wherein the first refresh rate is also used for the third memory die.

[0078] Example 19. The method according to Example 17, the method further includes: outputting a first refresh signal to the first memory die and the third memory die based on the first refresh rate; and outputting a second refresh signal to the second memory die based on the second refresh rate.

[0079] Example 20. The method according to Example 17, the method further comprising: receiving third temperature information from a third memory die; determining a third refresh rate of the third memory die based on the third temperature information; outputting a first refresh signal to the first memory die based on the first refresh rate; outputting a second refresh signal to the second memory die based on the second refresh rate; and outputting a third refresh signal to the third memory die based on the third refresh rate.

[0080] While the foregoing is directed to specific examples, other and additional examples may be devised without departing from the basic scope of the invention, the scope of which is defined by the appended claims.

Claims

1. A memory system, the memory system comprising: First memory die; Second memory die; and A memory controller circuit, coupled to the first memory die and the second memory die, wherein the memory controller circuit is configured to: Receive first temperature information corresponding to the temperature of the first memory die; Receive second temperature information corresponding to the temperature of the second memory die; The first refresh rate of the first memory die is determined based on the first temperature information. as well as The second refresh rate of the second memory die is determined based on the second temperature information, wherein the second refresh rate is different from the first refresh rate.

2. The memory system according to claim 1, further comprising: The third memory die, wherein: The first memory die and the third memory die are associated with a first identifier; The second memory die is associated with the second identifier; The first memory die and the second memory die are coupled to the memory controller circuit via a first channel; and The third memory die is coupled to the memory controller circuit via the second controller.

3. The memory system of claim 2, wherein the memory controller circuit is further configured to receive third temperature information corresponding to the temperature of the third memory die, wherein the first refresh rate is determined based on the third temperature information, and wherein the first refresh rate is also used for the third memory die.

4. The memory system of claim 3, wherein the memory controller circuit is further configured to: Based on the first refresh rate, a first refresh signal is output to the first memory die and the third memory die; and The second refresh signal is output to the second memory die based on the second refresh rate.

5. The memory system of claim 2, wherein the memory controller circuit is further configured to: Receive third temperature information from the third memory die; and The third refresh rate of the third memory die is determined based on the third temperature information.

6. The memory system of claim 1, wherein the temperature of the first memory die is greater than the temperature of the second memory die, and wherein the first refresh rate is greater than the second refresh rate.

7. The memory system of claim 1, wherein the first memory die and the second memory die are stacked vertically on top of each other.

8. A memory controller, the memory controller being configured to: Receive first temperature information corresponding to the temperature of the first memory die; Receive second temperature information corresponding to the temperature of the second memory die; The first refresh rate of the first memory die is determined based on the first temperature information. as well as The second refresh rate of the second memory die is determined based on the second temperature information, wherein the second refresh rate is different from the first refresh rate.

9. The memory controller of claim 8, wherein the memory controller is coupled to the first memory die and the second memory die via a first channel and to the third memory die via a second channel, wherein the first memory die and the third memory die are associated with a first identifier, and wherein the second memory die is associated with a second identifier.

10. The memory controller of claim 9, further configured to receive third temperature information corresponding to the temperature of the third memory die, wherein the first refresh rate is determined based on the third temperature information, and wherein the first refresh rate is also used for the third memory die.

11. The memory controller of claim 10, further configured to: Based on the first refresh rate, a first refresh signal is output to the first memory die and the third memory die; and The second refresh signal is output to the second memory die based on the second refresh rate.

12. The memory controller of claim 9, further configured to: Receive third temperature information from the third memory die; and The third refresh rate of the third memory die is determined based on the third temperature information.

13. The memory controller of claim 8, wherein the temperature of the first memory die is greater than the temperature of the second memory die, and wherein the first refresh rate is greater than the second refresh rate.

14. The memory controller of claim 8, wherein the first memory die and the second memory die are stacked vertically on top of each other.

15. A method, the method comprising: The memory controller receives first temperature information corresponding to the temperature of the first memory die. The memory controller receives second temperature information corresponding to the temperature of the second memory die. The first refresh rate of the first memory die is determined at the memory controller based on the first temperature information. as well as The second refresh rate of the second memory die is determined at the memory controller based on the second temperature information, wherein the second refresh rate is different from the first refresh rate.

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