Memory device and operating method thereof, memory system

Abstract

The present disclosure provides a memory device and an operating method thereof, a memory system, the memory device including a memory cell array including a plurality of memory cells each in one of Qx2 K states, the Q being a number of state groups, each of the state groups including 2 K states; wherein a plurality of state combinations of two of the memory cells are used to store a plurality of bits of data; and one of the two memory cells is in an intermediate state group of the Q state groups and the other is in one of a plurality of other state groups excluding the intermediate state group, or both of the two memory cells are in the plurality of other state groups; the plurality of other state groups being located on both sides of the intermediate state group, the Q and K each being an integer.

Description

Memory devices and their operating methods, memory systems Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to memory devices and methods of operating them, and memory systems. Background Technology

[0002] Since its introduction, NAND flash memory, in both the 2D and 3D eras, has been driven by core advancements in performance, lifespan, reliability, storage density, and cost reduction per unit cell. Achieving increased storage density and lower cost per unit cell primarily relies on expanding the capacity of NAND flash memory. A key method for this expansion is logical scaling, which increases storage density by expanding the number of bits in the memory cells. Maintaining performance while expanding logically is a critical challenge that needs to be addressed. Summary of the Invention

[0003] This disclosure provides a memory device, its operation method, and a memory system.

[0004] In a first aspect, embodiments of this disclosure provide a memory device, including:

[0005] A storage cell array comprising multiple storage cells, each of which is in a Q×2 array. K One of several states, where Q is the number of state groups, and each state group comprises 2... K The states described;

[0006] The states of the two storage units form multiple state combinations to store multi-bit data; and one of the two storage units is in an intermediate state group within Q state groups, while the other is in one of the other multiple state groups excluding the intermediate state group, or both storage units are in the other multiple state groups; the other multiple state groups are located on both sides of the intermediate state group, and Q and K are both integers.

[0007] Secondly, embodiments of this disclosure provide yet another memory device, including:

[0008] A storage cell array comprising: a plurality of storage cells, each of the storage cells being in a Q×2 array. K One of the states; wherein the states of two memory cells coupled to the same word line form multiple state combinations for storing Q+2K bits of data, where Q and K are both integers;

[0009] The peripheral circuitry is coupled to the memory cell array; wherein, when reading each bit of the Q-bit data, the peripheral circuitry is configured as follows:

[0010] Apply the first read voltage to the select word line;

[0011] After applying the first read voltage, a second read voltage is applied to the select word line.

[0012] Thirdly, embodiments of this disclosure provide a memory system, including:

[0013] At least one memory device as described in either the first or second aspect of this disclosure;

[0014] A memory controller, coupled to the memory device, is configured to control the memory device.

[0015] Fourthly, embodiments of this disclosure provide an operation method for a memory device, the memory device comprising: a memory cell array, the memory cell array comprising: a plurality of memory cells, each of the memory cells being in a Q×2 array. K One of the states; wherein the states of two memory cells coupled to the same word line form multiple state combinations for storing Q+2K bits of data, where Q and K are both integers;

[0016] The operation method includes:

[0017] When reading each bit of the Q-bit data, a first read voltage is applied to the select word line; after applying the first read voltage, a second read voltage is applied to the select word line.

[0018] In this embodiment, the intermediate state group is located among other state groups. For memory cells in the intermediate state group, when a threshold voltage shift occurs, they are more likely to cross the threshold voltage distribution and be incorrectly read as being in a state group lower or higher than the intermediate state group. In other words, the read noise of the intermediate state group is relatively high, and the read reliability is relatively low compared to other state groups. In this embodiment, both memory cells are in other state groups, or one of the two memory cells is in the intermediate state group and the other is in another state group. That is, state combinations formed by states within the intermediate state group of the two memory cells are excluded. This reduces the read noise of state combinations of the two memory cells, thereby improving the reliability of data reading. Attached Figure Description

[0019] Figure 1 is a schematic diagram of an exemplary system provided in an embodiment of this disclosure.

[0020] Figure 2a is a schematic diagram of a memory card provided in an embodiment of this disclosure.

[0021] Figure 2b is a schematic diagram of the SSD provided in an embodiment of this disclosure.

[0022] Figure 3 is a schematic diagram of a memory including peripheral circuitry provided in an embodiment of this disclosure.

[0023] Figure 4 is a schematic diagram of a memory cell array including NAND memory strings provided in an embodiment of this disclosure.

[0024] Figure 5 is a schematic diagram of the bit changes in the storage unit provided in the embodiments of this disclosure.

[0025] Figure 6 is a schematic diagram of the peripheral circuit provided in an embodiment of this disclosure.

[0026] Figure 7 shows the correspondence between the state groups of the two storage units and the 3-bit data provided in the embodiments of this disclosure.

[0027] Figure 8 is a table showing the correspondence between the state groups and 3-bit data of the two storage units provided in the embodiments of this disclosure.

[0028] Figure 9 shows the correspondence between the state groups of the two storage units and the 3-bit data provided in the embodiments of this disclosure.

[0029] Figure 10 shows the correspondence between the state groups of the two storage units and the 3-bit data provided in the embodiments of this disclosure.

[0030] Figure 11 shows the correspondence between the state groups of the two storage units and the 3-bit data provided in the embodiments of this disclosure.

[0031] Figure 12 shows the correspondence between the state groups of the two storage units and the 3-bit data provided in the embodiments of this disclosure.

[0032] Figure 13 shows the correspondence between the status codes and 3-bit data of the two storage units provided in the embodiments of this disclosure.

[0033] Figures 14a to 14c are schematic diagrams illustrating the relationship between the values ​​of bit0, bit1, and bit2 provided in the embodiments of this disclosure and the status codes of the two storage units.

[0034] Figure 15 shows the correspondence between the status codes and 3-bit data of the two storage units provided in the embodiments of this disclosure.

[0035] Figures 16 and 17 are schematic diagrams of the threshold voltage distribution of a storage cell storing 1.5 bits of data provided in an embodiment of this disclosure.

[0036] Figure 18 is a schematic diagram illustrating the reliability of the status codes provided in the embodiments of this disclosure.

[0037] Figure 19 is a schematic diagram of the threshold voltage distribution of a storage unit storing 4.5 bits of data provided in an embodiment of this disclosure.

[0038] Figure 20 is a schematic diagram of the peripheral circuit including the page buffer provided in an embodiment of this disclosure.

[0039] Figure 21 is a flowchart illustrating the operation method provided in an embodiment of this disclosure. Detailed Implementation

[0040] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0041] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0042] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0043] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0045] Increasing storage density to reduce the cost per unit of storage cell has always been the direction and driving force for the development of NAND flash memory. Achieving this increase in storage density and reduction in cost per unit of storage cell mainly relies on the expansion of NAND flash memory capacity. One important method of capacity expansion is logical expansion. Logical expansion refers to increasing storage density by expanding the number of bits in a storage cell. Currently, the conventional logical expansion method is to expand the number of bits in a single storage cell. NAND flash memory has successively progressed to SLC (Single-Cell Memory), MLC (Multi-Cell Memory), TLC (Telematics Memory), and QLC (Quick Memory Memory). While logical expansion provides storage density, it also comes at the cost of performance and lifespan. Considering both storage capacity and reliability, a solution allowing a single storage cell to store X.5 bits of data has been proposed.

[0046] Figure 1 is a block diagram of an exemplary system including memory provided in an embodiment of this disclosure. The exemplary system 100 may include a host 110 and a memory system 120. The exemplary system 100 may include, but is not limited to, a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory device 122 therein; the host 110 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)).

[0047] In one embodiment of this disclosure, host 110 may be configured to send data to or receive data from memory system 120. Here, memory system 120 may include memory controller 121 and one or more memory devices 122. Memory devices 122 may include, but are not limited to, NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), and nano random access memory (NRAM).

[0048] In one embodiment of this disclosure, a memory controller 121 may be coupled to a memory device 122 and a host 110, and is used to control the memory device 122. Exemplarily, the memory controller 121 may be designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, and mobile phones. In some embodiments, the memory controller 121 may also be designed to operate in a high duty cycle environment, such as a Solid State Disk (SSD) or an embedded Multi-Media Card (eMMC), and the SSD or eMMC may be used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0049] Furthermore, the memory controller 121 can manage the data in the memory device 122 and communicate with the host. The memory controller 121 can be configured to control operations such as reading, erasing, and programming of the memory device 122; it can also be configured to manage various functions related to data stored or to be stored in the memory device 122, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.; and it can also be configured to process error checking and correction codes (ECC) for data read from or written to the memory device 122. In addition, the memory controller 121 can perform any other suitable functions, such as formatting the memory device 122, or communicating with external devices (e.g., host 110 in FIG. 1) according to a specific communication protocol. For example, the memory controller 121 can communicate with an external host through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Development Equipment (IDE), FireWire, etc.

[0050] In one embodiment of this disclosure, the memory controller 121 and one or more memory devices 122 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 120 can be implemented and packaged into different types of end electronic products. As shown in FIG2a, the memory controller 121 and a single memory device 122 can be integrated together to form a memory card 210. The memory card 210 may include PC cards (Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, Multimedia Cards (MMC, RS-MMC (Reduced-Size MMC), MMCmicro), SD cards (SD, miniSD, microSD, SDHC (Secure Digital High Capacity)), UFS, etc. The memory card 210 may also include a memory card connector 211 that couples the memory card 210 to a host (e.g., host 110 in FIG1). In another embodiment shown in FIG2b, the memory controller 121 and a plurality of memory devices 122 may be integrated together to form an SSD 220. The SSD 220 may also include an SSD connector 221 that couples the SSD 220 to a host (e.g., host 110 in FIG1). In some embodiments, the storage capacity and / or operating speed of the SSD 220 is greater than the storage capacity and / or operating speed of the memory card 210.

[0051] It should be noted that the memory involved in one embodiment of this disclosure can be a semiconductor memory, which is a solid-state electronic device for storing data information manufactured using semiconductor integrated circuit technology. Figure 3 is a schematic diagram of a memory including peripheral circuitry provided in an embodiment of this disclosure, wherein the memory device 300 can be the memory device 122 in Figures 1 to 2b. As shown in Figure 3, the memory device 300 can include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301, etc. Here, the memory cell array can be a NAND flash memory cell array, wherein the memory cells are arranged in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above the substrate. In some embodiments, each NAND memory string 308 can include a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as voltage or charge, which depends on the number of electrons trapped in the memory cell region. In addition, each memory cell 306 in the aforementioned memory cell array 301 can be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0052] As shown in Figure 3, each NAND memory string 308 may include a source select transistor 310 at its source terminal and a drain select transistor 312 at its drain terminal. The source select transistor may also be referred to as a bottom select transistor, and the drain select transistor may also be referred to as an top select transistor. The source select transistor 310 and the drain select transistor 312 may be configured to activate the selected NAND memory string 308 (column of the array) during read and program operations.

[0053] In some implementations, the sources of NAND memory strings 308 within the same block 304 are coupled via a common source line (SL) 314 (e.g., a common source line). In other words, according to some implementations, all NAND memory strings 308 within the same block 304 have an array common source (ACS). According to some implementations, the drain selection transistor 312 of each NAND memory string 308 is coupled to a corresponding bit line 316, allowing data to be read from or written to the bit line 316 via an output bus (not shown).

[0054] In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than a threshold voltage having a drain select transistor 312) or a deselection voltage (e.g., 0V) to the gate of the corresponding drain select transistor 312 via one or more drain select gate lines (DSG lines) 313; and / or by applying a selection voltage (e.g., higher than a threshold voltage having a source select transistor 310) or a deselection voltage (e.g., 0V) to the gate of the corresponding source select transistor 310 via one or more source select gate lines 315. The NAND memory strings 308 can thus be distinguished as selected NAND memory strings or unselected NAND memory strings.

[0055] As shown in Figure 3, the NAND memory string 308 can be organized into multiple blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each block 304 is a basic data unit for an erase operation, i.e., all memory cells 306 on the same block 304 are erased simultaneously. To erase memory cells 306 in a selected block, an erase voltage (Vers), such as a high positive voltage (e.g., 20V or higher), can be used to bias the source line 314 of the selected block and the unselected blocks on the same plane as the selected block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks.

[0056] The memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318. There are multiple word lines 318, and each word line 318 is coupled to multiple memory cells 306. When a word line 318 is selected, read or program operations can be performed on the memory cells 306 coupled to the word line 318.

[0057] Figure 4 is a schematic diagram of a memory cell array including NAND memory strings provided in an embodiment of this disclosure. As shown in Figure 4, the NAND memory string 308 can extend vertically through the memory stack layer 404 above the substrate 402. The substrate 402 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0058] The memory stack 404 may include alternating gate conductive layers 406 and dielectric layers 408, wherein the number of pairs of gate conductive layers 406 and dielectric layers 408 determines the number of memory cells 306 in the memory cell array 301. The gate conductive layer 406 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. The gate conductive layer 406 may extend laterally at the top of the memory stack 404 as a drain select gate line 313, laterally at the bottom of the memory stack 404 as a source select gate line 315, or laterally between the drain select gate line 313 and the source select gate line 315 as a word line 318. It should be understood that although Figure 3 shows a source select gate line (SSG line) 315 and a drain select gate line (DSG line) 313, the number of source select gate lines 315 and the number of drain select gate lines 313 (as well as the number of source select transistors 310 and drain select transistors 312 coupled to the source select gate line 315 and the drain select gate line 313, respectively) may vary in other examples.

[0059] As shown in Figure 4, the NAND memory string 308 includes a channel structure extending vertically through the memory stack layer 404. In some embodiments, the channel structure includes channel holes filled with a semiconductor material (e.g., as a semiconductor channel) and a dielectric material (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping layer"), and a barrier layer. The channel structure may have a pillar shape (e.g., a cylindrical shape). According to some embodiments, the semiconductor channel 420, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer composed of silicon oxide / silicon oxynitride / silicon oxide (ONO). It should be understood that the channel structure depicted in Figure 4 is for illustrative purposes only and may be modified in other examples. It should also be understood that, although not shown in Figure 4, additional components may be formed for the memory cell array 301, including but not limited to gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0060] Figure 5 is a schematic diagram illustrating the bit changes of a storage cell provided in an embodiment of this disclosure. In some embodiments, the storage cell (e.g., storage cell 306 in Figure 3) may be a single-level storage cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, the first storage state "0" may correspond to a first threshold voltage distribution, and the second storage state "1" may correspond to a second threshold voltage distribution. In other embodiments, the storage cell may be a multi-level storage cell capable of storing more than one bit of data in more than four storage states. For example, the storage cell may store two bits of data in four storage states, referred to as a two-level storage cell or a multi-level storage cell (MLC). The storage cell may also store three bits of data in eight storage states, referred to as a triple-level storage cell (TLC). The storage cell may also store four bits of data in sixteen states, referred to as a quad-level storage cell (QLC). Alternatively, the storage cell may also store five bits of data in thirty-two states, referred to as a penta-level storage cell (PLC).

[0061] The division of storage cell states can be understood as dividing the threshold voltage of the storage cell. Taking MLC as an example, the threshold voltage of the storage cell can be divided into four intervals, corresponding to states P1, P2, P3, and P4. States P1 to P4 are the four states of MLC in Figure 5. As shown in Figure 5, as the number of bits stored in a storage cell increases, the amount of data stored in a single storage cell increases, resulting in increased storage density and reduced cost per unit storage cell. However, at the same time, the threshold voltage of a storage cell is divided more finely, so the control of the number of electrons entering the storage layer during write operations needs to be more precise, thus increasing the write time. Similarly, more read voltage is required during read operations, which may prolong the read time and reduce the read speed. Furthermore, as shown in Figure 5, the read window between the threshold voltage distributions of adjacent states becomes smaller and smaller, increasing the probability of errors during data writing or reading, leading to a decrease in the reliability of the storage cell. Therefore, in terms of performance, from PLC to SLC, reliability gradually deteriorates, and read and write speeds gradually decrease.

[0062] The embodiments of this disclosure propose a storage unit that stores X.5 bits of data, such as 1.5 bits, 2.5 bits, 3.5 bits, and 4.5 bits. Specifically, the storage density of a single storage unit storing 1.5 bits is between that of SLC and MLC; the storage density of a single storage unit storing 2.5 bits is between that of MLC and TLC; the storage density of a single storage unit storing 3.5 bits is between that of TLC and QLC; and the storage density of a single storage unit storing 4.5 bits is between that of QLC and PLC. Taking the single storage unit storing 4.5 bits of data shown in Figure 5 as an example, the storage unit can store 4.5 bits of data in 24 states, compared to the 32 states required by PLC. The read window between the 24 states is larger, resulting in better reliability and faster data retrieval. Compared to QLC, a single storage unit can store more data, thus achieving higher storage density and lower cost. Storing X.5 bits per storage unit achieves a better balance between storage density and reliability, meeting market demands.

[0063] Referring back to Figure 3, the peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, source select gate line 315, and drain select gate line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for implementing write and read operations on the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via bit line 316, word line 318, source line 314, source select gate line 315, and drain select gate line 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 is a schematic diagram of the peripheral circuit provided in an embodiment of this disclosure. The peripheral circuit 302 includes a page buffer / sensor amplifier 504, read logic circuit 505, column decoder / BL driver 506, row decoder / WL driver 508, voltage generator 510, control logic 512, register 514, interface (I / F) 516, and data bus 518. It should be understood that in some examples, additional peripheral circuitry not shown in Figure 6 may also be included.

[0064] Page buffer sense amplifier 504 can be configured to read data from memory cell array 301 and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer sense amplifier 504 can store programming data (write data) to be programmed into memory cell array 301 coupled to a word line 318. In another example, page buffer sense amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer sense amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during a read operation.

[0065] The read logic circuit 205 can be configured to perform logical operations on the hard read value output by the page buffer / sensor amplifier 504 during an X.5-bit data read operation to obtain the read data.

[0066] The column decoder / BL driver 506 can be configured to be controlled by control logic 512 and to select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0067] The row decoder / word WL driver 508 can be configured to be controlled by control logic 512 and to select / deselect block 304 of the memory cell array 301 and word lines 318 in block 304 according to control signals generated by the control logic. The row decoder / WL driver 508 can also be configured to drive word lines 318 using different word line voltages generated from voltage generator 510. In some embodiments, the row decoder / WL driver 508 can also select / deselect source select gate line 315 and drain select gate line 313. The row decoder / WL driver 508 is configured to drive source select gate line 315 using different SSG line voltages generated from voltage generator 510, and / or drive drain select gate line 313 using different DSG line voltages generated from voltage generator 510.

[0068] Voltage generator 510 can be configured to be controlled by control logic 512 and generate various word line voltages (e.g., read voltage, programming voltage, pass voltage, verification voltage, etc.), bit line voltages, ground voltages, various SSG line voltages (e.g., select voltage, deselect voltage) and various DSG line voltages (e.g., select voltage, deselect voltage) to be supplied to memory cell array 301.

[0069] Control logic 512 can be coupled to each of the peripheral circuit sections described above and is configured to control the operation of each peripheral circuit section. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register to store status information, command opcodes, and command addresses for controlling the operation of the peripheral circuits. In some embodiments, control logic 512 can receive programming commands from a memory controller (e.g., memory controller 106 in FIG. 1) and send control signals to various peripheral circuit sections, such as row decoder / word line driver 508, column decoder / bit line driver 506, and voltage generator 510, to perform programming operations on source selection transistors coupled to source selection gate lines.

[0070] Interface 516 can be coupled to control logic 512 and act as a control buffer to buffer control commands (e.g., programming commands) received from the memory controller or host and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the memory controller or host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and act as a data input / output (I / O) interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0071] Referring back to Figure 5, storing X.5 bits of data in a single memory cell is achieved through the combination of the states of two memory cells. This disclosure provides a programming method and a read operation method for jointly storing data in two memory cells. In some embodiments, the memory device includes a memory cell array, which includes a plurality of memory cells, each memory cell being in a Q×2 state. K A state is one of several states, where Q is the number of state groups, and each state group consists of 2 states. K There are 10 states; wherein, the states of two storage units form multiple state combinations for storing multiple bits of data, and one of the two storage units is in the middle state group within the Q state groups, and the other is in one of the other multiple state groups other than the middle state group, or both storage units are in the other multiple state groups, and the other multiple state groups are located on both sides of the middle state group; Q and K are both integers.

[0072] The memory device in this embodiment can be the memory device shown in any of the embodiments in Figures 1 to 6. The memory device includes a memory cell array, which includes a plurality of memory cells arranged in an array. The memory cells are NAND flash memory cells. For example, the memory cell array can be the memory cell array 301 in Figures 3 and 6, and the memory cells can be the memory cells shown in any of the embodiments in Figures 3 to 5.

[0073] In this embodiment of the disclosure, each storage cell is in Q×2 K A state is one of several states, where Q is the number of state groups, and each state group consists of two consecutive states. K There are two states. The states of two memory units can form Q. 2 ×2 2K There are several state combinations. After removing some unreliable state combinations, the remaining state combinations can store Q+2K bits of data.

[0074] This paper refers to the two storage units that jointly store data as the first storage unit and the second storage unit. In Q+2K bits of data, Q bits of data are jointly stored by combinations of the state groups of the first and second storage units. This can be understood as the Q state groups of the first and second storage units forming various combinations to store Q bits of data. However, not all combinations are used to store data; unreliable combinations are discarded, and the remaining 2... Q A combination is used to store Q-bit data.

[0075] Unreliable combinations that are eliminated include combinations where the first storage unit is in the intermediate state group and the second storage unit is in the intermediate state group. The intermediate state group is one of the Q state groups. The Q state groups include several other state groups besides the intermediate state group. These other state groups are located on either side of the intermediate state group; that is, the intermediate state group is neither the highest nor the lowest state group among the Q state groups, but rather has other state groups on both sides.

[0076] After eliminating unreliable combinations, the remaining combinations for storing Q-bit data include: combinations where both the first and second storage units are in other state groups; combinations where the first storage unit is in an intermediate state group and the second storage unit is in other state groups; and combinations where the first storage unit is in other state groups and the second storage unit is in an intermediate state group. That is, both storage units are in multiple other state groups, or one of the two storage units is in an intermediate state group and the other is in one of multiple other state groups.

[0077] For example, Q is greater than or equal to 3, and can be an odd number such as 3 or 7. That is, the number of state groups can be 3, 7, etc. The odd-numbered state groups are numbered in ascending order of threshold voltage distribution, and the middle state group is the state group in the middle position among the odd-numbered state groups. For example, it could be the second state group in a group of 3, or the fourth state group in a group of 7.

[0078] The following example, with Q=3, illustrates the combination of state groups used to store Q bit data.

[0079] Figure 7 illustrates a correspondence between the state groups of two storage units and 3-bit data. The three state groups of the first storage unit are arranged horizontally on the 3x3 grid, while the three state groups of the second storage unit are arranged vertically on the left side of the grid. The data in the 3x3 grid represents the possible values ​​of the 3-bit data jointly stored by the state groups of the two storage units. For example, the three state groups are ordered from smallest to largest according to the threshold voltage as low state group S0, intermediate state group S1, and high state group S2. The state groups of the first and second storage units can form 9 combinations. Excluding the combination formed by the intermediate state group S1 of the first and second storage units, the remaining 8 combinations can store 3-bit data.

[0080] The eight combinations are as follows: Combination 1 to Combination 8. Combination 1 includes the first storage unit in low state group S0 and the second storage unit in low state group S0; Combination 2 includes the first storage unit in low state group S0 and the second storage unit in intermediate state group S1; Combination 3 includes the first storage unit in low state group S0 and the second storage unit in high state group S2; Combination 4 includes the first storage unit in intermediate state group S1 and the second storage unit in high state group S2; Combination 5 includes the first storage unit in high state group S2 and the second storage unit in high state group S2; Combination 6 includes the first storage unit in high state group S2 and the second storage unit in intermediate state group S1; Combination 7 includes the first storage unit in high state group S2 and the second storage unit in low state group S0; Combination 8 includes the first storage unit in intermediate state group S1 and the second storage unit in low state group S0. As shown in Figure 7, each of these eight combinations can store 3 bits of data.

[0081] The threshold voltage of a memory cell is shifted due to electric field coupling between adjacent memory cells. Additionally, during read operations, the pass voltage applied to the non-select word line also causes a shift in the threshold voltage. Since the threshold voltage distribution of the intermediate state group lies between the threshold voltage distributions of the high and low state groups, memory cells within the intermediate state group are more prone to this threshold voltage shift, making them more likely to be incorrectly read as being in either the low or high state group. In other words, memory cells within the intermediate state group experience greater read noise, resulting in lower read reliability compared to other state groups. In this embodiment, combinations of intermediate state groups between two memory cells are excluded, ensuring that at least one of the two memory cells is in another state group. This reduces the read noise of state combinations between two memory cells and improves the reliability of data reads.

[0082] In some embodiments, Gray code encoding is used to encode the data corresponding to the first to eighth combinations.

[0083] Figure 8 shows the correspondence between the first to eighth combinations in Figure 7 and the 3-bit data in tabular form. As shown in Figures 7 and 8, the data corresponding to the first to eighth combinations are 111, 110, 010, 011, 001, 000, 100, and 101, respectively. Since there is only one bit change between adjacent codes in Gray code, even if a single bit error occurs during data storage or transmission, it is easier to detect and correct. This improves the reliability of data storage and reduces the risk of data loss.

[0084] Referring again to Figure 7, the center of the 3x3 grid corresponds to the combination formed by the intermediate state group S1 of the first storage unit and the intermediate state group S1 of the second storage unit, which is not used to store data. The first to eighth combinations are arranged counter-clockwise along the 3x3 grid. In some embodiments, the Gray code sequence in Figure 7 can be rotated to obtain different correspondences between the first to eighth combinations and 3-bit data. Figure 9 shows another correspondence obtained by rotating the Gray code sequence in the 3x3 grid of Figure 7 one step clockwise. Specifically, the data corresponding to the first to eighth combinations are 110, 010, 011, 001, 000, 100, 101, and 111, respectively.

[0085] Similarly, rotating the Gray code sequence in the 3x3 grid of Figure 7 clockwise by two steps yields the data corresponding to the first to eighth combinations as 010, 011, 001, 000, 100, 101, 111, and 110, respectively. Rotating by three steps yields the same data. Rotating by four steps yields the same data. Rotating by five steps, as shown in Figure 10, yields the same data. After six rotations, the data corresponding to the first to eighth combinations are 100, 101, 111, 110, 010, 011, 001, and 000, respectively. After seven rotations, the data corresponding to the first to eighth combinations are 101, 111, 110, 010, 011, 001, 000, and 100, respectively.

[0086] In some embodiments, the Gray code sequence in Figure 7 can be reversed to obtain another correspondence between the first to eighth combinations and the 3-bit data. Figure 11 shows another correspondence between the first to eighth combinations and the 3-bit data obtained after reversing the Gray code sequence in the nine-square grid of Figure 7. Specifically, the data corresponding to the first to eighth combinations are 111, 101, 100, 000, 001, 011, 010, and 110, respectively.

[0087] For example, the Gray code sequence in Figure 11 can be rotated to obtain another correspondence between the first to eighth combinations and the 3-bit data. For instance, rotating the Gray code sequence in the 3x3 grid of Figure 11 clockwise by one step yields the data corresponding to the first to eighth combinations as 101, 100, 000, 001, 011, 010, 110, and 111, respectively. Rotating by two steps yields the data corresponding to the first to eighth combinations as 100, 000, 001, 011, 010, 110, 111, and 101, respectively. Rotating by three steps, as shown in Figure 12, yields the data corresponding to the first to eighth combinations as 000, 001, 011, 010, 110, 111, 101, and 100, respectively. After four rotations, the data corresponding to the first to eighth combinations are 001, 011, 010, 110, 111, 101, 100, and 000, respectively. After five rotations, the data corresponding to the first to eighth combinations are 011, 010, 110, 111, 101, 100, 000, and 001, respectively. After six rotations, the data corresponding to the first to eighth combinations are 010, 110, 111, 101, 100, 000, 001, and 011, respectively. After seven rotations, the data corresponding to the first to eighth combinations are 110, 111, 101, 100, 000, 001, 011, and 010, respectively.

[0088] As shown above, rotating and reversing the Gray code sequence in the 3x3 grid of Figure 7 yields 16 correspondences between the first to eighth combinations and 3-bit data, resulting in 16 encoding schemes. None of these 16 encoding schemes include combinations formed by the intermediate state groups of the first and second storage units. Therefore, using any of these 16 encoding schemes can reduce read noise and improve data storage reliability. Furthermore, encoding the data corresponding to the first to eighth combinations using Gray code only causes errors in a single bit, which are easily detected and corrected, thus improving data storage reliability and reducing the risk of data loss.

[0089] In some embodiments, state groups can be represented by state codes, which may include multiple bits. In this embodiment, since the number of state groups Q is 3, the state code may include two bits, or simply two bits. Two bits have four possible values: 11, 01, 00, and 10. Three of these four values ​​can be used to represent three state groups. For example, 11, 01, and 00 can be used to represent three state groups, or 11, 10, and 00 can be used. In some specific implementations, state group S0 can be represented by 11, state group S1 by 01, and state group S2 by 00.

[0090] This disclosure uses 11 to represent state group S0, 01 to represent state group S1, and 00 to represent state group S2 as an example to illustrate how to obtain 3-bit data jointly stored in two storage units using the status codes of two storage units. Figure 13 shows a correspondence between the 3-bit data bits 0, 1, and 2 and the status codes of the two storage units. The encoding method in Figure 13 is the same as that in Figure 7, only further showing the status codes of each state group. Taking 110 for bits 0, 1, and 2 as an example, the status code of the first storage unit is 11, and the status code of the second storage unit is 01. Taking 011 for bits 0, 1, and 2 as 011, the status code of the first storage unit is 01, and the status code of the second storage unit is 00. Other cases can be understood by referring to Figure 13.

[0091] The correspondence in Figure 13 establishes the following first logical relationship between the values ​​of bit0, bit1, and bit2 and the status codes of the two storage units: bit0 = (M1V1 & M2V2) | M2V1 bit1 = (M1V2 & (~M2V2)) | M1V1 bit2 = (M1V2 & M2V1) | ((~M1V1) & (~M2V2))

[0092] This paper defines the status code of the first storage unit as the first status code and the status code of the second storage unit as the second status code. As shown in Figure 13, the first status code can be any one of 11, 01, and 00, and the second status code can also be any one of 11, 01, and 00. M1V1 represents the first bit of the first status code. When the first storage unit is in state group S0, the value of the first bit of the first status code is 1; when the first storage unit is in state group S1 or S2, the value of the first bit of the first status code is 0. M1V2 represents the second bit of the first status code. Refer to Figure 13 to understand the value of the second bit of the first status code corresponding to the first storage unit being in different state groups. M2V1 represents the first bit of the second status code, and M2V2 represents the second bit of the second status code. Refer to Figure 13 to understand the values ​​of the first and second bits of the second status code corresponding to the second storage unit being in different state groups.

[0093] Referring to the first logical relationship described above, the value of bit0 can be obtained by performing an AND operation on M1V1 and M2V2, and then performing an OR operation on the result with M2V1. Figure 14a verifies that bit0 in each data in the 3x3 grid of Figure 13 can be calculated using the above logical expression. Columns 1 to 3 in Figure 14a show the eight possible values ​​of the 3-bit data (bit0, bit1, bit2). Columns 4 and 5 show the state groups of the first and second storage units corresponding to each value. Columns 6 to 8 show the values ​​of M1V1, M2V2, and M2V1 respectively. Column 9 shows the result of the logical operation (M1V1 & M2V2) | M2V1. The result of the operation in column 9 is the same as the value of bit0 in column 1, verifying that bit0 can be calculated using the above logical expression.

[0094] The value of bit1 can be obtained by performing an AND operation on (~M2V2) and M1V2, and then performing an OR operation on the result of the AND operation with M1V1. Figure 14b verifies that bit1 in each data in the 3x3 grid can be calculated using the above logical expression. The value of bit2 can be obtained by performing an AND operation on M1V2 and M2V1, an AND operation on (~M1V1) and (~M2V2), and then performing an OR operation on the result of the two AND operations. Figure 14c verifies that bit2 in each data in the 3x3 grid can be calculated using the above logical expression.

[0095] Referring to the first logical relationship described above, each bit in bit0, bit1, and bit2 is calculated based on two bits of one of the first and second status codes, and at least one bit of the other. The 16 encoding methods described above have an equivalent logical topology to the encoding method shown in Figure 13. Therefore, when using any of the 16 encoding methods, calculating the value of each bit in bit0, bit1, and bit2 requires two bits of one of the first and second status codes, and at least one bit of the other.

[0096] The following verification uses the encoding method in Figure 10 as an example. Figure 15 has the same encoding method as Figure 10, only further showing the state codes of the state groups. The correspondence in Figure 15 makes the following second logical relationship exist between bit0, bit1, bit2 and the state codes of the two storage units: bit0=(M1V1&(~M2V1))|(~M2V2) bit1=((~M1V1)&(~M2V2))|(~M1V2) bit2=(M1V2&(~M2V2))|((~M1V1)&M2V1)

[0097] In the second logical relation, the logical expressions for calculating bit0, bit1 and bit2 are different from those in the first logical relation, but they have in common that the value of each bit in bit0, bit1 and bit2 is determined by two bits of one of the first status code and the second status code, and at least one bit of the other.

[0098] Each bit in the first status code of the first storage unit and the second status code of the second storage unit can be obtained during the read operation. By referring to the above logical relationship and performing logical operations, the values ​​of bit0, bit1 and bit2 can be calculated.

[0099] Figure 16 shows a schematic diagram of the threshold voltage distribution of a storage cell storing 1.5 bits of data. The following explanation, based on Figure 16 and from the perspective of status codes, explains how excluding combinations formed by intermediate state groups of two storage cells and using other combinations to jointly store data can reduce read noise.

[0100] When a single storage cell stores 1.5 bits of data, each state group includes one state. As shown in Figure 16, state group S0 includes state P0, state group S1 includes state P1, and state group S2 includes state P2. A first read voltage V1 is used to distinguish between state groups S0 and S1, and V1 can be located between the threshold voltage distribution corresponding to state P0 and the threshold voltage distribution corresponding to state P1. A second read voltage V2 is used to distinguish between state groups S1 and S2, and V2 can be located between the threshold voltage distribution corresponding to state P1 and the threshold voltage distribution corresponding to state P2.

[0101] When the first read voltage V1 is applied to the word line, since V1 is between the threshold voltage distributions of state groups S0 and S1, the probability of accurately reading the first digit of the status code of the memory cell in state groups S0 and S1 is the same. R- and R+ are used to indicate the read results of the memory cells in state groups S0 and S1, respectively. However, V1 is far from the threshold voltage distribution of state group S2, so the probability of accurately reading the first digit of the status code of the memory cell in state group S2 is higher. R++ is used to indicate the read result of the memory cell in state group S2, where R++ is more reliable than R+, and R- and R+ have the same reliability.

[0102] Similarly, as shown in Figure 17, when the second read voltage V2 is applied, since V2 is between the threshold voltage distributions of state groups S1 and S2, the probability of accurately reading the second bit of the status code of the memory cells in state groups S1 and S2 is the same. R- and R+ are used to indicate the read results of the memory cells in state groups S1 and S2, respectively. However, V2 is far from the threshold voltage distribution of state group S0, so the probability of accurately reading the second bit of the status code of the memory cells in state group S0 is higher. R-- is used to indicate the read result of the memory cells in state group S0, where R-- is more reliable than R-.

[0103] Figure 18 shows the read results of the memory cells in each state group when the first read voltage V1 and the second read voltage V2 are applied. As shown in Figure 18, in the combination formed by the intermediate state group of two memory cells, the read result of the status code is R- or R+, which has lower reliability, while the other 8 combinations all include the results R++ or R--, which have higher reliability. That is, the read reliability of the status code is higher in the other 8 combinations, and the reliability of the values ​​of bit0, bit1 and bit2 obtained after logical operation is higher, which improves the reliability of the read operation of the memory device and is conducive to high-speed reading.

[0104] In some embodiments, when the number of state groups is 3, each storage unit includes 3×2K states, and two storage units can be combined to form 9×2K states. 2K A combination of states. Eliminate 2 states from the intermediate state group of the first storage unit. K Within the intermediate state group of the first state and the second storage unit, 2 K The 2 states formed 2K A combination of states, using the remaining 8×2 2K A combination of states is used to store 3+2K bits of data.

[0105] In 3+2K bits of data, as described above, the 3 bits of data are jointly stored by the state groups of the first and second storage units. For example, K bits of data in the 2K data are stored separately in the first storage unit, and the remaining K bits are stored separately in the second storage unit.

[0106] In some implementations, when the memory device receives three bits of data (bit0, bit1, bit2), it can convert the data of bits0, bit1, bit2 into a first status code of the first memory cell and a second status code of the second memory cell. The first status code can be any one of 11, 01, and 00, and the first status code can determine the first target state group to which the first memory cell will be programmed. The second status code can be any one of 11, 01, and 00, and the second status code can determine the second memory cell to which the second target state group will be programmed.

[0107] As the memory device continues to receive K bits of data, it can be further determined that the first memory cell will be programmed to 2 bits within the first target state group. K Which of the states? That is, the first storage unit can use state group 2. K The memory device uses two states to store K bits of data. Similarly, when the memory device receives another K bits of data, it can further determine that the second memory cell will be programmed into the second target state group. K Which of the states? That is, the second storage unit can also use state 2 from the state group. K Each state is used to store an additional K bits of data.

[0108] K is an integer greater than or equal to 0, such as 0, 1, 2, 3, etc. That is, each state group can include 1 state, 2 states, 4 states, 8 states, etc.

[0109] When each of the three state groups includes one state (K=0), each storage unit can be in one of the three states. It can select eight state combinations from the nine possible combinations formed by two storage units to store three bits of data. On average, this means a single storage unit stores 1.5 bits of data.

[0110] When each state group includes 2 states (K=1), each storage unit can be in one of 6 (3×2) states. From the 36 possible state combinations formed by two storage units, 32 reliable state combinations can be selected to store 5 bits of data. Therefore, it can be understood that a single storage unit stores 2.5 bits of data. For example, two storage units can be used together to store 3 bits of data, with each storage unit storing 1 bit of data independently.

[0111] When each state group contains 4 states (K=2), each storage unit can be in one of 12 (3×4) states. From the 144 possible state combinations formed by two storage units, 128 state combinations can be selected to store 7 bits of data. Therefore, it can be understood that a single storage unit stores 3.5 bits of data. For example, two storage units can be used together to store 3 bits of data, with each storage unit storing 2 bits of data independently.

[0112] When each state group contains 8 states (K=3), each storage unit can be in one of 24 (3×8) states. From the 576 possible state combinations formed by two storage units, 512 state combinations can be selected to store 9 bits of data. Therefore, it can be understood that a single storage unit stores 4.5 bits of data. For example, two storage units can be used together to store 3 bits of data, with each storage unit storing 3 bits of data independently.

[0113] In summary, when a single storage unit stores X.5 bits of data, 1.5 bits of that data are achieved by two storage units jointly storing 3 bits of data. These 3 bits are determined by the state groups to which the two storage units belong. Either both storage units are in one of several state groups other than the intermediate state group, or one storage unit is in the intermediate state group while the other is in one of several other state groups. Eliminating the case where both storage units are in the intermediate state group reduces the reading noise of these 3 bits, improves signal quality, reduces the probability of error correction failure, and lowers decoding time. Furthermore, it improves read reliability and makes high-speed reading easier to achieve.

[0114] This disclosure also provides a memory device, including a memory cell array and peripheral circuitry. The memory cell array includes a plurality of memory cells, each memory cell being in a Q×2 array. K One of the states; wherein, the states of two memory cells coupled to the same word line form multiple state combinations for storing Q+2K bits of data, where Q and K are both integers; peripheral circuitry is coupled to the memory cell array; wherein, when reading each bit of the Q bits of data, the peripheral circuitry is configured as follows:

[0115] Apply the first read voltage V1 to the select word line;

[0116] After applying the first read voltage, a second read voltage V2 is applied to the select word line, the voltage value of the first read voltage V1 being different from that of the second read voltage V2.

[0117] The first read voltage V1 is used to distinguish between adjacent first and second state groups among the Q state groups, and the second read voltage V2 is used to distinguish between adjacent second and third state groups. For example, the threshold voltages of the first, second, and third state groups increase sequentially, or the threshold voltages of the first, second, and third state groups decrease sequentially.

[0118] After applying the first read voltage V1 and the second read voltage V2 to the select word line, the first target state group to which the first memory cell belongs and the second target state group to which the second memory cell belongs can be determined. The first target state group is any one of the first to third state groups, and the second target state group is any one of the first to third state groups. By combining the combination of the three state groups of the two memory cells with the correspondence between the Q-bit data, the value of the bit to be read in the Q-bit data can be determined using the first and second target state groups.

[0119] A word line can be word line 318 as shown in Figure 3, with each word line 318 coupled to multiple memory cells 306. For example, the multiple memory cells coupled to the word line may include a first memory cell group and a second memory cell group, where the number of first memory cells in the first memory cell group is equal to the number of second memory cells in the second memory cell group. The i-th first memory cell in the first memory cell group and the i-th second memory cell in the second memory cell group form a pair, jointly storing Q+2K bits of data. When a first read voltage and a second read voltage are applied to the select word line, the state groups to which all first memory cells and all second memory cells belong can be read, thereby determining the value of the bit to be read in the Q bits of data jointly stored by each pair of first and second memory cells.

[0120] In some embodiments, when reading each bit of the Q-bit data, the peripheral circuitry is configured as follows:

[0121] Obtain a first status code and a second status code; wherein the first status code indicates that the first storage unit of the two storage units is in the first target status group, and the second status code indicates that the second storage unit is in the second target status group; determine the value of the bit to be read in the Q bit data based on the first status code and the second status code.

[0122] A status group can be represented by a status code, which consists of multiple bits. The first status code is the status code corresponding to the first target status group in which the first memory cell is located. The first target status code can be any one of multiple status codes corresponding to multiple status groups. The second status code is the status code corresponding to the second target status group in which the second memory cell is located. The second target status code can also be any one of multiple status codes corresponding to multiple status groups. After applying the first read voltage and the second read voltage to the select word line, the page buffer can directly obtain the first status code and the second status code. Since the status code includes bits, it can support logical operations. Therefore, logical operations can be performed based on the first status code and the second status code to determine the value of the bit to be read.

[0123] In this embodiment, status codes are introduced to represent status groups. Since status codes support logical operations, the value of the bit to be read in the Q data can be calculated in the peripheral circuit using hardware logic circuitry. This method of using hardware for logical operations is simple in process and highly reliable in result, while adding very little to the cost.

[0124] In some embodiments, the number of state groups Q is 3, and the threshold voltages of the first, second, and third state groups increase sequentially. For example, the first, second, and third state groups are respectively the S0 state group, the S1 state group, and the S2 state group. The voltage value of the first read voltage V1 is less than the second read voltage V2. The first read voltage V1 may be located between the threshold voltage distribution of the highest state in the S0 state group and the threshold voltage distribution of the lowest state in the S1 state group, and the second read voltage V2 may be located between the threshold voltage distribution of the highest state in the S1 state group and the threshold voltage distribution of the lowest state in the S2 state group.

[0125] As shown in Figure 16, the S0 state group includes the P0 state, the S1 state group includes the P1 state, and the S2 state group includes the P2 state. A first reading voltage V1 is used to distinguish between the S0 and S1 state groups. The first reading voltage V1 can be located between the threshold voltage distribution corresponding to the P0 state and the threshold voltage distribution corresponding to the P1 state. A second reading voltage V2 is used to distinguish between the S1 and S2 state groups. The second reading voltage V2 can be located between the threshold voltage distribution corresponding to the P1 state and the threshold voltage distribution corresponding to the P2 state.

[0126] Figure 19 illustrates the threshold voltage distribution of a memory cell storing 4.5 bits of data. When a single memory cell stores 4.5 bits of data, each state group includes 8 states. As shown in Figure 19, state group S0 includes states P0 to P7, state group S1 includes states P8 to P15, and state group S2 includes states P16 to P23. The first read voltage V1 can be located between states P7 and P8, and the second read voltage V2 can be located between states P15 and P16.

[0127] In some embodiments, when the number of state groups Q is 3, the state code includes two bits. For example, as shown in Figures 13 and 15, state group S0 is represented by state code 11, state group S1 by state code 01, and state group S2 by state code 00. The peripheral circuit is configured to: after applying a first read voltage V1 to the select word line, acquire the first bit of each of the first and second state codes; after applying a second read voltage V2 to the select word line, acquire the second bit of each of the first and second state codes.

[0128] Referring to Figures 13 and 16, after applying the first read voltage V1 to the select word line, since the first read voltage V1 can distinguish between state groups S0 and S1, the value read from the memory cell of state group S0 is 1, and the values ​​read from the memory cells of state groups S1 and S2 are 0. This is the same as the first digit of the status code of each of state groups S0, S1, and S2. Therefore, regardless of which state group the first and second memory cells are in, the first digit of the status code of that state group can be read, thus obtaining the first digit of each of the first and second status codes.

[0129] Referring to Figures 13 and 17, after applying the second read voltage V2 to the select word line, since the second read voltage V2 can distinguish between state group S1 and state group S2, the value read from the memory cells of state group S0 and state group S1 is 1, and the value read from the memory cell of state group S2 is 0. This is the same as the second bit of the status code of each of state group S0, state group S1, and state group S2. Therefore, the second bit of both the first and second status codes can be obtained by applying the second read voltage V2.

[0130] In some embodiments, when reading each bit of the Q-bit data, the peripheral circuitry is configured as follows:

[0131] The value of the bit to be read in the Q bit data is determined based on two bits of one of the first status code and the second status code, and at least one bit of the other.

[0132] Referring to the logical operations for bits 0, 1, and 2 shown in the first and second logical relationships above, the value of any bit in bits 0, 1, and 2 can be obtained by performing logical operations on two bits of one of the first and second status codes and at least one bit of the other. If each bit in the first and second status codes is considered a read result, then determining the value of any bit in bits 0, 1, and 2 requires at least three read results. In the first and second logical relationships, determining the values ​​of bits 0 and 1 requires three read results, while determining the value of bit 2 requires four read results. In other encoding methods using 16 encoding schemes, it is also possible that determining the value of bit 0 requires four read results, and determining the values ​​of bits 1 and 2 requires three read results.

[0133] In some embodiments, the peripheral circuitry is configured as follows:

[0134] Perform a first logical operation on one bit of the first status code and two bits of the second status code to obtain the value of the first bit of the Q-bit data;

[0135] Perform a second logical operation on two bits of the first status code and one bit of the second status code to obtain the value of the second bit in the Q-bit data;

[0136] Perform a third logical operation on two bits in the first status code and two bits in the second status code to obtain the value of the third bit in the Q-bit data.

[0137] Here, the first, second, and third bits of the Q-bit data do not correspond sequentially to bit0, bit1, and bit2; they are merely used to distinguish the three bits. The first, second, and third logical operations can be determined based on the logical relationship between bit0, bit1, bit2, and the status codes of the two storage units. For example, when using the encoding method shown in Figure 13, the three logical operations can be determined based on the first logical relationship described above. Alternatively, when using the encoding method shown in Figure 15, the three logical operations can be determined based on the second logical relationship described above. For example, the first, second, and third logical operations are different from each other.

[0138] Referring to the first or second logical relationship described above, bit0 can be obtained by performing a first logical operation on one bit of the first status code and two bits of the second status code; bit1 can be obtained by performing a second logical operation on two bits of the first status code and one bit of the second status code; and bit2 can be obtained by performing a third logical operation on two bits of the first status code and two bits of the second status code. It should be noted that the first logical operation may differ in different encoding methods. For example, using the encoding method shown in Figure 13, the first logical operation includes AND and OR operations, while using the encoding method shown in Figure 15, the first logical operation includes two NOT operations, an AND operation, and an OR operation. Similarly, the second logical operation and the third logical operation may differ in different encoding methods.

[0139] In some embodiments, the peripheral circuitry is configured as follows:

[0140] In the first reading phase, a first reading voltage V1 and a second reading voltage V2 are sequentially applied to the select word line;

[0141] In the second reading phase, a first reading voltage V1 and a second reading voltage V2 are sequentially applied to the select word line;

[0142] In the third reading stage, a first reading voltage V1 and a second reading voltage V2 are sequentially applied to the select word line.

[0143] When Q is 3, reading 3 bits of data requires three reading stages. In each reading stage, a first reading voltage V1 and a second reading voltage V2 are applied to the select word line, for a total of 6 reading voltages.

[0144] In some embodiments, the peripheral circuitry is configured as follows:

[0145] In the first reading stage, a first reading voltage V1 and a second reading voltage V2 are applied to the select word line to obtain a first status code and a second status code; a first logical operation is performed on one bit of the first status code and two bits of the second status code to obtain the value of the first bit of the Q bit data;

[0146] In the second reading stage, a first reading voltage V1 and a second reading voltage V2 are applied to the select word line to obtain a first status code and a second status code; a second logical operation is performed on two bits in the first status code and one bit in the second status code to obtain the value of the second bit in the Q-bit data;

[0147] In the third reading stage, a first reading voltage V1 and a second reading voltage V2 are applied to the select word line, and a third logic operation is performed on two bits in the first status code and two bits in the second status code to obtain the value of the third bit in the Q bit data.

[0148] The peripheral circuit can read Q bits of data bit by bit. When reading each bit of the Q bits of data, after applying the first read voltage V1 and the second read voltage V2 to the select word line to obtain the first status code and the second status code, the peripheral circuit (e.g., the read logic circuit 620 described later) can directly perform the corresponding logic operation to obtain the value of the bit to be read and output it, without having to wait for the read voltages of all three read stages to be applied before performing the logic operation. In this disclosure, the order of the first read stage, the second read stage, and the third read stage depends on the encoding method. When using the encoding method of Figure 13 or Figure 15, the second read stage is located after the first read stage, and the third read stage is located after the second read stage.

[0149] In some embodiments, each of the first logical operation, the second logical operation, and the third logical operation includes an AND operation and an OR operation.

[0150] In the two encoding schemes shown in Figures 13 and 15, each of the first, second, and third logical operations includes an AND operation and an OR operation. The other encoding schemes among the 16 schemes have equivalent logical topological structures to these two schemes; therefore, in other encoding schemes, the requirement that each of the first, second, and third logical operations includes an AND operation and an OR operation is also satisfied. The first, second, or third logical operation may also include a NOT operation, but the position and number of NOT operations may differ in different encoding schemes.

[0151] In some embodiments, as shown in FIG20, the peripheral circuit further includes: a first page buffer PB1, a second page buffer PB2, and a read logic circuit 620; wherein, the first page buffer PB1 is coupled to the first storage unit A and is configured to: acquire a first status code; the second page buffer PB2 is coupled to the second storage unit B and is configured to: acquire a second status code; the read logic circuit 620 is coupled to the first page buffer PB1 and the second page buffer PB2 and is configured to: obtain the value of the Q bit data to be read based on two bits of one of the first status code and the second status code, and at least one bit of the other.

[0152] For example, the first page buffer PB1 and the second page buffer PB2 are two of a plurality of page buffers 610. The page buffers 610 can perform the same sensing operations as in single-level and multi-level memory cell read operations to obtain status codes. In this embodiment, a read logic circuit 620 is provided outside the page buffers. The read logic circuit 620 is capable of performing a first logic operation, a second logic operation, and a third logic operation to obtain the value of each bit in the Q-bit data. The addition of the read logic circuit 620 requires minimal modification to existing circuitry; for example, only some logic circuitry can be added while other peripheral circuit modules remain largely unchanged. This shortens the design and verification cycle and improves memory reliability. For example, the page buffer 610 can be the page buffer / sensing amplifier 504 in Figure 6, and the read logic circuit 620 can be the read logic circuit 505 in Figure 6.

[0153] In this embodiment of the disclosure, when reading each bit of the Q-bit data, the word line driver in the peripheral circuit (e.g., the line decoder / WL driver 508 in Figure 6) applies a first read voltage to the selected word line. The first page buffer obtains the first bit of the first status code, and the second page buffer obtains the first bit of the second status code. The word line driver continues to apply a second read voltage to the selected word line, and the first page buffer obtains the second bit of the first status code, and the second page buffer obtains the second bit of the second status code. The first page buffer and the second page buffer can send two bits of one of the first status code and the second status code, and at least one bit of the other, required for the logical operation to the read logic circuit according to the logical operation corresponding to the bit to be read. The read logic circuit performs the logical operation corresponding to the bit to be read (i.e., one of the first logical operation, the second logical operation, and the third logical operation) to obtain the value of the bit to be read.

[0154] When using this read operation, the AND, OR, and NOT gates in the read logic circuit can be time-division multiplexed, thereby simplifying the circuit structure and reducing the area occupied by the read logic circuit, which is beneficial for the miniaturization of the memory device. In addition, the page buffer can send the first bit of the status code to the read logic circuit as soon as it receives it, thereby reducing the occupation of the latch and reducing the area occupied by the page buffer, which is beneficial for the miniaturization of the device.

[0155] In another embodiment, when reading Q-bit data, a first read voltage and a second read voltage are applied only once to the select word line to obtain a first status code and a second status code. With this read operation, the read logic circuit can include a first logic operation circuit, a second logic operation circuit, and a third logic operation circuit, which simultaneously use the first and second status codes for logical operations. Alternatively, the read logic circuit can sequentially calculate each bit in the Q-bit data, using time-division multiplexing of AND gates, OR gates, and NOT gates, but this may require more latches in the page buffer to latch the status codes. This read operation requires more hardware circuitry, which is detrimental to the miniaturization of the memory device.

[0156] In some embodiments, the read logic circuit 620 includes at least: a first AND gate, a second AND gate, and an OR gate; wherein the first input terminal and the second input terminal of the first AND gate are respectively coupled to the first page buffer and the second page buffer; the first input terminal and the second input terminal of the second AND gate are respectively coupled to the first page buffer and the second page buffer; the first input terminal and the second input terminal of the OR gate are respectively coupled to the output terminal of the first AND gate and the output terminal of the second AND gate, and the output terminal of the OR gate outputs the value of the bit to be read in the Q bit data.

[0157] The first AND gate, the second AND gate, and the OR gate are used to implement the AND and OR operations in the first, second, and third logical operations. It should be understood that the read logic circuit 620 may also include NOT gates. In embodiments employing different encoding methods, the position and number of NOT gates can be set according to the logical expression for calculating bits 0, bit 1, and bit 2 shown, for example, in the first or second logical relation. The read logic circuit 620 may also include a selector, in which the time-division multiplexed first AND gate, second AND gate, and OR gate select different input signals when calculating bits 0, bit 1, and bit 2.

[0158] In some specific implementations, the FBC (Fail Bit Count) as a function of Eb / N0 can be used to evaluate the effectiveness of different encoding methods. For example, simulations can be performed to obtain the FBC as a function of Eb / N0 under different encoding methods. Eb / N0 represents the ratio of the energy (Eb) of each bit to the noise power spectral density (N0), used to measure the reliability of signal storage or transmission. A higher Eb / N0 ratio indicates higher reliability of signal storage or transmission. FBC (Fail Bit Count) refers to the proportion of erroneous bits to the total number of bits; a smaller FBC indicates a higher read accuracy and better data storage or transmission quality.

[0159] For example, curves 1 and 2 show the FBC variation with Eb / N0 when a single memory cell stores 1.5 bits of data. Curve 1 corresponds to an embodiment that uses the encoding method proposed in this disclosure, which eliminates combinations formed by intermediate state groups of two memory cells and uses the remaining eight combinations to store 3 bits of data. Curve 2 corresponds to a conventional encoding method that uses combinations formed by intermediate state groups of two memory cells to store data. Simulation data shows that when Eb / N0 decreases from 5.5 to 3.0, the encoding method of this disclosure consistently achieves a lower FBC. Especially when Eb / N0 is small, i.e., when signal quality is poor, the FBC obtained using the encoding method of this disclosure is significantly lower than the FBC obtained using conventional encoding methods.

[0160] In a specific comparative experiment, it was verified that when using the combination of intermediate state groups of two storage units to store data in the existing encoding method, the number of FBCs for reading bit0, bit1, and bit2 is 770, 1261, and 1062, respectively. However, when using the encoding method provided in Figure 7 to store data, the number of FBCs for reading bit0, bit1, and bit2 is 520, 745, and 1004, respectively. Compared with the existing encoding method, the FBCs are smaller, indicating that the noise of the read operation is smaller, the read reliability is higher, and the quality of data storage or transmission is better.

[0161] In some specific implementations, the CWER versus Eb / N0 curve can also be used to evaluate the effectiveness of different encoding methods. For example, simulations can be performed to obtain the CWER versus Eb / N0 curves for different encoding methods. CWER (Frame Error Rate) refers to the proportion of codewords that cannot be corrected by error correction algorithms during storage or transmission. The smaller the CWER value, the lower the read noise and the higher the data storage or transmission quality. For example, curves 1 and 2 can be obtained showing the CWER versus Eb / N0 when a single storage unit stores 1.5 bits of data. Curve 1 corresponds to an embodiment that uses the encoding method proposed in this disclosure, which eliminates combinations formed by intermediate state groups of two storage units and uses the remaining 8 combinations to store 3 bits of data. Curve 2 corresponds to an existing encoding method that uses combinations formed by intermediate state groups of two storage units to store data. Simulation data shows that when Eb / N0 decreases from 5.5 to 3.5, the encoding method provided by the embodiments of this disclosure has a lower frame error rate compared to existing encoding methods. Furthermore, with existing encoding methods, the frame error rate is more likely to increase as Eb / N0 decreases. For example, the frame error rate starts to rise when Eb / N0 decreases to 4.5 and reaches its maximum when Eb / N0 is 4.1. However, with the encoding method provided in this disclosure, the frame error rate can be delayed as Eb / N0 decreases. For example, the frame error rate starts to rise when Eb / N0 decreases to 4.1 and reaches its maximum when Eb / N0 is 3.7. Therefore, the encoding method provided in this disclosure results in less noise during read operations, higher quality data storage or transmission, and facilitates high-speed read operations.

[0162] Soft-decision information refers to additional probabilistic information about the state of a memory cell obtained during the reading process. Soft-decision information provides reliability information about each bit and can be used to evaluate the reliability of each bit read. Experiments have shown that the encoding method provided in this embodiment improves the quality of soft-decision processing.

[0163] In some embodiments, when using the encoding method shown in FIG13, using a higher-quality storage unit as the second storage unit can improve the quality of data storage. For example, RBER (Raw Bit Error Rate) can be used to measure the quality of a storage unit. RBER refers to the bit error rate before error correction processing; the bit error rate is the ratio of the number of erroneous bits to the total number of stored or transmitted bits. The smaller the RBER, the better the quality of the storage unit. In embodiments of this disclosure, a storage unit with a smaller RBER value can be designated as the second storage unit; that is, the RBER value of the second storage unit is smaller than that of the first storage unit, thereby obtaining better data storage and transmission quality.

[0164] In a specific comparative experiment, it was verified that when the RBER value of the second storage unit is less than that of the first storage unit, the number of FBCs read from bit2 is 1004. However, after swapping the first and second storage units, the number of FBCs read from bit2 is 1119. This indicates that the RBER value of the second storage unit is smaller, resulting in better data storage or transmission quality.

[0165] In some embodiments, the peripheral circuitry is configured to apply at least Q×2 to the select word line. K -Q read voltages to read 2K bits of data.

[0166] Taking a state group of Q = 3, with each state group containing 8 states as an example, the read operation for reading 2K bits of data is illustrated. Referring to Figure 19, each memory cell includes 24 states, requiring at least 23 read voltages. Of these 23 read voltages, subtracting the first read voltage V1 and the second read voltage V2 located between adjacent state groups, at least 21 read voltages still need to be applied to the select word line to read the remaining 2K bits of data.

[0167] In some embodiments, the K bits of data stored in the first storage unit and the other K bits of data stored in the second storage unit can be read synchronously. For example, the kth bit of the K bits of data stored in the first storage unit and the kth bit of the other K bits of data stored in the second storage unit can be read simultaneously, where k is any one from 1 to K.

[0168] The following description refers to an embodiment. As shown in Figure 19, in state group S0, states P0 to P7 correspond to 111, 110, 100, 101, 001, 000, 010, and 011, respectively. In state group S1, states P8 to P15 correspond to 011, 111, 101, 001, 000, 100, 110, and 010, respectively. In state group S2, states P16 to P23 correspond to 010, 011, 001, 101, 111, 110, 000, and 000, respectively.

[0169] For example, in the first read operation of 2K bits of data, seven read voltages are applied to the select word line, namely Vrd4, Vrd9, Vrd11, Vrd13, Vrd15, Vrd19, and Vrd23, to read the value of the first bit of the K bits of data stored in the first memory cell and the value of the first bit of the other K bits of data stored in the second memory cell.

[0170] In the second read operation, seven read voltages are applied to the select word line, namely Vrd2, Vrd6, Vrd10, Vrd14, Vrd18, Vrd20 and Vrd22, to read the value of the second bit in the K bits of data stored in the first memory cell and the value of the second bit in the other K bits of data stored in the second memory cell.

[0171] In the third read operation, seven read voltages are applied to the select word line, namely Vrd1, Vrd3, Vrd5, Vrd7, Vrd12, Vrd17 and Vrd21, to read the value of the third bit in the K bits of data stored in the first memory cell and the value of the third bit in the other K bits of data stored in the second memory cell.

[0172] It should be noted that the application of the 21 read voltages is not limited to this. In different implementations, the order of application of the read voltages can be adjusted according to the encoding method of the 8 states within each state group.

[0173] In summary, in this disclosure, if the first AND gate, the second AND gate, and the OR gate are reused, the page buffer of each memory cell can perform 2+2+2 sensing operations (6 in total) to obtain the data of bit0, bit1, and bit2. If the first AND gate, the second AND gate, and the OR gate are not reused, the page buffer of each memory cell can perform 2 sensing operations to obtain the data of bit0, bit1, and bit2. Performing 7+7+7 sensing operations (21 in total) can obtain the 3 bits of data stored separately. That is, the page buffer of each memory cell can perform 27 or 23 sensing operations to read the 9 bits of data jointly stored in the two memory cells.

[0174] This disclosure also provides a memory system including a memory device and a memory controller. The memory device can be any of the memory devices shown in the above embodiments. The memory controller is coupled to the memory device and configured to control the memory device to perform operations. For example, the memory system can be any of the memory systems shown in FIG1 to FIG2b.

[0175] This disclosure provides an operation method for a memory device, the memory device including a memory cell array, the memory cell array including: a plurality of memory cells, each memory cell being Q×2 K One of the states; wherein, the states of two memory cells coupled to the same word line form multiple state combinations for storing Q+2K bits of data, where Q and K are both integers. Figure 21 is a schematic diagram of an operation method of a memory device provided in an embodiment of this disclosure. As shown in Figure 21, the operation method includes:

[0176] S100: When reading each bit of the Q bit data, apply a first read voltage to the select word line; after applying the first read voltage, apply a second read voltage to the select word line.

[0177] In some embodiments, the method of operation further includes:

[0178] S200: When reading each bit in the Q bit data, obtain the first status code and the second status code; wherein, the first status code indicates that the first storage unit of the two storage units is in the first target status group, and the second status code indicates that the second storage unit is in the second target status group;

[0179] S300: Determine the value of the bit to be read in the Q bit data based on the first status code and the second status code.

[0180] In some embodiments, Q is 3, and the first and second status codes are represented by two bits;

[0181] Step S200, obtaining the first status code and the second status code, specifically includes:

[0182] After applying the first read voltage to the select word line, the first bit of each of the first and second status codes is obtained;

[0183] After applying the second read voltage to the select word line, the second bit of each of the first and second status codes is obtained.

[0184] In some embodiments, step S300, determining the value of the bit to be read in the Q-bit data based on the first status code and the second status code, specifically includes: determining the value of the bit to be read in the Q-bit data based on two bits of one of the first status code and the second status code, and at least one bit of the other.

[0185] In some embodiments, the value of the bit to be read in the Q-bit data is determined based on two bits of one of the first status code and the second status code, and at least one bit of the other, including:

[0186] If the bit to be read is the first bit in the Q-bit data, perform the first logical operation on one bit in the first status code and two bits in the second status code to obtain the value of the first bit in the Q-bit data.

[0187] If the bit to be read is the second bit in the Q-bit data, perform a second logical operation on two bits in the first status code and one bit in the second status code to obtain the value of the second bit in the Q-bit data;

[0188] If the bit to be read is the third bit in the Q-bit data, perform a third logical operation on two bits in the first status code and two bits in the second status code to obtain the value of the third bit in the Q-bit data.

[0189] In some embodiments, each of the first logical operation, the second logical operation, and the third logical operation includes an AND operation and an OR operation.

[0190] In some embodiments, the method further includes: applying at least Q×2 to the select word line. K -Q read voltages to read 2K bits of data.

[0191] The memory device operation method provided in this disclosure applies a first read voltage and a second read voltage to the select word line when reading each bit of Q-bit data, so as to read each bit of Q-bit data bit by bit. It can time-division multiplex the logic gate circuits in the read logic circuit to reduce the area of ​​the read logic circuit and take advantage of the miniaturization of the memory device.

[0192] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0193] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0194] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory device, comprising: A storage cell array comprising multiple storage cells, each of which is in a Q×2 array. K One of several states, where Q is the number of state groups, and each state group comprises 2... K The states described; The states of the two storage units form multiple state combinations to store multi-bit data; and one of the two storage units is in an intermediate state group within Q state groups, while the other is in one of the other multiple state groups excluding the intermediate state group, or both storage units are in the other multiple state groups; the other multiple state groups are located on both sides of the intermediate state group, and Q and K are both integers.

2. The memory device according to claim 1, wherein Q is 3; Furthermore, excluding the state combinations formed by the states within the intermediate state group of the first storage unit and the states within the intermediate state group of the second storage unit, the other 8×2 2K The combination of states stores 3+2K bits of data.

3. The memory device according to claim 2, wherein in the 3+2K bits of data, the 3 bits of data are jointly stored by a combination of the state group of the first storage unit and the state group of the second storage unit.

4. The memory device according to claim 3, wherein the three state groups are ordered in ascending order of threshold voltage as a low state group, an intermediate state group, and a high state group; the state groups of the first memory unit and the second memory unit respectively form eight combinations, as follows: The first combination includes the first storage unit being in a low state group and the second storage unit being in a low state group; The second combination includes the first storage unit being in a low state group and the second storage unit being in an intermediate state group; The third combination includes the first storage unit being in a low state group and the second storage unit being in a high state group; The fourth combination includes the first storage unit being in an intermediate state group and the second storage unit being in a high state group; The fifth combination includes the first storage unit being in a high state group and the second storage unit being in a high state group; The sixth combination includes the group where the first storage unit is in a high state and the group where the second storage unit is in an intermediate state; The seventh combination includes the group where the first storage unit is in a high state and the group where the second storage unit is in a low state; The eighth combination includes the first storage unit being in an intermediate state group and the second storage unit being in a low state group; in, Gray code encoding is used to encode the data corresponding to the first combination to the eighth combination.

5. The memory device according to claim 4, wherein the correspondence between the first combination to the eighth combination and the 3-bit data is any one of the following: The data corresponding to the first to the eighth combinations are 111, 110, 010, 011, 001, 000, 100 and 101 respectively; The data corresponding to the first to the eighth combinations are 110, 010, 011, 001, 000, 100, 101 and 111 respectively; The data corresponding to the first to the eighth combinations are 010, 011, 001, 000, 100, 101, 111 and 110 respectively; The data corresponding to the first to the eighth combinations are 011, 001, 000, 100, 101, 111, 110 and 010 respectively; The data corresponding to the first to the eighth combinations are 001, 000, 100, 101, 111, 110, 010 and 011 respectively; The data corresponding to the first to the eighth combinations are 000, 100, 101, 111, 110, 010, 011 and 001 respectively; The data corresponding to the first to the eighth combinations are 100, 101, 111, 110, 010, 011, 001 and 000 respectively; The data corresponding to the first to the eighth combinations are 101, 111, 110, 010, 011, 001, 000 and 100 respectively; The data corresponding to the first to the eighth combinations are 111, 101, 100, 000, 001, 011, 010 and 110 respectively; The data corresponding to the first to the eighth combinations are 101, 100, 000, 001, 011, 010, 110 and 111 respectively; The data corresponding to the first to the eighth combinations are 100, 000, 001, 011, 010, 110, 111 and 101 respectively; The data corresponding to the first combination to the eighth combination are 000, 001, 011, 010, 110, 111, 101 and 100 respectively; The data corresponding to the first to the eighth combinations are 001, 011, 010, 110, 111, 101, 100 and 000 respectively; The data corresponding to the first to the eighth combinations are 011, 010, 110, 111, 101, 100, 000 and 001 respectively; The data corresponding to the first to the eighth combinations are 010, 110, 111, 101, 100, 000, 001 and 011 respectively; The data corresponding to the first to the eighth combinations are 110, 111, 101, 100, 000, 001, 011 and 010 respectively.

6. The memory device according to claim 2, wherein K is 3; The first storage unit stores 3 bits of the 2×3 bit data separately, and the second storage unit stores the other 3 bits of data separately.

7. A memory device, comprising: A storage cell array comprising: a plurality of storage cells, each of the storage cells being in a Q×2 array. K One of the states; wherein, multiple state combinations formed by the states of two memory cells coupled to the same word line are used to store Q+2K bits of data, where Q and K are both integers; The peripheral circuitry is coupled to the memory cell array; wherein, when reading each bit of the Q-bit data, the peripheral circuitry is configured as follows: Apply the first read voltage to the select word line; After applying the first read voltage, a second read voltage is applied to the select word line.

8. The memory device of claim 7, wherein when reading each bit of the Q-bit data, the peripheral circuitry is configured as follows: Obtain the first status code and the second status code; where, The first status code indicates that the first storage unit of the two storage units is in the first target status group, and the second status code indicates that the second storage unit is in the second target status group; The value of the bit to be read in the Q bit data is determined based on the first status code and the second status code.

9. The memory device according to claim 8, wherein Q is 3, and the first status code and the second status code are represented by two bits; The peripheral circuit is configured as follows: After applying the first read voltage to the select word line, the first bit of each of the first status code and the second status code is obtained; After applying the second read voltage to the select word line, the second bit of each of the first status code and the second status code is obtained.

10. The memory device of claim 8, wherein when reading each bit of the Q-bit data, the peripheral circuitry is configured as follows: The value of the bit to be read in the Q bit data is determined based on two bits of one of the first status code and the second status code, and at least one bit of the other.

11. The memory device of claim 10, wherein the peripheral circuitry is configured as follows: Perform a first logical operation on one bit of the first status code and two bits of the second status code to obtain the value of the first bit of the Q-bit data; Perform a second logical operation on two bits of the first status code and one bit of the second status code to obtain the value of the second bit in the Q-bit data; A third logical operation is performed on two bits in the first status code and two bits in the second status code to obtain the value of the third bit in the Q-bit data.

12. The memory device of claim 11, wherein the peripheral circuitry is configured as follows: In the first reading stage, the first reading voltage and the second reading voltage are sequentially applied to the select word line to obtain the first status code and the second status code; the first logical operation is performed on one bit of the first status code and two bits of the second status code to obtain the value of the first bit in the Q bit data; In the second reading stage, the first reading voltage and the second reading voltage are sequentially applied to the select word line to obtain the first status code and the second status code; Perform the second logical operation on two bits of the first status code and one bit of the second status code to obtain the value of the second bit in the Q-bit data; In the third reading stage, the first reading voltage and the second reading voltage are applied sequentially to the select word line to obtain the first status code and the second status code; The third logical operation is performed on two bits of the first status code and two bits of the second status code to obtain the value of the third bit in the Q-bit data.

13. The memory device of claim 11, wherein each of the first logical operation, the second logical operation, and the third logical operation comprises an AND operation and an OR operation.

14. The memory device according to any one of claims 8 to 13, wherein the peripheral circuitry comprises: The first page buffer, coupled to the first storage unit, is configured to: acquire the first status code; The second page buffer, coupled to the second storage unit, is configured to: acquire the second status code; The read logic circuit, coupled to the first page buffer and the second page buffer, is configured to determine the value of the bit to be read in the Q bit data based on the first status code and the second status code.

15. The memory device of claim 14, wherein the read logic circuit comprises at least: The first AND gate has its first input terminal and second input terminal coupled to the first page buffer and the second page buffer, respectively. The second AND gate has its first and second input terminals coupled to the first page buffer and the second page buffer, respectively. The OR gate has its first and second input terminals coupled to the output terminals of the first and second AND gates, respectively, and the output terminal of the OR gate outputs the value of the bit to be read in the Q-bit data.

16. The memory device of claim 7, wherein the peripheral circuitry is configured as follows: Apply at least Q×2 to the select word line K -Q read voltages are used to read the 2K bits of data; where, The Q×2 K -Q read voltages, each of which differs from the first read voltage and the second read voltage.

17. A memory system comprising: At least one memory device as described in any one of claims 1 to 16; A memory controller, coupled to the memory device, is configured to control the memory device to perform operations.

18. A method of operating a memory device, the memory device comprising: A storage cell array, comprising: a plurality of storage cells, each storage cell being in a Q×2 array. K One of the states; wherein, multiple state combinations formed by the states of two memory cells coupled to the same word line are used to store Q+2K bits of data, where Q and K are both integers; The operation method includes: When reading each bit of the Q-bit data, a first read voltage is applied to the select word line; after applying the first read voltage, a second read voltage is applied to the select word line.

19. The method of operating a memory device according to claim 18, further comprising: When reading each bit of the Q-bit data, a first status code and a second status code are obtained; wherein, the first status code indicates that the first storage unit of the two storage units is in the first target status group, and the second status code indicates that the second storage unit is in the second target status group; The value of the bit to be read in the Q bit data is determined based on the first status code and the second status code.

20. The method of operating the memory device according to claim 19, wherein Q is 3, and the first status code and the second status code are represented by two bits; The process of obtaining the first status code and the second status code includes: After applying the first read voltage to the select word line, the first bit of each of the first status code and the second status code is obtained; After applying the second read voltage to the select word line, the second bit of each of the first status code and the second status code is obtained.

21. The method of operating a memory device according to claim 19, wherein determining the value of the bit to be read in the Q-bit data based on the first status code and the second status code comprises: The value of the bit to be read in the Q bit data is determined based on two bits of one of the first status code and the second status code, and at least one bit of the other.

22. The method of operating the memory device according to claim 21, wherein when reading each bit of the Q-bit data, a first read voltage is applied to the select word line; After applying the first read voltage, applying a second read voltage to the select word line includes: In the first reading phase, the first reading voltage and the second reading voltage are applied sequentially to the select word line; In the second reading phase, the first reading voltage and the second reading voltage are applied sequentially to the select word line; In the third reading phase, the first reading voltage and the second reading voltage are applied sequentially to the select word line.

23. The method of operating a memory device according to claim 22, wherein determining the value of the bit to be read in the Q-bit data based on two bits of one of the first status code and the second status code, and at least one bit of the other, comprises: In the first reading stage, a first logical operation is performed on one bit of the first status code and two bits of the second status code to obtain the value of the first bit in the Q bit data; In the second reading stage, a second logical operation is performed on two bits of the first status code and one bit of the second status code to obtain the value of the second bit in the Q bit data; In the third reading stage, a third logical operation is performed on two bits in the first status code and two bits in the second status code to obtain the value of the third bit in the Q-bit data.

24. The method of operating a memory device according to claim 23, wherein each of the first logical operation, the second logical operation, and the third logical operation includes an AND operation and an OR operation.

25. The method of operating a memory device according to claim 18, further comprising: Apply at least Q×2 to the select word line K -Q read voltages are used to read the 2K bits of data; Wherein, Q×2 K -Q read voltages, each of which differs from the first read voltage and the second read voltage.

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