Method for manufacturing nitride semiconductor multilayer film mirror, vertical cavity surface emitting laser wafer, and vertical cavity surface emitting laser

Abstract

In a method for manufacturing a semiconductor multilayer film mirror by laminating semiconductor layers having different refractive indexes on a substrate, the substrate is a GaN substrate, AlInN layers and GaN layers are alternately grown on the substrate, and the In composition of the AlInN is in a range of 18.9% to 20.0% that causes lattice mismatch with respect to the GaN layers at room temperature.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a nitride semiconductor multilayer mirror, a vertical cavity surface-emitting laser wafer, and a vertical cavity surface-emitting laser. Background Technology

[0002] Previously, vertical resonator type light-emitting elements, such as vertical cavity surface emitting lasers (VCSELs), have been known, which have a structure that makes light resonate perpendicularly with respect to the substrate surface and emits light in a direction perpendicular to the substrate surface.

[0003] In vertical resonator type light-emitting elements (VCSELs), semiconductor DBR (Distributed Bragg Reflector) is used as a semiconductor multilayer film reflector to form a resonator.

[0004] Previously, it was known that nitride semiconductor multilayer mirrors were formed by stacking multiple AlInN layers and GaN layers with different refractive indices. For example, Patent Document 1 disclosed a method of controlling growth conditions so that the AlInN layers stacked from the first to the last had the same In composition and were lattice-matched with the GaN layers.

[0005] Furthermore, Patent Document 2 describes that in a multilayer film reflector of a vertical resonator type light-emitting device, when the In composition of the AlInN film is 18%, the lattice constants of the AlInN film and the GaN film are the same, and preferably the In composition of the AlInN film is less than 18%. Patent Document 3 describes that InAlN has a lattice match with GaN when the In composition is 17% to 18%.

[0006] Existing technical documents

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 2021-34632

[0009] Patent Document 2: Japanese Patent Application Publication No. 2018-73853

[0010] Patent Document 3: Japanese Patent Application Publication No. 2018-56299 Summary of the Invention

[0011] The problem that the invention aims to solve

[0012] Previously, the In composition of AlInN in lattice matching with GaN at room temperature was around 17% to 18%. Therefore, research and development have been carried out on this In composition range in semiconductor DBRs for vertical cavity surface emitter lasers.

[0013] However, it has been found that when crystal growth of semiconductor DBRs is performed under lattice-matched conditions at room temperature, the stress in the growth layer causes warping of the DBR substrate, which is unacceptable for the device.

[0014] This invention is based on the above-mentioned insights, and its purpose is to provide a method for manufacturing a nitride semiconductor multilayer film mirror, which can obtain a DBR substrate with small warpage, flatness, and uniform reflection wavelength within the substrate surface. Furthermore, the present invention aims to provide a vertical-cavity surface-emitting laser (VCSEL) wafer with uniform emission wavelength, having a flat DBR substrate with uniform reflection wavelength within the substrate surface; and to provide a VCSEL with small resonant wavelength deviation and high performance.

[0015] Methods for solving problems

[0016] One embodiment of the present invention discloses a method for manufacturing a nitride semiconductor multilayer mirror, which involves stacking semiconductor layers with different refractive indices on a substrate to manufacture the semiconductor multilayer mirror. The substrate is a GaN substrate. AlInN and GaN layers are alternately grown on the substrate. The In composition of the AlInN layer is in the range of 18.9% to 20.0% at room temperature, which results in a lattice mismatch relative to the GaN layer.

[0017] Another embodiment of the present invention provides a vertical-cavity surface-emitting laser wafer in which a nitride semiconductor multilayer mirror is formed on a substrate, wherein... The vertical-cavity surface-emitting laser wafer comprises: a first semiconductor layer of a first conductivity type formed on the nitride semiconductor multilayer mirror; a second semiconductor layer of the opposite conductivity type to the first conductivity type; and an active layer sandwiched between the first semiconductor layer and the second semiconductor layer. The substrate is a GaN substrate. The nitride semiconductor multilayer mirror is composed of alternating and repeated layers of AlInN and GaN. The In composition of the AlInN layer is in the range of 18.9% to 20.0% at room temperature, which results in a lattice mismatch relative to the GaN layer.

[0018] Another embodiment of the present invention provides a vertical-cavity surface-emitting laser (VCSEL) in which a nitride semiconductor multilayer mirror is formed on a substrate, wherein... The vertical cavity surface-emitting laser comprises: a first semiconductor layer of a first conductivity type formed on the nitride semiconductor multilayer mirror; a second semiconductor layer of the opposite conductivity type to the first conductivity type; an active layer sandwiched between the first semiconductor layer and the second semiconductor layer; and a multilayer mirror formed on the second semiconductor layer and constituting a resonator with the nitride semiconductor multilayer mirror. The substrate is a GaN substrate. The nitride semiconductor multilayer mirror is composed of alternating and repeated layers of AlInN and GaN. The In composition of the AlInN layer is in the range of 18.9% to 20.0% at room temperature, which results in a lattice mismatch relative to the GaN layer. Attached Figure Description

[0019] Figure 1 This is a cross-sectional view schematically illustrating the structure of the semiconductor DBR substrate according to the first embodiment of the present invention.

[0020] Figure 2 This is a schematic cross-sectional view showing the tray for crystal growth of semiconductor DBR and the growth substrate placed on the tray.

[0021] Figure 3 This is a diagram showing the structure of the tray when viewed from above.

[0022] Figure 4 This is a flowchart illustrating a method for manufacturing a semiconductor DBR substrate.

[0023] Figure 5A This is a diagram showing the warpage of epitaxial wafer 1 in the X and Y directions.

[0024] Figure 5B This is a diagram showing the warpage of the epitaxial wafer 2 in the X and Y directions.

[0025] Figure 5C This is a diagram showing the warpage of the epitaxial wafer 3 in the X and Y directions.

[0026] Figure 6 This is a top view showing the measurement points of the reflectance spectrum of the semiconductor DBR substrate.

[0027] Figure 7A This is a diagram showing the superimposed reflectance spectra at each measurement point of epitaxial wafer 1.

[0028] Figure 7BThis is a diagram showing the superimposed reflection spectra at each measurement point of the epitaxial wafer 2.

[0029] Figure 7C This is a diagram showing the superimposed reflection spectra at each measurement point of the epitaxial wafer 3.

[0030] Figure 8 This is a diagram showing the lattice matching conditions of AlInN relative to GaN at the growth temperature.

[0031] Figure 9A This is a schematic top view of the vertical cavity surface-emitting laser wafer of the second embodiment.

[0032] Figure 9B This is a schematic cross-sectional view showing the structure of a vertical cavity surface-emitting laser wafer.

[0033] Figure 10 This is a schematic cross-sectional view showing the structure of the vertical cavity surface-emitting laser of the third embodiment. Detailed Implementation

[0034] The preferred embodiments of the present invention will be described below, but appropriate changes and combinations may be made to them. Furthermore, in the following description and drawings, substantially the same or equivalent parts will be labeled with the same reference numerals.

[0035] [First Implementation]

[0036] (1) Structure of semiconductor multilayer reflector substrate

[0037] Figure 1 This is a cross-sectional view schematically showing the structure of a substrate (hereinafter referred to as a semiconductor DBR substrate) 10 having a nitride semiconductor multilayer reflector formed according to the first embodiment of the present invention.

[0038] The growth substrate 11 used for crystal growth is a C-plane GaN substrate with the crystal growth surface being the C-plane. Specifically, it is a so-called off-angle substrate, i.e., a C-plane GaN substrate, in which the crystal growth surface is tilted at 0.5° from the C-plane towards the M-plane and at 0±0.1° towards the A-plane. It should be noted that the substrate is not limited to an off-angle substrate; it can also be a so-called positive-angle substrate.

[0039] The growth substrate 11 has a circular shape with a diameter of 2 inches and a thickness of 400 μm. It should be noted that it is more preferable for the growth substrate 11 to have a diameter of 2 inches or more.

[0040] Semiconductor DBR12 was grown on growth substrate 11 using metal-organic vapor phase growth (MOVPE). Semiconductor DBR12 is formed by alternating layers of semiconductor layers with different refractive indices and optical film thicknesses of 1 / 4 wavelength, namely AlInN layer (first thin film) 12A and GaN layer (second thin film) 12B.

[0041] More specifically, the semiconductor DBR12 is constructed by stacking k pairs (k being a natural number) of AlInN layers 12A and GaN layers 12B. Here, the semiconductor DBR12 is composed of 46 pairs (k=46) of AlInN layers 12A and GaN layers 12B.

[0042] Furthermore, the AlInN layer 12A and GaN layer 12B have a film thickness that results in a reflection center wavelength of 450 nm. Specifically, the AlInN layer 12A has a film thickness of 50 nm, and the GaN layer 12B has a film thickness of 45.0 nm. The total thickness of the semiconductor DBR12 is 4.39 μm.

[0043] Figure 2 This is a schematic cross-sectional view showing the tray 100 for crystal growth of semiconductor DBR12 and the growth substrate 11 placed on the tray 100. Figure 3 This is a diagram showing the structure of the tray 100 as viewed from above.

[0044] In this embodiment, a tray 100 is used to hold the growth substrate 11 within the crystal growth furnace. More specifically, the tray 100 has circular countersinking holes on the substrate mounting surface side, such as... Figure 3 As shown, a mounting portion 101 protruding into the countersinking hole is provided on the tray 100. The mounting portion 101 is annular in shape with center C as the center and is provided at a position lower than the upper surface of the tray 100.

[0045] The growth substrate 11 is mounted on the mounting portion 101 and held in the tray 100. At this time, a hollow portion 103 is formed between the growth substrate 11 and the bottom 102 of the tray 100, having a gap TG between the back surface of the growth substrate 11 and the upper surface of the bottom 102. It should be noted that this gap TG can be appropriately set to control the temperature of the growth substrate 11. In this embodiment, the gap TG is set to 0.1 mm, but it can also be set to 0.2 mm or more, for example.

[0046] Additionally, a heater 110 for heating the tray 100 and the growth substrate 11 is disposed on the back side of the bottom 102 of the tray 100. The heater 110 uses resistance heating, but high-frequency induction heating, lamp heating, or other heating methods may also be used.

[0047] (2) Manufacturing method of semiconductor DBR substrate

[0048] Figure 4 This is a flowchart illustrating a method for manufacturing a semiconductor DBR substrate 10. Hereinafter, refer to... Figure 4 Each step of the manufacturing method for the semiconductor DBR substrate 10 is described.

[0049] (S1) Mounting of the growth substrate

[0050] A 2-inch diameter C-side GaN substrate, i.e., growth substrate 11, is mounted on a tray 100 inside the crystal growth furnace. It should be noted that growth substrates with a diameter of 2 inches or larger can also be used. Furthermore, circular growth substrates are particularly suitable.

[0051] A tray is used in a manner that supports the outer periphery of the growth substrate 11 with the mounting portion 101, but it is not limited to this. A tray or base that is held in complete contact with the back side of the growth substrate 11 may also be used.

[0052] (S2) Growth of the basal layer

[0053] The temperature (growth temperature) of the growth substrate 11 was set to 1100°C, hydrogen (H2) was used as the carrier gas, and trimethylgallium (TMG) and ammonia (NH3) were supplied to grow a substrate layer 11A composed of undoped GaN. The thickness of the substrate layer 11A was 100 nm. That is, in this embodiment, the substrate layer 11A was formed as the initial growth layer on the growth substrate 11. Here, the growth temperature refers to the temperature measured using a thermocouple (not shown) located near the heater 110 in the crystal growth furnace.

[0054] It should be noted that the substrate layer 11A is preferably made of the same crystal (GaN) as the growth substrate 11, but a buffer layer or superlattice structure layer with a different composition than the growth substrate 11 can also be used. Alternatively, the substrate layer 11A may not be provided.

[0055] (S3) Formation of semiconductor DBR

[0056] As described below, the growth of the first and second thin films is performed alternately and repeatedly to form a semiconductor DBR12 with 46 pairs of the first and second thin films stacked together.

[0057] (S3-1) Growth of the first thin film

[0058] The temperature of the growth substrate 11 was lowered from 1100°C to 844°C, and the carrier gas was changed from hydrogen (H2) to nitrogen (N2). After the temperature stabilized, trimethylindium (TMI), trimethylaluminum (TMA), and ammonia (NH3) were supplied to grow an AlInN layer 12A as the first thin film on the substrate 11A with a layer thickness of 50 nm. After growth, the supply of organometallic materials (hereinafter also referred to as MO materials) TMI and TMA was stopped.

[0059] (S3-2) Growth of the second thin film

[0060] (i) Growth of the capping layer (GaN protective layer)

[0061] After the AlInN layer 12A (the first thin film) was grown, triethylgallium (TEG) and ammonia (NH3) were supplied to grow a GaN layer as a capping layer on the AlInN layer 12A with a thickness of 0.3 nm. After growth, the supply of MO material was stopped. Through the capping layer (GaN), the surface of the AlInN layer 12A was protected when the growth temperature was increased.

[0062] (ii) Growth of GaN layer

[0063] Next, the carrier gas was changed from N2 to H2, and the temperature of the growth substrate 11 was increased from 844°C to 1100°C. After heating, TMG and NH3 were supplied to grow a GaN layer with a thickness of 44.7 nm. After growth, the supply of MO material was stopped. At this point, the temperature for GaN growth can be within the range of 800°C to 1200°C.

[0064] Therefore, together with the capping layer (GaN), a GaN layer 12B (second thin film) with a thickness of 45.0 nm was formed on the AlInN layer 12A (first thin film).

[0065] (S3-3) Repeated growth

[0066] Steps (S3-1) and (S3-2) are repeated until AlInN layer 12A and GaN layer 12B are stacked in k pairs (k=46), forming a semiconductor DBR12 composed of a stack of AlInN / GaN layers.

[0067] It should be noted that during repeated growth, the In composition of each layer of AlInN 12A was adjusted to 19.1%.

[0068] It should be noted that organometallic materials (MO materials) are not limited to the materials mentioned above; triethylindium (TEI), triethylaluminum (TEA), etc., can also be used.

[0069] Through the above processes, a semiconductor DBR substrate 10 with a stacked structure of semiconductor DBR 12 formed on the growth substrate 11 is formed.

[0070] (3) Warping of semiconductor DBR substrate

[0071] In the above manufacturing method, the semiconductor DBR substrate 10 was manufactured by changing the In composition. Specifically, three types of semiconductor DBR substrates 10 were manufactured with In compositions of 18.6% (epitaxy wafer 1, EPI-1), 19.1% (epitaxy wafer 2, EPI-2), and 19.6% (epitaxy wafer 3, EPI-3), and were evaluated.

[0072] Figure 5A , Figure 5B and Figure 5C These figures illustrate the warpage (μm) of epitaxial wafer 1 (In composition: 18.6%), epitaxial wafer 2 (In composition: 19.1%), and epitaxial wafer 3 (In composition: 19.6%) in the X and Y directions, respectively. It should be noted that the X and Y directions are parallel and perpendicular to the positioning plane (OF), respectively. Furthermore, the negative direction (-direction) of the vertical axis represents the direction of the tray 100.

[0073] Epitaxial wafer 1 is a semiconductor DBR substrate 10 in which a semiconductor DBR12 crystal was grown at room temperature (RT) with an In composition of 18.6% where the AlInN layer 12A and GaN layer 12B are lattice matched. Figure 5A The warpage of the epitaxial wafer 1 when restored to room temperature is shown. Despite the conditions for lattice matching at room temperature, the semiconductor DBR substrate 10 still shows a large amount of downward convex (concave) warpage.

[0074] That is, it is believed that when the In composition of the AlInN layer 12A is less than the In composition that matches the lattice of the GaN layer 12B, tensile strain is generated, and the semiconductor DBR substrate 10 exhibits a downward convex warping.

[0075] More specifically, as crystal growth progresses, when the semiconductor DBR substrate develops a downward convex (concave) warp, the gap between the center of the semiconductor DBR substrate and the bottom surface of the tray 100 becomes smaller than that at the outer periphery of the substrate, causing the temperature at the center of the semiconductor DBR substrate to rise. Consequently, the amount of In detached increases, and the In composition at the center becomes lower, resulting in the downward convex warp. That is, the In composition gradually decreases from the center to the outer periphery. It is believed that as crystal growth continues, the In composition further decreases, and the warp increases.

[0076] The epitaxial wafer 2 is a semiconductor DBR substrate 10 in which a semiconductor DBR is grown from a crystal with an In composition (19.1%) that is lattice-matched at the growth temperature. Figure 5B The warpage of epitaxial wafer 2 is shown when it is restored to room temperature. Despite the lattice mismatch condition at room temperature, it is still a roughly flat shape compared to epitaxial wafer 1 at room temperature.

[0077] The epitaxial wafer 3 is a semiconductor DBR substrate 10 in which a semiconductor DBR crystal was grown with an In composition (19.6%) that is slightly larger than the In composition of the lattice-matched semiconductor at the growth temperature. Figure 5C The warpage of epitaxial wafer 3 upon returning to room temperature is shown, exhibiting a slightly upward convex (convex) warpage. Specifically, the warpage of epitaxial wafer 3 (warpage of the outer periphery relative to the center) is less than 30 μm, which is within the allowable range for a semiconductor DBR substrate with a diameter of 2 inches.

[0078] It should be noted that when the In composition of the AlInN layer 12A is larger than the In composition of the GaN layer 12B that matches the crystal lattice, compressive strain is generated, and the semiconductor DBR substrate 10 exhibits an upward convex warping shape.

[0079] The result of epitaxial wafer 2 is that the AlInN layer 12A achieves lattice matching with the GaN layer 12B, and the In composition remains unchanged (the In composition of each layer is equal), and crystal growth is carried out periodically to form the semiconductor DBR substrate 10. At this time, no thermal stress is generated. When the temperature returns to room temperature, the lattice constants of each layer constituting the semiconductor DBR12 become mismatched, but the above evaluation results show that the structure of the semiconductor DBR12 at room temperature is unchanged compared with the structure during crystal growth.

[0080] Furthermore, in the epitaxial wafer 3, a slight warpage occurs in the semiconductor DBR substrate 10, but it is substantially flat and within the allowable range for a semiconductor DBR substrate with a diameter of 2 inches. In the case of a substrate with a diameter of 2 inches (diameter: 5.8 cm), the warpage of the semiconductor DBR substrate 10 is preferably within 30 μm.

[0081] More specifically, the curvature Z (=1 / R) at this point is 9 × 10⁻⁶. -8 (μm -1 Therefore, the curvature Z of the semiconductor DBR substrate 10 is preferably 9 × 10⁻⁶. -8 (μm -1 Within a certain range. Therefore, a semiconductor DBR with uniform reflected wavelength can be provided for vertical cavity surface-emitting lasers. It should be noted that the numerical range of the curvature mentioned above is also applicable when using a dielectric DBR.

[0082] As explained above, when crystal growth is performed such that the AlInN layer 12A (first thin film) satisfies the lattice matching condition with the GaN layer (second thin film) 12B at the crystal growth temperature, the composition period of the semiconductor DBR 12 remains constant. Even when the layers constituting the semiconductor DBR 12 are under lattice mismatch conditions, the semiconductor DBR substrate 10 can maintain flatness upon returning to room temperature (RT). Therefore, a nitride semiconductor multilayer mirror and a vertical-cavity surface-emitting laser can be provided, which can obtain a DBR substrate with small warpage, flatness, and uniform reflection wavelength within the substrate surface.

[0083] (4) Reflectance spectrum of semiconductor DBR substrate

[0084] Figure 6 This is a top view showing the measurement points of the reflection spectrum of the semiconductor DBR substrate 10. For each of the semiconductor DBR substrates 10 of epitaxial wafers 1, 2, and 3, the reflection spectrum was measured at 25 points (r0, r1, ..., r24) at equal intervals in the radial direction (X direction) from the center C toward the outer periphery.

[0085] Figure 7A , Figure 7B Figures 7 and 75C show the superimposed reflectance spectra at each measurement point of epitaxial wafers 1, 2, and 3, respectively.

[0086] like Figure 7A As shown, in the epitaxial wafer 1 (In composition: 18.6%), at the outer periphery of the semiconductor DBR substrate 10, the reflection center wavelength shifts significantly from the designed center wavelength (450nm) to the longer wavelength side, and becomes shorter as it moves towards the center, gradually approaching the reflection spectrum of the center.

[0087] That is, in the epitaxial wafer 1, the reflection center wavelength of the reflection spectrum in the substrate surface is not uniform, and when applied to a vertical cavity surface-emitting laser, the emission wavelength and oscillation characteristics (threshold, efficiency) are not uniform.

[0088] like Figure 7B As shown, it can be seen that in the epitaxial wafer 2 (In composition: 19.1%), the reflection spectrum within the substrate surface is uniform, resulting in a semiconductor DBR substrate 10 with high uniformity of reflection spectrum.

[0089] In addition, such as Figure 7C As shown, in epitaxial wafer 3 (In composition: 19.6%), although the shift of the reflection center wavelength is slightly larger in a very small portion of the outer periphery than in epitaxial wafer 1, the uniformity of the reflection spectrum of semiconductor DBR substrate 10 is high.

[0090] In addition, as long as the distance from the design center wavelength is above -3nm and below 3nm in the center and outer periphery of the substrate, the uniformity of the reflection spectrum can be satisfied without affecting the characteristics of the laser.

[0091] (5) In composition of AlInN layer

[0092] Figure 8 This is a graph showing the lattice matching conditions of AlInN relative to GaN at the growth temperature. It should be noted that the vertical axis is the lattice constant of GaN along the a-axis. More specifically, it shows the lattice constant of GaN (solid line) relative to the growth temperature and the In composition of AlInN (dashed line) that matches its lattice. It should be noted that the lattice constant of GaN is referenced to M. Miyoshi et al. (Jpn. J. Appl. Phys. 58, (2019)SC1006); the lattice constants of AlN and InN are referenced to SL Rumyantsev et al. (Int. J. High Speed ​​Electron. Syst. 14 (2004) 1); and the thermal expansion coefficients of GaN, AlN, and InN are calculated from the a-axis lengths of AlInN and GaN at various temperatures using M. Miyoshi et al. (Jpn. J. Appl. Phys. 58, (2019)SC1006).

[0093] The reason why the warpage and reflection spectrum are so different in the epitaxial wafers 1 (EPI-1), 2 (EPI-2), and 3 (EPI-3) is that the strain varies with the composition of AlInN.

[0094] Reference Figure 8 When the In composition of AlInN layer 12A is greater than the In composition that matches the lattice of GaN layer 12B (single-dot dashed line), compressive strain is generated; when it is less, tensile strain is generated.

[0095] At growth temperatures within the suitable range of 800℃ to 900℃ for AlInN growth, the In composition of AlInN layer 12A is lattice-matched with that of GaN layer 12B around 19%.

[0096] Considering the warpage and reflection spectrum results described above, the In composition of the AlInN layer 12A is preferably 18.9% to 20.0%, more preferably 18.9% to 19.6%. It should be noted that, as described above, this In composition is based on lattice mismatch conditions at room temperature. Here, when the In composition is less than 18.9%, uneven growth with unacceptable in-plane reflection spectra may occur due to substrate warpage. Furthermore, when the In composition exceeds 20%, pits may sometimes form. Therefore, the In composition of the AlInN layer 12A is preferably 18.9% to 20.0%.

[0097] As detailed above, according to the present invention, a method for manufacturing a nitride semiconductor multilayer film reflector is provided, which yields a DBR substrate with small warpage, flatness, and uniform reflection wavelength within the substrate surface.

[0098] It should be noted that the above embodiment exemplifies a semiconductor DBR12 with a reflection center wavelength of 450 nm, but it is not limited thereto. Semiconductor DBRs with blue bands (e.g., 430–490 nm), green bands (e.g., 490–550 nm), and violet-near-ultraviolet bands (e.g., 380–430 nm) are also applicable.

[0099] [Second Implementation]

[0100] (1) Vertical cavity surface-emitting laser wafer

[0101] Figure 9A This is a schematic top view of the vertical-cavity surface-emitting laser wafer 50 according to the second embodiment of the present invention. Figure 9B This is a schematic cross-sectional view showing the structure of a vertical cavity surface-emitting laser wafer 50.

[0102] like Figure 9A As shown, the vertical-cavity surface-emitting laser (VCSEL) wafer 50 is formed such that, for example, by dividing the VCSEL wafer 50 in a matrix manner, it can be monolithically divided into multiple VCSELs 55.

[0103] like Figure 9B As shown, a vertical cavity surface emission laser wafer 50 is formed by sequentially crystal growing a first semiconductor layer 13, an active layer 15, and a second semiconductor layer 19 on a semiconductor DBR substrate 10 according to the first embodiment. The first semiconductor layer 13, the second semiconductor layer 19, and the active layer 15 sandwiched between the first semiconductor layer 19 function as light-emitting functional layers.

[0104] The first semiconductor layer 13, the active layer 15, and the second semiconductor layer 19 can also be formed by continuing crystal growth on the semiconductor DBR12 after the growth of the semiconductor DBR12 is completed.

[0105] Furthermore, a second reflector 25 is formed on the second semiconductor layer 19, which together with the semiconductor DBR 12 of the semiconductor DBR substrate 10 forms a vertical resonator.

[0106] It should be noted that, in Figure 9B The description of the current injection structure on the vertical cavity surface-emitting laser, such as electrodes and insulating films, is omitted, but it can be appropriately set according to the desired component structure.

[0107] like Figure 9A As shown, each vertical cavity surface-emitting laser 55 is obtained by monolithizing the vertical cavity surface-emitting laser wafer 50.

[0108] The vertical cavity surface emission laser 55 cut from the vertical cavity surface emission laser wafer 50 has high uniformity of oscillation wavelength and small deviation of resonant wavelength within the element plane, thus enabling the production of a low threshold and high efficiency vertical cavity surface emission laser.

[0109] [Third Implementation]

[0110] Figure 10 This is a cross-sectional view schematically illustrating the structure of a vertical-cavity surface-emitting laser 55 (VCSEL) according to a third embodiment of the present invention. In this embodiment, the vertical-cavity surface-emitting laser 55 is a nitride surface-emitting laser composed of a III-V group nitride semiconductor layer.

[0111] The vertical cavity surface-emitting laser 55 is formed by sequentially crystal growing a first semiconductor layer 13, an active layer 15, and a second semiconductor layer 19 on the semiconductor DBR substrate 10 of the first embodiment.

[0112] Furthermore, the case where the first semiconductor layer 13 is composed of an n-type (first conductivity type) semiconductor layer and the second semiconductor layer 19 is composed of a p-type (second conductivity type, which is the opposite conductivity type of the first conductivity type) semiconductor layer will be explained.

[0113] The active layer 15 is composed of multiple quantum wells (MQWs), and the second semiconductor layer 19 has an intermediate layer 16, an electronic barrier layer (EBL) 17, and a p-type semiconductor layer 18.

[0114] The manufacturing method and structure of the vertical cavity surface-emitting laser 55 are described in detail below.

[0115] The semiconductor layer is grown using metal-organic vapor phase growth (MOVPE), which is the same as in the first embodiment. Furthermore, after the growth of the semiconductor DBR12 is completed (step S3-3), crystal growth continues on the semiconductor DBR12 to form the vertical-cavity surface-emitting laser wafer 50.

[0116] A base layer 11A (GaN layer) with a thickness of about 1 μm is grown on the substrate 11, and a semiconductor DBR12 is formed on the base layer 11A.

[0117] Semiconductor DBR12 (first reflector) is formed by stacking 46 pairs of n-type AlInN layers 12A and GaN layers 12B. It should be noted that each semiconductor layer of semiconductor DBR12 has a film thickness of λ / 4n (where n is the refractive index of each semiconductor film) of the emission wavelength λ of active layer 15.

[0118] An n-type GaN layer doped with Si (silicon), namely the first semiconductor layer 13 (n-type semiconductor layer) (layer thickness: 350nm), is grown on the semiconductor DBR12 (first reflector) of the semiconductor DBR substrate 10.

[0119] A barrier layer (blocking layer) and a quantum well layer (well layer) are alternately formed on the first semiconductor layer 13 (n-type semiconductor layer) to form an active layer 15 with four quantum well layers. The barrier layer is made of GaInN (layer thickness: 3 nm), and the well layer is made of GaN (layer thickness: 4 nm). It should be noted that the composition and thickness of the barrier layer and the well layer can be appropriately selected according to the desired emission wavelength, emission characteristics, etc.

[0120] On the final well layer of the active layer 15, undoped GaN is grown with a thickness of 120 nm as the final barrier layer, i.e., the intermediate layer 16. That is, the intermediate layer 16 is the layer between the active layer 15 and the electron barrier layer (EBL) 17.

[0121] Next, Al₂O₃ with Mg (magnesium) dopants as impurities was grown. x Ga 1-x Electron barrier layer (EBL)17 composed of N (Al composition: x).

[0122] Next, a Mg-doped p-GaN layer with a thickness of 83 nm is grown on the electron barrier layer 17 (p-AlGaN) as a p-type semiconductor layer 18.

[0123] As described above, crystal growth is performed on the semiconductor DBR substrate 10 to form a surface-emitting laser wafer 50, which is a semiconductor stack constituting a vertical cavity surface-emitting laser 55.

[0124] The laser-emitting chip is etched from the outer periphery until it reaches the interior of the first semiconductor layer 13 (n-type semiconductor layer), forming a cylindrical mesa protrusion, or mesa 55M.

[0125] For the p-type semiconductor layer 18, which is the uppermost semiconductor layer of the mesa 55M, a recess is formed by dry etching at a depth of about 20 nm on the outer periphery, thus forming a p-type semiconductor layer 18 with a cylindrical mesa 55M.

[0126] An insulating film (SiO2)21 for lateral current and light containment was deposited with a thickness of 20 nm in the recess of the p-type semiconductor layer 18 formed by etching. As a result, the recess of the p-type semiconductor layer 18 was planarized and a current-narrowing structure was formed, creating a cylindrical (central axis: CX) current injection region.

[0127] Next, an ITO (indium tin oxide) film with a thickness of 20 nm was formed on the p-type semiconductor layer 18 and the insulating film 21 as a transparent conductive film 22.

[0128] Next, a dielectric (Nb2O5) film with a thickness of 38 nm is formed as spacer layer 24. Spacer layer 24 functions as a phase adjustment layer.

[0129] Furthermore, a dielectric DBR25 (second mirror) serving as a dielectric multilayer reflector is formed on the spacer layer 24. The dielectric DBR25 is composed of 10.5 pairs of SiO2 (11 layers) and Nb2O5 (10 layers). The dielectric DBR25 and the semiconductor DBR12 form a resonator. It should be noted that the dielectric DBR25 is preferably formed coaxially with the cylindrical mesa 55M of the p-type semiconductor layer 18.

[0130] It should be noted that dielectrics have less light absorption (light loss) and a higher refractive index. Therefore, compared with semiconductor DBRs, mirrors with high reflectivity and wide reflection bandwidth can be obtained with fewer stacked layers (logarithms). Thus, vertical-cavity surface-emitting lasers with improved threshold and efficiency can be obtained.

[0131] Next, an n-electrode 27 is formed on the recess of the outer periphery of the first semiconductor layer 13 (n-type semiconductor layer), and a p-electrode 28 is formed on the transparent conductive film 22. In addition, the back side of the substrate 11 is polished to form an anti-reflective coating 29 composed of two layers of Nb2O5 / SiO2.

[0132] Thus, the formation of a vertical-cavity surface-emitting laser (VCSEL) wafer 50, in which multiple VCSELs 55 are arranged, is completed. By dividing (monodividing) the VCSEL wafer 50 into individual elements, a laser with... Figure 10 The structure shown includes vertical cavity surface-emitting lasers 55.

[0133] It should be noted that the composition and thickness of the intermediate layer 16 described above are merely illustrative. That is, the intermediate layer 16 is described as a GaN layer, but other nitride semiconductor layers with different compositions, such as InGaN, AlGaN, InAlGaN, etc., can also be used. In addition, the intermediate layer 16 is an undoped layer, but it can also be mixed with dopants diffused from the electron barrier layer 17 or the p-type semiconductor layer 18.

[0134] Furthermore, the thickness of the electron barrier layer 17 is merely an example. The electron barrier layer 17 can have a thickness of, for example, 3 to 30 nm. Additionally, the electron barrier layer 17 is composed of a nitride semiconductor containing Al in its composition. Furthermore, the electron barrier layer 17 can also be formed as a composition-tilted layer where the Al composition varies in the thickness direction.

[0135] The electron barrier layer 17 is described as a p-type semiconductor layer (p-AlGaN), but it can also be a p-type semiconductor layer containing Al in its composition, grown as an i-layer and mixed with impurities (Mg) diffused from the p-type semiconductor layer 18.

[0136] Furthermore, an example is shown where the active layer 15 is a quantum well active layer and has four quantum well layers 15W, but it is sufficient to have at least one quantum well layer. Also, the active layer 15 is not limited to a quantum well active layer. A so-called bulk structure active layer can also be used.

[0137] Furthermore, the first semiconductor layer 13 and the second semiconductor layer 19 may also be composed of multiple semiconductor layers including layers with different compositions and / or doping concentrations and an undoped layer (i layer).

[0138] Furthermore, the example shown is of a dielectric DBR25 composed of SiO2 and Nb2O5 films, but it can also be composed of dielectric films with different refractive indices based on other combinations. Alternatively, it can be composed of a semiconductor DBR made of semiconductor films with different refractive indices.

[0139] As detailed above, according to this embodiment, the deviation of the resonant wavelength within the element plane is small, thus enabling a low-threshold and high-efficiency vertical-cavity surface-emitting laser.

[0140] Industrial applicability

[0141] The embodiments of the present invention have been described in detail above. According to the present invention, a method for manufacturing a nitride semiconductor multilayer mirror can be provided, which yields a DBR substrate with small warpage, flatness, and uniform reflection wavelength within the substrate surface. Furthermore, a vertical-cavity surface-emitting laser wafer with uniform emission wavelength, having a flat DBR substrate with uniform reflection wavelength within the substrate surface, can be provided; and a vertical-cavity surface-emitting laser with small resonant wavelength deviation and high performance can be provided.

[0142] Explanation of reference numerals in the attached figures

[0143] 10: Semiconductor DBR substrate

[0144] 11: Growth substrate

[0145] 12: Semiconductor DBR

[0146] 12A: AlInN layer (first thin film)

[0147] 12B: GaN layer (second thin film)

[0148] 13: First semiconductor layer (n-type semiconductor layer)

[0149] 19: Second semiconductor layer (p-type semiconductor layer)

[0150] 25: Dielectric DBR (Second Reflector)

[0151] 50: Vertical-cavity surface-emitting laser wafer

[0152] 55: Vertical-cavity surface-emitting laser

[0153] 100: Pallet

[0154] r0~r24: Points for measuring reflectance spectra

Claims

1. A method for manufacturing a nitride semiconductor multilayer mirror, comprising stacking semiconductor layers with different refractive indices on a substrate to manufacture the semiconductor multilayer mirror, wherein, The substrate is a GaN substrate. AlInN and GaN layers are alternately grown on the substrate. The In composition of the AlInN layer is in the range of 18.9% to 20.0% at room temperature, which results in a lattice mismatch relative to the GaN layer.

2. A method for manufacturing a nitride semiconductor multilayer mirror, comprising stacking semiconductor layers with different refractive indices on a substrate to manufacture the semiconductor multilayer mirror, wherein... The substrate is a GaN substrate. AlInN and GaN layers are alternately grown on the substrate. The growth temperature of the AlInN layer is in the range of 800℃ to 900℃. The AlInN layer is grown with an In composition that matches the lattice of the GaN layer within the range of the growth temperature.

3. The method for manufacturing a nitride semiconductor multilayer reflector according to claim 2, wherein, The In composition that matches the GaN layer lattice is in the range of 18.9% to 20.0% that would produce a lattice mismatch at room temperature.

4. The method for manufacturing a nitride semiconductor multilayer reflector according to claim 1 or 2, wherein, The curvature of the semiconductor multilayer mirror is 9×10. -8 μm -1 Within.

5. The method for manufacturing a nitride semiconductor multilayer reflector according to claim 1 or 2, wherein, The semiconductor multilayer film reflector is warped into a convex shape.

6. The method for manufacturing a nitride semiconductor multilayer reflector according to claim 1 or 2, wherein, The substrate has a circular shape with a diameter of 2 inches or more.

7. A vertical-cavity surface-emitting laser (VCSEL) wafer, comprising a VCSEL wafer on a substrate having a nitride semiconductor multilayer film mirror formed thereon, wherein, The vertical-cavity surface-emitting laser wafer comprises: a first semiconductor layer of a first conductivity type formed on the nitride semiconductor multilayer mirror; a second semiconductor layer of the opposite conductivity type to the first conductivity type; and an active layer sandwiched between the first semiconductor layer and the second semiconductor layer. The substrate is a GaN substrate. The nitride semiconductor multilayer mirror is composed of alternating and repeated layers of AlInN and GaN. The In composition of the AlInN layer is in the range of 18.9% to 20.0% at room temperature, which results in a lattice mismatch relative to the GaN layer.

8. The vertical-cavity surface-emitting laser wafer according to claim 7, wherein, The substrate has a circular shape with a diameter of 2 inches or more.

9. The vertical cavity surface-emitting laser wafer according to claim 7, wherein the wafer has a dielectric multilayer mirror formed on the second semiconductor layer and forming a resonator with the nitride semiconductor multilayer mirror.

10. A vertical-cavity surface-emitting laser, wherein a vertical-cavity surface-emitting laser having a nitride semiconductor multilayer film mirror formed on a substrate, wherein, The vertical cavity surface-emitting laser comprises: a first semiconductor layer of a first conductivity type formed on the nitride semiconductor multilayer mirror; a second semiconductor layer of the opposite conductivity type to the first conductivity type; an active layer sandwiched between the first semiconductor layer and the second semiconductor layer; and a multilayer mirror formed on the second semiconductor layer and constituting a resonator with the nitride semiconductor multilayer mirror. The substrate is a GaN substrate. The nitride semiconductor multilayer mirror is composed of alternating and repeated layers of AlInN and GaN. The In composition of the AlInN layer is in the range of 18.9% to 20.0% at room temperature, which results in a lattice mismatch relative to the GaN layer.

11. The vertical-cavity surface-emitting laser according to claim 10, wherein, The multilayer reflector is a dielectric multilayer reflector.

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