Transmission method, transmission device, and transceiving system

Abstract

The present technology relates to a transmission method, a transmission device, and a transceiving system that can more effectively reduce switching jitter. A transmission method is provided, including: by a transmission device, when transmitting data at different voltage levels on each transmission line through a plurality of transmission lines, for each data transition, based on a control signal, transitioning to a specific data pattern different from the data before transmission, wherein an eye pattern obtained by measuring the data is that a constant voltage waveform of a second voltage level disappears during a transition from the second voltage level to the second voltage level due to the transition proceeding toward the third voltage level, and a constant voltage waveform of a third voltage level disappears during a transition from the third voltage level to the third voltage level due to the transition proceeding toward the second voltage level. For example, the present technology can be applied to transmission in compliance with the MIPI C-PHY standard, etc.

Description

Technical Field

[0001] This technology relates to a transmission method, a transmission device, and a transceiver system, and particularly to a transmission method, a transmission device, and a transceiver system that can more effectively reduce switching jitter. Background Technology

[0002] The C-PHY standard is a data transmission standard for mobile devices developed by the Mobile Industry Processor Interface (MIPI) Alliance, a standardization organization. In the C-PHY standard, since the data waveform is obtained based on differential signals from three sets of lines, switching jitter may occur depending on the pattern. Techniques disclosed in Patent Documents 1 and 2 are used to reduce this switching jitter.

[0003] Patent Document 1 discloses a technique for reducing switching jitter by detecting the patterns of three sets of lines using a pattern detector and controlling a delay module to bring the zero-crossing timings of the differential signals of the three sets of lines closer to each other. Patent Document 2 discloses a technique for reducing switching jitter by performing a transition to an intermediate potential at each transition to align the zero-crossing timings of the differential signals of the three sets of lines.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: JP2017-527162A

[0007] Patent Document 2: JP2018-525902A Summary of the Invention

[0008] The technical problem that the invention aims to solve

[0009] In the technology disclosed in Patent Document 1, switching jitter is reduced by using a delay module. However, as a result of controlling the delay, electromagnetic interference (EMI) may occur because the common-mode voltage of the three lines shifts during transitions. Furthermore, in the technology disclosed in Patent Document 1, the need for mode detection raises concerns about increased area and power consumption due to additional circuitry. In the technology disclosed in Patent Document 2, switching jitter is reduced by causing all channels to transition to the intermediate potential with each transition. However, there are concerns that the low slew rate may cause the eye diagram to close during high-speed operation.

[0010] As mentioned above, various problems arise when reducing switch bounce in the technologies disclosed in Patent Documents 1 and 2, thus requiring technologies for effectively reducing switch bounce.

[0011] This technology was developed in light of this situation, enabling more effective reduction of switch bounce.

[0012] Technical solutions to solve technical problems

[0013] According to one aspect of the present technology, the transmission method includes: when a transmitting device transmits data through multiple transmission lines at different voltage levels on each transmission line, for each data transition, a control signal is used to transition to a specific data mode different from the data before the transition, wherein the eye diagram obtained by measuring the data is: when the second lowest voltage level among voltage levels above 0 is the first voltage level and the lowest voltage level is the second voltage level, and the highest voltage level among voltage levels below 0 is the third voltage level and the second highest voltage level is the fourth voltage level, during the transition from the second voltage level to the third voltage level, since the transition is towards the third voltage level, the constant voltage waveform of the second voltage level disappears, and during the transition from the third voltage level to the third voltage level, since the transition is towards the second voltage level, the constant voltage waveform of the third voltage level disappears.

[0014] In a transmission method according to one aspect of the present technology, when data is transmitted through multiple transmission lines at different voltage levels on each transmission line, for each data transition, a control signal causes a transition to a specific data pattern different from the data before the transition. Furthermore, in an eye diagram obtained by measuring data, among voltage levels above 0, the second lowest voltage level is the first voltage level and the lowest voltage level is the second voltage level; and among voltage levels below 0, the highest voltage level is the third voltage level and the second highest voltage level is the fourth voltage level. During the transition from the second voltage level to the third voltage level, since the transition proceeds towards the third voltage level, the constant voltage waveform of the second voltage level disappears; and during the transition from the third voltage level to the second voltage level, since the transition proceeds towards the second voltage level, the constant voltage waveform of the third voltage level disappears.

[0015] According to one aspect of the present technology, a transmitting device is a transmitting device that transmits data at different voltage levels on each of multiple transmission lines. The transmitting device includes: a generator that generates control signals; and a multiplexer that, for each data transition, causes a transition to a specific data mode different from the data before the transition based on the control signals.

[0016] A transceiver system according to one aspect of the present technology is a transceiver system comprising: a transmitting device that transmits data at different voltage levels on each of multiple transmission lines; and a receiving device that receives the data transmitted through the multiple transmission lines, wherein the transmitting device includes: a generator that generates control signals; and a multiplexer that, for each data transition, causes a transition to a specific data mode different from the data before the transition based on the control signals.

[0017] In a transmitting apparatus and transceiver system according to one aspect of the present technology, when data transmitted via multiple transmission lines is transmitted at different voltage levels on each transmission line, a control signal is generated, and for each data transition, the control signal is used to cause a transition to a specific data mode different from the data before the transition.

[0018] Note that the transmitting device according to one aspect of this technology can be a standalone device or an internal block constituting a device. Attached Figure Description

[0019] Figure 1 This is a diagram illustrating an example configuration of a transceiver system.

[0020] Figure 2 This is a diagram showing a detailed configuration example of a typical transceiver system.

[0021] Figure 3 It is shown Figure 2 A timing diagram illustrating the state of voltage levels in a transmission line.

[0022] Figure 4 This is a diagram illustrating a detailed configuration example of a transceiver system that utilizes this technology.

[0023] Figure 5 It is shown Figure 4 A timing diagram illustrating the state of voltage levels in a transmission line.

[0024] Figure 6 This is a diagram illustrating an example of voltage level state transitions in data.

[0025] Figure 7 This is a diagram illustrating an example of voltage level state transitions in data.

[0026] Figure 8 This is a diagram showing an example of simulation results for a typical C-PHY and the eye diagram of this technology.

[0027] Figure 9 This is a diagram showing an example of simulation results for a typical C-PHY and the eye diagram of this technology.

[0028] Figure 10This is a diagram showing an example of simulation results for the eye diagrams of a typical C-PHY and conventional technique 2.

[0029] Figure 11 This is a diagram showing an example of simulation results for the eye diagrams of a typical C-PHY and conventional technique 2.

[0030] Figure 12 This is a diagram showing an example of simulation results for the eye diagrams of a typical C-PHY and conventional technique 2.

[0031] Figure 13 This is a diagram showing an example of simulation results for the eye diagrams of a typical C-PHY and conventional technique 2.

[0032] Figure 14 This is a diagram used to illustrate the characteristics of the eye diagram generated by the flipping operation applied to this technology.

[0033] Figure 15 It is a diagram used to illustrate the voltage height of an eye diagram.

[0034] Figure 16 This is a diagram used to illustrate a case where a transition from WH to SH occurs towards WL.

[0035] Figure 17 This is a diagram used to illustrate a case where a transition from WH to SH occurs towards WL.

[0036] Figure 18 This is a diagram used to illustrate a case where a transition from WL to SL occurs towards WH.

[0037] Figure 19 This is a diagram used to illustrate a case where a transition from WL to SL occurs towards WH.

[0038] Figure 20 This is a diagram used to illustrate a case where a transition from WH to WH or from WL to WL occurs during a flipping operation towards WL or WH.

[0039] Figure 21 This is a diagram used to illustrate a case where the transition from WH to WH proceeds towards WL during the flipping operation.

[0040] Figure 22 This is a diagram used to illustrate a case where the transition from WL to WH occurs during the flipping operation.

[0041] Figure 23 This illustrates a case of switching towards SL during the transition from SH to WH.

[0042] Figure 24 This illustrates a case of switching towards SL during the transition from SH to WH.

[0043] Figure 25 This is a diagram showing an example configuration of the TX driver.

[0044] Figure 26 This is a diagram used to illustrate the configuration of the inverting pulse generator, the inverting multiplexer, and the TX driver in the first implementation example.

[0045] Figure 27 This is a diagram illustrating a configuration example of the inverting pulse generator when using the first implementation example.

[0046] Figure 28 This illustrates the relationship between the clock and the inverted pulse when using the first implementation example.

[0047] Figure 29 This is a diagram illustrating a configuration example of the inverting pulse generator when using the second implementation example.

[0048] Figure 30 This illustrates the relationship between the clock and the inverted pulse when using the second implementation example.

[0049] Figure 31 This is a diagram illustrating a configuration example of the inverting multiplexer and TX driver when using the first implementation example.

[0050] Figure 32 This is a diagram illustrating the relationship between the states of the PU logic, PD logic, and voltage levels when using the first implementation example.

[0051] Figure 33 This is a diagram illustrating a configuration example of the inverting multiplexer and TX driver when using the second implementation example.

[0052] Figure 34 This is a diagram illustrating the relationship between the states of the PU logic, PD logic, and voltage levels when using the second implementation example.

[0053] Figure 35 This is a diagram showing an example configuration of an inverting pulse generator.

[0054] Figure 36 This is a diagram showing an example configuration of an inverting pulse generator.

[0055] Figure 37 This is a diagram showing an example configuration of an inverting pulse generator.

[0056] Figure 38 This is a diagram showing an example configuration of an inverting pulse generator.

[0057] Figure 39 This is a diagram illustrating an example configuration of the variable delay circuit when using the first implementation example.

[0058] Figure 40 This is a diagram illustrating a configuration example of the variable delay circuit when using the second implementation example.

[0059] Figure 41 This is a diagram illustrating a configuration example of notifying a variable delay control signal when implementing Example 2. Detailed Implementation

[0060] <System Configuration>

[0061] Figure 1 This is a diagram illustrating a configuration example of one embodiment of the transceiver system. Figure 1 In this configuration, transmitting device 11 and receiving device 12 are installed in electronic devices such as displays and cameras, and are interconnected via transmission lines 13-1 to 13-3. Transmitting device 11 is a transmitting device configured as a transmitter (TX). Receiving device 12 is a receiving device configured as a receiver (RX).

[0062] Data transmission conforming to the C-PHY standard defined by MIPI is performed between the transmitting device 11 and the receiving device 12 via transmission lines 13-1 to 13-3. The transmitting device 11 uses these three lines 13-1 to 13-3 as a group to send data (signals) to the receiving device 12.

[0063] Figure 2 This is a diagram illustrating a detailed configuration example of a transceiver system performing data transmission conforming to the standard C-PHY. The following... Figure 2 The transceiver system configuration shown is referred to as a typical C-PHY configuration. Figure 2 In the transmission device 11, there are clock generator 21, serializers 22-1 to 22-3 and TX drivers 23-1 to 23-3.

[0064] Clock generator 21 generates a data clock and outputs the data clock to serializers 22-1 to 22-3. Each of serializers 22-1 to 22-3 uses the data clock input from clock generator 21 to convert one of the input parallel signals (i.e., multiple signals A, B, and C) into a serial signal as a single signal. TX drivers 23-1 to 23-3 output the signals input from serializers 22-1 to 22-3 as data to receiving device 12 via transmission lines 13-1 to 13-3.

[0065] exist Figure 2 In the transmitting device 11, the voltage level of the data output from the TX drivers 23-1 to 23-3 and transmitted through the transmission lines 13-1 to 13-3 is, for example, as shown in the figure. Figure 3 The timing diagram is shown below. Figure 3 In the text, the horizontal direction represents the time direction, and Figure 3The voltage level is shown to have three states: high (H), medium (M), and low (L). That is, transmission lines 13-1 to 13-3 are used as a group, and each line is always in a different voltage level state.

[0066] Figure 4 This is a diagram illustrating a detailed configuration example of a transceiver system applying this technology. The following... Figure 4 The configuration of the transceiver system shown is referred to as the configuration of this technology. Figure 4 In the transmission device 11, there are generation circuits 31, serializers 32-1 to 32-3, inverting multiplexers (MUX) 33-1 to 33-3 and TX drivers 34-1 to 34-3.

[0067] Generation circuit 31 includes clock generator 41 and inverting pulse generator 42. Clock generator 41 generates a data clock. The data clock is output to serializers 32-1 to 32-3. Serializers 32-1 to 32-3 each convert one of the input parallel signals (signals A, B, and C) into a serial signal as a single signal by using the data clock input from generation circuit 31. The signal from serializers 32-1 to 32-3 is output to inverting multiplexers 33-1 to 33-3.

[0068] In generation circuit 31, clock generator 41 outputs a data clock to inverting pulse generator 42. Inverting pulse generator 42 generates an inverted pulse using the data clock input from clock generator 41 and outputs the inverted pulse to inverting multiplexers 33-1 to 33-3. The inverted pulse is a control signal for the inverting multiplexers that controls the normal data mode and the inverted mode. That is, the inverted pulse is a pulse signal that controls the inverted mode. For example, the inverted pulse is a pulse signal with a predetermined time width. Hereinafter, this pulse signal is referred to as the inverted pulse. Furthermore, the inverted mode is an example of a specific data mode that is different from the data before the conversion. Hereinafter, the inverted mode will be described as a specific data mode.

[0069] Inverting multiplexers 33-1 to 33-3 are multiplexers that use an inverted pulse input from an inverting pulse generator 42 to switch the signals input from serializers 32-1 to 32-3 to an inverted mode during each data transition and maintain this switch for a predetermined time width. Inverting multiplexers 33-1 to 33-3 are multiplexers that use an inverted pulse signal to control the inverted mode to multiplex (synthesize) the normal data mode and the inverted mode.

[0070] Specifically, inverter multiplexer 33-1 multiplexes the normal data mode and the inverted mode for the signal input from serializer 32-1 using the inverted pulse input from inverted pulse generator 42 as the control signal, and outputs the resulting signal to TX driver 34-1. Inverter multiplexer 33-2 multiplexes the normal data mode and the inverted mode for the signal input from serializer 32-2 using the inverted pulse as the control signal, and outputs the resulting signal to TX driver 34-2. Inverter multiplexer 33-3 multiplexes the normal data mode and the inverted mode for the signal input from serializer 32-3 using the inverted pulse as the control signal, and outputs the resulting signal to TX driver 34-3.

[0071] TX drivers 34-1 to 34-3 output signals input from inverting multiplexers 33-1 to 33-3 as data to transmission lines 13-1 to 13-1. Data output (transmitted) from TX drivers 34-1 to 34-3 is input (received) to receiving device 12 via transmission lines 13-1 to 13-3.

[0072] That is, TX driver 34-1 outputs data corresponding to the signal input from inverting multiplexer 33-1 to transmission line 13-1. TX driver 34-2 outputs data corresponding to the signal input from inverting multiplexer 33-2 to transmission line 13-2. TX driver 34-3 outputs data corresponding to the signal input from inverting multiplexer 33-3 to transmission line 13-3.

[0073] exist Figure 4 In the transmitting device 11, the voltage level of the data output from TX drivers 34-1 to 34-3 and transmitted via transmission lines 13-1 to 13-3 is, for example, as shown in the following... Figure 5 The timing diagram is shown below. Figure 5 In, with Figure 3 Similarly, the horizontal direction is the time direction, and there are three voltage levels: H level, M level, and L level. Figure 5 The outputs of TX driver 34-1 (A_TX), TX driver 34-2 (B_TX), and TX driver 34-3 (C_TX) are shown, along with the timing of the inverted pulse generated by inverted pulse generator 42.

[0074] like Figure 5 As shown, since the inverting multiplexers 33-1 to 33-3, based on the inverting pulse input from the inverting pulse generator 42, switch to inverting mode and maintain it for a predetermined time width during each data transition, the voltage levels of A_TX, B_TX, and C_TX are inverted when the inverting pulse changes to H level. If... Figure 5 The timing diagram and Figure 3 If we compare the timing diagrams, then as follows: Figure 5 As shown in the dotted pattern portion, the voltage levels of A_TX, B_TX, and C_TX change from H level to L level and then from L level to H level respectively in response to the inverting pulse. However, when the voltage level is M level, the M level state remains unchanged.

[0075] exist Figure 5 In this process, the voltage level of the data changes accordingly with the inverting pulse, and the three transmission lines 13-1 to 13-3 are each in a different voltage level state. As mentioned above, in Figure 4 In the transmitting device 11, in order to perform the operation of applying a predetermined time width to the inverted mode of the data before the transition at each data transition (hereinafter also referred to as the flip operation), an inverted pulse generator 42 and inverted multiplexers 33-1 to 33-3 are additionally provided.

[0076] Note that in the following explanation, in Figure 4 In the transmitting device 11, when there is no need to distinguish between serializers 32-1 to 32-3, serializers 32-1 to 32-3 are referred to as serializer 32. Similarly, when there is no need to distinguish between inverting multiplexers 33-1 to 33-3, inverting multiplexers 33-1 to 33-3 are referred to as inverting multiplexers 33. When there is no need to distinguish between TX drivers 34-1 to 34-3, TX drivers 34-1 to 34-3 are referred to as TX drivers 34.

[0077] <State Transition>

[0078] Figure 6 and Figure 7 This is a diagram illustrating an example of voltage level state transitions in the data. Here, for comparison purposes, Figure 6 The voltage level state transitions of this technology are shown along with those of a typical C-PHY and conventional technology 1. Additionally, Figure 7 The voltage level state transitions of this technology are shown together with those of conventional technology 2. Here, conventional technology 1 is JP2017-527162A (especially...). Figures 1 to 3 The technology disclosed in (and 5 to 6). Conventional technology 2 is JP 2018-525902A (especially) Figure 13 and 14 (The technology is publicly available.)

[0079] exist Figure 6 In the text, five modes 111 to 115 are shown for the typical C-PHY, conventional technology 1, and this technology. That is, Figure 6 The upper part shows the five modes of a typical C-PHY. Figure 6 The middle section shows five modes of conventional technology 1, and Figure 6 The lower part illustrates five modes of this technology. Figure 6 In the above, signal A corresponds to the data transmitted via transmission line 13-1, signal B corresponds to the data transmitted via transmission line 13-2, and signal C corresponds to the data transmitted via transmission line 13-3.

[0080] exist Figure 6 At the bottom, solid lines represent voltage level changes for signal A, dashed lines represent voltage level changes for signal B, and double dashed lines represent voltage level changes for signal C. Additionally, in Figure 6 The lower part of the dot pattern corresponds to the time when the flip operation is performed (flip operation time), and the flip operation is applied to the five modes of this technology.

[0081] like Figure 6 As shown in the lower part, in the voltage level state transition of this technology, since a toggle operation is performed, the system transitions to the inverse mode of the data before the transition each time a data transition occurs. That is, during the toggle operation time, when the voltage level of the data before the transition is H level, it transitions to L level; when the voltage level of the data before the transition is L level, it transitions to H level; and when the voltage level of the data before the transition is M level, it remains at M level.

[0082] As described above, in this technology, by performing a switching operation, the timing of the differential voltage becoming zero becomes closer, eliminating dependence on the next mode and reducing switching jitter. Furthermore, in this technology, the switching operation is mode-independent, and a detector for mode detection is no longer needed, thus suppressing the increase in circuit area and power consumption caused by setting a detector.

[0083] Here, in conventional technique 1, switching jitter is reduced by using a variable delay module; however, the result of delay control is that the common-mode voltage sometimes shifts during transitions (e.g., Figure 6 (Modes 114 and 115 in the middle section). As a result, EMI may be generated.

[0084] In addition, Figure 7 In the section on conventional technique 2, a pattern 121 is shown for each case. Figure 7 The upper part shows a pattern of Case 1 of Conventional Technology 2, and Figure 7 The middle section shows a pattern of Case 2 of conventional technique 2. Here, Case 1 is defined as the operation when the intermediate potential is not optimized, and Case 2 is defined as the operation when the eye diagram opening is optimized. Furthermore, Figure 7 The lower part and Figure 6 The lower part similarly illustrates the five modes of this technology.

[0085] In conventional technique 2, switching jitter is reduced by causing all channels to transition to an intermediate potential with each transition. However, due to the low slew rate, the effect of reducing switching jitter during high-speed operation is small, and there is also a risk of the eye diagram opening closing. Furthermore, in conventional technique 2, assuming a real circuit, A, B, and C may not intersect each other during the intermediate potential transition of all channels. Therefore, the clock does not resume during the intermediate potential period, resulting in the eye diagram opening closing by an amount corresponding to the intermediate potential transition time. In this technique, by using a flip-flop operation, the slew rate is higher compared to conventional technique 2, which transitions to an intermediate potential. Therefore, the effect of reducing switching jitter is better, and the eye diagram opening is expanded.

[0086] As described above, in this technology, switching jitter can be reduced more effectively compared to conventional technology 1 and conventional technology 2.

[0087] <Eye Chart>

[0088] An eye diagram (eye diagram waveform) obtained from simulations performed by the inventors of this technology is illustrated. For comparison, eye diagrams of conventional C-PHY and conventional technologies, along with the eye diagram of this technology, are shown here. Note that, similar to the eye diagrams of conventional C-PHY and conventional technologies, the eye diagram of this technology is generated from a differential signal created using signals from three wires.

[0089] Figure 8 and Figure 9 This is a diagram showing an example of simulation results for a typical C-PHY and the eye diagram of this technology. Figure 8 The simulation results are shown in the lossless channel. Figure 9 Simulation results are shown for a high-loss channel (equivalent to a short channel as defined in the C-PHY standard). Figure 8 and Figure 9 In the diagram, the horizontal axis represents time (unit: ps), and the vertical axis represents voltage (unit: mV). The left side shows the eye diagram of a typical C-PHY, and the right side shows the eye diagram of this technology.

[0090] The eye diagram in this technique performs a flip operation, whereas a typical C-PHY eye diagram does not; therefore, if for Figure 8 By comparing the waveforms, multiple waveforms overlap at the same position in the eye diagram of this technique, resulting in a higher quality waveform (eye diagram opening) than that of a typical C-PHY eye diagram. Figure 9 The waveform is similar, and in the eye diagram of this technology, the eye diagram is more open than that of a typical C-PHY.

[0091] Figures 10 to 13 This is a diagram illustrating examples of eye diagrams for a typical C-PHY and conventional technique 2. Figures 10 to 13In the diagram, the horizontal axis represents time (unit: ps), the vertical axis represents voltage (unit: mV), the left side shows the eye diagram of a typical C-PHY, and the right side shows the eye diagram of conventional technology 2.

[0092] exist Figure 10 and Figure 11 In the simulation used to obtain the eye diagram of conventional technique 2, a simulation model with a small transition time width of the intermediate potential is used, corresponding to Case 1 above. On the other hand, in Figure 12 and Figure 13 In the simulation used to obtain the eye diagram of conventional technique 2, the transition time width of the intermediate potential is adjusted to maximize the opening of the horizontal eye diagram, corresponding to Case 2 above. Figure 10 and Figure 12 Simulation results for a lossless channel are illustrated, while Figure 11 and Figure 13 Simulation results for high-loss channels are shown.

[0093] Notice, Figure 10 and Figure 12 The typical C-PHY eye diagram shown is... Figure 8 The eye diagram shown is the same as that of a typical C-PHY. Figure 11 and Figure 13 The typical C-PHY eye diagram shown is... Figure 9 The eye diagram shown is the same as that of a typical C-PHY.

[0094] Here, if you pay attention Figure 8 The waveform within the dashed box 131 on the eye diagram of this technology shown is... Figure 10 The waveform within the dashed box 133 in the eye diagram of conventional technique 2, compared to the eye diagram of conventional technique 2, shows that the eye diagram of this technique has a larger slope for both the rising and falling edges. Therefore, when the transition time width of the intermediate potential is small, the eye diagram in this technique is more open. Similarly, when focusing on... Figure 9 The waveform within the dashed box 132 in the eye diagram of this technology shown below and Figure 11 When viewing the waveform within the dashed box 134 of the eye diagram of conventional technique 2, the eye diagram of this technique is more open compared to the eye diagram of conventional technique 2.

[0095] In addition, if you pay attention Figure 8 The waveform within the dashed box 131 on the eye diagram of this technology shown is... Figure 12 The waveform within the dashed box 135 on the eye diagram of conventional technique 2 shows that the eye diagram of this technique has a larger slope for both the rising and falling edges than the eye diagram of conventional technique 2. As a result, in conventional technique 2, when the horizontal eye diagram opening is maximized, the vertical eye diagram opening (eye diagram height) is smaller than the vertical eye diagram opening in this technique. Similarly, when focusing on... Figure 9The waveform within the dashed box 132 in the eye diagram of this technology shown below and Figure 13 When the waveform within the dashed box 136 on the eye diagram of conventional technique 2 is shown, the eye diagram of this technique has a larger slope for the rising and falling edges than the eye diagram of conventional technique 2, and in conventional technique 2, even if the pulse width increases, the height decreases.

[0096] Note that regarding the eye diagram of conventional technique 1, please refer to JP2017-527162A. Figure 5 and Figure 6 This confirms a reduction in switching jitter compared to the typical eye diagram of a C-PHY.

[0097] As mentioned above, such as Figure 14 As shown, the eye diagram of this technology is different not only from the eye diagram of a typical C-PHY, but also from the eye diagrams of conventional technology 1 and conventional technology 2. In other words, because a flip operation is performed, the eye diagram of this technology is different from any eye diagram in a typical C-PHY, conventional technology 1, and conventional technology 2, and has the following characteristics.

[0098] Reference Figures 15 to 25 This describes the characteristics of the eye diagram in this technology. Figure 15 This is a schematic diagram used to illustrate the voltage height of an eye diagram. In the C-PHY standard, there are four voltage height levels in the eye diagram, namely SH (strong high), WH (weak high), WL (weak low), and SL (strong low) in descending order of voltage.

[0099] like Figure 15 As shown, the voltage on the vertical axis is 0V at the center, with the upward direction being positive (+) and the downward direction being negative (-). Among the high voltage levels (above 0), the higher voltage level is SH and the lower voltage level is WH. Furthermore, among the low voltage levels (less than 0), the higher voltage level is WL and the lower voltage level is SL. Note that SH is also called S1, WH is also called W1, WL is also called W0, and SL is also called S0.

[0100] The eye diagram of this technology has the following characteristics caused by the flipping operation. Firstly, because the transition from WH to SH occurs towards WL, it necessarily includes a voltage waveform that drops once (hereinafter referred to as the first characteristic). Secondly, because the transition from WL to SL occurs towards WH, it necessarily includes a voltage waveform that rises once (hereinafter referred to as the second characteristic).

[0101] Third, it has the following characteristic: because the transition from WH to WH must proceed towards WL during the flipping operation, the constant voltage waveform of WH disappears (hereinafter referred to as the third characteristic). Fourth, it has the following characteristic: because the transition from WL to WH must proceed towards WH during the flipping operation, the constant voltage waveform of WL disappears (hereinafter referred to as the fourth characteristic). Fifth, it has the following characteristic: including a waveform with a high voltage slew rate that causes the transition towards SL during the transition from SH to WH (hereinafter referred to as the fifth characteristic).

[0102] <<First Characteristic>>

[0103] refer to Figure 16 and Figure 17 Here is a specific example to describe the first characteristic mentioned above.

[0104] exist Figure 16 In the eye diagram of this technology, since the transition from WH to SH occurs towards WL, the voltage will inevitably exhibit a waveform that drops once, as shown by the thick V-shaped line 141.

[0105] Furthermore, cases involving the transition from WH to SH towards WL during the transition period are as follows: Figure 6 When the state transition of the voltage level in the middle is associated with the acquisition, for example, Figure 17 The relationship shown. In Figure 17 The middle and upper parts correspond to Figure 6 The lower part of the mode 112 of this technology is a mode obtained by treating mode 112 of this technology as a differential signal. That is, Figure 17 The upper part is a schematic diagram obtained by observing individual signals (A, B, and C). Figure 17 The lower part is a schematic diagram obtained by observing the differential signals (AB, BC, and CA).

[0106] exist Figure 17 In the lower part, the differential signal AB is represented by a dotted line, the differential signal BC by a solid line, and the differential signal CA by a dashed line. Figure 17 The lower part, with Figure 17 Similar to the upper part, the flipping operation time is represented by a dotted pattern area, which approaches the timing of making the differential signal voltage become 0 through the flipping operation. Figure 17 In the lower part, the differential signal AB transitions from WH to WL, the differential signal BC transitions from WH to SH, and the differential signal CA transitions from SL to WL. Here, focusing on the differential signal BC shown by the solid line, the transition from WH to SH occurs during the flip operation time, which corresponds to... Figure 16 The transition from WH to SH is shown in the eye diagram of this technique.

[0107] <<Second Characteristic>>

[0108] refer to Figure 18 and Figure 19 Here is a specific example to describe the second characteristic mentioned above.

[0109] exist Figure 18 In the eye diagram of this technology, because the transition from WL to SL occurs towards WH, the voltage inevitably exhibits a single-rise waveform, as shown by the thick V-shaped line 142. Furthermore, when a pattern corresponding to the case where the transition from WL to SL occurs towards WH is shown, the voltage is obtained as follows... Figure 19 The relationships are shown. Note that the patterns corresponding to cases where the transition from WL to SL occurs towards WH are not included. Figure 6 In the example of voltage level state transition.

[0110] exist Figure 19 The upper part shows the pattern obtained by viewing individual signals (A, B, and C), with signal A represented by a solid line, signal B by a dotted line, and signal C by a double-dotted line. The lower part shows the pattern obtained by treating the upper pattern as differential signals (AB, BC, and CA).

[0111] exist Figure 19 In the lower part, the differential signal AB is represented by a dotted line, the differential signal BC by a solid line, and the differential signal CA by a dashed line. Figure 19 In the lower part, the differential signal AB transitions from SH to WH, the differential signal BC transitions from WL to SL, and the differential signal CA transitions from WL to WH. Here, if we focus on the differential signal BC represented by the solid line, the transition towards WH occurs during the flip-flop operation time in the transition from WL to SL, which corresponds to... Figure 18 The transition from WL to SL in the eye diagram of this technique is shown.

[0112] <<Third and Fourth Characteristics>>

[0113] refer to Figures 20 to 22 Specific examples describing the third and fourth characteristics mentioned above.

[0114] First, a specific example of the third characteristic is described. Figure 20 In the eye diagram of this technique, because the transition from WH to WL necessarily proceeds towards WL during the flipping operation, the constant voltage waveform of WH has disappeared, as shown by the horizontal dotted line 143. Here, if we compare the eye diagram of this technique with... Figure 15 Compared to the typical C-PHY eye diagram shown on the left, the constant voltage waveform present in the typical C-PHY eye diagram is absent in the dashed line 143 portion of the eye diagram of this technology.

[0115] Furthermore, in cases where the transition from WH to WH during the flipping operation will necessarily proceed towards WL, and... Figure 6 When the state transition of the voltage level in is associated with, for example, obtaining, as Figure 21 The relationship is shown. In Figure 21 The middle and upper parts are with Figure 6 The lower part is the mode corresponding to mode 115 of this technology, which is obtained by treating mode 115 of this technology as a differential signal. That is, Figure 21 The upper part shows the case where they are considered as single signals (A, B, and C). Figure 21 The lower part shows the case where the signals are considered as differential signals (AB, BC, and CA).

[0116] exist Figure 21 In the lower part, the differential signal AB is represented by a dotted line, the differential signal BC by a solid line, and the differential signal CA by a dashed line. Figure 21 In the lower part, the differential signal AB transitions from WH to SL, the differential signal BC transitions from WH to WH, and the differential signal CA transitions from SL to WH. Here, if we focus on the differential signal BC represented by the solid line, the transition from WH to WH occurs towards WL during the flip operation time, which corresponds to... Figure 20 The transition from WH to WH in the eye diagram of this technology is shown.

[0117] Next, we will describe a specific example of the fourth characteristic. Figure 20 In the eye diagram of this technique, because the transition from WL to WH necessarily proceeds towards WH during the flipping operation, the constant voltage waveform of WL has disappeared, as shown by the horizontal dotted line 144. Also, if the eye diagram of this technique is compared with... Figure 15 Compared to the typical C-PHY eye diagram shown on the left, the constant voltage waveform present in the typical C-PHY eye diagram is absent in the dashed line 144 portion of the eye diagram of this technology.

[0118] Furthermore, when a pattern corresponding to a case where the transition from WL to WL necessarily proceeds towards WH during the flipping operation is shown, the following is obtained: Figure 22 The relationship is shown. Note that in... Figure 6 The voltage level state transition examples do not include the pattern corresponding to the case where the transition from WL to WH occurs during the transition from WL to WH. Figure 22 The upper part shows the pattern obtained by viewing individual signals (A, B, and C), with signal A represented by a solid line, signal B by a dotted line, and signal C by a double-dotted line. The lower part shows the pattern obtained by treating the pattern in the upper part as differential signals (AB, BC, and CA).

[0119] exist Figure 22In the lower part, the differential signal AB is represented by a dotted line, the differential signal BC by a solid line, and the differential signal CA by a dashed line. Figure 22 In the lower part, the differential signal AB transitions from SH to WL, the differential signal BC transitions from WL to WL, and the differential signal CA transitions from WL to SH. Here, if we focus on the differential signal BC represented by the solid line, the transition from WL to WL occurs towards WH during the flip operation time, which corresponds to... Figure 20 The eye diagram shown illustrates the transition from WL to WL in this technique.

[0120] <<The Fifth Characteristic>>

[0121] refer to Figures 23 to 25 A specific example describing the fifth characteristic mentioned above.

[0122] exist Figure 23 In the eye diagram of this technology, during the transition from SH to WH, a waveform is obtained that causes the transition towards SL, as shown by the thick V-shaped line 145. Furthermore, when a pattern corresponding to the case where the transition towards SL occurs during the transition from SH to WH is shown, the waveform obtained is as follows: Figure 24 The relationship is shown. Note that in... Figure 6 The voltage level state transition examples do not include the pattern corresponding to the case where the transition from SH to WH occurs towards SL.

[0123] exist Figure 24 The upper part shows the pattern obtained by viewing individual signals (A, B, and C), with signal A represented by a solid line, signal B by a dotted line, and signal C by a double-dotted line. The lower part shows the pattern obtained by treating the pattern in the upper part as differential signals (AB, BC, and CA).

[0124] exist Figure 24 In the lower part, the differential signal AB is represented by a solid line, the differential signal BC by a dotted dashed line, and the differential signal CA by a dashed line. Figure 24 In the lower part, the differential signal AB transitions from SH to WH, the differential signal BC transitions from WL to SL, and the differential signal CA transitions from WL to WH. Here, if we focus on the differential signal AB represented by the solid line, the transition from SH to WH occurs towards SL during the flip operation time, which corresponds to... Figure 23 The transition from SH to WH in the eye diagram of this technique is shown.

[0125] The slew rate in the fifth characteristic is explained. As a premise, it is assumed that the voltage height of the eye diagram specified in the C-PHY standard has four levels, namely, SH, WH, WL and SL in descending order of voltage.

[0126] Furthermore, the high voltage on the transmitting side is defined as VH, and the low voltage on the transmitting side is defined as VL. Here, as... Figure 25 As shown, Figure 4 The TX driver 34 includes transistors Tr1 and Tr2. For example, transistor Tr1 is configured as a PMOS transistor, with its gate connected to the signal line on the PU (pull-up) side and its source connected to the voltage input terminal VH. Furthermore, transistor Tr2 is configured as an NMOS transistor, with its gate connected to the signal line on the PD (pull-down) side and its source connected to the voltage input terminal VL. The signal lines connected to the drain sides of transistors Tr1 and Tr2 are the outputs of the TX driver 34. The signal lines on the PU and PD sides are connected to an inverting multiplexer 33. Note that the detailed configuration of the TX driver 34 will be described later.

[0127] Under impedance matching conditions, SH, WH, WL and SL can be obtained by the following expressions (1) to (4).

[0128] [Mathematical Expression 1] ……(1) [Mathematical Expression 2] ……(2) [Mathematical Expression 3] ……(3) [Mathematical Expression 4] ……(4) Here, since the step response of the TX driver 34 circuit has similar characteristics to the step response of a typical first-order resistor-capacitor (RC) low-pass filter, the RC low-pass filter can be used to calculate the slew rate. The slew rate (SR) of the RC low-pass filter can be obtained by the following equation (5).

[0129] [Mathematical Expression 5] ……(5) In expression (5), V is the step voltage and τ is the RC time constant.

[0130] In a typical C-PHY, the SH is transformed The step voltage of WH is (VH-VL) / 4, while in this technology, due to the change SH SL WH, therefore the step voltage is VH-VL. Therefore, in this technique, the SH transition... The slew rate of WH is approximately four times higher than that of a typical C-PHY. Note that in conventional technique 2, due to the transformation of SH... 0 Therefore, the step voltage is (VH-VL) / 2. Thus, even compared to conventional technology 2, this technology has approximately twice the slew rate. As mentioned above, the eye diagram of this technology differs from that of typical C-PHY and conventional technology 2.

[0131] As a specific example of the fifth characteristic, a case has been illustrated where the transition from SH to WH occurs towards SL. However, simulations by the inventors of this technology have also confirmed such waveforms in other transitions. For example, in the transitions from SH to WL, from SL to WL, and from SL to WH, similar to the transition from SH to WH, waveforms with slew rates approximately four times higher than those in the typical C-PHY transition from SH to WH have been confirmed. More specifically, for example, during the transition from SL to WL, a waveform with a high slew rate that causes the transition towards SH is included.

[0132] Note that in the above description, the first to fifth characteristics are described as characteristics of the eye diagram of this technology, but other characteristics may also be included. For example, in the eye diagram of this technology, since there is always a transition by a flip operation during the transition, there is also the characteristic that the slew rate at the beginning of the transition does not depend on the next data.

[0133] <Implementation Example>

[0134] For the composition Figure 4 The generation circuit 31 (inverting pulse generator 42), inverting multiplexers 33-1 to 33-3, and TX drivers 34-1 to 34-3 of the transmitting device 11 can be implemented in various ways. For example, Figure 26 Examples are shown of the inverting pulse generator 42, inverting multiplexers 33-1 to 33-3, and TX drivers 34-1 to 34-3 configured according to the first implementation example.

[0135] The following describes the generation circuit 31 (inverting pulse generator 42), the inverting multiplexers 33-1 to 33-3, and the TX drivers 34-1 to 34-3 according to... Figure 26 The first implementation example configuration shown, along with the generation circuit 31, inverting multiplexers 33-1 to 33-3, and TX drivers 34-1 to 34-3, are configured according to a second implementation example configuration different from the first implementation example.

[0136] For example, as the data clock input to serializers 32-1 to 32-3, a first implementation example using an input half-data rate clock and a second implementation example using an input delayed half-data rate clock can be adopted. Furthermore, as a combination of the configuration of the inverting multiplexer 33 and the TX driver 34, a first implementation example where the PU side of the TX driver 34 is composed of PMOS transistors and the PD side is composed of NMOS transistors, and a second implementation example where both the PU side and PD side of the TX driver 34 are composed of NMOS transistors, can be adopted.

[0137] For example, as the data clock input to the inverting pulse generator 42, a first implementation example using a half-data-rate clock and a second implementation example using a 1 / 4-data-rate clock can be adopted. Furthermore, as the variable delay control signal for controlling the variable delay circuit included in the inverting pulse generator 42, a first implementation example using the TX register signal on the transmitting side and a second implementation example using a request signal notified from the receiving side can be adopted. Moreover, as the variable delay circuit included in the inverting pulse generator 42, a first implementation example consisting of a buffer, a load capacitor, and a switch and a second implementation example consisting of a phase interpolation circuit and a multiplexer can be adopted.

[0138] Note that each implementation example can be implemented independently, and, for example, assuming implementation via a combination of the first and second implementation examples described above, there are 2 5 = 32 combinations.

[0139] <<First Implementation Example: The Relationship Between Clock and Inverting Pulse>>

[0140] refer to Figure 27 and Figure 28 Describe the relationship between the clock and the inverted pulse when using the first implementation example.

[0141] Figure 27 This is a diagram illustrating an example configuration of the inverting pulse generator 42 when using the first implementation example. Figure 27 For ease of description, a single line of serializer 32, inverting multiplexer 33, and TX driver 34 is illustrated, but the illustrated line corresponds to the three lines mentioned above.

[0142] exist Figure 27 In this circuit, the inverting pulse generator 42 includes a variable delay circuit 51A and an EXNOR gate circuit 52A. A half-data-rate clock generated by the clock generator 41 is input to the inverting pulse generator 42. The inverting pulse generator 42 outputs the half-data-rate clock to the serializer 32. Additionally, in the inverting pulse generator 42, the half-data-rate clock is input to the variable delay circuit 51A and the EXNOR gate circuit 52A.

[0143] The variable delay circuit 51A delays the input half-data rate clock and outputs the delayed half-data rate clock to the EXNOR gate circuit 52A. The amount of the variable delay in the variable delay circuit 51A is adjusted by an externally output TX register signal. The TX register signal is a variable delay control signal used to adjust the amount of the variable delay. For example, the TX register signal is a signal (register value) stored in the register circuit on the transmitting side and is read as needed.

[0144] EXNOR gate circuit 52A generates an inverted pulse by performing an XOR operation on the input half-data rate clock and the delayed half-data rate clock, and outputs the inverted pulse to inverting multiplexer 33. The width of the inverted pulse can be adjusted by the variable delay circuit 51A according to the TX register signal, which adjusts the amount of the variable delay.

[0145] Figure 28 It is shown Figure 27 The timing diagram shows the relationship between the clock and the inverted pulse in the inverted pulse generator 42. Figure 28 The timing diagram illustrates the input half-data rate clock, the delayed half-data rate clock delayed by the variable delay circuit 51A, and the inverted pulse output from the EXNOR gate circuit 52A.

[0146] like Figure 28 As shown, when both the half-data rate clock and the delayed half-data rate clock are at H level or both are at L level, the inverted pulse is at H level. As indicated by the double arrows in the figure, the width of the inverted pulse can be adjusted by adjusting the delay of the delayed half-data rate clock according to the TX register signal.

[0147] <<Second Implementation Example: The Relationship Between Clock and Inverting Pulse>>

[0148] refer to Figure 29 and Figure 30 Describe the relationship between the clock and the inverted pulse when using the second implementation example.

[0149] Figure 29 This is a diagram illustrating an example configuration of the inverting pulse generator 42 when using the second implementation example. Figure 29 In, with Figure 27 Similarly, a serializer 32, an inverting multiplexer 33, and a TX driver 34 are illustrated for a single line.

[0150] exist Figure 29 In the inverting pulse generator 42, there are a variable delay circuit 51B and an EXOR gate circuit 52B. In the inverting pulse generator 42, a half-data rate clock is input to the variable delay circuit 51B and the EXOR gate circuit 52B.

[0151] The variable delay circuit 51B delays the input half-data rate clock based on the TX register signal output from the outside. The delayed half-data rate clock is output to the serializer 32 and the EXOR gate circuit 52B.

[0152] The EXOR gate circuit 52B generates an inverted pulse by performing an XOR operation on the input half-data rate clock and the delayed half-data rate clock, and outputs the inverted pulse to the inverting multiplexer 33. The width of the inverted pulse can be adjusted by the variable delay circuit 51B according to the TX register signal, which adjusts the amount of the variable delay.

[0153] Figure 30 It is shown Figure 29 The timing diagram shows the relationship between the clock and the inverted pulse in the inverted pulse generator 42. Figure 30 The timing diagram shows the input half-data rate clock, the delayed half-data rate clock delayed by the variable delay circuit 51B, and the inverted pulse output from the EXOR gate circuit 52B.

[0154] like Figure 30 As shown, when the half-data rate clock and the delayed half-data rate clock are at H level and L level, or at L level and H level, that is, when the levels are different, the inverted pulse is at H level. As shown by the double-headed arrow in the figure, the width of the inverted pulse can be adjusted by adjusting the delay of the delayed half-data rate clock according to the TX register signal.

[0155] <<First Implementation Example: The Relationship Between the Inverted MUX and the TX Driver>>

[0156] refer to Figure 31 and Figure 32 Describe the relationship between the inverting multiplexer 33 and the TX driver 34 when using the first implementation example.

[0157] Figure 31 This is a diagram illustrating an example configuration of the inverting multiplexer 33 and the TX driver 34 using the first implementation example. Figure 31 For ease of description, only one line is shown for the serializer 32, the inverting multiplexer 33, and the TX driver 34, but the line shown corresponds to the three lines mentioned above.

[0158] exist Figure 31In this configuration, the inverter multiplexer 33 includes switches SW11 to SW14 and inverters INV1 and INV2. Switch SW11 is connected to the PU (pull-up) side signal line, and switch SW12 is connected to the PD (pull-down) side signal line. Inverter INV1 and switch SW13 are connected to the signal lines that connect the PU side signal lines to the PD side signal lines. Inverter INV2 and switch SW14 are connected to the signal lines that connect the PD side signal lines to the PU side signal lines.

[0159] The TX driver 34 includes transistors Tr11 and Tr12, and resistors R11 and R12. Transistor Tr11 is configured as a PMOS transistor, and its gate is connected to the PU-side signal line. Transistor Tr12 is configured as an NMOS transistor, and its gate is connected to the PD-side signal line. The signal lines connected to the drain sides of transistors Tr11 and Tr12 are the outputs of the TX driver 34. In the TX driver 34, the output voltage level corresponds to the PU signal input to the gate of transistor Tr11 and the PD signal input to the gate of transistor Tr12. The PU signal is used to raise the voltage level. The PD signal is used to lower the voltage level.

[0160] Figure 32 This is a diagram illustrating the relationship between the PU logic, PD logic, and voltage level states when using the first implementation example. Figure 32 It shows from Figure 31 The correspondence between the voltage level state output by the TX driver 34 and the values ​​of the PU logic corresponding to the PU signal and the PD logic corresponding to the PD signal. For example... Figure 32 As shown, when both PU logic and PD logic are 0, the voltage level is H level; when PU logic is 0 and PD logic is 1, the voltage level is M level; when both PU logic and PD logic are 1, the voltage level is L level.

[0161] exist Figure 31 In the inverting multiplexer 33, switches SW11 to SW14 are supplied with inverted pulses from the inverting pulse generator 42, and the upper switches SW11 and SW12 and the lower switches SW13 and SW14 operate in a complementary manner. By performing this operation via switches SW11 to SW14, in the TX driver 34, transistor Tr11 on the PU side performs on / off operation corresponding to the PU signal input to the gate, and transistor Tr12 on the PD side performs on / off operation corresponding to the PD signal input to the gate. This enables the data output from the TX driver 34 to be switched to an inverted mode at each data transition and maintained for a predetermined time width.

[0162] <<Second Implementation Example: The Relationship Between the Inverted MUX and the TX Driver>>

[0163] refer to Figure 33 and Figure 34 The relationship between the inverting multiplexer 33 and the TX driver 34 is described when the second implementation example is used.

[0164] Figure 33 This is a diagram illustrating an example configuration of the inverting multiplexer 33 and the TX driver 34 when using the second implementation example. Figure 33 In, with Figure 31 Similarly, a serializer 32, an inverting multiplexer 33, and a TX driver 34 are shown for a single line.

[0165] exist Figure 33 In this circuit, the inverting multiplexer 33 includes switches SW21 to SW24. Switch SW21 is connected to the PU-side signal line, and switch SW22 is connected to the PD-side signal line. Switch SW23 is connected to the signal line that connects the PU-side signal line to the PD-side signal line, and switch SW24 is connected to the signal line that connects the PD-side signal line to the PU-side signal line.

[0166] The TX driver 34 includes transistors Tr21 and Tr22, and resistors R21 and R22. Transistor Tr21 is configured as an NMOS transistor, and its gate is connected to the PU-side signal line. Transistor Tr22 is configured as an NMOS transistor, and its gate is connected to the PD-side signal line. The signal line connected to the source side of transistor Tr21 and the drain side of transistor Tr22 is the output of the TX driver 34. In the TX driver 34, the output voltage level corresponds to the PU signal input to the gate of transistor Tr21 and the PD signal input to the gate of transistor Tr22.

[0167] Figure 34 This is a diagram illustrating the relationship between the PU logic, PD logic, and voltage level states when using the second implementation example. Figure 34 It shows from Figure 33 The correspondence between the voltage level states output by the TX driver 34 and the values ​​of the PU and PD logic is shown. Figure 34 As shown, when the PU logic is 1 and the PD logic is 0, the voltage level is H level; when both the PU logic and PD logic are 1, the voltage level is M level; and when the PU logic is 0 and the PD logic is 1, the voltage level is L level.

[0168] exist Figure 33In the inverting multiplexer 33, switches SW21 to SW24 are supplied with inverted pulses from the inverting pulse generator 42. The upper switches SW21 and SW22, and the lower switches SW23 and SW24 operate in a complementary manner. By performing the operation via switches SW21 to SW24, in the TX driver 34, transistor Tr21 on the PU side performs an on / off operation corresponding to the PU signal input to the gate, and transistor Tr22 on the PD side performs an on / off operation corresponding to the PD signal input to the gate. This enables the data output from the TX driver 34 to be switched to an inverted mode at each data transition and maintained for a predetermined time width.

[0169] Note that if comparing Figure 31 TX driver 34 and Figure 33 The TX driver 34, then Figure 31 The transistor Tr11 is configured as a PMOS transistor, while Figure 33 The transistor Tr21 is configured as an NMOS transistor. If compared... Figure 31 Inverting multiplexer 33 and Figure 33 The inverting multiplexer 33, then in Figure 31 In the inverting multiplexer 33, inverters INV1 and INV2 are provided corresponding to transistor Tr11, which is configured as a PMOS transistor. That is, the circuit configuration of the inverting multiplexer 33 depends on the circuit configuration of the TX driver 34.

[0170] <<Implementation Example of an Inverting Pulse Generator>>

[0171] refer to Figures 35 to 38 Describe an implementation example of the inverted pulse generator 42.

[0172] like Figure 35 and Figure 36 As shown, in the inverted pulse generator 42, the variable delay circuit 51 delays the half-data rate clock, and the logic circuit 52 performs logic operations (such as XOR NOT) on the half-data rate clock and the delayed half-data rate clock, thereby generating an inverted pulse.

[0173] like Figure 35 As shown, the variable delay circuit 51 can adjust the amount of the variable delay according to the TX register signal. For example... Figure 36 As shown, the variable delay circuit 51 can adjust the amount of the variable delay according to the request signal. The request signal is a variable delay control signal used to adjust the amount of the variable delay. For example, the request signal is a signal requested from the receiving side and notified through a predetermined transmission path.

[0174] like Figure 37 and Figure 38As shown, in the inverted pulse generator 42, the variable delay circuit 51 delays the output signal of the logic circuit 53, and the logic circuit 52 performs logical operations on the output signal of the logic circuit 53 and the delayed output signal of the logic circuit 53, thereby generating an inverted pulse. Figure 37 and Figure 38 In the example, I and Q 1 / 4 data rate clocks with different phases are used, and the result of the logic operation (logical OR) of logic circuit 53 is used as the input.

[0175] like Figure 37 As shown, the variable delay circuit 51 can adjust the amount of the variable delay according to the TX register signal. Additionally, as... Figure 38 As shown, the variable delay circuit 51 can adjust the amount of delay according to the request signal.

[0176] In summary, the configuration using a half-data-rate clock ( Figure 35 and Figure 36 This corresponds to the first implementation example, using a 1 / 4 data rate clock configuration. Figure 37 and Figure 38 This corresponds to the second implementation example. Additionally, the configuration using the TX register signal ( Figure 35 and Figure 37 Corresponding to the first implementation example, the configuration using request signals ( Figure 36 and Figure 38 This corresponds to the second implementation example.

[0177] <<Implementation Example of Variable Delay Circuit>>

[0178] refer to Figure 39 and Figure 40 Describe an implementation example of the variable delay circuit 51.

[0179] Figure 39 This is a diagram illustrating a configuration example of the variable delay circuit 51 using the first implementation example. Figure 39 In this circuit, the variable delay circuit 51 includes buffers 61 and 62, a switch 63, and a load capacitor 64. Switch 63 consists of multiple switches, and the load capacitor is connected to each switch. In switch 63, each switch switches between on and off states according to the TX register signal, thereby changing the load capacitance value of buffer 61.

[0180] The variable delay circuit 51 delays the input half-data rate clock based on the load capacitance value of the buffer 61, and outputs the delayed half-data rate clock to the logic circuit 52. As described above, in the variable delay circuit 51, the delay amount is adjusted by changing the load capacitance value of the buffer 61 using the switch 63 and the load capacitor 64.

[0181] Figure 40This diagram illustrates an example configuration of the variable delay circuit 51 using the second implementation example. Figure 40 In the variable delay circuit 51, a multi-bit phase interpolation circuit 71 and a multiplexer 72 are included. In the variable delay circuit 51, the multi-bit phase interpolation circuit 71 receives a half-data rate clock and a half-data rate clock with a phase delay of 90 degrees compared to the half-data rate clock. The multi-bit phase interpolation circuit 71 generates half-data rate clocks with various phase delays by using the input half-data rate clock and the half-data rate clock with a 90-degree phase delay, and outputs the generated half-data rate clocks to the multiplexer 72.

[0182] Multiplexer 72 selects a half-data rate clock with a desired phase delay from the half-data rate clocks with various phase delays input from the multi-bit phase interpolation circuit 71, corresponding to the TX register signal. Using this arrangement, multiplexer 72 can output a half-data clock with a phase delay of 0 to 90 degrees based on the TX register signal. As described above, in the variable delay circuit 51, the delay amount of the variable delay is adjusted by generating clocks with various phase delays using the multi-bit phase interpolation circuit 71 and selecting a clock with the desired phase delay.

[0183] <<Implementation Example of Variable Delay Control Signal>>

[0184] Figure 41 This is a diagram illustrating a configuration example of notifying a variable delay control signal when implementing Example 2. Figure 41 The variable delay circuit 51 is illustrated in the inverting pulse generator 42, which adjusts the delay amount of the variable delay according to the request signal from the receiving side.

[0185] The request signal is a variable delay control signal notified from the receiving device 12 and is transmitted through a transmission path (transmission line) capable of transmitting the signal from the receiving device 12 to the transmitting device 11. The transmission path used here is not particularly limited, and any transmission path can be used as long as it can transmit the request signal from the receiving device 12 to the transmitting device 11.

[0186] In the inverting pulse generator 42, the variable delay circuit 51 delays the half-data rate clock according to a request signal sent from the receiving device 12 via a predetermined transmission path, and outputs the delayed half-data rate clock to the logic circuit 52. That is, the variable delay circuit 51 adjusts the amount of the variable delay according to the control from the receiving device 12.

[0187] Note that the variable delay control signal is notified by the receiving device 12 on the receiving side, and the register value stored in the register circuit of the transmitting device 11 on the transmitting side is rewritten thereby, which can adjust the TX register signal (register value) read from the register circuit.

[0188] <Measurement Method>

[0189] The eye diagram of this technology can be measured, for example, by the following method. Specifically, the measurement system is disclosed in the specification document of the MIPI C-PHY standard (MIPI Alliance-mipi_C-PHY-v2-1_cts_v1-0.pdf), and can be obtained using the measurement system. Figure 14 The eye diagram of this technology is shown. Specifically, the measurement system described in “Figure B.1.2-1 HS Transmitter Test Setup #1 (Differential Probes, with RTB)” (page 266) in the specification document can be used.

[0190] <Variation Example>

[0191] The above description illustrates a scenario where data transmitted via three transmission lines is transmitted at different voltage levels (H, M, and L levels) on each line. However, the number of transmission lines is not limited to three, and the different voltage levels on each line only require multiple voltage levels. In other words, this technology is applicable to transceiver systems that transmit data via multiple transmission lines at different voltage levels on each line.

[0192] Furthermore, the above description has already explained the use of the four levels SH, WH, WL, and SL corresponding to the MIPI C-PHY standard as the voltage levels of the eye diagram. However, the voltage levels of the eye diagram are not limited to four levels and can be more than four. For example, the voltage levels can be more than four, and among the voltage levels above 0, the second lowest voltage level can be the first voltage level, and the lowest voltage level can be the second voltage level. Among the voltage levels below 0, the highest voltage level can be the third voltage level, and the second highest voltage level can be the fourth voltage level.

[0193] Figure 4 The receiving device 12 performs clock recovery every unit interval (UI) and also performs clock recovery by detecting a signal that must cross a first threshold among the clock recovery thresholds. This technology is applicable to a transmitting device for communication that performs such clock recovery.

[0194] As described above, in the transmitting device 11 applying this technology ( Figure 4 In ), compared with the usual transmitting device ( Figure 2Compared to the previous version, an inverting pulse generator 42 and an inverting multiplexer 33 are additionally provided. In implementing the transmitting device 11 ( Figure 4 When arranging circuits corresponding to each function on the substrate, the following layout is adopted: additional circuits including an inverting pulse generator (42) and an inverting multiplexer (33) are arranged after the serializer (32) and between the serializer (32) and the TX driver (34).

[0195] Note that the embodiments of this technology are not limited to the above embodiments, and various modifications can be made without departing from the spirit of this technology. Furthermore, the effects described in the specification are merely illustrative and not restrictive, and other effects can be obtained.

[0196] In addition, this technology can be configured as follows.

[0197] (1) A method for sending data, comprising: When a transmitting device transmits data through multiple transmission lines at different voltage levels on each line, for each data transition, a control signal is used to switch to a specific data mode different from the data before the transition. The eye diagram obtained through measurement data is as follows: When the second lowest voltage level among voltage levels above 0 is the first voltage level and the lowest voltage level is the second voltage level, and the highest voltage level among voltage levels below 0 is the third voltage level and the second highest voltage level is the fourth voltage level, then... During the transition from the second voltage level to the third voltage level, since the transition occurs towards the third voltage level, the constant voltage waveform of the second voltage level disappears, and During the transition from the third voltage level to the second voltage level, the constant voltage waveform of the third voltage level disappears because the transition is towards the second voltage level.

[0198] (2) According to the sending method described in (1), The specific data pattern mentioned above includes the inverted pattern obtained by inverting the data before the transformation.

[0199] (3) The sending method according to (1) or (2), The control signal includes a pulse signal with a predetermined time width.

[0200] (4) The sending method according to any one of (1) to (3), The eye diagram includes a waveform in which the voltage drops once as the transition from the second voltage level to the first voltage level occurs.

[0201] (5) The sending method according to any one of (1) to (4), The eye diagram includes a waveform in which the voltage rises once as the transition from the third voltage level to the fourth voltage level occurs towards the second voltage level.

[0202] (6) The sending method according to any one of (1) to (5), The eye diagram includes a waveform having a high slew rate that causes a transition toward the fourth voltage level during the transition from the first voltage level to the second voltage level.

[0203] (7) The sending method according to any one of (1) to (6), The eye diagram includes a waveform having a high slew rate that causes a transition towards the first voltage level during the transition from the fourth voltage level to the third voltage level.

[0204] (8) The transmission method according to any one of (1) to (7), The eye diagram is measured using the differential signal of the data.

[0205] (9) The transmission method according to any one of (1) to (8), The transmission follows the MIPI C-PHY standard. The multiple transmission lines include three transmission lines. The voltage level states include three states: H level, M level, and L level. The first voltage level is SH (strong high), the second voltage level is WH (weak high), the third voltage level is WL (weak low), and the fourth voltage level is SL (strong low).

[0206] (10) A transmitting device that transmits data at different voltage levels on multiple transmission lines, the transmitting device comprising: Generator, generates control signals; and The multiplexer, for each data transformation, causes the data to be transformed into a specific data pattern different from the data before the transformation, based on the control signal.

[0207] (11) The transmitting device according to (10), The specific data pattern mentioned above includes the inverted pattern obtained by inverting the data before the transformation.

[0208] (12) The transmitting device according to (10) or (11), The generator generates a pulse signal with a predetermined time width as the control signal.

[0209] (13) The transmitting device according to (12), The generator mentioned above includes: Delay circuits delay the input data clock; and The logic circuit outputs the pulse signal by performing logical operations on the data clock and the delayed data clock.

[0210] (14) The transmitting device according to (13), The delay circuit adjusts the amount of variable delay based on register signals read from the register circuit on the data sending side or request signals notified from the data receiving side.

[0211] (15) The transmitting device according to (13) further includes: A serializer converts an input parallel signal into a serial signal and outputs the serial signal as the data. The data clock mentioned above includes a half-data rate clock, and The half-data-rate clock or the delayed half-data-rate clock is input to the serializer.

[0212] (16) The transmitting device according to any one of (13) to (15), A half-data-rate clock or a 1 / 4-data-rate clock is input to the inverting pulse generator.

[0213] (17) The transmitting device according to (14), The delay circuit includes: A buffer, a load capacitor, and a switch connected to the logic circuit are included. The data clock is input to the buffer, and The switch electrically connects the buffer and the load capacitor according to the register signal or the request signal.

[0214] (18) The transmitting device according to (14), The delay circuit includes: Phase interpolation circuit and second multiplexer The phase interpolation circuit generates multiple phase-delayed data clocks using the data clock, and The second multiplexer selects the desired data clock from the plurality of phase-delayed data clocks based on the register signal or the request signal.

[0215] (19) The transmitting apparatus according to any one of (10) to (18) further comprises: The driver outputs the data to the multiple transmission lines. The driver includes a first transistor disposed on the side that raises the voltage level and a second transistor disposed on the side that lowers the voltage level. The multiplexer is configured corresponding to the first transistor and the second transistor.

[0216] (20) The transmitting device according to (19), Wherein the first transistor is configured as a PMOS transistor and the second transistor is configured as an NMOS transistor, or The first transistor is configured as an NMOS transistor and the second transistor is configured as an NMOS transistor.

[0217] (21) The transmitting device according to any one of (10) to (20), The transmission follows the MIPI C-PHY standard. The multiple transmission lines include three transmission lines, and The voltage level states include three states: H level, M level, and L level.

[0218] (22) A transceiver system comprising a transmitting device and a receiving device, wherein the transmitting device transmits data at different voltage levels on each of multiple transmission lines, and the receiving device receives the data transmitted through the multiple transmission lines. The transmitting device includes: Generator, generates control signals; and The multiplexer, for each data transformation, causes the data to be transformed into a specific data pattern different from the data before the transformation, based on the control signal.

[0219] Figure Labels

[0220] 11: Transmitting device; 12: Receiving device; 13-1 to 13-3: Transmission lines; 31: Generating circuit; 32, 32-1 to 32-3: Serializer; 33, 33-1 to 33-3: Inverting multiplexer; 34, 34-1 to 34-3: TX driver; 41: Clock generator; 42: Inverting pulse generator; 51, 51A, 51B: Variable delay circuit; 52: Logic circuit; 52A: EXNOR gate circuit; 52B: EXOR gate circuit; 53: Logic circuit; 61, 62: Buffer; 63: Switch; 64: Load capacitor; 71: Multi-bit phase interpolation circuit; 72: Multiplexer; SW11 to SW14: Switch; INV1, INV2: Inverter; Tr11, Tr12: Transistor; SW21 to SW24: Switch; Tr21, Tr22: Transistor.

Claims

1. A method for sending data, comprising: When a transmitting device transmits data through multiple transmission lines at different voltage levels, for each data transition, a control signal causes the data to switch to a specific data mode different from the data before the transition. The eye diagram obtained by measuring the data is as follows: When the second lowest voltage level among voltage levels above 0 is the first voltage level and the lowest voltage level is the second voltage level, and the highest voltage level among voltage levels below 0 is the third voltage level and the second highest voltage level is the fourth voltage level, then... During the transition from the second voltage level to the third voltage level, since the transition occurs towards the third voltage level, the constant voltage waveform of the second voltage level disappears, and During the transition from the third voltage level to the second voltage level, the constant voltage waveform of the third voltage level disappears because the transition is towards the second voltage level.

2. The sending method according to claim 1, The specific data pattern mentioned above includes the inverted pattern obtained by inverting the data before the transformation.

3. The sending method according to claim 1, The control signal includes a pulse signal with a predetermined time width.

4. The sending method according to claim 1, The eye diagram includes a waveform in which the voltage drops once as the transition from the second voltage level to the first voltage level occurs.

5. The sending method according to claim 1, The eye diagram includes a waveform in which the voltage rises once as the transition from the third voltage level to the fourth voltage level occurs towards the second voltage level.

6. The sending method according to claim 1, The eye diagram includes a waveform having a high slew rate that causes a transition toward the fourth voltage level during the transition from the first voltage level to the second voltage level.

7. The sending method according to claim 1, The eye diagram includes a waveform having a high slew rate that causes a transition towards the first voltage level during the transition from the fourth voltage level to the third voltage level.

8. The sending method according to claim 1, The eye diagram is measured using the differential signal of the data.

9. The sending method according to claim 8, The transmission follows the MIPI C-PHY standard. The multiple transmission lines include three transmission lines. The voltage level states include three states: H level, M level, and L level. The first voltage level is SH (strong high), the second voltage level is WH (weak high), the third voltage level is WL (weak low), and the fourth voltage level is SL (strong low).

10. A transmitting device that transmits data at different voltage levels on multiple transmission lines, the transmitting device comprising: Generator, generates control signals; as well as The multiplexer, for each data transformation, causes the data to be transformed into a specific data pattern different from the data before the transformation, based on the control signal.

11. The transmitting device according to claim 10, The specific data pattern mentioned above includes the inverted pattern obtained by inverting the data before the transformation.

12. The transmitting device according to claim 10, The generator generates a pulse signal with a predetermined time width as the control signal.

13. The transmitting device according to claim 12, The generator mentioned above includes: Delay circuits delay the input data clock. as well as The logic circuit outputs the pulse signal by performing logical operations on the data clock and the delayed data clock.

14. The transmitting device according to claim 13, The delay circuit adjusts the amount of variable delay based on register signals read from the register circuit on the data sending side or request signals notified from the data receiving side.

15. The transmitting apparatus according to claim 13, further comprising: A serializer converts an input parallel signal into a serial signal and outputs the serial signal as the data. The data clock mentioned above includes a half-data rate clock, and The half-data-rate clock or the delayed half-data-rate clock is input to the serializer.

16. The transmitting device according to claim 13, A half-data-rate clock or a 1 / 4-data-rate clock is input to the generator.

17. The transmitting device according to claim 14, The delay circuit includes: A buffer, a load capacitor, and a switch connected to the logic circuit are included. The data clock is input to the buffer, and The switch electrically connects the buffer and the load capacitor according to the register signal or the request signal.

18. The transmitting device according to claim 14, The delay circuit includes: Phase interpolation circuit and second multiplexer The phase interpolation circuit generates multiple phase-delayed data clocks using the data clock, and The second multiplexer selects the desired data clock from the plurality of phase-delayed data clocks based on the register signal or the request signal.

19. The transmitting apparatus according to claim 10, further comprising: The driver outputs the data to the multiple transmission lines. The driver includes a first transistor disposed on the side that raises the voltage level and a second transistor disposed on the side that lowers the voltage level. The multiplexer is configured corresponding to the first transistor and the second transistor.

20. The transmitting device according to claim 19, Wherein the first transistor is configured as a PMOS transistor and the second transistor is configured as an NMOS transistor, or The first transistor is configured as an NMOS transistor and the second transistor is configured as an NMOS transistor.

21. The transmitting device according to claim 10, The transmission follows the MIPI C-PHY standard. The multiple transmission lines include three transmission lines, and The voltage level states include three states: H level, M level, and L level.

22. A transceiver system comprising a transmitting device and a receiving device, wherein the transmitting device transmits data at different voltage levels on each of multiple transmission lines, and the receiving device receives the data transmitted through the multiple transmission lines. The transmitting device includes: Generator, generates control signals; as well as The multiplexer, for each data transformation, causes the data to be transformed into a specific data pattern different from the data before the transformation, based on the control signal.

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