Image sensor with row drive circuit

Abstract

A pixel control line of an image sensor is connected with a pixel circuit of a pixel row. A row drive circuit drives a first digital voltage level to the pixel control line for a first time period and has a high output impedance for a second time period. A source follower amplifier controls a voltage on the pixel control line in the second time period according to a signal applied to a gate of the source follower amplifier. The row drive circuit can drive a second digital voltage level to the pixel control line for a time period after the second time period.

Description

[0001] This disclosure relates to an image sensor having a row driving circuit that outputs pixel control signals to multiple pixel circuits. Specifically, this disclosure relates to a row driving circuit that outputs a high-impedance state. Background Technology

[0002] Image sensors for solid-state imaging devices have pixel arrays with pixel circuits organized by pixel rows and pixel columns. Pixel circuits in the same pixel row receive the same pixel control signals. Pixel circuits in the same pixel column can share the same data signal line. Each pixel circuit includes one or more photoelectric conversion elements and pixel transistors. The photoelectric conversion elements generate a current proportional to the intensity of the received radiation. The pixel transistors control the initialization of the photoelectric conversion elements during the initialization period, the integration of the photocurrent during the exposure period, the conversion of the integrated photocurrent into an analog voltage signal, and the output of the analog voltage signal during the readout period.

[0003] The vertical scan unit generates a preamplifier pixel control signal. The line drive circuit converts the preamplifier pixel control signal into a pixel control signal, which is transmitted on the pixel control line. The pixel control line connects the output of the line drive circuit to the pixel transistors of the pixel circuit controlled by the line drive circuit. For image sensors with a rolling shutter, the same pixel control signal is transmitted to all pixel transistors with the same function in the pixel circuit with the same line address. For image sensors with a global shutter, the same pixel control signal is applied to all pixel transistors with the same function regardless of the line address. Summary of the Invention

[0004] The steep slope (edge) of the pixel control signal at the beginning of the pixel control line near the output of the row drive circuit may become less steep at the end of the pixel control line farther from the output of the row drive circuit. Signals with varying degrees of steepness can cause pixel circuits at the ends of pixel rows to switch later than those at the beginning of pixel rows. When a large number of pixel transistors simultaneously switch from a state where the pixel circuit consumes very little current to a state where the pixel circuit consumes more current, the supply voltage of the pixel circuit may drop slightly for a short period of time. When a pixel transistor that connects the floating node to the reference potential is turned off, channel charge may accumulate at the floating node and distort the pixel signal.

[0005] This disclosure mitigates the aforementioned and other drawbacks of the prior art. To this end, the pixel control line of the image sensor is connected to the pixel circuitry of the pixel row. The row driving circuit drives a first digital voltage level to the pixel control line during a first time period and has a high output impedance during a second time period. A source follower amplifier controls the voltage on the pixel control line during the second time period based on a signal applied to the gate of the source follower amplifier. During a time period following the second time period, the row driving circuit can apply a second digital voltage level to the pixel control line.

[0006] Because the output signal of a source follower amplifier follows the signal applied to its gate, it provides additional degrees of freedom for shaping the pixel control signal transmitted on the pixel control line. This additional design option can be used to slow down the transitions between different signal states and / or signal levels of the pixel control signal. For example, in an image sensor with a global shutter, the leading edge of the effective global selection signal that triggers the transmission of the analog pixel signal from the radiative receiver of the pixel circuit to the signal storage unit can be made less steep to avoid a significant drop in the pixel power supply voltage. The turn-off phase of the reset transistor can be extended to prevent the accumulation of channel charge at the floating node.

[0007] Compared to solutions that provide row drive circuits with long transistor channels for similar purposes, this implementation offers higher area efficiency and is less susceptible to process variations. Compared to examples that provide row drive circuits as current-mode drivers with adjustable constant current sinking / pulling, the slope of the pixel control signal is independent of, or only minimally dependent on, the pixel load, which varies slightly for each pixel circuit and is susceptible to fluctuations in process parameters, power supply voltage, and temperature. Attached Figure Description

[0008] A more complete understanding of this disclosure and its many accompanying advantages will readily become apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a simplified block diagram of a solid-state imaging device according to an embodiment of the present technology, the solid-state imaging device having an image sensor including a row drive circuit and a source follower amplifier, the source follower amplifier controlling the voltage on the pixel control line.

[0009] Figure 2A and Figure 2B A circuit diagram of a transistor circuit according to an embodiment is shown, along with timing diagrams of pixel control signals and voltage ramp signals applied to the gate of a source follower amplifier. The transistor circuit has a row drive circuit including a p-channel field-effect transistor (pFET) and a source follower amplifier.

[0010] Figure 3A and Figure 3BA circuit diagram of a transistor circuit according to another embodiment is shown, along with a timing diagram of a pixel control signal and a voltage ramp signal applied to the gate of a source follower amplifier. The transistor circuit has a row drive circuit including an n-channel field-effect transistor (nFET) and a source follower amplifier.

[0011] Figure 4 This is a simplified block diagram of a source follower amplifier according to an embodiment of the present technology, which receives a voltage ramp signal from a voltage ramp circuit.

[0012] Figure 5 yes Figure 4 A simplified block diagram of the integrator circuit of the voltage ramp circuit.

[0013] Figure 6 yes Figure 4 A simplified circuit diagram of the integrator circuit of the voltage ramp circuit.

[0014] Figure 7A , Figure 7B and Figure 7C It shows Figure 6 The various states of the integrator circuit.

[0015] Figure 8 According to another embodiment Figure 4 The circuit diagram of the integrator circuit of the voltage ramp circuit.

[0016] Figure 9A A circuit diagram is shown showing a combination of a row drive circuit with a CMOS inverter output and a source follower amplifier with a pFET, according to an embodiment.

[0017] Figure 9B It shows the application to Figure 9A The timing diagram of the row drive circuit and the source follower amplifier and the signal output from it.

[0018] Figure 10A A circuit diagram is shown showing a combination of a row drive circuit with a CMOS inverter output and a source follower amplifier with an nFET, according to another embodiment.

[0019] Figure 10B It shows the application to Figure 10A The timing diagram of the row drive circuit and the source follower amplifier and the signal output from it.

[0020] Figure 11 This is a simplified block diagram of a solid-state imaging device according to an embodiment of the present technology, which has an image sensor employing a global shutter and a source follower amplifier, wherein the source follower amplifier controls the voltage on the pixel control line.

[0021] Figure 12This is a circuit diagram of a pixel circuit with a reset transistor and a selection transistor, used to illustrate the effects of the implementation method.

[0022] Figure 13A and Figure 13B A diagram is shown illustrating the effect of the embodiment on the timing of pixel control signals received from the pixel circuit at the beginning of the pixel control line near the row drive circuit and from the pixel circuit at the end of the pixel control line far from the row drive circuit.

[0023] Figure 14 and Figure 15 The diagrams, including those according to embodiments, illustrate the difference between the reset signal and the floating diffusion potential of pixel circuits located at the beginning and end of pixel rows in embodiments with and without source follower amplifiers.

[0024] Figure 16 This is a schematic circuit diagram of the pixel circuit of the global shutter according to the implementation method.

[0025] Figure 17 This is a timing diagram illustrating the effect of the source follower amplifier on the current consumption gradient when the pixel selection signal becomes active, according to the implementation method.

[0026] Figure 18 This is a diagram illustrating an example of a stacked structure of a solid-state imaging apparatus according to an embodiment of the present disclosure.

[0027] Figure 19 It is a block diagram illustrating an example of a schematic configuration of a vehicle control system.

[0028] Figure 20 It is used for explanation Figure 19 An auxiliary diagram illustrating the installation locations of the vehicle's external information detection unit and imaging unit in a vehicle control system. Detailed Implementation

[0029] The following describes in detail, using the accompanying drawings, embodiments for implementing the technology of this disclosure (hereinafter also referred to as "implementations"). The technology of this disclosure is not limited to the described embodiments; various features in the embodiments are merely illustrative. Identical elements or elements having the same function are indicated by the same reference numerals. Repeated descriptions are omitted.

[0030] Connected electronic components can be electrically connected via direct, permanent, low-resistance connections (e.g., through conductive lines). The terms "electrical connection" and "signal connection" can also include connections via other electronic components provided for and suitable for permanent and / or temporary signal and / or energy transmission. Electronic components can be electrically or signal connected via resistors, capacitors, electronic switches such as FETs (field-effect transistors), or transistor circuits such as transmission gates. Directly electrically connected electronic components are connected via low-resistance wiring, ohmic contacts, and / or unipolar semiconductor junctions.

[0031] The load path of a transistor is the controlled current path of the transistor. The voltage applied to the gate of a field-effect transistor (FET) controls the current flow in the load path (controlled path) between the source and drain of the FET through the field effect.

[0032] Digital signals alternate between at least one active level and at least one inactive level. A digital signal with an active level is valid. A digital signal with an inactive level is invalid. For each signal individually, the active level can be a digital high level and the inactive level can be a digital low level, or the active level can be a digital low level and the inactive level can be a digital high level.

[0033] Although the techniques for improving image quality of solid-state imaging devices are described below in the context of certain types of pixel circuits used for voltage-domain global shutter pixels and progressive signal readout, the techniques can also be used for other types of pixel circuits and progressive signal readout.

[0034] Figure 1 An example configuration of a solid-state imaging apparatus 90 according to an embodiment of the present technology is shown. The solid-state imaging apparatus 90 includes an image sensor 70 and a signal processing unit 80. The image sensor 70 includes a pixel array 10, a column signal processing unit 20, a vertical scanning unit 30, a readout buffer memory 40, and a sensor controller 50.

[0035] The pixel array unit 10 includes a plurality of identical pixel circuits 100. Each pixel circuit 100 can be uniquely identified by a combination of its position in pixel row 11 and its position in pixel column 12.

[0036] Pixel circuit 100 can be any active pixel sensor for intensity readout, having one or two photoelectric conversion elements and three, four, or more pixel transistors 105. When pixel circuit 100 is selected, pixel circuit 100 is signal-connected to data signal line 19 and outputs an analog pixel signal through data signal line 19. The voltage level of the analog pixel signal depends on the illumination intensity detected by pixel circuit 100.

[0037] The photoelectric conversion elements of the pixel array 10 are typically arranged in a column and row matrix corresponding to pixel rows 11 and pixel columns 12, wherein a subset of pixel circuits 100 assigned to the same column of photoelectric conversion elements 101 can form pixel column 12, and a subset of pixel circuits 100 assigned to the same row of photoelectric conversion elements 101 can form pixel row 11.

[0038] The vertical scanning unit 30 includes a decoder unit 35 and multiple row drive circuits 220. The decoder unit 35 generates a preamplifier control signal for controlling the pixel transistor 105 based on a drive timing signal provided by the sensor controller 50. The preamplifier control signal is a logic signal whose voltage amplitude and output drive current conform to the specifications of the decoder unit 35. The row drive circuits 220 convert the preamplifier control signal into a more stable digital signal. The voltage level of the digital signal is defined by the specifications of the addressed pixel transistor 105. The drive capability of the row drive circuits 220 is matched to the load applied by the pixel control line 210, which connects the output of the row drive circuits 220 to the gate of the receiving pixel transistor 105.

[0039] Each pixel control signal is transmitted to a group of pixel circuits 100 via pixel control line 210. Pixel control line 210 connects the output of row drive circuit 220 to the input of the pixel circuits 100 in this group of pixel circuits 100. All pixel circuits 100 in the selected group of pixel circuits 100 synchronously receive the same pixel control signal. The selected group of pixel circuits 100 may include some pixel circuits 100 of a pixel row 11, all pixel circuits 100 of a pixel row 11, some or all pixel circuits 100 of more than one pixel row 11, or all pixel circuits 100 of the pixel array 10. In the following description, for simplicity, "pixel row" is often referred to as an example of "a group of pixel circuits".

[0040] The pixel control signal can control pixel reset, pixel exposure, temporary storage of photocurrent charge within the pixel, transfer of charge or analog voltage signal from the radiation-sensitive part to the voltage storage part, and output of analog pixel signal through data signal line 19.

[0041] At least some of the line drive circuits 220 drive a first digital voltage level to the pixel control line 210 during a first time period, have high output impedance during a second time period, and can drive a second digital voltage level complementary to the first digital voltage level at some point after the second time period. The line drive circuits 220 are combined with a source follower amplifier 230, which controls the voltage on the pixel control line 210 during the second time period. The controlled voltage depends on the signal applied to the gate of the source follower amplifier 230 through the source follower control line 239 during the second time period. The source follower amplifier 230 can be used to shape the slope of the pixel control signal according to various requirements.

[0042] The column signal processing unit 20 may include a column signal processing circuit for each data signal line 19 or each pair of data signal lines 19. The column signal processing circuit converts analog pixel signals into digital pixel values, preprocesses the digital pixel values, and outputs the digital pixel values ​​or preprocessed digital pixel values ​​to the read buffer memory 40. The read buffer memory 40 temporarily stores the digital pixel values.

[0043] The sensor controller 50 generates a drive timing signal and outputs the drive timing signal to the decoder unit 35 of the vertical scanning unit 30. The sensor controller 50 generates a column control signal for controlling the column signal processing unit 20, and can also generate a readout control signal that controls the digital pixel value to be read from the readout buffer memory 40 to the signal processing unit 80 and / or the digital interface.

[0044] Figure 2A and Figure 2B This relates to a minimum configuration for the combination of line drive circuit 220 and source follower amplifier 230, which is suitable for situations where the source follower amplifier 230 shapes the falling slope of the pixel control signal.

[0045] Figure 3A and Figure 3B This relates to a minimum configuration for the combination of line drive circuit 220 and source follower amplifier 230, which is suitable for situations where the source follower amplifier 230 shapes the rising slope of the pixel control signal.

[0046] In both cases, the image sensor 70 includes a pixel control line 210 connected to the pixel circuit 100 of pixel row 11. The row drive circuit 220 drives a first digital voltage level to the pixel control line 210 during a first time period t1 and has a high output impedance during a second time period t2. The source follower amplifier 230 controls the voltage on the pixel control line 210 according to a signal applied to the gate of the source follower amplifier 230 during the second time period t2. At some point after the end of the second time period t2, the row drive circuit 220 can drive a complementary second digital voltage level to the pixel control line 210. The row drive circuit 220 can drive the second digital voltage either immediately after the end of the second time period t2 or after a third time period following the second time period t2.

[0047] exist Figure 2A In this circuit, the horizontal drive circuit 220 includes a p-channel field-effect transistor (pFET) 226, the load path of which is connected between a high potential V1 and a pixel control line 210. The gate of the pFET 226 (horizontal drive pFET 226) of the horizontal drive circuit 220 receives a preamplifier control signal VC1. The source follower amplifier 230 includes a pFET 231, the load path of which is connected between the pixel control line 210 and a low potential V2. The gate of the pFET 231 (source follower pFET 231) of the source follower amplifier 230 receives a source follower control signal via a source follower control line 239. For the following example, the source follower control signal is a voltage ramp signal VRMP.

[0048] according to Figure 2B The preamplifier control signal VC1 turns on the row drive pFET 226 and connects the pixel control line 210 to a high potential V1 during a first time period t1. The voltage ramp signal VRMP is high, at which point the source follower pFET 231 is completely or almost completely turned off during the first time period t1, causing the pixel control line 210 to be charged to the high potential V1. Shortly before tx at the end of the first time period t1 and at the latest at tx, the preamplifier control signal VC1 turns off the row drive pFET 226 at least for a second time period t2. At tx, the voltage ramp signal VRMP begins to fall. The source follower pFET 231 discharges the pixel control line 210 at a rate given by the slew rate of the falling slope of the voltage ramp signal VRMP. The voltage of the pixel control line 210 reaches the threshold voltage Vth1 of the source follower pFET 231 at ty at the end of the second time period t2. The line drive circuit 220 can be configured to drive an effective low level to the pixel control line 210 for a period of time at some point after the end of the second time period t2.

[0049] The voltage level of the pixel control signal VOUT is equal to the high potential V1 during the first time period t1, and drops to the threshold voltage Vth1 of the source follower pFET 231 at a rate given by the slew rate of the voltage ramp signal VRMP during the second time period t2.

[0050] The descent rate of the voltage ramp signal VRMP is significantly lower than the slew rate of the preamplifier control signal. For example, the slew rate of the voltage ramp signal VRMP is at most 50%, 10%, or 5% of the slew rate of the preamplifier control signal VC1. For example, the rise / fall time of the preamplifier signal can be in the range of 100ns to 200ns, while the fall time of the voltage ramp signal VRMP can be in the range of approximately 300ns to 3000ns.

[0051] exist Figure 3A In this circuit, the horizontal drive circuit 220 includes an n-channel field-effect transistor (nFET) 221, the load path of which is connected between the pixel control line 210 and the low potential V2. The gate of the nFET 221 (horizontal drive nFET 221) of the horizontal drive circuit 220 receives a preamplifier control signal VC2. The source follower amplifier 230 includes an nFET 236, the load path of which is connected between the high potential V2 and the pixel control line 210. The gate of the nFET 236 (source follower nFET 236) of the source follower amplifier 230 receives a source follower control signal via a source follower control line 239. For the following example, the source follower control signal is a voltage ramp signal VRMP.

[0052] according to Figure 3BThe preamplifier control signal VC2 turns on the row drive nFET 221 and connects the pixel control line 210 to a low potential V2 during a first time period t1. The voltage ramp signal VRMP is low, at which point the source follower nFET 236 is completely or almost completely turned off during the first time period t1, causing the pixel control line 210 to discharge to the low potential V2. Shortly before tx at the end of the first time period t1 and at the latest at tx, the preamplifier control signal VC2 turns off the row drive nFET 221 at least for a second time period t2. At tx, the voltage ramp signal VRMP begins to rise. The source follower nFET 236 charges the pixel control line 210 at a rate given by the slew rate of the rising slope of the voltage ramp signal VRMP. The voltage of the pixel control line 210 reaches a voltage (V2-Vth2) at ty at the end of the second time period t2, which is the voltage given by subtracting the threshold voltage Vth2 of the source follower nFET 236 from the high potential V2. The line drive circuit 220 can be configured to drive a valid high level to the pixel control line 210 during the time period after ty, which is the end of the second time period t2.

[0053] The voltage level of the pixel control signal VOUT is equal to the low potential V2 during the first time period t1, and rises to V1–Vth2 at a rate given by the slew rate of the voltage ramp signal VRMP, where Vth2 is the threshold voltage of the source follower nFET 236.

[0054] The rise rate of the voltage ramp signal VRMP is significantly lower than the slew rate of the preamplifier control signal. For example, the slew rate of the voltage ramp signal VRMP's rise slope is at most 50%, 10%, or 5% of the slew rate of the preamplifier control signal VC2's fall slope. For example, the rise / fall time of the preamplifier signal can be in the range of 100ns to 200ns, while the rise time of the voltage ramp signal VRMP can be in the range of approximately 300ns to 3000ns.

[0055] Figure 4 A voltage ramp circuit 240 is shown, configured to output a voltage ramp signal VRMP to the gate of a source follower amplifier 230.

[0056] The voltage ramp signal VRMP can have a slowly falling slope or a slowly rising slope, wherein the slew rate of the slowly rising slope is at most 50%, 10%, or 5% of the slew rate of the fast slope. The slew rate can be constant or at least approximately constant for at least 90% of the voltage difference covered by the slope.

[0057] The voltage ramp circuit 240 includes a current source 243 configured to output a constant auxiliary current IAUX, and an integrator circuit 244 configured to obtain a voltage ramp signal VRMP by integrating the auxiliary current.

[0058] Current source 243 may include a configurable register for selecting one of several selectable constant auxiliary currents. Integrator input line 249 transmits the constant auxiliary current IAUX from current source 243 to integrator circuit 244. By integrating the constant auxiliary current, integrator circuit 244 inherently generates a linear voltage ramp signal VRMP with a constant slew rate.

[0059] Figure 5 An integrator circuit 244 is shown, comprising an inverting amplifier element 245 and a capacitor element 246, wherein the capacitor element 246 is located in the feedback path between the amplifier output and the amplifier input of the amplifier element 245.

[0060] A constant auxiliary current IAUX is provided to the input of integrator circuit 244 through integrator input line 249. Integrator circuit 244 outputs a voltage ramp signal VRMP on source follower control line 239.

[0061] Figure 6 The integrator circuit 244 shown generates a falling voltage ramp. An integrator circuit 244 that generates a rising ramp can be similarly formed.

[0062] The integrator circuit 244 can be disconnected from the current source 243 to perform self-zeroing of the amplifier element 245, initialize the voltage across the capacitor element 246, and initialize the output voltage of the amplifier element 245 during self-zeroing.

[0063] The inverting amplifier element 245 includes an amplifier nFET 247, the load path of which is connected between the source follower control line 239 and the reference potential VRL. An integrator control signal SINTEG controls a first switch 251 between the integrator input line 249 and the gate of the amplifier nFET 247. An integrator initialization signal SINIT controls a second switch 252 between the positive power supply potential VDD and the first electrode of the capacitor element 246. The second electrode of the capacitor element 246 is electrically connected to the gate of the amplifier nFET 247. An integrator turn-on signal SON controls a third switch 253 between the source follower control line 239 and the first electrode of the capacitor element 246. An integrator self-zeroing signal SAZ controls a fourth switch 254 between the source follower control line 239 and the gate of the amplifier nFET 247. A constant current source 248 of the integrator circuit 244 is electrically connected between the positive power supply potential VDD and the source follower control line 239.

[0064] Each of the first, second, third, and fourth switches 251, 252, 253, and 254 may include a field-effect transistor and / or a transmission gate. The constant current source 248 may be a field-effect transistor with a constant gate voltage. The source follower control line 239 may branch into multiple connection lines that transmit the voltage ramp signal VRMP to multiple source follower amplifiers 230-0, 230-1, ... assigned to different pixel rows.

[0065] Figure 7A Show Figure 6 The integrator circuit 244 operates until the first operating phase of tr1. In the first operating phase, the valid integrator initialization signal SINIT turns on the second switch 252, and the valid integrator self-zeroing signal SAZ turns on the fourth switch 254. The first switch 251 and the third switch 253 are turned off. The fourth switch 254 short-circuits the drain and gate of the amplifier nFET, causing the voltage ramp signal VRMP at the source follower control line 239 to adjust to the threshold voltage VGS of the amplifier nFET 247. The first electrode of the capacitor element 246 is pre-charged to the positive power supply potential VDD via the second switch 252. The voltage across the pre-charged capacitor element 246 is VDD - VGS.

[0066] Figure 7B The second operating phase between tr1 and tr2 is shown. In this second operating phase, the integrator on signal SON becomes active and turns on the third switch 253, connecting the constant current source 248 to the source follower control line 239 and the first electrode of the capacitor element 246. The integrator self-zero signal SAZ becomes inactive and turns off the fourth switch 254, disconnecting the gate and drain of the amplifier nFET 247. The first switch 251 remains off, and the second switch 252 remains on. The gate of the amplifier nFET 247 remains low. The constant current source 248 charges the source follower control line 239 to the positive supply potential VDD.

[0067] Figure 7C The third operating phase between tr2 and tr3 is shown. In this third operating phase, the integrator control signal SINTEG becomes active and turns on the first switch 251 to connect the integrator input line 249 to the gate of the amplifier nFET 247. The integrator initialization signal SINIT becomes inactive and turns off the second switch 252 to disconnect the first electrode of the capacitor element 246 from the positive power supply potential VDD. The third switch 253 remains on, and the fourth switch 254 remains off. The capacitor element 247 integrates the constant auxiliary current IAUX. The voltage at the gate of the amplifier nFET 247 rises linearly, and the potential of the source follower control line 239 falls accordingly.

[0068] Figure 8 Details of integrator circuit 244 and line drive circuit 220 are shown. First switch 251 includes a current mirror, where a constant auxiliary current IAUX is a replica of the constant DAC output current IDAC. An integrator control signal SINTEG is applied to a pFET in the tail path of the current mirror. A valid integrator control signal SINTEG turns on the tail current of the current mirror. An invalid integrator control signal SINTEG pulls the gate of the current mirror to a positive supply potential VDD, thus turning it off. Second switch 252 includes a pFET. An integrator initialization signal SINIT is applied to the gate of this pFET. Third switch 253 includes a transmission gate controlled by the inverted and non-inverted instances of the integrator turn-on signal SON. Fourth switch 254 includes an nFET. An integrator self-zero signal SAZ is applied to the gate of this nFET. The integrator control signal SINTEG also controls a fifth switch 255 between the drain and source follower control line 239 of amplifier nFET 247. The fifth switch 255 includes a transmission gate that connects the source follower control line 239 to the drain of the amplifier nFET 247 when the integrator control signal SINTEG is active. The fifth switch 255 also includes a pFET that connects the source follower control line 239 to the positive power supply potential VDD when the integrator control signal SINTEG is inactive. The row drive circuit 220 includes a CMOS inverter, wherein the load paths of pFET 226 and nFET 221 are electrically connected in series between the positive power supply potential and the reference potential. The pixel control line 210 is shown with a line capacitance C1.

[0069] exist Figure 9A and Figure 9B as well as Figure 10A and Figure 10B In each of the diagrams, the row drive circuit 220 drives the second digital voltage level to the pixel control line 210 during the period after the second time period t2.

[0070] The first digital voltage level and the second digital voltage level are complementary. If the first digital voltage level is high, the second digital voltage level is low. If the first digital voltage level is low, the second digital voltage level is high.

[0071] The row drive circuit 220 includes a pFET 226 and an nFET 221. The load paths of pFET 226 and nFET 221 are electrically connected in series between the positive power supply potential VDD and the reference potential VRL. A first digital preamplifier control signal VC1 is applied to the gate of pFET 226. A second digital preamplifier control signal VC2 is applied to the gate of nFET 221.

[0072] exist Figure 9AIn this configuration, the first digital voltage level is a digital high level. The source follower amplifier 230 includes a pFET 231, whose source / drain path is electrically connected between the pixel control line 210 and the reference potential VRL. During the second time period t2, the voltage on the pixel control line 210 decreases.

[0073] exist Figure 9B In the diagram, line 401 shows the voltage ramp signal VRMP applied to the gate of source amplifier 230, line 402 shows the pixel control signal VOUT on pixel control line 210, and line 403 shows the second preamplifier control signal VC2. The first preamplifier control signal VC1 turns on the row drive pFET 226 and connects pixel control line 210 to the positive power supply potential VDD during a first time period t1. The voltage ramp signal VRMP is high during the first time period t1, enabling the row drive pFET 226 to charge pixel control line 210 to the positive power supply potential VDD. At the beginning of the second time period t2, the first preamplifier control signal VC1 turns off the row drive pFET 226. The voltage ramp signal VRMP begins to fall. The source follower pFET 231 discharges pixel control line 210 at a rate given by the slew rate of the falling slope of the voltage ramp signal VRMP. At the end of the second time period t2, the pixel control signal VOUT on pixel control line 210 reaches the threshold voltage Vth1 of the source follower pFET 231. The voltage of pixel control line 210 remains almost constant during the third time period t3. At the end of the third time period t3, the second preamplifier control signal VC2 becomes active and turns on the row drive nFET 221. The row drive nFET 221 pulls the potential of pixel control line 210 down to the reference potential VRL during the fourth time period t4.

[0074] exist Figure 10A In the first digital voltage level, the source follower amplifier 230 includes an nFET 236, whose source / drain path is electrically connected between the pixel control line 210 and the positive power supply potential VDD. During the second time period t2, the voltage on the pixel control line 210 rises.

[0075] according to Figure 10BDuring the first time period t1, the second preamplifier control signal VC2 turns on the row drive nFET 221. The voltage ramp signal VRMP is low during the first time period t1, enabling the row drive nFET 221 to pull the pixel control line 210 down to the reference potential VRL during this period. At the beginning of the second time period t2, the second preamplifier control signal VC2 turns off the row drive nFET 221. The voltage ramp signal VRMP begins to rise. The source follower nFET 236 charges the pixel control line 210 at a rate given by the slew rate of the rising slope of the voltage ramp signal VRMP. At the end of the second time period t2, the potential of the pixel control line 210 reaches the positive supply potential VDD minus the threshold voltage Vth2 of the source follower nFET 236. The voltage of the pixel control line 210 remains almost constant during the third time period t3. At the end of the third time period t3, the first preamplifier control signal VC1 turns on the row drive pFET 226. The row driver pFET 226 pulls the potential of the pixel control line 210 to the positive power supply potential VDD during the fourth time period t4.

[0076] Figure 11 The image sensor 70 includes multiple pixel rows 11 and multiple pixel control lines 210, wherein each pixel control line 210 is connected to a pixel circuit 100 of a single pixel row 11. Multiple row drive circuits 220 drive a first digital voltage level to the pixel control lines 210 during a first time period and have high output impedance during a second time period. The decoder unit 35 simultaneously applies a digital preamplifier signal to the inputs of the multiple row drive circuits 220.

[0077] The image sensor 70 also includes a plurality of source follower amplifiers 230 configured to control the voltage on the pixel control line 210 based on a signal applied to the gate of the source follower amplifiers 230 during a second time period. A voltage ramp circuit 240 outputs a voltage ramp signal to the gate of the source follower amplifiers 230.

[0078] The first pixel control line 210-1 connects the first row drive circuit 220-1 to the reset transistor 107 of the pixel circuit 100. For the first pixel control line 210-1, the first digital voltage level is a digital high level. The first source follower amplifier 230-1 includes a pFET, whose load path is electrically connected between the first pixel control line 210-1 and the reference potential VRL. The voltage on the first pixel control line 210-1 decreases during a second time period.

[0079] The second pixel control line 210-2 connects the second row drive circuit 220-2 to the selection transistor 109 of the pixel circuit 100. For the second pixel control line 210-2, the first digital voltage level is digital low. The second source follower amplifier 230-2 includes an nFET, whose load path is electrically connected between the positive power supply potential VDD and the first pixel control line 210-1. The voltage on the second pixel control line 210-2 rises during a second time period.

[0080] The image sensor 70 also includes a first voltage ramp circuit 240-1, which outputs a first voltage ramp signal to the gate of a first source follower amplifier 231-1 during a second time period. A second voltage ramp circuit 240-2 outputs a second voltage ramp signal to the gate of a second source follower amplifier 231-2 during the second time period.

[0081] Figure 12 Show Figure 1 and Figure 11 Details of an example of a pixel circuit 100. Pixel circuit 100 includes a photoelectric conversion element 101. The photoelectric conversion element 101 photoelectrically converts incident electromagnetic radiation into electrical charge. The amount of charge generated in the photoelectric conversion element 101 corresponds to the intensity of the incident electromagnetic radiation. The photoelectric conversion element 101 may include or be composed of a photodiode that converts electromagnetic radiation incident on a detection surface into a detector current via the photoelectric effect. The electromagnetic radiation may include visible light, infrared radiation, and / or ultraviolet radiation. The amplitude of the detector current corresponds to the intensity of the incident electromagnetic radiation, wherein, within the intensity range of interest, the detector current increases approximately linearly with increasing intensity of the detected electromagnetic radiation.

[0082] Each pixel circuit 100 also includes a charge accumulation region 105 for temporarily storing charge according to the received light intensity; and a reset transistor 107 for initializing the charge in the charge accumulation region 105 in response to a valid reset signal RST applied to the gate of the reset transistor 107. Pixel control line 210 is electrically connected to the gate of the reset transistor 107 of pixel row 11.

[0083] The charge accumulation region 105 may include a floating diffusion region and / or capacitor electrodes. During the reset phase, the potential Vfd of the charge accumulation region 105 is a function of the pixel dark current representing noise. During the data phase, the potential Vfd is a function of the integrated current. The pixel control line 210 may be... Figure 11 One of the first pixel control lines 210-1.

[0084] A reset signal RST is provided to the gate of reset transistor 107 via a reset control line. The reset signal RST varies between a valid signal level (“valid reset signal”) and an invalid signal level (“invalid reset signal”). In response to the valid reset signal RST, reset transistor 107 connects charge accumulation region 105 to the positive power supply potential VDD. In the illustrated embodiment, the valid signal level is high.

[0085] The load path of the transfer transistor 102 is electrically connected between the cathode of the photoelectric conversion element 101 and the charge accumulation region 105. The transfer transistor 102 functions as a transfer element for transferring charge from the photoelectric conversion element 101 to the charge accumulation region 105 during an integration period. The charge accumulation region 105 serves as a temporary local charge storage area. A transfer signal TRG is provided to the gate (transfer gate) of the transfer transistor 102 via a transfer control line. The transfer signal TRG varies between an active signal level (“active transfer signal”) and an inactive signal level (“inactive transfer signal”). In response to the active transfer signal TRG, the transfer transistor 102 transfers electrons photoelectrically converted by the photoelectric conversion element 101 to the charge accumulation region 105. In the illustrated embodiment, the active signal level is high.

[0086] Amplifying transistor 108 is configured as a source follower, wherein the controlled load path is electrically connected between the positive power supply potential VDD and the data node 18. The data node 18 can form a signal interface between the radiation-sensitive portion and the voltage storage portion of a global shutter-type pixel circuit 100, or form a data signal line connecting pixel circuits in the same pixel column. A charge accumulation region 105 is connected to the gate of amplifying transistor 108. The potential at the gate of the pre-amplifying transistor 108 is equal to the potential Vfd of the charge accumulation region 105.

[0087] Each pixel circuit 100 includes a selection transistor 109 configured to transmit a pixel voltage signal in response to a valid selection signal SEL applied to the gate of the selection transistor 109, and wherein a pixel control line 210 is electrically connected to the gate of the selection transistor 109 of the pixel row 11.

[0088] The load path of amplifying transistor 108 and the load path of select transistor 109 are electrically connected in series between the positive power supply potential VDD and data node 18. A row select signal SEL is provided to the gate of select transistor 109 via a select control line. The select signal SEL varies between a valid signal level (“valid select signal”) and an invalid signal level (“invalid select signal”). In the illustrated embodiment, select transistor 109 is an nFET, and the valid signal level is high.

[0089] Figure 13A and Figure 13BEach of the following diagrams illustrates a row drive circuit 220 that outputs a reset signal RST on a pixel control line 210 electrically connected to a reset transistor in a pixel row 11 having 1280 pixel circuits 100. The pixel circuits 100 at the left proximal end of the pixel row 11 are close to the output of the row drive circuit 220. The pixel circuits 100 at the right distal end of the pixel row 11 are farther from the output of the row drive circuit 220. Without further wiring, the row drive circuit 220 outputs a reset signal RST with a steep, rapid slope.

[0090] exist Figure 13A As the distance to the output of the row drive circuit 220 increases, the inherent delay on the pixel control line 210 increasingly distorts the reset signal RST along the pixel control line 210. The rapid fall time at the near end suffers relatively high dispersion before the reset signal RST reaches the far end. The charge injected into the charge accumulation structure 105 when the reset transistor 107 is turned off varies depending on the pixel row and may cause artifacts characterized by artificial brightness gradients along the pixel row direction.

[0091] exist Figure 13B In this configuration, source follower amplifier 230 is connected between pixel control line 210 and reference potential VRL. Voltage ramp signal VRMP controls source follower amplifier 230. The reset signal RST has a flatter falling slope and a slower slew rate. The slow fall time near the end has relatively low dispersion before the reset signal RST reaches the far end. The longer the fall time relative to the time constant of pixel control line 210, the more uniform the falling slope is across the length of pixel control line 210. Gradient artifacts can be significantly reduced.

[0092] exist Figure 14 In the above diagram, line 501 shows... Figure 13A The diagram shows the falling slope of the reset signal RST for row driver configuration at the near end, and line 502 shows the falling slope of the reset signal RST at the far end. The timing difference of the threshold voltage can be tens of nanoseconds.

[0093] exist Figure 14 In the figure below, line 511 shows the response of the potential Vfd of the charge accumulation structure 105 to the reset signal RST at the proximal end, and line 512 shows the response of the potential Vfd of the charge accumulation structure 105 to the reset signal RST at the distal end. The potential Vfd at the distal end can be tens of millivolts higher than that at the proximal end.

[0094] exist Figure 15 In the above diagram, line 521 shows... Figure 13B The diagram shows the falling slope of the reset signal RST for row driver configuration at the near end, and line 522 shows the falling slope of the reset signal RST at the far end. The timing difference is relatively small.

[0095] exist Figure 15 In the figure below, line 531 shows the response of the potential Vfd of the charge accumulation structure 105 to the reset signal RST at the near end, and line 532 shows the response of the potential Vfd of the charge accumulation structure 105 to the reset signal RST at the far end. The potential difference between the far and near ends is about an order of magnitude lower than that without the source follower amplifier 230.

[0096] Figure 16 A pixel circuit 100 for an image sensor used for a global shutter is shown. Each pixel circuit 100 includes: a radiation receiver 310, 320 configured to supply a pixel voltage signal, the voltage level of which is a function of the incident radiation intensity; a voltage storage unit 330 configured to receive and temporarily store the pixel voltage signal; and at least one selection transistor 109 for transferring the pixel voltage signal from the radiation receiver 310, 320 to the voltage storage unit 330 in response to an effective global shutter signal SEL applied to the gate of the selection transistor 109.

[0097] The pixel circuit 100 shown in the figure includes two radiation receivers 310 and 320. Each radiation receiver 310 and 320 is a four-transistor pixel used for analog readout, as referenced above. Figure 12 The effective first global shutter signal SEL1 turns on the selection transistor 109 in the first radiation receiver 310, and the first radiation receiver 310 outputs the analog pixel voltage signals of the data phase and reset phase to the voltage storage unit 330. The effective second global shutter signal SEL2 turns on the selection transistor 109 in the second radiation receiver 320, and the second radiation receiver 320 outputs the analog pixel voltages of the data phase and reset phase to the voltage storage unit 330. The voltage storage unit 330 continuously stores the analog pixel voltages on a capacitor.

[0098] Radiation receiving units 310 and 320 can be formed on the first chip 910. Voltage storage unit 330 can be formed on the second chip 920. The first chip 910 and the second chip 920 are bonded together. Pixel voltage signals are transmitted from the first chip 910 to the second chip 920 via direct bonding connection 915.

[0099] Figure 17 The following figure shows the rising slope of different selection signals SEL with a valid high level. The selection signal SEL can be... Figure 16 Each of the first and second global shutter signals SEL1 and SEL2. Line 911 shows the selection signal with the fastest rising slope. Lines 912, 913, and 914 show selection signals with gradually decreasing rising slopes.

[0100] exist Figure 17In the figure above, line 921 shows the surge current of the slew rate selection signal SEL indicated by line 911, line 922 shows the surge current of the slew rate selection signal SEL indicated by line 912, line 923 shows the surge current of the slew rate selection signal SEL indicated by line 913, and line 924 shows the surge current of the slew rate selection signal SEL indicated by line 914.

[0101] If the selected signal is the global shutter signal, a large number of pixel circuits are triggered simultaneously for pixel readout, and the peak inrush current can be in the range of 0.5A. High inrush current can cause a very high instantaneous power supply voltage drop and may overload the external power supply. Both of these effects negatively impact the performance of the image sensor. A source follower amplifier can precisely control the turn-on slope, thereby optimizing the inrush current compared to the delay that may be associated with a slower signal slope.

[0102] This disclosure relates to a solid-state imaging device, which includes, as follows: Figure 1 or Figure 11 The image sensor 70 is shown. The image sensor includes a pixel array 10 having a plurality of pixel rows 11, wherein each pixel row 11 includes a plurality of pixel circuits 100. The image sensor includes first pixel control lines 210-1, wherein each first pixel control line 210-1 is connected to the pixel circuits 100 of a single pixel row 11. The image sensor includes first row drive circuits 220-1, wherein each first row drive circuit 220-1 is configured to output a first digital voltage level to a single first pixel control line 210-1 during a first time period and to have a high output impedance during a second time period. The image sensor includes first source follower amplifiers 230-1, wherein each first source follower amplifier 230-1 is configured to control the voltage on one of the first pixel control lines 210-1 according to a signal applied to the gate of the first source follower amplifier 230-1 during a second time period.

[0103] The first voltage ramp circuit 240-1 can be configured to output a voltage ramp signal to the gate of the first source follower amplifier 231 during a second time period. The image sensor may include second pixel control lines 210-2, each second pixel control line 210-2 connected to the pixel circuit 100 of a single pixel row 11. The image sensor may include second row drive circuits 220-2, each second row drive circuit 220-2 configured to output a second digital voltage level to a single second pixel control line 210-2 during a fifth time period and have a high output impedance during a sixth time period. The image sensor may include second source follower amplifiers 230-2, each second source follower amplifier 230-2 configured to control the voltage on one of the second pixel control lines 210-2 according to a signal applied to the gate of the second source follower amplifier 230-2 during the sixth time period. The second voltage ramp circuit 240-2 can be configured to output a second voltage ramp signal to the gate of the second source follower amplifier 230-2 during the sixth time period.

[0104] Each pixel circuit 100 may include a charge accumulation region 105 for temporarily storing charge according to the received light intensity, and a reset transistor 107 for initializing the charge in the charge accumulation region 105 in response to a reset signal RST applied to the gate of a reset transistor 107. A first pixel control line 210-1 is electrically connected to the gate of the reset transistor 107.

[0105] Alternatively or additionally, each pixel circuit 100 may include: a radiation receiver 310, 320 configured to provide a pixel voltage signal whose voltage level is a function of incident radiation intensity; a voltage storage unit 330 configured to receive and temporarily store the pixel voltage signal; and a selection transistor 109 for transferring the pixel voltage signal from the radiation receiver 310, 320 to the voltage storage unit 330. Each second pixel control line 210-2 is electrically connected to the gate of the selection transistor 109.

[0106] Figure 18 The following diagram illustrates an example: Figure 1 and Figure 11 Image sensor 70 of A is formed from a stacked CMOS image sensor (CIS) with a dual-layer structure, having a first chip 910 (radiation receiving chip) and a second chip 920 (processing chip). The radiation receiving chip includes at least a photoelectric conversion element. For example, the radiation receiving chip may include only the photoelectric conversion element, only the conversion section of the pixel circuit, or at least some elements including the conversion section and the PWM section of the pixel circuit. An image sensor assembly as a sensor is formed by bonding the radiation receiving chip and the processing chip, while simultaneously making contact pads on the radiation receiving chip electrically contact the corresponding contact pads on the processing chip.

[0107] Figure 19 This is a block diagram illustrating an example configuration of a vehicle control system that can be applied as an example of the technology according to embodiments of this disclosure.

[0108] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 19 In the illustrated example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network interface 12053 are shown as functional configurations of the integrated control unit 12050.

[0109] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device for the following devices: a drive force generating device (such as an internal combustion engine, drive motor, etc.) for generating vehicle driving force, a drive force transmission mechanism for transmitting driving force to the wheels, a steering mechanism for adjusting the vehicle's steering angle, and a braking device for generating vehicle braking force.

[0110] The body system control unit 12020 controls the operation of various devices provided to the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, reversing lights, brake lights, turn signals, fog lights, etc. In this case, radio waves emitted from a moving device that serves as a key substitute, or signals from various switches, can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.

[0111] The exterior information detection unit 12030 detects information outside the vehicle, including the vehicle control system 12000. The exterior information detection unit 12030 can be connected to the imaging unit 12031. The exterior information detection unit 12030 causes the imaging unit 12031 to image the exterior of the vehicle and receives the image. Based on the received image, the exterior information detection unit 12030 can perform processing such as detecting objects like people, vehicles, obstacles, signs, and characters on the road surface, or detecting the distance to objects.

[0112] The imaging unit 12031 may be or may include an image sensor assembly according to embodiments of the present disclosure. The light received by the imaging unit 12031 may include visible light and / or invisible light such as infrared light.

[0113] The in-vehicle information detection unit 12040 detects information inside the vehicle and may be, or may include, an image sensor assembly according to embodiments of the present disclosure. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that includes a solid-state imaging device and focuses on the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's level of concentration, or it can determine whether the driver is dozing off.

[0114] The microcomputer 12051 can calculate control target values ​​for the drive force generating device, steering mechanism, or braking device based on information about the vehicle's interior or exterior obtained by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control designed to realize advanced driver assistance system (ADAS) functions, including collision avoidance or impact mitigation, following distance-based driving, speed maintenance, collision warning, lane departure warning, etc.

[0115] Furthermore, the microcomputer 12051 can perform cooperative control aimed at achieving autonomous driving by controlling the drive force generating device, steering mechanism, braking device, etc., based on information about the exterior or interior of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040. This autonomous driving enables the vehicle to drive autonomously without relying on the driver's operation.

[0116] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the exterior of the vehicle obtained by the exterior information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control aimed at preventing glare by controlling the headlights, such as switching the headlights from high beam to low beam based on the position of the preceding or oncoming vehicle detected by the exterior information detection unit 12030.

[0117] The audio-visual / output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of providing visual or auditory notification information to the occupants of the vehicle or to the exterior of the vehicle. Figure 19In the example, audio speaker 12061, display unit 12062, and dashboard 12063 are shown as output devices. Display unit 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0118] Figure 20 This is a diagram depicting an example of the mounting position of the imaging unit 12031, wherein the imaging unit 12031 may include imaging units 12101, 12102, 12103, 12104 and 12105.

[0119] Imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, arranged on the front nose, side mirrors, rear bumper, and rear door of vehicle 12100, as well as on the upper part of the interior windshield. Imaging unit 12101 at the front nose and imaging unit 12105 on the upper part of the interior windshield primarily acquire images of the front of vehicle 12100. Imaging units 12102 and 12103 at the side mirrors primarily acquire images of the sides of vehicle 12100. Imaging unit 12104 at the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. Imaging unit 12105 on the upper part of the interior windshield is mainly used to detect vehicles ahead, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0120] in addition, Figure 20 An example depicting the imaging range of imaging units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of imaging unit 12101 located at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 located at the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 located at the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 to 12104, a bird's-eye view of the vehicle 12100 viewed from above is obtained.

[0121] At least one of the imaging units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements (the imaging elements have pixels for phase difference detection), or may include a ToF module including an image sensor according to an embodiment of the present disclosure.

[0122] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of that distance (relative speed relative to the vehicle 12100) based on distance information obtained from the imaging units 12101 to 12104. This allows it to extract the nearest three-dimensional object, specifically existing on the vehicle 12100's travel path and traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in approximately the same direction as the vehicle 12100, as the preceding vehicle. Furthermore, the microcomputer 12051 can pre-set a following distance to be maintained in front of the preceding vehicle and execute automatic braking control (including stop-and-go control), automatic acceleration control (including start-and-go control), etc. Thus, cooperative control aimed at achieving autonomous driving, which allows the vehicle to drive autonomously without relying on the operation of a driver or other personnel, can be performed.

[0123] For example, the microcomputer 12051 can classify three-dimensional object data about three-dimensional objects into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from imaging units 12101 to 12104. It then extracts the classified three-dimensional object data and uses the extracted data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that the driver of vehicle 12100 cannot visually recognize. Then, the microcomputer 12051 determines the collision risk representing the probability of collision with each obstacle. If the collision risk is equal to or higher than a set value, and therefore a collision is possible, the microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and executes forced deceleration or evasive steering via driving system control unit 12010. Thus, the microcomputer 12051 can assist driving to avoid collisions.

[0124] At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. Such pedestrian identification is performed, for example, by extracting feature points from the images captured by the imaging units 12101 to 12104 (which use infrared cameras), and performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and thereby identifies the pedestrian, the audio-visual output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed superimposed on the identified pedestrian. The audio-visual output unit 12052 can also control the display unit 12062 so that an icon or the like representing a pedestrian is displayed at a desired position.

[0125] The foregoing describes examples of vehicle control systems to which the technologies involved in the embodiments of this disclosure are applicable. By applying image sensors according to the various embodiments of this disclosure, better image quality can be achieved.

[0126] Furthermore, the implementation of this technology is not limited to the above-described implementation. Various modifications can be made within the scope of this technology without departing from its essential points.

[0127] The image sensor according to this disclosure can be any device for analyzing and / or processing radiation such as visible light, infrared light, ultraviolet light, and X-rays. For example, the image sensor according to various embodiments can be any electronic device in the fields of transportation, home appliances, healthcare, security, beauty, sports, agriculture, image reproduction, etc.

[0128] Specifically, in the field of image reproduction, the image sensor according to each embodiment can be a device for capturing images for viewing, such as a digital camera, a smartphone, or a mobile phone device with camera functionality. In the transportation field, for example, a solid-state imaging device including the image sensor according to each embodiment can be integrated into an onboard sensor for safe driving (such as automatic stop, driver status recognition, etc.) that captures images of the front, rear, surroundings, and interior of the vehicle; integrated into a monitoring camera that monitors driving vehicles and roads; or integrated into a ranging sensor that measures distances between vehicles.

[0129] In the field of home appliances, the image sensor according to various embodiments can be integrated into any type of sensor that can be used in devices provided with home appliances such as television receivers, refrigerators, and air conditioners to capture user gestures and perform device operations based on these gestures. Therefore, the image sensor according to various embodiments can be integrated into home appliances such as TV receivers, refrigerators, and air conditioners, and / or devices that control these home appliances. Furthermore, in the field of healthcare, the image sensor according to various embodiments can be integrated into any type of sensor (e.g., solid-state imaging device) provided for healthcare, such as endoscopes or devices that perform angiography by receiving infrared light.

[0130] In the security field, image sensors according to various embodiments can be integrated into devices provided for security purposes, such as surveillance cameras for theft prevention or cameras for personnel authentication. Furthermore, in the beauty field, image sensors according to various embodiments can be used in devices provided for beauty purposes, such as skin measurement instruments that capture skin texture or microscopes that capture probes. In the sports field, image sensors according to various embodiments can be integrated into devices provided for sports purposes, such as action cameras or wearable cameras. Furthermore, in the agricultural field, the image sensor can be used in devices provided for agriculture, such as cameras that monitor field and crop conditions.

[0131] The technology can also adopt the following structure: [1] an image sensor, including: a pixel control line (210) connected to a pixel circuit (100) of a pixel row (11); a row driving circuit (220) configured to drive a first digital voltage level to the pixel control line (210) in a first time period and have a high output impedance in a second time period; and a source follower amplifier (230) configured to control the voltage on the pixel control line (210) according to a signal applied to the gate of the source follower amplifier (230) in the second time period.

[0132] [2] The image sensor according to [1] also includes: a voltage ramp circuit (240) configured to output a voltage ramp signal to the gate of the source follower amplifier (230).

[0133] [3] According to the image sensor of [2], the voltage ramp circuit (240) includes: a current source (243) configured to output a constant auxiliary current; and an integrator circuit (244) configured to obtain a voltage ramp signal by integrating the auxiliary current.

[0134] [4] According to the image sensor of [3], the integrator circuit (244) includes an inverting amplifier element (245) and a capacitor element (246) in the feedback path between the amplifier output and the amplifier input of the amplifier element (245).

[0135] [5] According to the image sensor of [4], the integrator circuit (244) can be disconnected from the current source (243) to perform self-zeroing of the amplifier element (245), initialize the voltage across the capacitor element (246), and initialize the output voltage of the amplifier element (245) during self-zeroing.

[0136] [6] According to any one of [1] to [5], the image sensor wherein the line drive circuit (220) is further configured to drive the second digital voltage level to the pixel control line (210) during a time period after the second time period.

[0137] [7] An image sensor according to any one of [1] to [6], wherein the first digital voltage level is a digital high level, the source follower amplifier (230) includes a p-channel field-effect transistor (231), the source / drain path of the p-channel field-effect transistor (231) is electrically connected between the pixel control line (210) and the reference potential, and the voltage on the pixel control line (210) decreases during the second time period.

[0138] [8] An image sensor according to any one of [1] to [7], wherein the first digital voltage level is a digital low level, the source follower amplifier (230) includes an n-channel field-effect transistor (236), the source / drain path of the n-channel field-effect transistor (236) is electrically connected between the pixel control line (210) and the positive power supply potential, and wherein the voltage on the pixel control line (210) rises during a second time period.

[0139] [9] The image sensor according to any one of [1] to [8] further includes: a plurality of pixel rows (11); a plurality of pixel control lines (210), wherein each pixel control line (210) is connected to a pixel circuit (100) of a single pixel row; a plurality of row driving circuits (220) configured to drive a first digital voltage level to the pixel control lines (210) in a first time period and have a high output impedance in a second time period; and a decoder unit (35) configured to simultaneously apply a digital preamplifier control signal to the input of the row driving circuits (220).

[0140]

[10] The image sensor according to [9] includes: a plurality of source follower amplifiers (230) configured to control the voltage on the pixel control line (210) according to a signal applied to the gate of the source follower amplifier (230) in a second time period; and a voltage ramp circuit (240) configured to output a voltage ramp signal to the gate of the source follower amplifier (230).

[0141]

[11] The image sensor according to

[10] further includes: a first voltage ramp circuit (240-1) configured to output a first voltage ramp signal to the gate of a first source follower amplifier (231-1) during a second time period; and a second voltage ramp circuit (240-2) configured to output a second voltage ramp signal to the gate of a second source follower amplifier (231-2) during a second time period.

[0142]

[12] An image sensor according to any one of [1] to

[11] , wherein each pixel circuit (100) includes: a charge accumulation region (105) for temporarily storing charge according to the intensity of received light; and a reset transistor (107) for initializing the charge in the charge accumulation region (105) in response to a valid reset signal applied to the gate of the reset transistor (107), and wherein a pixel control line (210) is electrically connected to the gate of the reset transistor (107) of the pixel row (11).

[0143]

[13] An image sensor according to any one of [1] to

[12] , wherein each pixel circuit (100) includes: a selection transistor (109) configured to transmit a pixel voltage signal in response to an effective selection signal applied to the gate of the selection transistor (109), and wherein a pixel control line (210) is electrically connected to the gate of the selection transistor (109) of the pixel row (11).

[0144]

[14] An image sensor according to any one of [1] to

[13] , wherein each pixel circuit (100) includes: a radiation receiving unit (310, 320) configured to supply a pixel voltage signal whose voltage level is a function of incident radiation intensity; a voltage storage unit (330) configured to receive and temporarily store the pixel voltage signal; and at least one selection transistor (109) for transferring the pixel voltage signal from the radiation receiving unit (310, 320) to the voltage storage unit (330) in response to a global shutter signal applied to the gate of the selection transistor (109).

[0145]

[15] A solid-state imaging device includes: a pixel array (10) including a plurality of pixel rows (11), each pixel row (11) including a plurality of pixel circuits (100); a first pixel control line (210-1), wherein each first pixel control line (210-1) is connected to the pixel circuit (100) of a single pixel row (11); a first row driving circuit (220-1), wherein each first row driving circuit (220-1) is configured to output a first digital voltage level to a single first pixel control line (210-1) in a first time period and have a high output impedance in a second time period; and a first source follower amplifier (230-1), wherein each first source follower amplifier (230-1) is configured to control the voltage on a first pixel control line (210-1) according to a signal applied to the gate of the first source follower amplifier (230-1) in a second time period.

Claims

1. An image sensor, comprising: Pixel control lines connect to the pixel circuitry of the pixel row; The row driving circuit is configured to drive a first digital voltage level to the pixel control line in a first time period and have a high output impedance in a second time period. as well as A source follower amplifier is configured to control the voltage on the pixel control line based on a signal applied to the gate of the source follower amplifier during a second time period.

2. The image sensor according to claim 1, further comprising: A voltage ramp circuit is configured to output a voltage ramp signal to the gate of the source follower amplifier.

3. The image sensor according to claim 2, in, The voltage ramp circuit includes: a current source configured to output a constant auxiliary current; and an integrator circuit configured to obtain the voltage ramp signal by integrating the auxiliary current.

4. The image sensor according to claim 3, in, The integrator circuit includes an inverting amplifier element and a capacitor element, with the capacitor element located in the feedback path between the amplifier output terminal and the amplifier input terminal of the amplifier element.

5. The image sensor according to claim 4, in, The integrator circuit can be disconnected from the current source to perform self-zeroing of the amplifier element, initialize the voltage across the capacitor element, and initialize the output voltage of the amplifier element during self-zeroing.

6. The image sensor according to claim 1, in, The row driving circuit is also configured to drive a second digital voltage level to the pixel control line during a period of time following the second time period.

7. The image sensor according to claim 1, in, The first digital voltage level is a digital high level, the source follower amplifier includes a p-channel field-effect transistor, the source / drain path of the p-channel field-effect transistor is electrically connected between the pixel control line and the reference potential, and the voltage on the pixel control line decreases during the second time period.

8. The image sensor according to claim 1, in, The first digital voltage level is a digital low level, the source follower amplifier includes an n-channel field-effect transistor, the source / drain path of the n-channel field-effect transistor is electrically connected between the pixel control line and the positive power supply potential, and the voltage on the pixel control line rises during the second time period.

9. The image sensor according to claim 1, further comprising: Multiple pixel rows; The plurality of said pixel control lines, wherein each of said pixel control lines is connected to the pixel circuitry of a single pixel row; Multiple of the aforementioned row driving circuits are configured to drive the first digital voltage level to the pixel control line during the first time period and have high output impedance during the second time period; as well as The decoder unit is configured to simultaneously apply digital preamplifier control signals to the input of the line drive circuit.

10. The image sensor according to claim 9, comprising: The plurality of source follower amplifiers are configured to control the voltage on the pixel control line according to a signal applied to the gate of the source follower amplifier during the second time period; as well as A voltage ramp circuit is configured to output a voltage ramp signal to the gate of the source follower amplifier.

11. The image sensor of claim 10, further comprising: The first voltage ramp circuit is configured to output a first voltage ramp signal to the gate of the first source follower amplifier during the second time period. And a second voltage ramp circuit, configured to output a second voltage ramp signal to the gate of a second source follower amplifier during the second time period.

12. The image sensor according to claim 1, in, Each pixel circuit includes: a charge accumulation region for temporarily storing charge according to the received light intensity; and a reset transistor for initializing the charge in the charge accumulation region in response to a valid reset signal applied to the gate of the reset transistor, wherein the pixel control line is electrically connected to the gate of the reset transistor of the pixel row.

13. The image sensor according to claim 1, in, Each pixel circuit includes: a selection transistor configured to transmit a pixel voltage signal in response to a valid selection signal applied to the gate of the selection transistor, wherein the pixel control line is electrically connected to the gate of the selection transistor of the pixel row.

14. The image sensor according to claim 1, in, Each pixel circuit includes: a radiation receiver configured to supply a pixel voltage signal, the voltage level of which is a function of incident radiation intensity; a voltage storage unit configured to receive and temporarily store the pixel voltage signal; and at least one selection transistor configured to transfer the pixel voltage signal from the radiation receiver to the voltage storage unit in response to a global shutter signal applied to the gate of the selection transistor.

15. A solid-state imaging device, comprising: A pixel array, comprising multiple pixel rows, with each pixel row comprising multiple pixel circuits; First pixel control lines, wherein each first pixel control line is connected to the pixel circuitry of a single pixel row; First row driving circuits, wherein each first row driving circuit is configured to output a first digital voltage level to a single first pixel control line in a first time period and have a high output impedance in a second time period; as well as First source follower amplifiers, wherein each first source follower amplifier is configured to control a voltage on a first pixel control line during the second time period based on a signal applied to the gate of the first source follower amplifier.

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