Semiconductor device, circuit, and electronic device

Abstract

A semiconductor device according to one embodiment includes a channel layer including a two-dimensional electron gas region, a barrier layer provided on the channel layer, a gate electrode provided on the barrier layer, and a contact layer provided on the channel layer. The contact layer includes an inclined surface that is inclined downward toward a side of the gate electrode.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, circuits, and electronic devices. Background Technology

[0002] As semiconductor devices, high electron mobility transistors (HEMTs) using nitride semiconductors are known, for example. HEMTs possess characteristics such as high breakdown voltage, high heat resistance, high saturation electron velocity, and high channel electron concentration, and are expected to be used in small and high-performance power devices as well as high-frequency devices.

[0003] Typically, HEMTs include a barrier layer on the channel layer. Due to the potential barrier in the barrier layer, it is difficult to form a good ohmic contact, and the contact resistance tends to be high. As one method to reduce contact resistance, there is a technique of regrowing contact layers in the source and drain regions on the channel layer (e.g., see PTL 1). By connecting the channel layer and the source electrode with the contact layer and similarly connecting the channel layer and the drain electrode with the contact layer, the contact resistance can be reduced.

[0004] Reference List

[0005] Patent documents

[0006] PTL 1: JP 2017-085062 A Summary of the Invention

[0007] Technical issues

[0008] When HEMTs are applied to high-frequency applications, it is desirable to use HEMTs with low on-resistance. To achieve low on-resistance HEMTs, in addition to selecting the barrier layer material and reducing contact resistance, reducing the source-drain distance is also effective. However, when the source-drain distance is reduced, the gate-source capacitance and gate-drain capacitance (capacitance between electrodes) increase, and the breakdown voltage and reliability decrease due to the increased electric field strength at each end of the gate and drain regions. Furthermore, the unevenness caused by the contact layer formed through regeneration typically impairs the photoresist flatness during subsequent steps of forming the source / drain electrodes and gate, thus increasing the difficulty of microfabrication.

[0009] Therefore, this disclosure provides semiconductor devices, circuits, and electronic devices that can reduce capacitance between electrodes, improve voltage withstand and reliability, and enhance microfabrication performance.

[0010] Solution to the problem

[0011] A semiconductor device according to an embodiment includes: a channel layer including a two-dimensional electron gas region; a barrier layer disposed on the channel layer; a gate electrode disposed on the barrier layer; and a contact layer disposed on the channel layer. The contact layer includes a sloped surface inclined downward toward the gate electrode side.

[0012] The circuit according to an embodiment includes a semiconductor device. The semiconductor device includes: a channel layer including a two-dimensional electron gas region; a barrier layer disposed on the channel layer; a gate electrode disposed on the barrier layer; and a contact layer disposed on the channel layer. The contact layer includes a sloped surface inclined downward toward the gate electrode side.

[0013] An electronic device according to an embodiment includes a circuit comprising a semiconductor device. The semiconductor device includes: a channel layer including a two-dimensional electron gas region; a barrier layer disposed on the channel layer; a gate electrode disposed on the barrier layer; and a contact layer disposed on the channel layer. The contact layer includes a sloped surface inclined downward toward the gate electrode side. Attached Figure Description

[0014] Figure 1 This is a cross-sectional view illustrating an example configuration of a semiconductor device according to an embodiment.

[0015] Figure 2 It is a diagram used to describe the gradient of the inclined surface of the contact layer according to an embodiment.

[0016] Figure 3 This is a diagram used to illustrate an example of the effects of a semiconductor device according to an embodiment.

[0017] Figure 4 This is a diagram illustrating examples of contact layer configurations in each case according to the embodiments.

[0018] Figure 5 This is a diagram used to describe the contact resistance in each case according to the embodiments.

[0019] Figure 6 This is a cross-sectional view showing an example configuration of a semiconductor device according to a variation of embodiment 1.

[0020] Figure 7 This is a cross-sectional view showing an example configuration of a semiconductor device according to a variation 2 of the embodiment.

[0021] Figure 8 This is a cross-sectional view showing an example configuration of a semiconductor device according to a variation 3 of the embodiment.

[0022] Figure 9 This is a cross-sectional view showing an example configuration of a semiconductor device according to a variation 4 of the embodiment.

[0023] Figure 10This is a perspective view showing a configuration example of a wireless communication device according to Application Example 1.

[0024] Figure 11 This is a block diagram illustrating a configuration example of a wireless communication device according to Application Example 2. Detailed Implementation

[0025] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Embodiments include examples, variations, etc. It should be noted that the technology related to this disclosure is not limited to the embodiments. Furthermore, in the embodiments, redundant descriptions are substantially omitted by assigning the same reference numerals to substantially the same components.

[0026] This disclosure will be described in the order listed below.

[0027] 1. Example

[0028] 1-1. Example of a semiconductor device configuration

[0029] 1-2. Example of gradient on the inclined surface of the contact layer

[0030] 1-3. Examples of the effects of semiconductor devices

[0031] 1-3-1. Examples of effects 1 to 3

[0032] 1-3-2. Example of effect 4

[0033] 1-4. Variations of semiconductor devices

[0034] 1-4-1. Variation Example 1

[0035] 1-4-2. Variation Example 2

[0036] 1-4-3. Variation Example 3

[0037] 1-4-4. Variation Example 4

[0038] 1-5. Actions and Effects

[0039] 2. Other embodiments

[0040] 3. Application Examples

[0041] 4. Appendix

[0042] 1. Example

[0043] 1-1. Example of a semiconductor device configuration

[0044] Reference Figure 1 A configuration example of semiconductor device 1A according to this embodiment is described. Figure 1 This is a cross-sectional view showing an example configuration of the semiconductor device 1A according to this embodiment.

[0045] like Figure 1 As shown, the semiconductor device 1A according to this embodiment includes a substrate 11, a buffer layer 12, a back barrier layer 15A, a channel layer 13, a spacer layer 14, a barrier layer 15, a cap layer 16, two contact layers 17, a source electrode 18, a drain electrode 19, and a gate electrode 20.

[0046] A buffer layer 12 is disposed on the substrate 11. A back barrier layer 15A is disposed on the buffer layer 12. A channel layer 13 is disposed on the back barrier layer 15A. A spacer layer 14 is disposed on the channel layer 13. A barrier layer 15 is disposed on the spacer layer 14. A cap layer 16 is disposed on the barrier layer 15. That is, the buffer layer 12, the back barrier layer 15A, the channel layer 13, the spacer layer 14, the barrier layer 15, and the cap layer 16 are sequentially stacked on the substrate 11.

[0047] Each contact layer 17 is provided on the channel layer 13. One of the contact layers 17 is formed in the source region and another is formed in the drain region. For example, each of the contact layers 17 is formed from the upper surface of the channel layer 13 by crystal growth. Each contact layer 17 is in contact with the upper part (protrusion) of the channel layer 13 and the side surface of each of the spacer layer 14, the barrier layer 15 and the cap layer 16.

[0048] A source electrode 18 is disposed on a portion of the cap layer 16 and the contact layer 17. Similarly, a drain electrode 19 is also disposed on a portion of the cap layer 16 and the contact layer 17. A gate electrode 20 is disposed on the cap layer 16. The gate electrode 20 is formed between the source electrode 18 and the drain electrode 19.

[0049] The phrase "layers, electrodes, etc. are placed on an object" includes the following situations: when layers, electrodes, etc. are directly placed on the object and in contact with the object; when layers, electrodes, etc. are placed on the object through another layer or not in contact with the object, etc.

[0050] In the following text, each of the above-described elements constituting the semiconductor device 1A according to this embodiment will be described in detail, starting from substrate 11.

[0051] substrate

[0052] The substrate 11 is a support for the various components (layers, electrodes, etc.) of the semiconductor device 1A. The substrate 11 is made of, for example, a compound semiconductor material. As an example, the substrate 11 is formed of single-crystal GaN (a semi-insulating III-V compound semiconductor material). Furthermore, by controlling the lattice constant using the buffer layer 12, the substrate 11 can be made of a substrate having a different lattice constant than the channel layer 13, such as a SiC substrate, a sapphire substrate, a Si substrate, etc.

[0053] Buffer layer

[0054] The buffer layer 12 is formed from, for example, a compound semiconductor layer epitaxially grown on the substrate 11. When the lattice constant of the substrate 11 differs from that of the channel layer 13, the lattice constant is controlled by the buffer layer 12, thereby improving the crystal quality of the channel layer 13 and controlling warpage after the formation of the channel layer 13. For example, when the substrate 11 is made of single-crystal Si and the channel layer 13 is made of GaN, the buffer layer 12 is made of AlN, AlGaN, GaN, AlInGaN, etc.

[0055] Back barrier layer

[0056] The back barrier layer 15A is formed from, for example, a compound semiconductor layer epitaxially grown on the buffer layer 12. By providing the back barrier layer 15A, short-channel effects can be suppressed. The back barrier layer 15A can be made of, for example, AlGaN. Note that, as long as the short-channel effect can be suppressed, the back barrier layer 15A can be formed from AlxInyGa1-x-yN (0≤x≤1, 0≤y≤1, x+y≤1) containing Al or In in addition to Ga.

[0057] Channel layer

[0058] The channel layer 13 is formed from, for example, a compound semiconductor layer epitaxially grown on the buffer layer 12. For example, the channel layer 13 is formed from an epitaxially grown GaN layer. The channel layer 13 may be formed from an undoped GaN (u-GaN) layer without added impurities. In this case, impurity dispersion of charge carriers in the channel layer 13 is suppressed, and carrier transport at high mobility is achieved. Furthermore, the channel layer 13 may be made of AlxInyGa1-x-yN (0≤x<1, 0≤y≤1, x+y≤1). For example, it is desirable for the channel layer 13 to be configured to have a thickness capable of suppressing short-channel effects (e.g., in the range of 30 to 300 nm).

[0059] The channel layer 13 includes a two-dimensional electron gas region 13a. The two-dimensional electron gas region 13a constitutes part of a current path, for example, between the source electrode 18 and the drain electrode 19. The two-dimensional electron gas region 13a is a region where charge carriers (i.e., a two-dimensional electron gas (2DEG)) exist. Specifically, due to the difference in polarization charge between the channel layer 13 and the barrier layer 15, electrons accumulate at the interface of the channel layer 13 on the barrier layer 15 side. The region where electrons accumulate (the region where electrons are distributed) is the two-dimensional electron gas region 13a. The two-dimensional electron gas region 13a serves as a channel, for example, through which electrons flow. The two-dimensional electron gas region 13a may include, for example, a region with near-zero electron concentration (a region where the two-dimensional electron gas is depleted), a region with zero electron concentration, etc. That is, the two-dimensional electron gas region 13a need not be a region with uniform electron concentration, and may include, for example, one or both a region with near-zero electron concentration and a region with zero electron concentration.

[0060] Spacer layer

[0061] Spacer layer 14 is formed, for example, by an AlN layer epitaxially grown on channel layer 13. Spacer layer 14 is disposed between channel layer 13 and barrier layer 15. By providing spacer layer 14 made of binary compound AlN between channel layer 13 and barrier layer 15, the influence of alloy dispersion from barrier layer 15 (which is a ternary or quaternary compound) on charge carriers (i.e., two-dimensional electron gas) accumulating at the interface of channel layer 13 on the barrier layer 15 side can be reduced, thereby increasing charge carrier mobility. Note that spacer layer 14 may be absent if the reduction in charge carrier mobility is acceptable.

[0062] Spacer layer 14 may contain Ga or In due to diffusion from channel layer 13 or barrier layer 15. Spacer layer 14 may be made of AlxInyGa1-x-yN (0≤x≤1, 0≤y≤1, x+y≤1), wherein Ga or In is intentionally added to a degree that does not impair channel characteristics.

[0063] Barrier layer

[0064] The barrier layer 15 is formed from a compound semiconductor layer epitaxially grown, for example, on the spacer layer 14. For example, the barrier layer 15 is formed from an AlInN layer. For AlInN, it is preferable to use an AlInN with a composition of 17-18% In that matches the GaN lattice of the channel layer 13. Alternatively, to reduce the on-resistance by achieving a lower sheet resistance (Rs), AlInN with a composition where the In composition is set to less than 17% (e.g., 10% or 14%) can be used, as long as it does not compromise crystallinity. The barrier layer 15 can be formed directly on the channel layer 13 without the spacer layer 14 interposed therebetween.

[0065] The material used for this barrier layer 15 can be any nitride semiconductor material in which a two-dimensional electron gas accumulates at the interface of the channel layer 13 on the barrier layer 15 side due to the difference in polarization charge between the channel layer 13 and the barrier layer 15. For example, the barrier layer 15 can be formed from an epitaxial growth layer of AlxInyGa1-x-yN (0≤x≤1, 0≤y<1, x+y≤1). Alternatively, the barrier layer 15 can be made of undoped u-AlxInyGa1-x-yN. In this case, impurity dispersion of charge carriers in the channel layer 13 is suppressed, and carrier movement at high mobility is achieved. To increase the two-dimensional electron gas concentration, a barrier layer 15 doped with N-type impurities such as Si or Ge can be used.

[0066] Here, the preferred sheet carrier concentration in the two-dimensional electron gas region 13a, which is mainly composed of two-dimensional electron gas, is 5 × 10⁻⁶. 12 cm -2The above is preferred, specifically 7×10 12 cm -2 The sheet resistance of the two-dimensional electron gas region 13a is preferably 300 Ω / □ (Ω / sq) or less. In order to obtain the desired threshold voltage, the concentration of the two-dimensional electron gas in the lower part of the gate electrode 20 is not limited to the above characteristics, and is controlled to a necessary value by the gate formation process.

[0067] In GaN-based HEMTs, using AlInN for the barrier layer 15 structure is very promising for high-frequency device applications. This is because when the In composition of AlInN is set to approximately 17 to 18%, the lattice constant becomes the same as that of GaN used for the channel layer 13. Therefore, good crystallinity can be expected, while a high sheet carrier concentration (>1×10⁻⁶) can be obtained. 13 cm -2 And low sheet resistance (<300Ω / □). Examples of nitride semiconductors include GaN, AlGaN and AlInN, and the use of AlInN, for example, in barrier layer 15, can reliably reduce sheet resistance.

[0068] Hat layer

[0069] The cap layer 16 is formed, for example, from a GaN layer epitaxially grown on the barrier layer 15. When a material with a high Al content (e.g., AlInN) is used for the barrier layer 15, the barrier layer 15 is prone to oxidation in the atmosphere. However, oxidation is suppressed by forming the cap layer 16 on the barrier layer 15. Furthermore, the cap layer 16 can be formed from an insulating layer (such as SiN). The cap layer 16 can be made of, for example, AlxInyGa1-x-yN (0≤x<1, 0≤y<1, x+y≤1), as long as the effect of suppressing oxidation is achieved. The cap layer 16 may also be absent if the negative effects of the barrier layer 15 being formed on the outer surface are not a problem.

[0070] Contact layer

[0071] Each contact layer 17 is formed on the channel layer 13. For example, the contact layer 17 is formed by regrowth in the source and drain regions on the channel layer 13. As the material for the contact layer 17, for example, GaN, the same material as the channel layer 13, is used. By connecting the channel layer 13 and the source electrode 18 with the contact layer 17 and connecting the channel layer 13 and the drain electrode 19 with the contact layer 17, the contact resistance can be reduced.

[0072] In the formation of each contact layer 17, the source and drain regions in the upper portion of the channel layer 13 are patterned open. Then, the source and drain regions are excavated and exposed, for example, by about 30 nm, using dry or wet etching, forming a recess 17A as the exposed region. At this time, the end (peripheral end) of the two-dimensional electron gas region 13a formed at the interface of the channel layer 13 on the barrier layer 15 side is exposed from the surface 17B of the recess 17A on the barrier layer 15 side. Subsequently, the contact layer 17 is formed on the recess 17A.

[0073] In this way, each contact layer 17 is formed to contact at least the two-dimensional electron gas region 13a at the interface of the channel layer 13 on the barrier layer 15 side. This makes each contact layer 17 adjacent to the two-dimensional electron gas region 13a, thereby further reducing the contact resistance.

[0074] The inner surface 17B of the recess 17A on the side of the barrier layer 15 can be formed to intersect with a vertical direction (the stacking direction of each layer) perpendicular to the plane of the substrate 11 or perpendicular to the plane of the substrate 11. Figure 1 In the example, the corresponding surfaces 17B of the two recesses 17A on the barrier layer 15 side are formed in a conical shape so as to intersect with the vertical direction. Furthermore, the corresponding surfaces 17B of the two recesses 17A on the barrier layer 15 side can be formed in an inverse conical shape. As the cone angle increases, for example, a high-electron-concentration two-dimensional electron gas region 13a is formed until near each contact layer 17. Therefore, it is desirable that the corresponding surface 17B of each recess 17A on the barrier layer 15 side, i.e., the surface of each contact layer 17 on the two-dimensional electron gas region 13a side, is perpendicular to the plane of the substrate 11.

[0075] Each contact layer 17 includes a sloped surface 17a and a flat surface 17b. The sloped surface 17a slopes downward toward the gate electrode 20. More specifically, the sloped surface 17a is a surface (sloping region) where the thickness (layer thickness) of the contact layer 17 gradually decreases from the edge of the flat surface 17b toward the gate electrode 20. The flat surface 17b is a flat surface (flat region) and is connected to the sloped surface 17a. The contact layer 17 is formed to include at least these two regions: the sloped surface 17a and the flat surface 17b.

[0076] For example, each contact layer 17 is formed such that the height of the inclined surface 17a is higher than the surface of the cap layer 16 on the gate electrode 20 side. Figure 1The height of the surface is the height position in the vertical direction (the stacking direction of each layer). Each contact layer 17 can be formed such that the height of the inclined surface 17a is the same as the height of the surface of the cap layer 16 on the gate electrode 20 side. Furthermore, in the absence of the cap layer 16, each contact layer 17 is formed such that, for example, the height of the inclined surface 17a is higher than the surface of the barrier layer 15 on the gate electrode 20 side. Figure 1 (the upper surface of the middle).

[0077] Each contact layer 17 is formed by, for example, metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), sputtering, etc. In this case, the contact layer 17 is preferably a material whose main component is a C-axis oriented surface, but it can also be polycrystalline or amorphous.

[0078] Note that a high concentration of N-type impurities can be added to each contact layer 17. This reduces the contact resistance between the contact layer 17 and the source electrode 18, as well as the contact resistance between the contact layer 17 and the drain electrode 19. The N-type impurities can be composed of, for example, Si, Ge, etc. The carrier concentration of the contact layer 17 is preferably 1 × 10⁻⁶. 19 / cm -3 That's all. To achieve this, the carrier concentration in contact layer 17 must be equal to or greater than 1 × 10⁻⁶. 19 / cm -3 The amount of N-type impurities added is [amount missing]. N-type impurities can be added during the formation of contact layer 17, or after the formation of contact layer 17 via ion implantation, diffusion, or other methods. The sheet resistance of contact layer 17 is preferably 250 Ω / □ or less, and the mobility of contact layer 17 is preferably 30 cm⁻¹. 2 / V·s or more. The contact layer 17 can be made of, for example, AlxInyG1-x-yN (0≤x≤1, 0≤y≤1, x+y≤1).

[0079] Source electrode / drain electrode

[0080] Source electrode 18 and drain electrode 19 are each formed on contact layer 17 to cover the entire surface of contact layer 17 (sloping surface and flat surface 17b). Source electrode 18 and drain electrode 19 are each configured to be connected to contact layer 17. Source electrode 18 or drain electrode 19 is formed of conductive material and is configured, for example, to be sequentially stacked from the bottom layer with Ti, Al, Ni and Au. The stack of Ti, Al, Ni and Au is heat-treated as needed.

[0081] gate electrode

[0082] Gate electrode 20 is formed on cap layer 16. When cap layer 16 is absent, gate electrode 20 is formed on barrier layer 15. Gate electrode 20 is formed of a conductive material and is configured, for example, to sequentially stack Ni and Au from the bottom layer. Furthermore, an insulating film may be formed between gate electrode 20 and cap layer 16 to form a metal-insulator-oxide (MIS) gate structure. In this case, the insulating film may be made of, for example, SiO2, Si3N4, Al2O3, AlTiO, HfO2, NiO, MgO, or a stack of any of these. When cap layer 16 is absent, the insulating film is formed on barrier layer 15.

[0083] 1-2. Example of gradient on the inclined surface of the contact layer

[0084] Reference Figure 2 An example describing the gradient of the inclined surface 17a of the contact layer 17 according to this embodiment. Figure 2 This is a diagram used to describe the gradient of the inclined surface 17a of the contact layer 17 according to this embodiment.

[0085] like Figure 2 As shown, the inclined surface 17a preferably has a gentle inclination (gradient), wherein the aspect ratio (gradient) between the vertical length A1 and the horizontal length A2 of the inclined surface 17a is 0.5 or less, and more preferably has an inclination with an aspect ratio of 0.05 or more and 0.5 or less. The vertical direction is the aforementioned stacking direction, and the horizontal direction is a direction orthogonal to the stacking direction. Furthermore, the horizontal length A2 of the inclined surface 17a is preferably 0.1 μm or more, and more preferably 0.15 μm or more.

[0086] 1-3. Examples of the effects of semiconductor devices

[0087] 1-3-1. Examples of effects 1 to 3

[0088] Reference Figure 3 Examples 1 to 3 describe the effects of the semiconductor device 1A according to this embodiment. Figure 3 These are figures used to illustrate examples 1 to 3 of the effects according to this embodiment.

[0089] exist Figure 3 In the example, as a comparative example, each of the contact layer 17C, source electrode 18C, and drain electrode 19C is represented by dashed lines. Figure 3As shown, each contact layer 17C includes a sloped surface 17a but not a flat surface 17b. Therefore, each contact layer 17C includes a vertical corner portion (see dashed line) or a nearly vertical corner portion (e.g., a corner portion with rounded corners) on the gate electrode 20 side. Similarly, each of the source electrode 18C and drain electrode 19C includes a vertical corner portion (see dashed line) or a nearly vertical corner portion (e.g., a corner portion with rounded corners) on the gate electrode 20 side.

[0090] On the other hand, in the semiconductor device 1A according to this embodiment, each of the contact layers 17 includes a sloped surface 17a on the gate electrode 20 side. Therefore, each of the source electrode 18 and the drain electrode 19 also includes a sloped portion (sloped surface) on the gate electrode 20 side. The sloped portion has a gradient equivalent to the sloped surface 17a.

[0091] According to semiconductor device 1A, each contact layer 17 includes a sloped surface 17a on the gate electrode 20 side. Therefore, in the comparative example, the vertical corner portion on the gate electrode 20 side of each contact layer 17C is absent. Consequently, the surface area of ​​the source electrode 18 on the gate electrode 20 side and the surface area of ​​the drain electrode 19 on the gate electrode 20 side are smaller than the surface area of ​​the source electrode 18C on the gate electrode 20 side and the surface area of ​​the drain electrode 19C on the gate electrode 20 side in the comparative example. As a result, the gate-source capacitance Cgs and gate-drain capacitance Cgd in this embodiment are smaller than those in the comparative example. Therefore, by providing a sloped surface 17a in each contact layer 17, the gate-source capacitance Cgs and gate-drain capacitance Cgd can be suppressed (Effect Example 1).

[0092] Furthermore, since each contact layer 17 in this embodiment includes a sloped surface 17a on the gate electrode 20 side, the electric field at the end of the source electrode 18 on the gate electrode 20 side and the electric field at the end of the drain electrode 19 on the gate electrode 20 side can be reduced. This reduces the electric field strength at the end of the source electrode 18 on the gate electrode 20 side and the electric field strength at the end of the drain electrode 19 on the gate electrode 20 side, thereby improving withstand voltage and reliability (effect example 2).

[0093] Furthermore, since each contact layer 17 in this embodiment includes a sloped surface 17a on the gate electrode 20 side, the unevenness caused by the contact layer 17 is less than that caused by each contact layer 17C in the comparative example. By reducing the unevenness, it becomes possible to suppress the reduction in photoresist flatness during subsequent processes of forming the source / drain electrodes and the gate as a process of forming the contact layer 17, thereby improving microfabrication performance (Effect Example 3).

[0094] 1-3-2. Example of effect 4

[0095] Reference Figure 4 and Figure 5 Example 4 describes the effect of the semiconductor device 1A according to this embodiment. Figure 4 This is a diagram illustrating an example configuration of the contact layer 17 for each of cases A to C according to this embodiment. Figure 5 This is a diagram used to describe the contact resistance for each case A to C according to this embodiment.

[0096] like Figure 4 As shown, in case A, the depth of recess 17A (recess depth) is d1 nm, and the thickness of contact layer 17 (contact layer thickness) is d1 + d2 nm. In this case, the height of the upper surface of contact layer 17 is d2 nm higher than the height of the upper surface of barrier layer 15. At this time, contact layer 17 is in contact with two-dimensional electron gas region 13a. For example, d1 is approximately tens of nanometers, and d2 is approximately several nanometers to tens of nanometers.

[0097] In case B, the depth of recess 17A (recess depth) is d1 nm as in case A, and the thickness of contact layer 17 (contact layer thickness) is d1 nm. In this case, the height of the upper surface of contact layer 17 is the same as the height of the upper surface of barrier layer 15. At this time, contact layer 17 is in contact with two-dimensional electron gas region 13a.

[0098] In case C, the depth of recess 17A (recess depth) is d1 nm, as in cases A and B, and the thickness of contact layer 17 (contact layer thickness) is d1-d2 nm. In this case, the height of the upper surface of contact layer 17 is d2 nm lower than the height of the upper surface of barrier layer 15. At this time, contact layer 17 does not contact the two-dimensional electron gas region 13a.

[0099] like Figure 5 As shown, the contact resistance in each of cases A and B is approximately a (Ω). On the other hand, the contact resistance in case C is approximately 4a (Ω). It should be understood that the contact resistance in each of cases A and B is approximately one-quarter of the contact resistance in case C, which is very small.

[0100] The main difference between cases A and B and case C lies in whether contact layer 17 contacts the two-dimensional electron gas region 13a. In cases A and B, contact layer 17 contacts the two-dimensional electron gas region 13a. However, in case C, contact layer 17 does not contact the two-dimensional electron gas region 13a. Therefore, by forming contact layer 17 that contacts the two-dimensional electron gas region 13a, contact resistance can be suppressed (effect example 4).

[0101] 1-4. Examples of modifications to semiconductor devices

[0102] 1-4-1. Modify Example 1

[0103] Reference Figure 6 The semiconductor device 1B according to the modified example 1 of this embodiment is described. Figure 6 This is a cross-sectional view showing a configuration example of semiconductor device 1B according to modified example 1 of this embodiment.

[0104] like Figure 6 As shown, in the semiconductor device 1B of Modified Example 1, the source electrode 18 is formed on the flat surface 17b, exposing the entire surface of the inclined surface 17a of the contact layer 17. Similarly, the drain electrode 19 is formed on the flat surface 17b, exposing the entire surface of the inclined surface 17a of the contact layer 17. This further suppresses the gate-source capacitance Cgs and the gate-drain capacitance Cgd, and further improves withstand voltage and reliability. The source electrode 18 or the drain electrode 19 can be formed such that only a portion of the inclined surface 17a of the contact layer 17 is exposed.

[0105] 1-4-2. Modify Example 2

[0106] Reference Figure 7 The semiconductor device 1C according to the modified example 2 of this embodiment is described. Figure 7 This is a cross-sectional view showing a configuration example of the semiconductor device 1C according to Modified Example 2 of this embodiment.

[0107] like Figure 7 As shown, in the semiconductor device 1C of modified Example 2, each of the contact layers 17 is formed such that the height of the inclined surface 17a is lower than the surface of the cap layer 16 on the gate electrode 20 side. Figure 7 The height of the upper surface (in). Figure 7 In the example, each contact layer 17 is formed such that the height of the inclined surface 17a is lower than the surface of the barrier layer 15 on the gate electrode 20 side. Figure 7 The height of the upper surface (in the middle). In either case, the contact layer 17 contacts the two-dimensional electron gas region 13a. In this way, improved design flexibility can be achieved.

[0108] 1-4-3. Modify Example 3

[0109] Reference Figure 8 The semiconductor device 1D according to the modified example 3 of this embodiment is described. Figure 8 This is a cross-sectional view showing a configuration example of the semiconductor device 1D according to Modified Example 3 of this embodiment.

[0110] like Figure 8As shown, in the semiconductor device 1D of Modified Example 3, the inclined surface 17a of the contact layer 17 on the drain electrode 19 side is a curved surface. The curved surface faces the channel layer 13 side ( Figure 8 The surface is curved (on the lower side of the gate electrode 20). For example, the surface is formed as a gradient that becomes steeper as it moves away from the gate electrode 20. This improves the photoresist coatability during source / drain electrode formation and gate formation. For example, during source / drain electrode formation or gate formation, the photoresist diffuses due to centrifugal force caused by the rotation of the object being coated. At this time, the photoresist gradually diffuses, and because the inclined surface 17a is curved, the photoresist is uniformly coated onto the surface of the object being coated.

[0111] According to this embodiment, since there are two contact layers 17, one of the inclined surfaces 17a of each of the two contact layers 17 can be a curved surface, or they can both be curved surfaces.

[0112] 1-4-4. Variation Example 4

[0113] The following will refer to Figure 9 The semiconductor device 1E according to variant 4 of this embodiment is described. Figure 9 This is a cross-sectional view showing an example configuration of the semiconductor device 1E according to Variation 4 of this embodiment.

[0114] like Figure 9 As shown, in the semiconductor device 1E of Variation 4, the inclined surface 17a of the contact layer 17 on the drain electrode 19 side includes uneven portions 17c. For example, uneven portions are formed on the entire surface of the inclined surface 17a. This increases the contact area between the contact layer 17 and the drain electrode 19, thereby reducing the contact resistance between the contact layer 17 and the drain electrode 19.

[0115] According to this embodiment, since there are two contact layers 17, one of the inclined surfaces 17a of each contact layer 17 may include a protrusion 17c, or both may include a protrusion 17c. The protrusion may be formed on the entire surface of the inclined surface 17a, or it may be formed only on a portion of the inclined surface 17a.

[0116] For example, the inclined surface 17a of the contact layer 17 on the source electrode 18 side may include a protrusion 17c, similar to the inclined surface 17c of the contact layer 17 on the drain electrode 19 side. In this case, the contact area between the contact layer 17 and the source electrode 18 on the source electrode 18 side is increased, and thus the contact resistance between the contact layer 17 and the source electrode 18 can be reduced.

[0117] 1-5. Actions and Effects

[0118] As described above, the semiconductor device 1A (or each of semiconductor devices 1B to 1E) according to this embodiment includes: a channel layer 13 containing a two-dimensional electron gas region 13a, a barrier layer 15 disposed on the channel layer 13, a gate electrode 20 disposed on the barrier layer 15, and a contact layer 17 disposed on the channel layer 13, wherein the contact layer 17 includes an inclined surface 17a that slopes downward toward the gate electrode 20 (for example, see...). Figure 1 This reduces the capacitance between the source electrode 18 or drain electrode 19 disposed on the contact layer 17 and the gate electrode 20 (e.g., gate-source capacitance Cgs or gate-drain capacitance Cgd), thereby suppressing the capacitance between the electrodes. Furthermore, since the electric field at the end of the source electrode 18 or drain electrode 19 on the gate electrode 20 side can be alleviated, improved breakdown voltage and reliability can be achieved. Moreover, the reduction in photoresist flatness during subsequent processes, such as forming the source / drain electrodes and the gate as part of the process of forming the contact layer 17, becomes suppressable, thereby improving microfabrication performance.

[0119] Furthermore, the contact layer 17 can contact the two-dimensional electron gas region 13a (see [link]). Figure 1 (etc.). This allows the contact layer 17 to contact the two-dimensional electron gas region 13a, thereby suppressing contact resistance.

[0120] Contact layer 17 can be formed such that the height of the inclined surface 17a is higher than the height of the barrier layer 15 on the gate electrode 20 side (see...). Figure 1 (etc.). This allows for improved design flexibility.

[0121] Furthermore, the contact layer 17 can be formed such that the height of the inclined surface 17a is lower than the height of the barrier layer 15 on the gate electrode 20 side (see [reference]). Figure 7 This allows for improved design flexibility.

[0122] Semiconductor device 1A (or each of semiconductor devices 1B to 1E) may further include a cap layer 16 disposed on the barrier layer 15, and a gate electrode 20 may be disposed on the cap layer 16 (see See Figure 1 (etc.). Therefore, the cap layer 16 exists on the barrier layer 15 and thus can protect the barrier layer 15.

[0123] Contact layer 17 can be formed such that the height of the inclined surface 17a is higher than the height of the cap layer 16 on the gate electrode 20 side (see...). Figure 1 (etc.). This allows for improved design flexibility.

[0124] Contact layer 17 can be formed such that the height of the inclined surface 17a is lower than the height of the cap layer 16 on the gate electrode 20 side (see...). Figure 7This allows for improved design flexibility.

[0125] Inclined surface 17a may be a curved surface that bends toward the channel layer 13 (see [reference]). Figure 8 This allows the photoresist to be applied evenly to the surface of the object being coated, thereby ensuring improved micromachining performance.

[0126] In addition, the inclined surface 17a may include a concave-convex portion 17c (see Figure 9 This increases the contact area between the contact layer 17 and the electrode (e.g., source electrode 18 or drain electrode 19), thereby reducing the contact resistance.

[0127] Furthermore, the ratio (gradient) of the vertical length A1 of the inclined surface 17a to the horizontal length A2 of the inclined surface 17a can be 0.5 or less (see [reference]). Figure 2 This ensures reduced capacitance between electrodes, improved withstand voltage and reliability, and better micromachining performance.

[0128] Furthermore, the horizontal length A2 of the inclined surface 17a can be 0.1 μm or greater (see [reference]). Figure 2 This ensures reduced capacitance between electrodes, improved withstand voltage and reliability, and better micromachining performance.

[0129] Furthermore, semiconductor device 1A (or each of semiconductor devices 1B to 1E) may also include an electrode (e.g., source electrode 18 or drain electrode 19) covering the entire surface or a portion of the inclined surface 17a (see [reference]). Figure 1 (etc.). This allows for improved design flexibility.

[0130] Furthermore, semiconductor device 1A (or each of semiconductor devices 1B to 1E) may also include a spacer layer 14 disposed between channel layer 13 and barrier layer 15 (see Figure 1 (etc.). This can, for example, increase carrier mobility.

[0131] In addition, the contact layer 17 may also include a flat surface 17b connected to the inclined surface 17a (see Figure 1 (etc.). This allows for improved design flexibility.

[0132] Furthermore, semiconductor device 1A (or each of semiconductor devices 1B to 1E) may also include electrodes (e.g., source electrode 18 or drain electrode 19) covering the entire surface or a portion of the inclined surface 17a and the flat surface 17b (see [reference]). Figure 1 and Figure 6 (etc.). This enables greater design flexibility.

[0133] In addition, two contact layers 17 are provided, and each of the two contact layers 17 may include an inclined surface 17a (see Figure 1 (etc.). This ensures reduced capacitance between electrodes, improved voltage withstand and reliability, and enhanced micromachining performance.

[0134] Furthermore, the material of the barrier layer 15 can be AlInN (see Figure 1 (etc.). This can increase the surface carrier concentration and suppress sheet resistance, thereby reducing the on-resistance of semiconductor device 1A (or each of semiconductor devices 1B to 1E).

[0135] The surface carrier concentration in the two-dimensional electron gas region 13a can be 5 × 10⁻⁶. 12 cm -2 The sheet resistance of the two-dimensional electron gas region 13a can be less than 300 Ω / □ (see above). Figure 1 (etc.). This can suppress the on-resistance of semiconductor device 1A (or each of semiconductor devices 1B to 1E).

[0136] 2. Other embodiments

[0137] Each construction, process, etc., according to the above embodiments (including examples and variations) can be implemented in various forms other than the above embodiments. For example, the construction and process are not limited to the above examples, but can adopt various modes. In addition, for example, unless otherwise stated, the construction, process, specific name, or information including various data and parameters explained in the above description and drawings can be arbitrarily modified.

[0138] Furthermore, each construction, process, etc., according to the above embodiments (including examples and variations) need not be physically configured as shown in the figures. That is, the specific form of distribution or integration of each construction and process is not limited to the examples shown in the figures, and they can be functionally or physically distributed in any unit or integrated together according to various loads, usage conditions, etc.

[0139] Furthermore, each construction, process, etc., according to the above embodiments (including examples and variations) can be appropriately combined. For example, at least a portion of one embodiment can be appropriately combined with at least a portion of another embodiment. Additionally, the effects in the embodiments are merely illustrative and not limiting, and other effects may also be obtained.

[0140] 3. Application Examples

[0141] The semiconductor devices 1A to 1E according to this embodiment are applied to various products. For example, any one of the semiconductor devices 1A to 1E according to this embodiment is applied to various circuits (e.g., electronic circuits), various electronic devices, etc. Examples of electronic devices include power equipment and high-frequency equipment. Specifically, examples of electronic devices include power supply devices, wireless communication devices, etc. Power supply devices, wireless communication devices, etc., include circuits including, for example, power amplifiers, high-frequency switches, etc.

[0142] For example, wireless communication devices can be installed on any mobile body such as a car, electric car, hybrid electric car, motorcycle, bicycle, personal mobility device, airplane, drone, boat, robot, construction machinery, and agricultural machinery (tractor). Wireless communication devices can also be installed on any surgical system such as an endoscopic surgical system or a microsurgical system. It should be noted that wireless communication devices are merely examples of electronic devices.

[0143] Reference Figure 10 and Figure 11 The description applies to any one of the semiconductor devices 1A to 1E according to this embodiment of the wireless communication device (e.g., wireless communication device 100 and wireless communication device 200). Figure 10 This is a perspective view showing a configuration example of the wireless communication device 100 according to Application Example 1. Figure 11 This is a block diagram illustrating a configuration example of the wireless communication device 200 according to Application Example 2.

[0144] like Figure 10 As shown, the wireless communication device 100 of Application Example 1 includes, for example, a substrate 110, a plurality of edge antennas 120, and a front-end component assembly 130. The wireless communication device 100 is an antenna integration module in which the edge antennas 120 and the front-end component assembly 130 are integrated and mounted as a single module. Each edge antenna 120 is formed as an array on the substrate 110. The front-end component assembly 130 includes a switch 131, a low-noise amplifier 132, a bandpass filter 133, a power amplifier 134, etc. The front-end component assembly 130 serves as a circuit.

[0145] Such a wireless communication device 100 can be used as a transceiver for communication. Any of the semiconductor devices 1A to 1E according to this embodiment can be applied to transistors that constitute, for example, a switch 131, a low-noise amplifier 132, or a power amplifier 134. Therefore, the wireless communication device 100 can achieve the same effects as any of the embodiments (and variations) described above.

[0146] like Figure 11As shown, the wireless communication device 200 of Application Example 2 includes an antenna (ANT) 210, an antenna switching circuit 220, a high power amplifier (HPA) 230, a radio frequency integrated circuit (RFIC) 240, a baseband unit 250, a voice output unit (MIC) 260, a data output unit (DT) 270, and an interface unit (I / F) 280.

[0147] The wireless communication device 200 is used as a mobile phone system with multiple functions, such as voice and data communication and local area network (LAN) connection. Any of the semiconductor devices 1A to 1E according to this embodiment can be applied to transistors, for example, constituting antenna switch circuit 220, high-power amplifier 230, radio frequency integrated circuit 240, baseband unit 250, etc. Therefore, the wireless communication device 200 can achieve the same effects as any of the above embodiments (and variations).

[0148] 4. Appendix

[0149] This technology can be constructed as described below. (1)

[0151] A semiconductor device, comprising: The channel layer includes a two-dimensional electron gas region; A barrier layer is disposed on the channel layer; A gate electrode is disposed on the barrier layer; and A contact layer is disposed on the channel layer. The contact layer includes an inclined surface that slopes downward toward the gate electrode side.

[0152] (2) The semiconductor device according to (1), wherein, The contact layer is in contact with the two-dimensional electron gas region.

[0153] (3) The semiconductor device according to (2), wherein, The contact layer is formed such that the height of the inclined surface is higher than the height of the barrier layer on the gate electrode side.

[0154] (4) The semiconductor device according to (2), wherein, The contact layer is formed such that the height of the inclined surface is lower than the height of the barrier layer on the gate electrode side.

[0155] (5) The semiconductor device according to (2) further includes: A cap layer is disposed on the barrier layer. The gate electrode is disposed on the cap layer.

[0156] (6) The semiconductor device according to (5), wherein, The contact layer is formed such that the height of the inclined surface is higher than the height of the cap layer on the gate electrode side.

[0157] (7) The semiconductor device according to (5), wherein, The contact layer is formed such that the height of the inclined surface is lower than the height of the cap layer on the surface of the gate electrode.

[0158] (8) The semiconductor device according to any one of (1)-(7), wherein, The inclined surface is a curved surface that bends toward the channel layer side.

[0159] (9) The semiconductor device according to any one of (1)-(8), wherein, The inclined surface includes concave and convex portions.

[0160] (10) The semiconductor device according to any one of (1)-(9), wherein, The ratio of the length of the inclined surface in the vertical direction to the length of the inclined surface in the horizontal direction is less than 0.5.

[0161] (11) The semiconductor device according to any one of (1)-(10), wherein, The length of the inclined surface in the horizontal direction is 0.1 μm or more.

[0162] (12) The semiconductor device according to any one of (1)-(11) further comprises: Electrodes that cover the entire surface or a portion of the inclined surface.

[0163] (13) The semiconductor device according to any one of (1)-(12) further comprises: A spacer layer is disposed between the channel layer and the barrier layer.

[0164] (14) The semiconductor device according to any one of (1)-(13), wherein, The contact layer also includes a flat surface connected to the inclined surface.

[0165] (15) The semiconductor device according to (14) further includes: Electrodes that cover the entire surface or a portion of the inclined surface and the flat surface.

[0166] (16) The semiconductor device according to any one of (1)-(15), wherein, It has two contact layers, and Each of the two contact layers includes an inclined surface.

[0167] (17) The semiconductor device according to any one of (1)-(16), wherein, The material of the barrier layer is AlInN.

[0168] (18) The semiconductor device according to any one of (1)-(17), wherein, The two-dimensional electron gas region has a size of 5×10 12 cm -2 The above surface carrier concentrations, and The two-dimensional electron gas region has a sheet resistance of less than 300 Ω / □.

[0169] (19) A circuit comprising: a semiconductor device, The semiconductor device includes: The channel layer includes a two-dimensional electron gas region; A barrier layer is disposed on the channel layer; A gate electrode is disposed on the barrier layer; and A contact layer is disposed on the channel layer, and The contact layer includes a sloping surface that slopes downward toward the gate electrode side.

[0170] (20) An electronic device comprising: The circuit includes a semiconductor device, wherein The semiconductor device includes: The channel layer includes a two-dimensional electron gas region; A barrier layer is disposed on the channel layer; A gate electrode is disposed on the barrier layer; and A contact layer is disposed on the channel layer, and The contact layer includes a sloping surface that slopes downward toward the gate electrode side.

[0171] (21) A circuit comprising a semiconductor device according to any one of (1)-(18).

[0172] (22) An electronic device comprising the circuit according to (21).

[0173] (List of reference numerals in the attached image)

[0174] 1A Semiconductor Device

[0175] 1B Semiconductor Device

[0176] IC semiconductor device

[0177] 1D semiconductor device

[0178] 1E Semiconductor Devices

[0179] 11 base plate

[0180] 12 Buffer Layer

[0181] 13a Channel layer

[0182] 13a Two-dimensional electron gas region

[0183] 14 Spare Layers

[0184] 15. Barrier layer

[0185] 15A Back Barrier Layer

[0186] 16-layer cap

[0187] 17 Contact Layer

[0188] 17a Inclined surface

[0189] 17A recess

[0190] 17b Flat surface

[0191] 17B surface

[0192] 17c Concave and convex parts

[0193] 17C contact layer

[0194] 18 Source Electrode

[0195] 18C source electrode

[0196] 19 Drain electrode

[0197] 19C Drain Electrode

[0198] 20 Gate electrode

[0199] 100 Wireless communication devices

[0200] 130 Front-end component group

[0201] 131 switch

[0202] 132 Low Noise Amplifier

[0203] 133 bandpass filter

[0204] 134 Power Amplifier

[0205] 200 Wireless communication devices

[0206] 210 antenna

[0207] 220 Antenna Switching Circuit

[0208] 230 High Power Amplifier

[0209] 240 Radio Frequency Integrated Circuit

[0210] 250 baseband units

[0211] 260 audio output unit

[0212] 270 Data Output Unit

[0213] 280 Interface Unit

Claims

1. A semiconductor device, comprising: The channel layer includes a two-dimensional electron gas region; A barrier layer is disposed on the channel layer; A gate electrode is disposed on the barrier layer; as well as A contact layer is disposed on the channel layer. The contact layer includes an inclined surface that slopes downward toward the gate electrode side.

2. The semiconductor device according to claim 1, wherein The contact layer is in contact with the two-dimensional electron gas region.

3. The semiconductor device according to claim 2, wherein The contact layer is formed such that the height of the inclined surface is higher than the height of the barrier layer on the gate electrode side.

4. The semiconductor device according to claim 2, wherein The contact layer is formed such that the height of the inclined surface is lower than the height of the barrier layer on the gate electrode side.

5. The semiconductor device according to claim 2, further comprising: A cap layer is disposed on the barrier layer. The gate electrode is disposed on the cap layer.

6. The semiconductor device according to claim 5, wherein The contact layer is formed such that the height of the inclined surface is higher than the height of the cap layer on the gate electrode side.

7. The semiconductor device according to claim 5, wherein The contact layer is formed such that the height of the inclined surface is lower than the height of the cap layer on the surface of the gate electrode.

8. The semiconductor device according to claim 1, wherein The inclined surface is a curved surface that bends toward the channel layer side.

9. The semiconductor device according to claim 1, wherein The inclined surface includes concave and convex portions.

10. The semiconductor device of claim 1, wherein The ratio of the length of the inclined surface in the vertical direction to the length of the inclined surface in the horizontal direction is less than 0.

5.

11. The semiconductor device of claim 1, wherein The length of the inclined surface in the horizontal direction is 0.1 μm or more.

12. The semiconductor device according to claim 1, further comprising: Electrodes that cover the entire surface or a portion of the inclined surface.

13. The semiconductor device according to claim 1, further comprising: A spacer layer is disposed between the channel layer and the barrier layer.

14. The semiconductor device of claim 1, wherein The contact layer also includes a flat surface connected to the inclined surface.

15. The semiconductor device of claim 14, further comprising: Electrodes that cover the entire surface or a portion of the inclined surface and the flat surface.

16. The semiconductor device of claim 1, wherein It has two contact layers, and Each of the two contact layers includes an inclined surface.

17. The semiconductor device of claim 1, wherein The material of the barrier layer is AlInN.

18. The semiconductor device of claim 1, wherein The two-dimensional electron gas region has a size of 5×10 12 cm -2 The above surface carrier concentrations, and The two-dimensional electron gas region has a sheet resistance of less than 300 Ω / □.

19. A circuit comprising: Semiconductor devices, The semiconductor device includes: The channel layer includes a two-dimensional electron gas region; A barrier layer is disposed on the channel layer; A gate electrode is disposed on the barrier layer; and A contact layer is disposed on the channel layer, and The contact layer includes a sloping surface that slopes downward toward the gate electrode side.

20. An electronic device, comprising: The circuit includes a semiconductor device, wherein The semiconductor device includes: The channel layer includes a two-dimensional electron gas region; A barrier layer is disposed on the channel layer; A gate electrode is disposed on the barrier layer; and A contact layer is disposed on the channel layer, and The contact layer includes a sloping surface that slopes downward toward the gate electrode side.

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