Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device (1) includes: a channel layer (14); a barrier layer (16) provided above the channel layer (14) and having a larger band gap than the channel layer (14); a p-type semiconductor layer (18) provided above the barrier layer (16); a source electrode (32) and a drain electrode (34) provided so as to sandwich the p-type semiconductor layer (18); an i-type Al-containing layer (20) provided above the p-type semiconductor layer (18), having a larger band gap than the p-type semiconductor layer (18), and containing Al; an i-type Al-free layer (22) provided above the Al-containing layer (20) and not containing Al; and a gate electrode (30) provided above the Al-free layer (22).

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] Patent documents 1 and 2 disclose field-effect transistors (FETs) designed to reduce gate leakage current. In the FETs disclosed in Patent Documents 1 and 2, a p-type GaN layer is disposed between the semiconductor stacked structure that generates a two-dimensional electron gas layer and the gate electrode. In the FET disclosed in Patent Document 1, an AlGaN layer is disposed between the p-type GaN layer and the gate electrode. In the FET disclosed in Patent Document 2, a GaN layer is disposed between the p-type GaN layer and the gate electrode.

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2014-140024 Patent Document 2: Japanese Patent Application Publication No. 2014-110345 Summary of the Invention

[0004] The problem that the invention aims to solve However, in the field-effect transistor disclosed in Patent Document 1, an oxide layer is formed on the surface of the AlGaN layer because the AlGaN layer is exposed to the atmosphere before the gate electrode is formed. Due to the formation of the oxide layer, the Schottky characteristics of the AlGaN layer and the gate electrode become unstable. Furthermore, the thickness of the oxide layer is prone to deviation, resulting in a deviation in the threshold voltage.

[0005] In the field-effect transistor disclosed in Patent Document 2, a GaN layer is formed with a Schottky junction to the gate electrode. However, the reduction effect on gate leakage current is insufficient solely through the Schottky junction.

[0006] Therefore, this disclosure provides a semiconductor device and a method for manufacturing the same that can reduce gate leakage current and suppress threshold voltage deviation.

[0007] Methods for solving problems One aspect of the semiconductor device disclosed herein includes: a first nitride semiconductor layer; a second nitride semiconductor layer disposed above the first nitride semiconductor layer, having a larger band gap than the first nitride semiconductor layer; a p-type third nitride semiconductor layer disposed above the second nitride semiconductor layer; a source electrode and a drain electrode disposed such that the third nitride semiconductor layer is sandwiched between them; an i-type fourth nitride semiconductor layer disposed above the third nitride semiconductor layer, having a larger band gap than the third nitride semiconductor layer and containing Al; an i-type fifth nitride semiconductor layer disposed above the fourth nitride semiconductor layer and not containing Al; and a gate electrode disposed above the fifth nitride semiconductor layer.

[0008] One aspect of the semiconductor device disclosed herein includes: a first nitride semiconductor layer; a second nitride semiconductor layer disposed above the first nitride semiconductor layer, having a larger band gap than the first nitride semiconductor layer; a p-type third nitride semiconductor layer disposed above the second nitride semiconductor layer; a source electrode and a drain electrode disposed such that the third nitride semiconductor layer is sandwiched between them; a fourth nitride semiconductor layer disposed above the third nitride semiconductor layer, having a larger band gap than the third nitride semiconductor layer and containing Al; a fifth nitride semiconductor layer disposed above the fourth nitride semiconductor layer and not containing Al; and a gate electrode disposed above the fifth nitride semiconductor layer, wherein at least a portion of the fifth nitride semiconductor layer has a thickness of less than 3 nm.

[0009] A method for manufacturing a semiconductor device according to one aspect of this disclosure includes: a first step of sequentially forming a first nitride semiconductor layer and a second nitride semiconductor layer with a band gap larger than the first nitride semiconductor layer; a second step of sequentially forming a p-type third nitride semiconductor layer, a fourth nitride semiconductor layer with a band gap larger than the third nitride semiconductor layer and containing Al, and an i-type fifth nitride semiconductor layer without Al above the second nitride semiconductor layer; a third step of forming a source electrode and a drain electrode in such a way that the third nitride semiconductor layer is sandwiched in between; and a fourth step of forming a gate electrode above the fifth nitride semiconductor layer.

[0010] A method for manufacturing a semiconductor device according to one aspect of this disclosure includes: a first step of sequentially forming a first nitride semiconductor layer and a second nitride semiconductor layer with a band gap larger than the first nitride semiconductor layer; a second step of sequentially forming a p-type third nitride semiconductor layer, a fourth nitride semiconductor layer with a band gap larger than the third nitride semiconductor layer and containing Al, and a fifth nitride semiconductor layer without Al above the second nitride semiconductor layer; a third step of forming a source electrode and a drain electrode in such a way that the third nitride semiconductor layer is sandwiched in between; and a fourth step of forming a gate electrode above the fifth nitride semiconductor layer, wherein at least a portion of the fifth nitride semiconductor layer has a thickness of less than 3 nm.

[0011] The effects of the invention According to this disclosure, it is possible to reduce gate leakage current and suppress threshold voltage deviation. Attached Figure Description

[0012] Figure 1 This is a cross-sectional view of the semiconductor device according to Embodiment 1.

[0013] Figure 2A This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 1.

[0014] Figure 2B This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 1.

[0015] Figure 2C This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 1.

[0016] Figure 2D This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 1.

[0017] Figure 3 This is a cross-sectional view of the semiconductor device according to Embodiment 2.

[0018] Figure 4 This is a cross-sectional view showing the vicinity of the gate structure of the semiconductor device in Embodiment 2.

[0019] Figure 5A This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 2.

[0020] Figure 5B This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 2.

[0021] Figure 6 This is a cross-sectional view of the semiconductor device according to Embodiment 3.

[0022] Figure 7A This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 3.

[0023] Figure 7B This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 3.

[0024] Figure 7C This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 3.

[0025] Figure 7D This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 3.

[0026] Figure 7E This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 3.

[0027] Figure 8 This is a cross-sectional view of the semiconductor device according to Embodiment 4.

[0028] Figure 9A This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 4.

[0029] Figure 9B This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 4.

[0030] Figure 9C This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 4.

[0031] Figure 9D This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 4.

[0032] Figure 10 This is a cross-sectional view of the semiconductor device according to Embodiment 5.

[0033] Figure 11A This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device in Embodiment 5.

[0034] Figure 11B This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device in Embodiment 5.

[0035] Figure 11C This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device in Embodiment 5.

[0036] Figure 11DThis is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device in Embodiment 5.

[0037] Figure 11E This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device in Embodiment 5.

[0038] Figure 11F This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device in Embodiment 5.

[0039] Figure 12 This is a cross-sectional view of a semiconductor device according to a variation of Embodiment 5.

[0040] Figure 13 This is a cross-sectional view of the semiconductor device according to Embodiment 6.

[0041] Figure 14A This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 6.

[0042] Figure 14B This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 6.

[0043] Figure 14C This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 6.

[0044] Figure 14D This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 6.

[0045] Figure 14E This is a cross-sectional view illustrating one step of the manufacturing method of the semiconductor device according to Embodiment 6. Detailed Implementation

[0046] (Summary of this disclosure) The semiconductor device according to a first aspect of this disclosure includes: a first nitride semiconductor layer; a second nitride semiconductor layer disposed above the first nitride semiconductor layer, having a larger band gap than the first nitride semiconductor layer; a p-type third nitride semiconductor layer disposed above the second nitride semiconductor layer; a source electrode and a drain electrode disposed such that the third nitride semiconductor layer is sandwiched between them; an i-type fourth nitride semiconductor layer disposed above the third nitride semiconductor layer, having a larger band gap than the third nitride semiconductor layer, and containing Al; and an i-type fifth nitride semiconductor layer disposed above the fourth nitride semiconductor layer, not containing Al; and a gate electrode disposed above the fifth nitride semiconductor layer.

[0047] Therefore, by providing a fifth nitride semiconductor layer without Al above the fourth nitride semiconductor layer containing Al, oxidation of the upper surface of the fourth nitride semiconductor layer can be suppressed. Consequently, the Schottky characteristics are stable, enabling a stable threshold voltage. Furthermore, since the band gap of the fourth nitride semiconductor layer containing Al is larger than that of the third nitride semiconductor layer, gate leakage current can be reduced. Thus, the semiconductor device according to this embodiment can reduce gate leakage current and suppress threshold voltage deviation.

[0048] Furthermore, when the fourth nitride semiconductor layer with a large bandgap is bonded to the gate electrode in a Schottky configuration, no two-dimensional electron gas (2DEG) is generated near the interface between the first and second nitride semiconductor layers if a large positive bias voltage is not applied to the gate electrode. That is, a normally-off transistor with a large threshold voltage can be realized.

[0049] The semiconductor device of the second aspect of this disclosure is the semiconductor device of the first aspect, wherein at least a portion of the fifth nitride semiconductor layer has a thickness of less than 3 nm.

[0050] Therefore, oxidation of the upper surface of the fourth nitride semiconductor layer can be suppressed, and the threshold voltage can be stabilized. In addition, by thinning the fifth nitride semiconductor layer, unwanted rises in the threshold voltage can be suppressed.

[0051] The semiconductor device of the third aspect of this disclosure includes: a first nitride semiconductor layer; a second nitride semiconductor layer disposed above the first nitride semiconductor layer, having a larger band gap than the first nitride semiconductor layer; a p-type third nitride semiconductor layer disposed above the second nitride semiconductor layer; a source electrode and a drain electrode disposed such that the third nitride semiconductor layer is sandwiched between them; a fourth nitride semiconductor layer disposed above the third nitride semiconductor layer, having a larger band gap than the third nitride semiconductor layer and containing Al; a fifth nitride semiconductor layer disposed above the fourth nitride semiconductor layer and not containing Al; and a gate electrode disposed above the fifth nitride semiconductor layer, wherein at least a portion of the fifth nitride semiconductor layer has a thickness of less than 3 nm.

[0052] Therefore, similar to the first embodiment, a fifth nitride semiconductor layer without Al is disposed above the fourth nitride semiconductor layer containing Al, thus suppressing oxidation of the upper surface of the fourth nitride semiconductor layer. Consequently, the Schottky characteristics are stable, enabling a stable threshold voltage. Furthermore, since the band gap of the fourth nitride semiconductor layer containing Al is larger than that of the third nitride semiconductor layer, the gate leakage current can be reduced. Thus, the semiconductor device according to this embodiment can reduce gate leakage current and suppress threshold voltage deviation.

[0053] Furthermore, when the fourth nitride semiconductor layer with a large bandgap is bonded to the gate electrode in a Schottky configuration, no 2DEG is generated near the interface between the first and second nitride semiconductor layers if a large positive bias voltage is not applied to the gate electrode. That is, a normally-off transistor with a large threshold voltage can be realized.

[0054] The semiconductor device of the fourth aspect of this disclosure is a semiconductor device of any one of the first to third aspects, wherein the fifth nitride semiconductor layer includes an inner region and an outer region located outside the gate length direction in a cross section parallel to the gate length direction and the thickness direction, respectively, and the semiconductor device has an insulating film disposed between the upper surface of the outer region and the gate electrode, and the gate electrode is in contact with the upper surface of the inner region.

[0055] This allows for a shorter actual gate length, thus enabling steeper gate operations. For example, it enables high-speed switching operations.

[0056] The semiconductor device of the fifth aspect of this disclosure is the semiconductor device of the fourth aspect, wherein the thickness of the inner region is thinner than the thickness of the outer region.

[0057] Therefore, by thinning the inner region that contacts the gate electrode, unwanted rises in the threshold voltage can be suppressed. Furthermore, because the outer region is thicker, oxidation of the upper surface of the fourth nitride semiconductor layer can be further suppressed in the direction directly below the outer region.

[0058] The semiconductor device of the sixth aspect of this disclosure is the semiconductor device of the fifth aspect, wherein the difference between the thickness of the outer region and the thickness of the inner region is 1 nm or more.

[0059] Therefore, it is possible to both suppress unnecessary rises in threshold voltage and suppress oxidation of the upper surface of the fourth nitride semiconductor layer.

[0060] The semiconductor device of the seventh aspect of this disclosure is a semiconductor device of any one of the fourth to sixth aspects, wherein the length of the outer region in the gate length direction is 0.1 μm or more.

[0061] Therefore, during conduction, the gate current mainly flows through the inner region, preventing it from flowing through the side where the gate current might be rendered ineffective. This helps suppress deviations in the Schottky characteristics.

[0062] The semiconductor device of the eighth aspect of this disclosure is a semiconductor device of any one of the fourth to seventh aspects, wherein the hydrogen concentration in the inner region is higher than the p-type impurity concentration in the inner region.

[0063] In the fifth nitride semiconductor layer, p-type impurities sometimes diffuse from the third nitride semiconductor layer through the fourth nitride semiconductor layer. According to this method, the charge caused by the p-type impurities can be neutralized by hydrogen. Therefore, the Schottky characteristics of the gate electrode are improved, enabling the realization of a normally-off transistor with a large threshold voltage.

[0064] The semiconductor device of the ninth aspect of this disclosure is a semiconductor device of any one of the fourth to eighth aspects, wherein an n-type sixth nitride semiconductor layer is provided between the upper surface of the outer region and the insulating film.

[0065] Therefore, the charge caused by p-type impurities diffusing into the fifth nitride semiconductor layer can be neutralized by n-type impurities. This improves the Schottky characteristics of the gate electrode, enabling normally-off transistors with large threshold voltages.

[0066] The semiconductor device of the tenth aspect of this disclosure is a semiconductor device of the ninth aspect, wherein the boundary between the inner region and the outer region is coplanar with a portion of the side surface of the sixth nitride semiconductor layer.

[0067] Therefore, the sixth nitride semiconductor layer of the n-type can be left unplaced in the inner region, thus suppressing the degradation of Schottky characteristics.

[0068] The semiconductor device of the eleventh aspect of this disclosure is a semiconductor device of any one of the first to tenth aspects, wherein the third nitride semiconductor layer comprises GaN as the main component.

[0069] Therefore, compared with mixed crystals such as AlGaN, p-type dopants have a higher activation rate and thus are more likely to maintain their normally-off characteristics.

[0070] The semiconductor device of the 12th aspect of this disclosure is a semiconductor device of any one of the 1st to 11th aspects, wherein the fourth nitride semiconductor layer comprises AlGaN as the main component.

[0071] This increases the resistivity between the gate electrode and the 2DEG, thereby reducing gate leakage current.

[0072] The semiconductor device of the 13th aspect of this disclosure is a semiconductor device of any one of the 1st to 12th aspects, wherein the 5th nitride semiconductor layer comprises GaN as the main component.

[0073] Therefore, oxidation of the upper surface of the fourth nitride semiconductor layer can be suppressed, and the threshold voltage can be stabilized.

[0074] The semiconductor device of the 14th aspect of this disclosure is a semiconductor device of any one of the 1st to 13th aspects, wherein a 7th nitride semiconductor layer is provided, the 7th nitride semiconductor layer is disposed between the 3rd nitride semiconductor layer and the 4th nitride semiconductor layer, and the 7th nitride semiconductor layer has a larger band gap than the 4th nitride semiconductor layer.

[0075] Therefore, the 7th nitride semiconductor layer functions as a band barrier layer between the 3rd and 4th nitride semiconductor layers. Since the resistive component between the gate electrode and the 2DEG can be further improved, the gate leakage current can be reduced.

[0076] The semiconductor device of the 15th aspect of this disclosure is the semiconductor device of the 14th aspect, wherein the thickness of the 7th nitride semiconductor layer is less than 3 nm.

[0077] Therefore, it is possible to suppress crystal defects in the upper layer caused by lattice mismatch between the third and seventh nitride semiconductor layers. Consequently, it is possible to suppress the degradation of the Schottky characteristics of the gate electrode and the fourth nitride semiconductor layer.

[0078] The semiconductor device of the 16th aspect of this disclosure is a semiconductor device of any one of the 1st to 15th aspects, wherein a p-type 8th nitride semiconductor layer is provided, the p-type 8th nitride semiconductor layer is disposed in the 2nd nitride semiconductor layer at a position overlapping the 3rd nitride semiconductor layer in planar view, and the upper surface of the 8th nitride semiconductor layer is coplanar with the upper surface of the 2nd nitride semiconductor layer.

[0079] This allows for thinning of the portion of the third nitride semiconductor layer located directly below the gate electrode. It enables the adjustment of the threshold voltage while maintaining a low resistance without affecting the concentration of 2DEG between the gate and drain or between the gate and source.

[0080] The method for manufacturing a semiconductor device according to the 17th aspect of this disclosure includes: a first step of sequentially forming a first nitride semiconductor layer and a second nitride semiconductor layer with a band gap larger than the first nitride semiconductor layer; a second step of sequentially forming a p-type third nitride semiconductor layer, a fourth nitride semiconductor layer with a band gap larger than the third nitride semiconductor layer and containing Al, and an i-type fifth nitride semiconductor layer without Al above the second nitride semiconductor layer; a third step of forming a source electrode and a drain electrode in such a way that the third nitride semiconductor layer is sandwiched in between; and a fourth step of forming a gate electrode above the fifth nitride semiconductor layer.

[0081] Therefore, by providing a fifth nitride semiconductor layer without Al above the fourth nitride semiconductor layer containing Al, oxidation of the upper surface of the fourth nitride semiconductor layer can be suppressed. Consequently, the Schottky characteristics are stable, enabling a stable threshold voltage. Furthermore, since the band gap of the fourth nitride semiconductor layer containing Al is larger than that of the third nitride semiconductor layer, gate leakage current can be reduced. Thus, according to this method, a semiconductor device with reduced gate leakage current and suppressed threshold voltage deviation can be manufactured.

[0082] Furthermore, when the fourth nitride semiconductor layer with a large bandgap is bonded to the Schottky gate electrode, 2DEG is not generated unless a large forward bias voltage is applied to the gate electrode. That is, it is possible to fabricate normally-off transistors with a large threshold voltage.

[0083] The method for manufacturing a semiconductor device according to the 18th aspect of this disclosure includes: a first step of sequentially forming a first nitride semiconductor layer and a second nitride semiconductor layer with a band gap larger than the first nitride semiconductor layer; a second step of sequentially forming a p-type third nitride semiconductor layer, a fourth nitride semiconductor layer with a band gap larger than the third nitride semiconductor layer and containing Al, and a fifth nitride semiconductor layer without Al above the second nitride semiconductor layer; a third step of forming a source electrode and a drain electrode in such a way that the third nitride semiconductor layer is sandwiched in between; and a fourth step of forming a gate electrode above the fifth nitride semiconductor layer, wherein at least a portion of the fifth nitride semiconductor layer has a thickness of less than 3 nm.

[0084] Therefore, similar to the 17th embodiment, a 5th nitride semiconductor layer without Al is disposed above the 4th nitride semiconductor layer containing Al, thus suppressing oxidation of the upper surface of the 4th nitride semiconductor layer. Consequently, the Schottky characteristics are stable, enabling a stable threshold voltage. Furthermore, since the band gap of the 4th nitride semiconductor layer containing Al is larger than that of the 3rd nitride semiconductor layer, the gate leakage current is reduced. Thus, according to this embodiment, a semiconductor device with reduced gate leakage current and suppressed threshold voltage deviation can be manufactured.

[0085] Furthermore, when the fourth nitride semiconductor layer with a large bandgap is bonded to the Schottky gate electrode, 2DEG is not generated unless a large forward bias voltage is applied to the gate electrode. That is, it is possible to fabricate normally-off transistors with a large threshold voltage.

[0086] The method for manufacturing a semiconductor device according to the 19th aspect of this disclosure is a method for manufacturing a semiconductor device according to the 17th or 18th aspect, wherein the 5th nitride semiconductor layer includes an inner region and an outer region located on the outer side of the gate length direction in a cross section parallel to the gate length direction and the thickness direction, respectively, and the method for manufacturing the semiconductor device includes a 5th step of forming a 1st insulating film covering the upper surface of the outer region, wherein in the 4th step, the gate electrode is formed in a manner that contacts the upper surface of the inner region.

[0087] This allows for a shorter actual gate length, thus enabling steeper gate operations. For example, it enables high-speed switching operations.

[0088] The semiconductor device manufacturing method of the 20th aspect of this disclosure is a semiconductor device manufacturing method of the 19th aspect, wherein a 6th step is included, wherein the thickness of the inner region is thinner than the thickness of the outer region by etching the first insulating film as a mask.

[0089] Therefore, by thinning the inner region that contacts the gate electrode, unwanted rises in the threshold voltage can be suppressed. Furthermore, because the outer region is thicker, oxidation of the upper surface of the fourth nitride semiconductor layer can be further suppressed in the direction directly below the outer region.

[0090] The semiconductor device manufacturing method of the 21st aspect of this disclosure is the semiconductor device manufacturing method of the 20th aspect, wherein the etching is a dry etching using a gas containing hydrogen.

[0091] Thus, by allowing hydrogen to penetrate the inner region, the charge caused by p-type impurities diffusing from the third nitride semiconductor layer can be neutralized. Consequently, the Schottky characteristics of the gate electrode are improved, and 2DEG is not generated unless a large forward bias voltage is applied to the gate electrode. That is, a normally-off transistor with a large threshold voltage can be realized.

[0092] The semiconductor device manufacturing method of the 22nd aspect of this disclosure is a semiconductor device manufacturing method of the 20th or 21st aspect, wherein, in the 6th step, etching is performed until the thickness of the inner region is less than 3 nm.

[0093] Therefore, oxidation of the upper surface of the fourth nitride semiconductor layer can be suppressed, and the threshold voltage can be stabilized. In addition, by thinning the fifth nitride semiconductor layer, unwanted rises in the threshold voltage can be suppressed.

[0094] The semiconductor device manufacturing method of the 23rd aspect of this disclosure is a semiconductor device manufacturing method of any one of the 19th to 22nd aspects, wherein, after the first step and before the second step, a 7th step is included to form a second insulating film having an opening, and in the second step, the 3rd nitride semiconductor layer, the 4th nitride semiconductor layer and the 5th nitride semiconductor layer are formed in the opening.

[0095] Therefore, the second nitride semiconductor layer and the second insulating film can be formed continuously, thus suppressing oxidation of the upper surface of the second nitride semiconductor layer. Since impurity levels are less likely to form on the upper surface of the second nitride semiconductor layer, the lateral breakdown voltage can be improved.

[0096] The semiconductor device manufacturing method of the 24th aspect of this disclosure is a semiconductor device manufacturing method of any one of the 17th to 22nd aspects, wherein, in the second step, a nitride semiconductor layer is formed by continuously performing crystal growth from the first step, and the third nitride semiconductor layer, the fourth nitride semiconductor layer, and the fifth nitride semiconductor layer are formed by patterning the formed nitride semiconductor layer.

[0097] Therefore, the second and third nitride semiconductor layers can be formed continuously, making it less likely for impurity levels to form at the interface. This allows for a stable threshold voltage. Furthermore, it reduces gate leakage current.

[0098] The semiconductor device manufacturing method of the 25th aspect of this disclosure is a semiconductor device manufacturing method of the 24th aspect, wherein, in the patterning of the stacked film, the gate electrode is etched as a mask.

[0099] Therefore, the gate electrode, the third nitride semiconductor layer, and the fourth nitride semiconductor layer can be formed simultaneously. Because the gate length can be shortened, steeper gate operation is possible. Furthermore, because the parasitic resistance of the transistor can be reduced, the on-resistance can be lowered.

[0100] The method for manufacturing a semiconductor device according to the 26th aspect of this disclosure is a method for manufacturing a semiconductor device according to any one of the 17th to 25th aspects, wherein, in the second step, an n-type sixth nitride semiconductor layer is formed above the fifth nitride semiconductor layer.

[0101] Therefore, the charge caused by p-type impurities diffusing into the fifth nitride semiconductor layer can be neutralized by n-type impurities. This improves the Schottky characteristics of the gate electrode, enabling normally-off transistors with large threshold voltages.

[0102] The semiconductor device manufacturing method of the 27th aspect of this disclosure is a semiconductor device manufacturing method of any one of the 17th to 26th aspects, wherein, in the second step, a 7th nitride semiconductor layer with a larger band gap than the 4th nitride semiconductor layer is formed between the 3rd nitride semiconductor layer and the 4th nitride semiconductor layer.

[0103] Therefore, the 7th nitride semiconductor layer functions as a band barrier layer between the 3rd and 4th nitride semiconductor layers. Since the resistive component between the gate electrode and the 2DEG can be further improved, the gate leakage current can be reduced.

[0104] The embodiments will now be described in detail with reference to the accompanying drawings.

[0105] Furthermore, the embodiments described below are either general or specific examples. The numerical values, shapes, materials, constituent elements, the arrangement and connection methods of the constituent elements, the steps, and the order of the steps shown in the following embodiments are examples and are not intended to limit this disclosure. In addition, the constituent elements in the following embodiments that are not described in the independent claims are described as optional constituent elements.

[0106] Furthermore, these figures are schematic diagrams and may not be strictly representational. Therefore, for example, the scale may not be consistent across different figures. Additionally, substantially identical structures are labeled with the same reference numerals across different figures, and repetitive descriptions are omitted or simplified.

[0107] Furthermore, in this specification, terms such as parallel and perpendicular that indicate the relationship between elements, terms that indicate the shape of elements, and numerical ranges do not only indicate a strict meaning, but also mean that they include substantially equal ranges, such as differences of a few percent.

[0108] Furthermore, in this specification, the terms "above" and "below" do not refer to the absolute spatial orientation of upward (vertically above) and downward (vertically below), but are used as terms defined by relative positional relationships based on the stacking order in a stacked structure. Additionally, the terms "above" and "below" apply not only to cases where two constituent elements are arranged spaced apart from each other and another constituent element exists between them, but also to cases where two constituent elements are arranged close together and connected. In this specification, the direction in which the gate electrode is disposed is considered "above" relative to the substrate. Furthermore, in this specification, unless otherwise specified, "planar view" refers to the view taken from a direction perpendicular to the upper surface of the substrate.

[0109] Furthermore, in this specification, a nitride semiconductor is a group III nitride semiconductor that contains one or more group III elements and nitrogen. Examples of group III elements include aluminum (Al), gallium (Ga), and indium (In). Examples of group III nitride semiconductors include GaN, AlN, InN, AlGaN, InGaN, and AlInGaN. Group III nitride semiconductors may also contain one or more elements other than group III, such as silicon (Si), phosphorus (P), and magnesium (Mg). Additionally, in the following description, unless otherwise specified, AlInGaN refers to a group III nitride semiconductor that simultaneously contains Al, In, Ga, and N. The same applies to other designations such as AlGaN and GaN.

[0110] In this specification, n-type and p-type refer to the conductivity types of a semiconductor, which are conductivity types with opposite polarities. Typically, i-type represents the so-called undoped state, where no n-type or p-type dopants are added. However, n-type or p-type dopants can also be added to the i-type semiconductor layer, provided that the n-type or p-type dopants are not activated. Furthermore, impurities that are not n-type or p-type dopants can also be added to the i-type semiconductor layer.

[0111] In addition, in this specification, "main component" refers to the component with the highest content among all the components constituting the component. For example, a component with a content of 50% or more is a main component. Components can be materials, elements, or compounds, etc.

[0112] (Implementation Method 1) First, the semiconductor device of Embodiment 1 will be described.

[0113] Figure 1 This is a cross-sectional view of the semiconductor device 1 according to this embodiment. Specifically, Figure 1 This represents a cross-section parallel to both the gate length direction and the thickness direction. Furthermore, the gate length direction is... Figure 1The left-right direction is the arrangement direction of the source electrode 32, gate electrode 30, and drain electrode 34. The gate length direction is sometimes referred to as the channel length direction. Additionally, the thickness direction is... Figure 1 The vertical direction is perpendicular to the main surface of the substrate 10. The thickness direction is sometimes referred to as the stacking direction.

[0114] Figure 1 The semiconductor device 1 shown is a normally-off HEMT (High Electron Mobility Transistor). The semiconductor device 1 includes a substrate 10, a buffer layer 12, a channel layer 14, a barrier layer 16, a p-type semiconductor layer 18, an Al-containing layer 20, an Al-free layer 22, a gate electrode 30, a source electrode 32, a drain electrode 34, and an insulating film 40.

[0115] Substrate 10 is the support substrate that supports the main structure of HEMT. Substrate 10 is, for example, a Si substrate, but it can also be an SOI (Silicon on Insulator) substrate. Alternatively, substrate 10 can also be a substrate containing SiC, Sapphire, diamond, GaN, or AlN as the main components.

[0116] The buffer layer 12 is a nitride semiconductor layer containing nitride semiconductor as the main component. The buffer layer 12 is provided to mitigate the lattice mismatch between the substrate 10 and the channel layer 14. For example, the buffer layer 12 has a superlattice structure formed by alternating layers of AlN film and AlGaN film, but is not limited to this. Other layers, such as a back barrier layer, may also be provided between the buffer layer 12 and the channel layer 14. The back barrier layer is, for example, a layer with a band gap larger than that of the channel layer 14, and is a nitride semiconductor layer containing i-type AlGaN as the main component, but is not limited to this. Alternatively, the buffer layer 12 and the substrate 10 may not be provided.

[0117] The channel layer 14 is an example of a first nitride semiconductor layer, sometimes referred to as an electron transport layer. The channel layer 14 contains, but is not limited to, i-type GaN as the main component. For example, the channel layer 14 may also contain i-type InGaN, AlGaN, InAlGaN, etc., as the main component.

[0118] Barrier layer 16 is an example of a second nitride semiconductor layer, sometimes referred to as an electron supply layer. Barrier layer 16 is disposed above channel layer 14 and has a larger band gap than channel layer 14. Barrier layer 16 contains i-type AlGaN as the main component, but is not limited to this. Barrier layer 16 may also contain i-type GaN, InAlGaN, etc., as the main component.

[0119] The barrier layer 16 contacts the upper surface of the channel layer 14, forming a heterojunction. Electrons generated by piezoelectric polarization and spontaneous polarization accumulate along the interface between the barrier layer 16 and the channel layer 14, generating 2DEG on the channel layer 14 side of the interface. By controlling the generation and disappearance of 2DEG using the potential applied to the gate electrode 30, the semiconductor device 1 can operate as a transistor.

[0120] Furthermore, 2DEG can be generated within the channel layer 14, and the barrier layer 16 and the channel layer 14 do not need to be in contact. For example, a nitride semiconductor layer such as AlN can also be disposed between the barrier layer 16 and the channel layer 14.

[0121] The p-type semiconductor layer 18 is an example of a p-type third nitride semiconductor layer. The p-type semiconductor layer 18 is disposed above the barrier layer 16. For example, the p-type semiconductor layer 18 is disposed in contact with the upper surface 16a of the barrier layer 16. The p-type semiconductor layer 18 contains p-type GaN as the main component. Compared to mixed crystals such as AlGaN, p-type dopants have a higher activation rate, thus making it easier to maintain normally-off characteristics. For example, Mg can be used as a p-type dopant. Alternatively, the p-type semiconductor layer 18 may also contain p-type AlGaN, InGaN, InAlGaN, etc., as the main component.

[0122] A p-type semiconductor layer 18 is disposed between and separately from the source electrode 32 and the drain electrode 34. For example... Figure 1 As shown, the side of the p-type semiconductor layer 18 faces the source electrode 32 or the drain electrode 34, and does not contact either the source electrode 32 or the drain electrode 34.

[0123] The Al-containing layer 20 is an example of a fourth nitride semiconductor layer containing Al. The Al-containing layer 20 is disposed above the p-type semiconductor layer 18, and its band gap is larger than that of the p-type semiconductor layer 18. For example, the Al-containing layer 20 is disposed in contact with the upper surface of the p-type semiconductor layer 18. The Al-containing layer 20 contains i-type AlGaN as its main component. This improves the resistive component between the gate electrode 30 and the 2DEG, thereby reducing the gate leakage current. Alternatively, the Al-containing layer 20 may also contain i-type GaN, InGaN, InAlGaN, etc., as its main component. Furthermore, the conductivity type of the Al-containing layer 20 is i-type, but it can also be p-type or n-type.

[0124] The Al-free layer 22 is an example of an Al-free fifth nitride semiconductor layer. The Al-free layer 22 is disposed above the Al-containing layer 20. For example, the Al-free layer 22 is disposed in contact with the upper surface of the Al-containing layer 20. For example, the Al-free layer 22 contains i-type GaN as its main component. This suppresses oxidation of the upper surface of the Al-containing layer 20, thereby stabilizing the threshold voltage. Furthermore, the Al-free layer 22 may also contain i-type InGaN, InN, etc., as its main component. Additionally, the conductivity type of the Al-free layer 22 is i-type, but it can also be p-type or n-type.

[0125] A cross-section of the excluding Al layer 22 that is parallel to both the gate length direction and the thickness direction ( Figure 1 The cross-section shown includes an inner region 23 and an outer region 24. The outer region 24 is located outside the inner region 23 in the gate length direction. The outer region 24 is disposed on both the source electrode 32 side and the drain electrode 34 side of the inner region 23. In this embodiment, the thickness of the inner region 23 is the same as the thickness of the outer region 24.

[0126] The gate electrode 30 is disposed above the surface without the Al layer 22. For example, the gate electrode 30 contacts and covers the upper surface without the Al layer 22. Specifically, the gate electrode 30 contacts the upper surface 23a of the inner region 23 without the Al layer 22 via an opening 41 provided in the insulating film 40.

[0127] The gate electrode 30 may contain conductive materials such as elemental metals, metal alloys, or metal nitrides as the main component. For example, the gate electrode 30 may have a monolayer structure containing a conductive film with Ti or TiN as the main component. Alternatively, the gate electrode 30 may also have a stacked structure of multiple conductive films. For example, the gate electrode 30 may also be a conductive film containing Al, W, or WSi as the main component.

[0128] The source electrode 32 and the drain electrode 34 are arranged such that the p-type semiconductor layer 18 is sandwiched in between. Specifically, the source electrode 32 and the drain electrode 34 sandwich the p-type semiconductor layer 18, the Al-containing layer 20, the Al-free layer 22, and the gate electrode 30 in between.

[0129] In this embodiment, the source electrode 32 and the drain electrode 34 are disposed in contact with the upper surface 16a of the barrier layer 16. Both the source electrode 32 and the drain electrode 34 are electrically connected to the 2DEG.

[0130] The source electrode 32 and drain electrode 34 contain a conductive material as the main component that is ohmically connected to the n-type nitride semiconductor. For example, the source electrode 32 and drain electrode 34 have a stacked structure of a conductive film containing Ti as the main component, a conductive film containing Al as the main component, and a conductive film containing Ti as the main component. Alternatively, the source electrode 32 and drain electrode 34 may also have a single-layer structure of a conductive film. The conductive film may be a metal film containing an elemental metal as the main component, a metal film containing an alloy of metals as the main component, or a conductive metal nitride film, etc. Furthermore, the source electrode 32 and drain electrode 34 may contain the same material as each other as the main component, but they may also contain different materials as the main components.

[0131] At least one of the source electrode 32 and the drain electrode 34 can be in contact with the channel layer 14. For example, a source opening and a drain opening can be provided that penetrate the barrier layer 16 and reach the channel layer 14, or the source electrode 32 can be provided in a manner that covers the bottom and side surfaces of the source opening, and the drain electrode 34 can be provided in a manner that covers the bottom and side surfaces of the drain opening.

[0132] The insulating film 40 is an example of the first insulating film, and is disposed between the upper surface 24a of the outer region 24 (excluding the Al layer 22) and the gate electrode 30. By providing the insulating film 40, the gate electrode 30 does not contact the upper surface 24a of the outer region 24.

[0133] In this embodiment, the insulating film 40 not only covers the upper surface 24a of the outer region 24, but also covers the sides of the layer without Al layer 22, the layer with Al layer 20, and the p-type semiconductor layer 18, as well as the upper surface 16a of the barrier layer 16. For example, in planar view, the insulating film 40 contacts and covers the upper surface 16a of the barrier layer 16 between the gate electrode 30 and the source electrode 32, and between the gate electrode 30 and the drain electrode 34.

[0134] Openings 41, 42, and 43 are provided in the insulating film 40. Opening 41 is provided in plan view at a position overlapping with the inner region 23 without Al layer 22. Opening 41 is provided to expose the upper surface 23a of the inner region 23 and to allow the upper surface 23a to contact the gate electrode 30.

[0135] The opening 42 is provided to expose the upper surface 16a of the barrier layer 16 and to allow the upper surface 16a to contact the source electrode 32. The opening 43 is provided to expose the upper surface 16a of the barrier layer 16 and to allow the upper surface 16a to contact the drain electrode 34. In this embodiment, the source electrode 32 and the drain electrode 34 respectively cover the ends of the openings 42 and 43, but this is not a limitation. The insulating film 40 may also not be in contact with the source electrode 32 or the drain electrode 34.

[0136] The insulating film 40 may contain SiN as a main component, but is not limited to this. The insulating film 40 may also contain SiO2, SiON, Al2O3, etc., as main components. Furthermore, the insulating film 40 may have a single-layer structure or a stacked structure of multiple insulating films. The insulating film 40 is formed by plasma CVD (Chemical Vapor Deposition) or similar methods.

[0137] By providing the insulating film 40, the lateral breakdown voltage of the semiconductor device 1 can be improved. Specifically, the breakdown voltage between the gate and drain can be improved.

[0138] As described above, in the semiconductor device 1 of this embodiment, an Al-containing layer 20 is provided between the p-type semiconductor layer 18 and the gate electrode 30. Since the band gap of the Al-containing layer 20 is larger than that of the p-type semiconductor layer 18, the resistance between the gate electrode 30 and the p-type semiconductor layer 18 becomes higher. Therefore, the gate leakage current can be reduced.

[0139] Furthermore, since an Al-free layer 22 is disposed above the Al-containing layer 20, oxidation of the upper surface of the Al-containing layer 20 can be suppressed. Therefore, the Schottky characteristics are stable, and the threshold voltage can be stabilized.

[0140] Furthermore, when the Al-containing layer 20 with a large bandgap is Schottky bonded to the gate electrode 30, no 2DEG is generated near the interface between the channel layer 14 and the barrier layer 16 if a large forward bias voltage is not applied to the gate electrode 30. That is, the semiconductor device 1 can be operated as a normally-off transistor with a large threshold voltage.

[0141] As an example, the dimensions of the main components of semiconductor device 1 can be as follows.

[0142] The thickness of the channel layer 14 is, for example, 100 nm or more and 400 nm or less, with 200 nm as an example. The thickness of the barrier layer 16 is, for example, 10 nm or more and 80 nm or less, with 30 nm as an example. The thickness of the p-type semiconductor layer 18 is, for example, 50 nm or more and 200 nm or less, with 100 nm as an example. The thickness of the Al-containing layer 20 is, for example, 5 nm or more and 30 nm or less, with 20 nm as an example. The thickness of the Al-free layer 22 is, for example, 0.5 nm or more and less than 3 nm, with 2 nm as an example. For example, the Al-containing layer 20 is thinner than the p-type semiconductor layer 18 and thicker than the Al-free layer 22. By having the Al-free layer 22 less than 3 nm in thickness, unwanted rises in threshold voltage can be suppressed.

[0143] The gate lengths of the p-type semiconductor layer 18, the Al-containing layer 20, and the non-Al-containing layer 22 are, for example, 1 μm or more and 2 μm or less. The gate lengths of the p-type semiconductor layer 18, the Al-containing layer 20, and the non-Al-containing layer 22 are equal, for example, 1.6 μm. In the p-type semiconductor layer 18, the concentration of the p-type dopant is 1 × 10⁻⁶. 19 cm -3 Above and 2×10 20 cm -3 The following is an example of 6×10 19 cm -3 The concentration of p-type dopants can be determined, for example, by secondary ion mass spectrometry (SIMS).

[0144] The length L2 of the outer region 24 on the source electrode 32 side (left side) without Al layer 22 in the gate length direction is, for example, 0.1 μm or more and 0.3 μm or less, and 0.2 μm as an example. The length L2 of the outer region 24 on the drain electrode 34 side (right side) without Al layer 22 in the gate length direction is, for example, 0.1 μm or more and 0.3 μm or less, and 0.2 μm as an example. By setting the length L2 of the outer region 24 to 0.1 μm or more, it is possible to separate the region through which the gate current mainly flows during conduction (specifically, the inner region 23) from the side surface of the gate structure. When the gate current flows through the side surface of the gate structure, it may be ineffective. Therefore, by moving the inner region 23 away from the side surface of the gate structure, deviations in Schottky characteristics can be suppressed. Furthermore, the length L2 of the outer region 24 is equal on both sides of the inner region 23, but it may also be different. In addition, the outer region 24 can be considered as the region covered by the insulating film 40 when viewing the substrate 10 in planar view.

[0145] When viewing the substrate 10 in planar view, the inner region 23 can be considered as a region not covered by the insulating film 40, that is, a region exposed at the opening 41 of the insulating film 40. The length L1 of the inner region 23 in the gate length direction is, for example, 0.4 μm or more and 1.8 μm or less, and 1.2 μm as an example. The length L1 of the inner region 23 in the gate length direction corresponds to the gate length of the semiconductor device 1. The gate length is shorter than the length of the gate electrode 30 in the gate length direction, thus enabling steep gate operation.

[0146] Furthermore, the thickness of the gate electrode 30 is, for example, 200 nm or more and 500 nm or less, with 400 nm being an example. Additionally, in Figure 1The diagram shows an example where the upper surface of the gate electrode 30 is coplanar, and a step is provided on the lower surface, with the thickness of the gate electrode 30 varying depending on its position. In this case, the thickness of the gate electrode 30 is represented by the distance between the upper surface of the gate electrode 30 and the upper surface (upper surface 23a) without the Al layer 22. Furthermore, even if the thickness of the gate electrode 30 is substantially uniform, a step (recess) corresponding to the step on the lower surface may be provided on the upper surface. The length L of the gate electrode 30 in the gate length direction is... G For example, it is between 1μm and 2μm, with 1.6μm as an example.

[0147] The thickness of the insulating film 40 is, for example, more than 100 nm and less than 300 nm, and for example, 140 nm.

[0148] In addition, such as Figure 1 As shown, the distance L between the source electrode 32 and the p-type semiconductor layer 18 GS For example, a diameter of 1 μm or larger but less than 3 μm, with 2 μm as an example. The distance L between the drain electrode 34 and the p-type semiconductor layer 18. GD For example, a value between 7 μm and 13 μm is considered as 10 μm. Additionally, the distance L... GS This is equivalent to the so-called gate-source distance, distance L GD This is equivalent to the so-called gate-drain distance. By making the gate-drain distance L... GD The increased length improves pressure resistance. Figure 1 In the middle, L is shown GS With L GD Same example, but L GS It can also be compared to L GD short.

[0149] [Manufacturing Method] Next, the manufacturing method of the semiconductor device 1 of this embodiment will be described.

[0150] The method for manufacturing semiconductor device 1 includes: a first step and a second step, sequentially forming a plurality of nitride semiconductor layers; a third step, forming a source electrode 32 and a drain electrode 34; a fourth step, forming a gate electrode 30; and a fifth step, forming an insulating film. In this embodiment, the steps are performed in the order of the first step, the second step, the fifth step, the third step, and the fourth step. Hereinafter, [the method will use...] Figures 2A-2D Please provide a detailed explanation of each process. Figures 2A-2D These are cross-sectional views of each step in the manufacturing method of the semiconductor device 1 according to this embodiment.

[0151] First, such as Figure 2AAs shown, in the first step, a channel layer 14 and a barrier layer 16 are formed sequentially. Then, in the second step, a p-type semiconductor layer 18, an Al-containing layer 20, and an Al-free layer 22 are formed sequentially. In the second step of this embodiment, a nitride semiconductor layer is formed by continuously performing crystal growth from the first step. This layer is a layer comprising the p-type semiconductor layer 18 before it is patterned into a predetermined shape, the Al-containing layer 20, and the Al-free layer 22. Specifically, a nitride semiconductor film is formed on the upper surface of the substrate 10 by epitaxial growth, thereby sequentially forming a buffer layer 12, a channel layer 14, a barrier layer 16, a p-type semiconductor layer 18, an Al-containing layer 20, and an Al-free layer 22. By adjusting the introduced gas, dopant, growth temperature, growth time, etc., during epitaxial growth, the composition and thickness of each layer can be controlled.

[0152] Next, as Figure 2B As shown, in the second step, a p-type semiconductor layer 18, an Al-containing layer 20, and an Al-free layer 22 of a predetermined shape are formed by patterning the formed stacked film. For example, portions of the Al-free layer 22, the Al-containing layer 20, and the p-type semiconductor layer 18 located outside the gate region are selectively removed by photolithography and dry etching. In the region outside the gate region, the upper surface 16a of the barrier layer 16 is exposed.

[0153] Next, as Figure 2C As shown, as the fifth step, an insulating film 40 is formed. For example, the insulating film 40 is formed as a SiN film by plasma CVD in a manner that covers the upper surface 16a of the barrier layer 16 and the upper surface 22a without the Al layer 22.

[0154] Next, as Figure 2D As shown, as the third process, the source electrode 32 and the drain electrode 34 are formed with the p-type semiconductor layer 18 sandwiched in between. Specifically, firstly, openings 42 and 43 are formed in the insulating film 40. For example, the areas in the insulating film 40 used to form the source electrode 32 and the drain electrode 34 are removed by photolithography and dry etching, thereby forming the openings 42 and 43. Then, for example, after forming a conductive film over the entire surface by sputtering or evaporation, the conductive film is patterned into a predetermined shape by photolithography and dry etching, thereby forming the source electrode 32 and the drain electrode 34. Patterning can also be performed by a lift-off method. Alternatively, the source electrode 32 and the drain electrode 34 can be formed by different processes.

[0155] Next, as the fourth step, a gate electrode 30 is formed above the Al-free layer 22. Specifically, firstly, an opening 41 is formed in the insulating film 40. For example, the portion above the inner region 23 of the insulating film 40 without the Al-free layer 22 is removed by photolithography and dry etching, thereby forming the opening 41. The portion of the Al-free layer 22 exposed in the opening 41 is the inner region 23. In the opening 41, the upper surface 23a of the inner region 23 is exposed. Then, for example, after forming a conductive film over the entire surface by sputtering or vapor deposition, the conductive film is patterned into a predetermined shape by photolithography and dry etching, thereby forming the gate electrode 30. Patterning can also be performed by a lift-off method. Thus, the gate electrode 30 contacts the upper surface 23a of the inner region 23 via the opening 41. Furthermore, the portion of the Al-free layer 22 covered by the insulating film 40 is the outer region 24. The upper surface 24a of the outer region 24 is covered by the insulating film 40 and does not contact the gate electrode 30.

[0156] Through the above processes, it is possible to manufacture Figure 1 Semiconductor device 1 is shown.

[0157] Typically, the substrate 10 is transported between the crystal growth process and the etching process, thus exposing the substrate 10 to the atmosphere during this transport. In the manufacturing method of the semiconductor device 1 of this embodiment, if using Figure 2A As explained, an Al-containing layer 20 and an Al-free layer 22 are formed sequentially. Even if the substrate 10 is exposed to the atmosphere for etching after the Al-free layer 22 is formed, it will not be exposed to the atmosphere because the upper surface of the Al-containing layer 20 is covered by the Al-free layer 22. Therefore, oxidation of the upper surface of the Al-containing layer 20 is suppressed, thereby suppressing deviations in Schottky characteristics.

[0158] Furthermore, the manufacturing method of semiconductor device 1 is not limited to the examples described above. The fourth step of forming the gate electrode 30 may also be performed before the third step of forming the source electrode 32 and the drain electrode 34. In addition, the openings 41, 42 and 43 may also be formed in the same step.

[0159] (Implementation Method 2) Next, Embodiment 2 will be described. Hereinafter, the description will focus on the differences from Embodiment 1, and the description of the commonalities will be omitted or simplified.

[0160] [structure] Figure 3 This is a cross-sectional view of the semiconductor device 100 of this embodiment. Figure 4 This is a cross-sectional view showing an enlarged view of the vicinity of the gate structure of the semiconductor device 100 in this embodiment. (See attached image.) Figure 3 as well as Figure 4 As shown, the semiconductor device 100 has an Al-free layer 122 instead of an Al-free layer 22, compared to the semiconductor device 1 of Embodiment 1.

[0161] Al-free layer 122 is an example of an Al-free fifth nitride semiconductor layer, and its cross-sectional shape differs from that of Al-free layer 22. Specifically, unlike Al-free layer 22 which has a uniform thickness, Al-free layer 122 contains portions of varying thickness. Furthermore, Al-free layer 122 has an i-type conductivity, but it could also be p-type or n-type.

[0162] like Figure 3 as well as Figure 4 As shown, the region excluding the Al layer 122 includes an inner region 123 and an outer region 124. The thickness T1 of the inner region 123 is thinner than the thickness T2 of the outer region 124. Specifically, the lower surfaces of the inner region 123 and the outer region 124 are coplanar, and a step is formed on their upper surfaces. More specifically, the upper surface 123a of the inner region 123 is located below (on the substrate 10 side) the upper surface 124a of the outer region 124.

[0163] Therefore, by thinning the inner region 123 that contacts the gate electrode 30, it is possible to suppress unnecessary rises in the threshold voltage. In addition, since the outer region 124 is thick, oxidation of the upper surface containing the Al layer 20 can be further suppressed in the direction directly below the outer region 124.

[0164] For example, the thickness T1 of the inner region 123 is 0.5 nm or more and less than 3 nm, with 2 nm being an example. Furthermore, the difference between the thickness T2 of the outer region 124 and the thickness T1 of the inner region 123 is 1 nm or more. By increasing the difference between the thickness T2 and the thickness T1, it is possible to both suppress unnecessary rises in the threshold voltage and suppress oxidation of the upper surface containing the Al layer 20.

[0165] Furthermore, in this embodiment, the hydrogen concentration in the inner region 123 is higher than the p-type impurity concentration in the inner region 123. In the absence of the Al layer 122, p-type impurities (p-type dopants) sometimes diffuse from the p-type semiconductor layer 18 via the Al-containing layer 20. Because of the high hydrogen concentration in the inner region 123, the charge caused by the p-type impurities can be neutralized by hydrogen. Therefore, the Schottky characteristics of the gate electrode 30 are improved, enabling the realization of a normally-off transistor with a large threshold voltage.

[0166] Next, the manufacturing method of the semiconductor device 100 of this embodiment will be described.

[0167] The manufacturing method of the semiconductor device 100 includes: a first step and a second step of sequentially forming a plurality of nitride semiconductor layers; a third step of forming a source electrode 32 and a drain electrode 34; a fourth step of forming a gate electrode 30; a fifth step of forming an insulating film 40; and a sixth step of etching without the Al layer 122. In this embodiment, the first step, the second step, the fifth step, the third step, the sixth step, and the fourth step are performed in that order. The first step, the second step, the fifth step, and the third step are related to the use of... Figures 2A-2D The procedures described are the same. The following uses... Figure 5A as well as Figure 5B The following detailed explanations are provided for each process after step 6. Figure 5A as well as Figure 5B These are cross-sectional views of each step in the manufacturing method of the semiconductor device 100 of this embodiment.

[0168] If used Figures 2A-2C As explained, after the source electrode 32 and drain electrode 34 are formed, as Figure 5A As shown, an opening 41 is formed in the insulating film 40. For example, by photolithography and dry etching, the upper portion of the inner region 123 of the insulating film 40 without the Al layer 122 is removed, thereby forming the opening 41 and exposing a portion of the upper surface 122a without the Al layer 122.

[0169] Next, as Figure 5B As shown, as the sixth process, the insulating film 40 with the opening 41 is used as a mask for etching, so that the thickness of the inner region 123 is thinner than the thickness of the outer region 124. For example, etching is performed until the thickness of the inner region 123 is less than 3 nm.

[0170] The etching is a dry etching process using a gas containing hydrogen. The Al-free layer 122 contains undoped GaN as the main component, but sometimes p-type dopants (e.g., Mg) contained in the p-type semiconductor layer 18 diffuse into the Al-free layer 122 via the Al-containing layer 20. If p-type dopants are present in the Al-free layer 122, the Schottky characteristics of the Al-free layer 122 and the gate electrode 30 may degrade. In contrast, by performing dry etching using a gas containing hydrogen, hydrogen penetrates into the Al-free layer 122, neutralizing the charge caused by the p-type dopants. This improves the Schottky characteristics of the Al-free layer 122 and the gate electrode 30.

[0171] Dry etching is performed, for example, using an ICP (Inductively Coupled Plasma) dry etching apparatus. As gaseous feedstocks, chlorine gas at a concentration of 10 sccm or more and 30 sccm or less, and hydrogen gas at a concentration of 1 sccm or more and 10 sccm or less can be used. As an example, chlorine gas (Cl2) at 20 sccm and hydrogen gas (H2) at 2 sccm can be used. The pressure is 0.5 Pa or more and 5 Pa or less, with 2 Pa being an example. As plasma output, a power of 50 W or more and 200 W or less is supplied to the upper electrode of the ICP, and a power of 5 W or more and 20 W or less is supplied to the lower electrode of the ICP. As an example, 100 W of power is supplied to the upper electrode of the ICP, and 10 W of power is supplied to the lower electrode of the ICP.

[0172] Alternatively, CCP (Capacitively Coupled Plasma) or ECR (Electron Cyclotron Resonance) dry etching apparatuses can be used as dry etching devices. Chlorine-based gases (gases containing chlorine atoms) such as SiCl4, BCl3, and CCl4 can be used instead of chlorine gas. Hydrogen-based gases (gases containing hydrogen atoms) such as NH3, HCl, HBr, CH2F2, CHF3, CH4, and SiH4 can be used instead of hydrogen gas. Chlorine-based and hydrogen-based gases can be mixtures of two or more of each. Inert gases such as Ar and He can also be used.

[0173] After thinning the inner region 123 by etching, as a fourth step, a gate electrode 30 is formed on top of the area without the Al layer 122. For example, after forming a conductive film over the entire surface by sputtering or evaporation, the conductive film is patterned into a predetermined shape by photolithography and dry etching, thereby forming the gate electrode 30. Patterning can also be performed by a lift-off method. Thus, the gate electrode 30 contacts the upper surface 23a of the inner region 23 via the opening 41.

[0174] Through the above processes, it is possible to manufacture Figure 1 The semiconductor device 100 is shown. Furthermore, the manufacturing method of the semiconductor device 100 is not limited to the example described above. The third step of forming the source electrode 32 and the drain electrode 34 may also be performed after the fourth step of forming the gate electrode 30.

[0175] (Implementation Method 3) Next, Embodiment 3 will be described. Hereinafter, the description will focus on the differences from Embodiment 2, and the description of the commonalities will be omitted or simplified.

[0176] [structure] Figure 6 This is a cross-sectional view of the semiconductor device 200 according to this embodiment. (As shown...) Figure 6 As shown, the semiconductor device 200, compared to the semiconductor device 100 of Embodiment 2, further includes an n-type semiconductor layer 226.

[0177] The n-type semiconductor layer 226 is an example of an n-type sixth nitride semiconductor layer, disposed between the upper surface 124a of the outer region 124 (excluding the Al layer 122) and the insulating film 40. For example, the n-type semiconductor layer 226 is disposed in contact with the upper surface 124a of the outer region 124 and the lower surface of the insulating film 40, respectively.

[0178] The n-type semiconductor layer 226, for example, contains n-type GaN as the main component. Alternatively, the n-type semiconductor layer 226 may contain n-type dopants such as Si. The concentration of the n-type dopant is 1.0 × 10⁻⁶. 19 cm -3 Above and 5.0×10 19 cm -3 The following is an example of 3.0 × 10 19 cm -3 Furthermore, the n-type semiconductor layer 226 may also contain n-type InGaN, InN, AlGaN, AlInGaN, etc., as the main components. The thickness of the n-type semiconductor layer 226 is, for example, 1 nm or more and 10 nm or less, with 3 nm as an example.

[0179] By providing the n-type semiconductor layer 226, the charge caused by the p-type dopant diffused from the p-type semiconductor layer 18 to the Al-free layer 122 can be neutralized. This improves the Schottky characteristics of the Al-free layer 122 and the gate electrode 30. By improving the Schottky characteristics, a normally-off transistor with a large threshold voltage can be realized.

[0180] Furthermore, in this embodiment, the n-type semiconductor layer 226 does not contact the inner region 123 without the Al layer 122. The boundary between the inner region 123 without the Al layer 122 and the outer region 124 is coplanar with a portion of the side surface of the n-type semiconductor layer 226. The n-type semiconductor layer 226 is configured not to overlap (not exposed) with the opening 41 of the insulating film 40 when the substrate 10 is viewed in planar view. The gate electrode 30 contacts the upper surface 123a of the inner region 123. As a result, ohmic connection between the gate electrode 30 and the n-type semiconductor layer 226 can be suppressed, thereby improving Schottky characteristics. Therefore, a normally-off transistor with a large threshold voltage can be realized.

[0181] [Manufacturing Method] Next, the manufacturing method of the semiconductor device 200 of this embodiment will be described.

[0182] The method for manufacturing a semiconductor device 200 includes: a first step and a second step sequentially forming a plurality of nitride semiconductor layers; a third step forming a source electrode 32 and a drain electrode 34; a fourth step forming a gate electrode 30; a fifth step forming an insulating film 40; and a sixth step performing etching without the Al layer 122. In this embodiment, the steps are performed in the order of the first step, the second step, the fifth step, the third step, the sixth step, and the fourth step. Hereinafter, the method will use... Figures 7A-7E Please provide a detailed explanation of each process. Figures 7A-7E These are cross-sectional views of each step in the manufacturing method of the semiconductor device 200 of this embodiment.

[0183] First, such as Figure 7A As shown, in the first step, a channel layer 14 and a barrier layer 16 are formed sequentially. Then, in the second step, a p-type semiconductor layer 18, an Al-containing layer 20, an Al-free layer 122, and an n-type semiconductor layer 226 are formed sequentially. In the second step of this embodiment, a nitride semiconductor layer is formed by continuously performing crystal growth from the first step. This layer is a composite film including the p-type semiconductor layer 18, the Al-containing layer 20, the Al-free layer 122, and the n-type semiconductor layer 226 before they are patterned into a predetermined shape. Specifically, a nitride semiconductor film is formed on the upper surface of the substrate 10 by epitaxial growth, thereby sequentially forming a buffer layer 12, a channel layer 14, a barrier layer 16, a p-type semiconductor layer 18, an Al-containing layer 20, an Al-free layer 122, and an n-type semiconductor layer 226. By adjusting the introduced gas, dopant, growth temperature, and growth time during epitaxial growth, the composition and thickness of each layer can be controlled.

[0184] Next, as Figure 7B As shown, in the second step, a p-type semiconductor layer 18, an Al-containing layer 20, an Al-free layer 122, and an n-type semiconductor layer 226 of a predetermined shape are formed by patterning the formed multilayer film. For example, portions of the n-type semiconductor layer 226, the Al-free layer 22, the Al-containing layer 20, and the p-type semiconductor layer 18 located outside the gate region are selectively removed by photolithography and dry etching. Outside the gate region, the upper surface 16a of the barrier layer 16 is exposed.

[0185] Next, as Figure 7CAs shown, as the fifth step, an insulating film 40 is formed. For example, the insulating film 40 is formed as a SiN film by plasma CVD, covering the upper surface 16a of the barrier layer 16 and the upper surface 226a of the n-type semiconductor layer 226. Next, as the third step, a source electrode 32 and a drain electrode 34 are formed with the p-type semiconductor layer 18 sandwiched in between. Specifically, first, after forming openings 42 and 43 in the insulating film 40, the source electrode 32 and the drain electrode 34 are formed. The methods for forming the openings 42 and 43, and the methods for forming the source electrode 32 and the drain electrode 34, are the same as in Embodiment 1.

[0186] Next, as Figure 7D As shown, an opening 41 is formed in the insulating film 40. For example, by photolithography and dry etching, the upper portion of the inner region 123 of the insulating film 40, which does not contain the Al layer 122, is removed, thereby forming the opening 41 and exposing a portion of the upper surface 226a of the n-type semiconductor layer 226.

[0187] Next, as Figure 7E As shown, the portion of the n-type semiconductor layer 226 exposed at the opening 41 is removed by etching using the insulating film 40 with the opening 41 as a mask. Furthermore, by continuously etching, the thickness of the inner region 123 is made thinner than the thickness of the outer region 124 (step 6). For example, etching is performed until the thickness of the inner region 123 is less than 3 nm. The etching can be performed using the same method as the etching for thin-film formation of the inner region 123 in Embodiment 2.

[0188] After thinning the inner region 123 by etching, as a fourth step, a gate electrode 30 is formed on top of the area free of the Al layer 122. The gate electrode 30 can be formed using the same method as in Embodiment 1.

[0189] Through the above processes, it is possible to manufacture Figure 6 The semiconductor device 200 shown.

[0190] In the manufacturing method of the semiconductor device 200 of this embodiment, by continuously removing the n-type semiconductor layer 226 and thinning the inner region 123 without the Al layer 122, a portion of the side surface of the n-type semiconductor layer 226 (the side surface on the opening 41 side) can be made coplanar with the interface between the inner region 123 and the outer region 124. Since so-called self-alignment is possible, the etching process can be simplified. Furthermore, since the n-type semiconductor layer 226 is less likely to be positioned between the gate electrode 30 and the inner region 123, Schottky characteristics can be improved. Therefore, a normally-off transistor with a large threshold voltage can be realized.

[0191] Furthermore, the manufacturing method of the semiconductor device 200 is not limited to the examples described above. The third step of forming the source electrode 32 and the drain electrode 34 can also be performed after the fourth step of forming the gate electrode 30. In addition, the removal of the n-type semiconductor layer 226 and the thinning of the inner region 123 can be performed in stages in different steps.

[0192] Alternatively, the semiconductor device 200 of this embodiment may also include the Al-free layer 22 of Embodiment 1 instead of the Al-free layer 122. That is, the thickness of the Al-free layer 22 may be uniform, and the sixth process may not be performed after the etching of the n-type semiconductor layer 226.

[0193] (Implementation Method 4) Next, Embodiment 4 will be described. Hereinafter, the description will focus on the differences from Embodiment 1, and the description of the commonalities will be omitted or simplified.

[0194] [structure] Figure 8 This is a cross-sectional view of the semiconductor device 300 according to this embodiment. Figure 8 As shown, the semiconductor device 300 further includes a band barrier layer 328 compared to the semiconductor device 1 of Embodiment 1.

[0195] The band barrier layer 328 is an example of the seventh nitride semiconductor layer, and its band gap is larger than that of the Al-containing layer 20. The band barrier layer 328 is disposed between the p-type semiconductor layer 18 and the Al-containing layer 20. For example, the band barrier layer 328 is disposed in contact with the upper surface of the p-type semiconductor layer 18 and the lower surface of the Al-containing layer 20, respectively.

[0196] The band barrier layer 328 may contain, for example, type i AlN as the principal component, but is not limited to this. The band barrier layer 328 may also contain AlGaN, AlInGaN, etc. as the principal component.

[0197] The thickness of the band barrier layer 328 is thinner than either the thickness of the p-type semiconductor layer 18 or the thickness of the Al-containing layer 20. For example, the thickness of the band barrier layer 328 is 0.5 nm or more and less than 3 nm, with 2 nm being an example. When AlN is crystallized on GaN, the critical film thickness of AlN is approximately 3 nm. By making the thickness of the band barrier layer 328 less than the critical film thickness, crystal defects generated in the upper layers (with and without the Al layer 20) can be suppressed. As a result, the degradation of the Schottky characteristics of the gate electrode 30 and the Al-containing layer 20 can be suppressed.

[0198] In the semiconductor device 300 of this embodiment, by providing a band barrier layer 328, the resistivity between the gate electrode 30 and the 2DEG can be further improved, thereby reducing the gate leakage current.

[0199] [Manufacturing Method] Next, the manufacturing method of the semiconductor device 300 of this embodiment will be described.

[0200] The method for manufacturing a semiconductor device 300 includes: a first step and a second step of sequentially forming a plurality of nitride semiconductor layers; a third step of forming a source electrode 32 and a drain electrode 34; a fourth step of forming a gate electrode 30; and a fifth step of forming an insulating film 40. In this embodiment, the steps are performed in the order of the first step, the second step, the fifth step, the third step, and the fourth step. Hereinafter, [the method will use...] Figures 9A-9D Please provide a detailed explanation of each process. Figures 9A-9D These are cross-sectional views of each step in the manufacturing method of the semiconductor device 300 of this embodiment.

[0201] First, such as Figure 9A As shown, in the first step, a channel layer 14 and a barrier layer 16 are formed sequentially. Then, in the second step, a p-type semiconductor layer 18, a band barrier layer 328, an Al-containing layer 20, and an Al-free layer 22 are formed sequentially. In the second step of this embodiment, a nitride semiconductor layer is formed by continuously performing crystal growth from the first step. This layer is a layer comprising the p-type semiconductor layer 18, the band barrier layer 328, the Al-containing layer 20, and the Al-free layer 22 before being patterned into a predetermined shape. Specifically, a nitride semiconductor film is formed on the upper surface of the substrate 10 by epitaxial growth, thereby sequentially forming a buffer layer 12, a channel layer 14, a barrier layer 16, a p-type semiconductor layer 18, a band barrier layer 328, an Al-containing layer 20, and an Al-free layer 22. By adjusting the introduced gas, dopant, growth temperature, growth time, etc., during epitaxial growth, the composition and thickness of each layer can be controlled.

[0202] Next, as Figure 9B As shown, in the second step, a p-type semiconductor layer 18, a band barrier layer 328, an Al-containing layer 20, and an Al-free layer 22 are formed by patterning the formed multilayer film. For example, portions of the Al-free layer 22, the Al-containing layer 20, the band barrier layer 328, and the p-type semiconductor layer 18 located outside the gate region are selectively removed by photolithography and dry etching. Outside the gate region, the upper surface 16a of the barrier layer 16 is exposed.

[0203] Next, as Figure 9CAs shown, as the fifth step, an insulating film 40 is formed. For example, the insulating film 40 is formed as a SiN film by plasma CVD, covering the upper surface 16a of the barrier layer 16 and the upper surface 22a without the Al layer 22. Next, as the third step, a source electrode 32 and a drain electrode 34 are formed with a p-type semiconductor layer 18 sandwiched in between. Specifically, first, after forming openings 42 and 43 in the insulating film 40, the source electrode 32 and the drain electrode 34 are formed. The methods for forming the openings 42 and 43, and the methods for forming the source electrode 32 and the drain electrode 34, are the same as in Embodiment 1.

[0204] Next, as Figure 9D As shown, an opening 41 is formed in the insulating film 40. For example, by photolithography and dry etching, the upper portion of the inner region 23 without the Al layer 22 in the insulating film 40 is removed, thereby forming the opening 41 and exposing a portion of the upper surface 22a without the Al layer 22.

[0205] Next, as a fourth step, a gate electrode 30 is formed on top of the layer 22, which does not contain the Al layer. The gate electrode 30 can be formed using the same method as in Embodiment 1.

[0206] Through the above processes, it is possible to manufacture Figure 8 The semiconductor device 300 shown is described above. Furthermore, the manufacturing method of the semiconductor device 300 is not limited to the examples described above. The third step of forming the source electrode 32 and the drain electrode 34 can also be performed after the fourth step of forming the gate electrode 30. Additionally, the semiconductor device 300 of this embodiment can also include the Al-free layer 122 of Embodiment 2 instead of the Al-free layer 22. A sixth step of thinning the thickness of the inner region 123 of the Al-free layer 122 can also be performed after the opening 41 is formed in the insulating film 40. Furthermore, the semiconductor device 300 can also include the n-type semiconductor layer 226 of Embodiment 3.

[0207] (Implementation Method 5) Next, Embodiment 5 will be described. Hereinafter, the description will focus on the differences from Embodiment 1, and the description of the commonalities will be omitted or simplified.

[0208] [structure] Figure 10 This is a cross-sectional view of the semiconductor device 400 according to this embodiment. (As shown...) Figure 10 As shown, the semiconductor device 400 further includes an insulating film 440 compared to the semiconductor device 1 of Embodiment 1.

[0209] The insulating film 440 is an example of a second insulating film, covering the upper surface 16a of the barrier layer 16. The insulating film 440 is disposed between the upper surface 16a of the barrier layer 16 and the insulating film 40. For example, the insulating film 440 is in contact with the upper surface 16a and the lower surface of the insulating film 40, respectively.

[0210] An opening 441 is provided in the insulating film 440. The opening 441 is for forming a gate structure. The length of the opening 441 in the gate length direction is the same as the length of the p-type semiconductor layer 18 in the gate length direction. In addition, openings 442 and 443 are provided in the insulating film 440. The opening 442, like the opening 42 provided in the insulating film 40, is provided to allow the source electrode 32 to contact the upper surface 16a of the barrier layer 16. The opening 443, like the opening 43 provided in the insulating film 40, is provided to allow the drain electrode 34 to contact the upper surface 16a of the barrier layer 16.

[0211] The insulating film 440 contains, for example, SiN as the main component. The insulating film 440 is formed continuously from the crystal growth of the nitride semiconductor.

[0212] [Manufacturing Method] Next, the manufacturing method of the semiconductor device 400 of this embodiment will be described.

[0213] The manufacturing method of the semiconductor device 400 includes: a first step and a second step sequentially forming a plurality of nitride semiconductor layers; a third step forming a source electrode 32 and a drain electrode 34; a fourth step forming a gate electrode 30; a fifth step forming an insulating film 40; and a seventh step forming an insulating film 440. In this embodiment, the steps are performed in the order of the first step, the seventh step, the second step, the fifth step, the third step, and the fourth step. Hereinafter, the method will use... Figures 11A-11F Please provide a detailed explanation of each process. Figures 11A-11F These are cross-sectional views of each step in the manufacturing method of the semiconductor device 400 of this embodiment.

[0214] First, such as Figure 11A As shown, as the first process, a channel layer 14 and a barrier layer 16 are formed sequentially. Furthermore, as the seventh process, an insulating film 440 is formed. The formation of the insulating film 440 is performed continuously from the formation of the barrier layer 16. That is, the channel layer 14, the barrier layer 16, and the insulating film 440 are formed sequentially within the same growth furnace without exposure to the atmosphere. Specifically, on the upper surface of the substrate 10, a buffer layer 12, a channel layer 14, a barrier layer 16, and an insulating film 440 are formed sequentially by crystal growth based on epitaxial growth. By adjusting the introduced gas, dopant, growth temperature, and growth time during epitaxial growth, the composition and thickness of each layer can be controlled.

[0215] Next, as Figure 11B As shown, an opening 441 is formed in the gate region of the insulating film 440. For example, the opening 441 is formed by removing a portion of the insulating film 440 located in the gate region through photolithography and dry etching. In the opening 441, the upper surface 16a of the barrier layer 16 is exposed.

[0216] Next, as Figure 11C As shown, in the second process, a p-type semiconductor layer 18, an Al-containing layer 20, and an Al-free layer 22 are formed sequentially. In this embodiment, by selectively growing crystals within the opening 441 of the insulating film 440, the p-type semiconductor layer 18, the Al-containing layer 20, and the Al-free layer 22 can be formed sequentially. Furthermore, by adjusting the introduced gas, dopant, growth temperature, and growth time during epitaxial growth, the composition and thickness of each layer can be controlled.

[0217] Next, as Figure 11D As shown, as the fifth step, an insulating film 40 is formed. For example, the insulating film 40 is formed as a SiN film by plasma CVD in a manner that covers the upper surface of the insulating film 440 and the upper surface 22a without the Al layer 22.

[0218] Next, as Figure 11E As shown, in the third step, the source electrode 32 and the drain electrode 34 are formed with the p-type semiconductor layer 18 sandwiched in between. Specifically, firstly, openings 42 and 43 are formed in the insulating film 40, and openings 442 and 443 are formed in the insulating film 440. For example, the areas in the insulating films 40 and 440 used to form the source electrode 32 and the drain electrode 34 are removed by photolithography and dry etching, thereby forming openings 42 and 442, and openings 43 and 443. Then, for example, after forming a conductive film over the entire surface by sputtering or evaporation, the conductive film is patterned into a predetermined shape by photolithography and dry etching, thereby forming the source electrode 32 and the drain electrode 34. Patterning can also be performed by a lift-off method. Alternatively, the source electrode 32 and the drain electrode 34 can be formed by different processes.

[0219] Next, as Figure 11F As shown, an opening 41 is formed in the insulating film 40. For example, by photolithography and dry etching, the upper portion of the inner region 23 without the Al layer 22 in the insulating film 40 is removed, thereby forming the opening 41 and exposing a portion of the upper surface 22a without the Al layer 22.

[0220] Next, as a fourth step, a gate electrode 30 is formed on top of the layer 22, which does not contain the Al layer. The gate electrode 30 can be formed using the same method as in Embodiment 1.

[0221] Through the above processes, it is possible to manufacture Figure 10 The semiconductor device 400 is shown. In this embodiment, the barrier layer 16 and the insulating film 440 are formed continuously, thus preventing the upper surface 16a of the barrier layer 16 from being exposed to the atmosphere. This suppresses oxidation of the upper surface 16a of the barrier layer 16. Since impurity levels are less likely to form on the upper surface 16a of the barrier layer 16, the lateral breakdown voltage is improved.

[0222] Furthermore, the manufacturing method of the semiconductor device 400 is not limited to the examples described above. The third step of forming the source electrode 32 and the drain electrode 34 can also be performed after the fourth step of forming the gate electrode 30. Additionally, the semiconductor device 400 of this embodiment can also include the Al-free layer 122 of Embodiment 2 instead of the Al-free layer 22. A sixth step of thinning the thickness of the inner region 123 of the Al-free layer 122 can also be performed after the opening 41 is formed in the insulating film 40. Furthermore, the semiconductor device 400 can also include the n-type semiconductor layer 226 of Embodiment 3. Additionally, the semiconductor device 400 can also include the band barrier layer 328 of Embodiment 4.

[0223] Next, a variation of embodiment 6 will be described.

[0224] Figure 12 This is a cross-sectional view of the semiconductor device 401 in this modified example. Figure 12 The semiconductor device 401 shown differs from the semiconductor device 100 of Embodiment 6 in that it has a p-type semiconductor layer 418.

[0225] The p-type semiconductor layer 418 is configured such that a barrier layer 16 is embedded at a position where it overlaps with the p-type semiconductor layer 18 in a planar view. The upper surface 418a of the p-type semiconductor layer 418 is coplanar with the upper surface 16a of the barrier layer 16. For example, the upper surface 418a of the p-type semiconductor layer 418 is in contact with the lower surface of the p-type semiconductor layer 18. In a planar view of the substrate 10, the outline of the p-type semiconductor layer 418 is substantially the same as the outline of the p-type semiconductor layer 18.

[0226] The p-type semiconductor layer 418 has the same parent semiconductor as the barrier layer 16 and contains the same type of p-type dopant as the p-type dopant contained in the p-type semiconductor layer 18. Specifically, the p-type semiconductor layer 418 is formed by diffusing the p-type dopant contained in the p-type semiconductor layer 18 to the surface portion of the barrier layer 16. The diffusion of the p-type dopant is performed, for example, by heat treatment or annealing during epitaxial growth. As an example, the temperature of the heat treatment or annealing is 900°C or higher. By adjusting the temperature or processing time, the diffusion distance of the p-type dopant can be adjusted, and the thickness of the p-type semiconductor layer 418 can be adjusted.

[0227] By providing a p-type semiconductor layer 418, the thickness of the barrier layer 16 is locally reduced. Specifically, the portion of the barrier layer 16 located directly below the gate electrode 30 is thinner than the portions located between the gate and drain and between the gate and source, respectively. As a result, the concentration of 2DEG is maintained at a higher level between the gate and drain and between the gate and source, thus reducing the on-resistance. Furthermore, by thinning the portion located directly below the gate electrode 30, the threshold voltage of the transistor can be adjusted.

[0228] (Implementation Method 6) Next, Embodiment 6 will be described. Hereinafter, the description will focus on the differences from Embodiment 2, and the description of the commonalities will be omitted or simplified.

[0229] [structure] Figure 13 This is a cross-sectional view of the semiconductor device 500 according to this embodiment. Figure 13 As shown, compared with the semiconductor device 100 of Embodiment 2, the semiconductor device 500 has a gate electrode 530 and a gate wiring 530G instead of the gate electrode 30.

[0230] The gate electrode 530 is disposed above the area without the Al layer 122. Specifically, the gate electrode 530 is disposed between the outer region 124 without the Al layer 122 and the insulating film 40. For example, the gate electrode 530 is in contact with the upper surface 124a of the outer region 124 and the lower surface of the insulating film 40, respectively. The gate electrode 530 contains a conductive material as its main component. For example, the gate electrode 530 is formed using the same material as the gate electrode 30 of Embodiment 1.

[0231] In this embodiment, the gate electrode 530 does not contact the inner region 123 without the Al layer 122. The boundary between the inner region 123 without the Al layer 122 and the outer region 124 is coplanar with a portion of the side surface of the gate electrode 530 (the side surface on the side of the opening 41). The gate electrode 530 is configured not to overlap with (not be exposed) the opening 41 of the insulating film 40 when the substrate 10 is viewed in planar view.

[0232] Furthermore, a portion of the side surface of the gate electrode 530 (the side surface of the source electrode 32 and the side surface of the drain electrode 34) is coplanar with each side surface (side surface of the gate structure) of the electrode without the Al layer 122, the electrode with the Al layer 20, and the p-type semiconductor layer 18. For example, the length of the gate electrode 530 in the gate length direction (including the length of the opening 41) is the same as the length of the p-type semiconductor layer 18 in the gate length direction. This shortens the actual gate length, enabling steeper gate operation. Additionally, since the parasitic resistance of the transistor can be reduced, the on-resistance can be reduced.

[0233] Gate wiring 530G is disposed above the area excluding the Al layer 122. Specifically, gate wiring 530G contacts and covers the upper surface 123a of the inner region 123 excluding the Al layer 122. More specifically, gate wiring 530G contacts the upper surface 123a of the inner region 123 excluding the Al layer 122 via an opening 41 provided in the insulating film 40. Gate wiring 530G is electrically connected to the gate electrode 530. Gate wiring 530G and gate electrode 530 can also be considered as a single gate electrode. Alternatively, gate wiring 530G can also be a gate pad.

[0234] The gate wiring 530G contains a conductive material as its main component. For example, the gate wiring 530G is formed using the same material as the gate electrode 30 in Embodiment 1.

[0235] [Manufacturing Method] Next, the manufacturing method of the semiconductor device 500 of this embodiment will be described.

[0236] The method for manufacturing a semiconductor device 500 includes: a first step and a second step of sequentially forming a plurality of nitride semiconductor layers; a third step of forming a source electrode 32 and a drain electrode 34; a fourth step of forming a gate electrode 30; a fifth step of forming an insulating film 40; and a sixth step of etching without the Al layer 122. In this embodiment, the steps are performed in the order of the first step, the second step, the fourth step, the fifth step, the third step, and the sixth step. Hereinafter, the method will use... Figures 14A-14E Please provide a detailed explanation of each process. Figures 14A-14E These are cross-sectional views of each step in the manufacturing method of the semiconductor device 200 of this embodiment.

[0237] First, such as Figure 14AAs shown, in the first process, a channel layer 14 and a barrier layer 16 are formed sequentially. Then, in the second process, a p-type semiconductor layer 18, an Al-containing layer 20, and an Al-free layer 122 are formed sequentially. Furthermore, in the fourth process, a gate electrode 530 is formed. In the second process of this embodiment, a nitride semiconductor layer is formed by continuously performing crystal growth from the first process. This layer includes the p-type semiconductor layer 18, the Al-containing layer 20, and the Al-free layer 122 before they are patterned into a predetermined shape. Specifically, a nitride semiconductor film is formed on the upper surface of the substrate 10 by epitaxial growth, thereby sequentially forming a buffer layer 12, a channel layer 14, a barrier layer 16, a p-type semiconductor layer 18, an Al-containing layer 20, and an Al-free layer 122. By adjusting the introduced gas, dopant, growth temperature, and growth time during epitaxial growth, the composition and thickness of each layer can be controlled. Then, the gate electrode 530, patterned into a predetermined shape, is formed in a manner that covers the upper surface without the Al layer 122. For example, a conductive film is formed on the entire surface as the gate electrode 530 by sputtering or evaporation.

[0238] Next, as Figure 14B As shown, in the second step, a p-type semiconductor layer 18, an Al-containing layer 20, an Al-free layer 122, and a gate electrode 530 of a predetermined shape are formed by patterning the formed nitride semiconductor stack and the gate electrode 530. For example, portions of the gate electrode 530, the Al-free layer 122, the Al-containing layer 20, and the p-type semiconductor layer 18 located outside the gate region are selectively removed by photolithography and dry etching. Outside the gate region, the upper surface 16a of the barrier layer 16 is exposed.

[0239] Next, as Figure 14C As shown, as the fifth step, an insulating film 40 is formed. For example, the insulating film 40 is formed as a SiN film by plasma CVD in such a way that it covers the upper surface 16a of the barrier layer 16 and the upper surface 530a of the gate electrode 530.

[0240] Next, as Figure 14D As shown, as the third step, the source electrode 32 and the drain electrode 34 are formed with the p-type semiconductor layer 18 sandwiched in between. Specifically, first, after forming openings 42 and 43 in the insulating film 40, the source electrode 32 and the drain electrode 34 are formed. The methods for forming the openings 42 and 43, and the methods for forming the source electrode 32 and the drain electrode 34, are the same as in Embodiment 1.

[0241] Next, as Figure 14EAs shown, an opening 41 is formed in the insulating film 40. For example, by photolithography and dry etching, the upper portion of the inner region 123 in the insulating film 40, which does not contain the Al layer 122, is removed, thereby forming the opening 41 and exposing a portion of the upper surface 530a of the gate electrode 530. Furthermore, by etching the insulating film 40 with the opening 41 as a mask, the portion of the gate electrode 530 exposed in the opening 41 is removed. Furthermore, by continuously etching, the thickness of the inner region 123 is made thinner than the thickness of the outer region 124 (step 6). For example, etching is performed until the thickness of the inner region 123 is less than 3 nm. The etching can be performed using the same method as the etching for thin-film formation of the inner region 123 in Embodiment 2.

[0242] Next, gate wiring 530G is formed above the area without Al layer 22. For example, after forming a conductive film over the entire surface by sputtering or evaporation, the conductive film is patterned into a predetermined shape by photolithography and dry etching, thereby forming gate wiring 530G. Patterning can also be performed by a lift-off method. Thus, gate wiring 530G contacts the upper surface 123a of the inner region 123 via opening 41. Alternatively, gate wiring 530G can also be formed by electroplating.

[0243] Through the above processes, it is possible to manufacture Figure 13 The semiconductor device 500 shown. In the manufacturing method of the semiconductor device 500 of this embodiment, the patterning between the gate electrode 530 and the layers without Al layer 122, with Al layer 20, and p-type semiconductor layer 18 can be performed simultaneously. As a result, the gate length can be shortened, and steep gate operation can be performed.

[0244] Furthermore, the manufacturing method of the semiconductor device 500 is not limited to the examples described above. The third step of forming the source electrode 32 and the drain electrode 34 can also be performed after the step of forming the gate wiring 530G. Additionally, the semiconductor device 500 of this embodiment can also include the Al-free layer 22 of Embodiment 1 instead of the Al-free layer 122. That is, the sixth step of thinning the thickness of the inner region 123 of the Al-free layer 122 can be omitted. Furthermore, the semiconductor device 500 can also include the n-type semiconductor layer 226 of Embodiment 3. Furthermore, the semiconductor device 500 can also include the band barrier layer 328 of Embodiment 4. Furthermore, the semiconductor device 500 can also include the insulating film 440 of Embodiment 5.

[0245] (Other implementation methods) The above description illustrates one or more embodiments of a semiconductor device and its manufacturing method, but this disclosure is not limited to these embodiments. Various modifications conceived by those skilled in the art to these embodiments, as well as combinations of constituent elements from different embodiments, are also included within the scope of this disclosure, provided they do not depart from its spirit.

[0246] For example, the semiconductor devices of the above embodiments may not include the insulating film 40. Furthermore, for example, the manufacturing methods of the semiconductor devices of the above embodiments may not include the fifth step of forming the insulating film 40.

[0247] Additionally, for example, in various embodiments, examples are shown where the sides of the p-type semiconductor layer 18, the Al-containing layer 20, the Al-free layer 22 or 122, the n-type semiconductor layer 226, and the band barrier layer 328 (each side of the gate structure) are coplanar and perpendicular to the main surface of the substrate 10, but this is not a limitation. Each side of the gate structure may be inclined relative to the main surface of the substrate 10, or may be formed in a stepped shape.

[0248] Furthermore, for example, in various embodiments, if the conductivity type without Al layer 22 or 122 is type i, the conductivity type with Al layer 20 can also be type p. Alternatively, if the conductivity type without Al layer 22 or 122 is type i, the conductivity type with Al layer 20 can also be type n. Alternatively, the conductivity type without Al layer 22 or 122 can also be type p. Furthermore, if the conductivity type without Al layer 22 or 122 is type p, the conductivity type with Al layer 20 can be type i, type p, or type n. Furthermore, the conductivity type without Al layer 22 or 122 can also be type n. Furthermore, if the conductivity type without Al layer 22 or 122 is type n, the conductivity type with Al layer 20 can be type i, type p, or type n. Furthermore, both the absence of Al layer 22 or 122 and the presence of Al layer 20 can be undoped.

[0249] Furthermore, the above-described embodiments can be modified, substituted, added, or omitted in various ways within the scope of the claims or their equivalents.

[0250] Industrial availability This disclosure can be used, for example, in power amplifiers for high-output or high-frequency applications, in wireless communication base stations or terminal equipment using the power amplifier, or in wireless power supply devices that utilize microwave power transmission.

[0251] Explanation of reference numerals in the attached figures 1, 100, 200, 300, 400, 401, 500 Semiconductor Devices 10 substrate 12 Buffer Layer 14. Channel layer 16 Barrier Layer Upper surfaces of 16a, 22a, 23a, 24a, 122a, 123a, 124a, 226a, 418a, and 530a 18, 418 p-type semiconductor layer 20 Contains Al layer 22 and 122 do not contain an Al layer. 23, 123 inner area 24, 124 outer regions 30, 530 gate electrodes 32 Source Electrode 34 Drain electrode 40, 440 insulating film 41, 42, 43, 441, 442, 443 Openings 226 n-type semiconductor layer 328 band barrier layer 530G gate wiring

Claims

1. A semiconductor device, wherein, have: First nitride semiconductor layer; A second nitride semiconductor layer is disposed above the first nitride semiconductor layer, and has a larger band gap than the first nitride semiconductor layer; A third p-type nitride semiconductor layer is disposed above the second nitride semiconductor layer; The source electrode and the drain electrode are arranged such that the third nitride semiconductor layer is sandwiched in between; A fourth nitride semiconductor layer of type i is disposed above the third nitride semiconductor layer, has a larger band gap than the third nitride semiconductor layer, and contains Al; A fifth nitride semiconductor layer of type i, disposed above the fourth nitride semiconductor layer and not containing Al; and The gate electrode is disposed above the fifth nitride semiconductor layer.

2. The semiconductor device according to claim 1, wherein, At least a portion of the fifth nitride semiconductor layer has a thickness of less than 3 nm.

3. A semiconductor device, wherein, have: First nitride semiconductor layer; A second nitride semiconductor layer is disposed above the first nitride semiconductor layer, and has a larger band gap than the first nitride semiconductor layer; A third p-type nitride semiconductor layer is disposed above the second nitride semiconductor layer; The source electrode and the drain electrode are arranged such that the third nitride semiconductor layer is sandwiched in between; A fourth nitride semiconductor layer is disposed above the third nitride semiconductor layer, has a larger band gap than the third nitride semiconductor layer, and contains Al. A fifth nitride semiconductor layer is disposed above the fourth nitride semiconductor layer and does not contain Al; and The gate electrode is disposed above the fifth nitride semiconductor layer. At least a portion of the fifth nitride semiconductor layer has a thickness of less than 3 nm.

4. The semiconductor device according to any one of claims 1 to 3, wherein, The fifth nitride semiconductor layer includes an inner region and an outer region in a cross-section parallel to the gate length direction and thickness direction, respectively. The outer region is located on the outer side of the gate length direction compared to the inner region. The semiconductor device includes an insulating film disposed between the upper surface of the outer region and the gate electrode. The gate electrode is in contact with the upper surface of the inner region.

5. The semiconductor device according to claim 4, wherein, The thickness of the inner region is thinner than the thickness of the outer region.

6. The semiconductor device according to claim 5, wherein, The difference between the thickness of the outer region and the thickness of the inner region is greater than 1 nm.

7. The semiconductor device according to any one of claims 4 to 6, wherein, The length of the outer region in the gate length direction is 0.1 μm or more.

8. The semiconductor device according to any one of claims 4 to 7, wherein, The hydrogen concentration in the inner region is higher than the p-type impurity concentration in the inner region.

9. The semiconductor device according to any one of claims 4 to 8, wherein, It has an n-type sixth nitride semiconductor layer disposed between the upper surface of the outer region and the insulating film.

10. The semiconductor device according to claim 9, wherein, The boundary between the inner region and the outer region is coplanar with a portion of the side surface of the sixth nitride semiconductor layer.

11. The semiconductor device according to any one of claims 1 to 10, wherein, The third nitride semiconductor layer contains GaN as the main component.

12. The semiconductor device according to any one of claims 1 to 11, wherein, The fourth nitride semiconductor layer contains AlGaN as the main component.

13. The semiconductor device according to any one of claims 1 to 12, wherein, The fifth nitride semiconductor layer contains GaN as the main component.

14. The semiconductor device according to any one of claims 1 to 13, wherein, It has a seventh nitride semiconductor layer, which is disposed between the third nitride semiconductor layer and the fourth nitride semiconductor layer, and has a larger band gap than the fourth nitride semiconductor layer.

15. The semiconductor device according to claim 14, wherein, The thickness of the 7th nitride semiconductor layer is less than 3 nm.

16. The semiconductor device according to any one of claims 1 to 15, wherein, The device includes an eighth p-type semiconductor layer, wherein the eighth p-type semiconductor layer is configured to be embedded in the second semiconductor layer at a position overlapping with the third semiconductor layer in a planar view. The upper surface of the 8th nitride semiconductor layer is coplanar with the upper surface of the 2nd nitride semiconductor layer.

17. A method for manufacturing a semiconductor device, wherein, include: In the first step, a first nitride semiconductor layer and a second nitride semiconductor layer with a band gap larger than the first nitride semiconductor layer are formed sequentially. In the second step, a p-type third nitride semiconductor layer, an i-type fourth nitride semiconductor layer with a larger band gap than the third nitride semiconductor layer and containing Al, and an i-type fifth nitride semiconductor layer without containing Al are sequentially formed above the second nitride semiconductor layer. The third step involves forming the source electrode and the drain electrode by sandwiching the third nitride semiconductor layer in between. as well as In the fourth step, a gate electrode is formed above the fifth nitride semiconductor layer.

18. A method for manufacturing a semiconductor device, wherein, include: In the first step, a first nitride semiconductor layer and a second nitride semiconductor layer with a band gap larger than the first nitride semiconductor layer are formed sequentially. In the second step, a p-type third nitride semiconductor layer, a fourth nitride semiconductor layer with a larger band gap than the third nitride semiconductor layer and containing Al, and a fifth nitride semiconductor layer without containing Al are sequentially formed above the second nitride semiconductor layer. The third step involves forming the source electrode and the drain electrode by sandwiching the third nitride semiconductor layer in between. as well as In the fourth step, a gate electrode is formed above the fifth nitride semiconductor layer. At least a portion of the fifth nitride semiconductor layer has a thickness of less than 3 nm.

19. The method of manufacturing a semiconductor device according to claim 17 or 18, wherein, The fifth nitride semiconductor layer includes an inner region and an outer region in a cross-section parallel to the gate length direction and thickness direction, respectively. The outer region is located on the outer side of the gate length direction compared to the inner region. The method for manufacturing the semiconductor device includes a fifth step, wherein the fifth step forms a first insulating film covering the upper surface of the outer region. In the fourth step, the gate electrode is formed in a manner that contacts the upper surface of the inner region.

20. The method of manufacturing a semiconductor device according to claim 19, wherein, The process includes a sixth step, in which the thickness of the inner region is made thinner than that of the outer region by etching the first insulating film as a mask.

21. The method of manufacturing a semiconductor device according to claim 20, wherein, The etching is a dry etching process using a gas containing hydrogen.

22. The method of manufacturing a semiconductor device according to claim 20 or 21, wherein, In the sixth step, etching is performed until the thickness of the inner region is less than 3 nm.

23. The method for manufacturing a semiconductor device according to any one of claims 19 to 22, wherein, A seventh step, which occurs after the first step and before the second step, includes forming a second insulating film with an opening. In the second step, the third nitride semiconductor layer, the fourth nitride semiconductor layer, and the fifth nitride semiconductor layer are formed within the opening.

24. The method for manufacturing a semiconductor device according to any one of claims 17 to 22, wherein, In the second step, a nitride semiconductor layer is formed by continuously growing crystals starting from the first step, and the third, fourth, and fifth nitride semiconductor layers are formed by patterning the formed nitride semiconductor layer.

25. The method of manufacturing a semiconductor device according to claim 24, wherein, In the patterning of the stacked film, the gate electrode is used as a mask for etching.

26. The method for manufacturing a semiconductor device according to any one of claims 17 to 25, wherein, In the second step, an n-type sixth nitride semiconductor layer is formed above the fifth nitride semiconductor layer.

27. The method for manufacturing a semiconductor device according to any one of claims 17 to 26, wherein, In the second step, a seventh nitride semiconductor layer with a larger band gap than the fourth nitride semiconductor layer is formed between the third nitride semiconductor layer and the fourth nitride semiconductor layer.

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