Semiconductor device

Abstract

A semiconductor device with good electrical characteristics is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor and a second conductor over the oxide semiconductor and separated from each other, a second insulator provided over the first conductor and the second conductor and formed with an opening overlapping a region between the first conductor and the second conductor, a third insulator provided in the opening and in contact with a top surface of the oxide semiconductor, side surfaces of the first conductor, side surfaces of the second conductor, and side surfaces of the second insulator, and a third conductor provided over the third insulator in the opening and having a region overlapping with the oxide semiconductor through the third insulator. The oxide semiconductor contains indium, and the first insulator includes a silicon oxide film containing nitrogen dioxide.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device using an oxide semiconductor. Another aspect of the present invention relates to a method for manufacturing the aforementioned semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and driving or manufacturing methods for the aforementioned devices.

[0003] Note that in this specification, etc., a semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Besides semiconductor elements such as transistors, semiconductor circuits, arithmetic processing devices, and storage devices are also types of semiconductor devices. Sometimes it can be said that display devices (liquid crystal displays, light-emitting displays, etc.), projection devices, lighting devices, electro-optical devices, energy storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, etc., include semiconductor devices. Background Technology

[0004] In recent years, semiconductor devices have been developed, with LSI (Large Scale Integration), CPU (Central Processing Unit), and memory being the main components used in semiconductor devices. A CPU is an assembly of semiconductor integrated circuits (including at least transistors and memory) that are fabricated from semiconductor wafers into chips and have electrodes formed as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards, such as printed circuit boards, and are used as components of various electronic devices.

[0006] Furthermore, the technique of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. Among other materials, oxide semiconductors have also garnered attention.

[0007] Furthermore, it is known that the leakage current of transistors using oxide semiconductors is extremely small in the non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes the characteristic of low leakage current of transistors using oxide semiconductors. Additionally, for example, Patent Document 2 discloses a storage device that utilizes the characteristic of low leakage current of transistors using oxide semiconductors to achieve long-term retention of stored content. [Preliminary Technology Documents] [Patent Literature]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 Summary of the Invention The technical problem that the invention aims to solve

[0009] One objective of this invention is to provide a semiconductor device with good electrical characteristics. Another objective is to provide a semiconductor device with high field-effect mobility. Another objective is to provide a semiconductor device with high reliability. Another objective is to provide a semiconductor device that can be miniaturized or highly integrated. Another objective is to provide a semiconductor device with high operating speed. Another objective is to provide a semiconductor device with low power consumption. Another objective is to provide a semiconductor device with less non-uniformity in the electrical characteristics of transistors. Another objective is to provide a novel semiconductor device. Another objective is to provide a method for manufacturing a semiconductor device with high productivity. Another objective is to provide a novel method for manufacturing a semiconductor device.

[0010] Note that the description of these objectives does not preclude the existence of other objectives. One aspect of the invention does not necessarily require achieving all of the above objectives. Objectives other than those described above can be extracted from the description, drawings, and claims. means of solving technical problems

[0011] One aspect of the present invention is a semiconductor device comprising: a first insulator; an oxide semiconductor on the first insulator; a first conductor and a second conductor separated from each other on the oxide semiconductor; a second insulator disposed on the first conductor and the second conductor and having an opening overlapping a region between the first conductor and the second conductor; a third insulator disposed within the opening and in contact with a top surface of the oxide semiconductor, a side surface of the first conductor, a side surface of the second conductor, and a side surface of the second insulator; and a third conductor disposed within the opening on the third insulator and having a region overlapping the third insulator and the oxide semiconductor, wherein the oxide semiconductor comprises indium, the first insulator comprises a silicon oxide film, and the silicon oxide film comprises nitrogen dioxide.

[0012] In the aforementioned semiconductor device, nitrogen dioxide preferably does not bond with the silicon dioxide contained in the silicon oxide film.

[0013] In the aforementioned semiconductor device, one of the migration energy levels of nitrogen dioxide in the first insulator is preferably above the valence band top and below the conduction band bottom of the oxide semiconductor.

[0014] Furthermore, in the aforementioned semiconductor device, it is preferred that the oxide semiconductor includes a first layer and a second layer on the first layer, the first layer comprising indium, the second layer comprising indium, gallium, zinc and oxygen, and the indium content in the first layer being higher than the indium content in the second layer.

[0015] Furthermore, in the aforementioned semiconductor device, the second layer is preferably separated into a third layer located under the first conductor and a fourth layer located under the second conductor.

[0016] Furthermore, in the aforementioned semiconductor device, it is preferable that the side of the third conductor of the third layer is arranged in a manner that is recessed from the side of the third conductor of the first conductor, and that the side of the third conductor of the fourth layer is arranged in a manner that is recessed from the side of the third conductor of the second conductor.

[0017] Furthermore, in the aforementioned semiconductor device, it is preferable that the third insulator has a stacked structure, and that the layer of the third insulator in contact with the oxide semiconductor comprises hafnium oxide.

[0018] Furthermore, in the aforementioned semiconductor device, it is preferable that an oxide layer is included between the oxide semiconductor and the first insulator, and the oxide layer comprises yttrium, zirconium, and oxygen.

[0019] Another aspect of the present invention is a semiconductor device comprising: a first insulator; an oxide semiconductor on the first insulator; a first conductor and a second conductor separated from each other on the oxide semiconductor; a second insulator disposed on the first conductor and the second conductor and having an opening overlapping a region between the first conductor and the second conductor; a third insulator disposed within the opening and in contact with the top surface of the oxide semiconductor, the side surface of the first conductor, and the side surface of the second conductor; a fourth insulator disposed within the opening between the second insulator and the third insulator; and a third insulator disposed within the opening on the third insulator and having a space between the third insulator and the oxide semiconductor. A third conductor in the overlapping region of the bodies, wherein the oxide semiconductor includes indium, the first insulator includes a silicon oxide film, the silicon oxide film includes nitrogen dioxide, the first conductor and the second conductor respectively include a first conductive layer and a second conductive layer on the first conductive layer, the shortest distance between the first conductive layer of the first conductor and the first conductive layer of the second conductor is less than the shortest distance between the second conductive layers of the first conductor and the second conductive layer of the second conductor, and the fourth insulator is in contact with the top surface of the first conductive layer of the first conductor, the side surface of the second conductive layer of the first conductor, the top surface of the first conductive layer of the second conductor, and the side surface of the second conductive layer of the second conductor.

[0020] In the aforementioned semiconductor device, nitrogen dioxide preferably does not bond with the silicon dioxide contained in the silicon oxide film.

[0021] Furthermore, in the aforementioned semiconductor device, one of the migration energy levels of nitrogen dioxide in the first insulator is preferably above the valence band top and below the conduction band bottom of the oxide semiconductor.

[0022] Furthermore, in the aforementioned semiconductor device, it is preferred that the oxide semiconductor includes a first layer and a second layer on the first layer, the first layer comprising indium, the second layer comprising indium, gallium, zinc and oxygen, and the indium content in the first layer being higher than the indium content in the second layer.

[0023] Furthermore, in the aforementioned semiconductor device, the second layer is preferably divided into a third layer located under the first conductive layer of the first conductor and a fourth layer located under the first conductive layer of the second conductor.

[0024] Furthermore, in the aforementioned semiconductor device, it is preferable that the side of the third conductor of the third layer is arranged to be recessed from the side of the third conductor of the first conductive layer of the first conductor, and that the side of the third conductor of the fourth layer is arranged to be recessed from the side of the third conductor of the first conductive layer of the second conductor.

[0025] Furthermore, in the aforementioned semiconductor device, it is preferable that the third insulator has a stacked structure, and that the layer of the third insulator in contact with the oxide semiconductor comprises hafnium oxide.

[0026] Furthermore, in the aforementioned semiconductor device, it is preferable that an oxide layer is included between the oxide semiconductor and the first insulator, and the oxide layer comprises yttrium, zirconium, and oxygen. Invention Effects

[0027] According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high field-effect mobility can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high operating speed can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with less non-uniformity in the electrical characteristics of transistors can be provided. Furthermore, according to one aspect of the present invention, a novel semiconductor device can be provided. Furthermore, according to one aspect of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. Furthermore, according to one aspect of the present invention, a novel method for manufacturing a semiconductor device can be provided. Furthermore, according to one aspect of the present invention, a novel display device can be provided.

[0028] Note that the description of these effects does not preclude the existence of other effects. One aspect of the invention does not necessarily require all of the aforementioned effects. Effects other than those described above can be extracted from the specification, drawings, and claims. Brief description of the attached figures

[0029] Figure 1A This is a schematic diagram illustrating an example of a semiconductor device. Figure 1B It is based on the calculation model of semiconductor devices. Figure 2 It is based on the energy band diagram of a semiconductor device. Figure 3A This is a plan view showing an example of a semiconductor device. Figures 3B to 3D This is a cross-sectional view showing an example of a semiconductor device. Figure 4A and Figure 4B This is a cross-sectional view showing an example of a semiconductor device. Figures 5A to 5C This is a cross-sectional view showing an example of a semiconductor device. Figure 6A This is a plan view showing an example of a semiconductor device. Figures 6B to 6D This is a cross-sectional view showing an example of a semiconductor device. Figures 7A to 7C This is a cross-sectional view showing an example of a semiconductor device. Figure 8 This is a cross-sectional view showing an example of a semiconductor device. Figures 9A to 9C This is a cross-sectional view showing an example of a semiconductor device. Figures 10A to 10E This is a cross-sectional view showing an example of a semiconductor device. Figure 11A This is a plan view showing an example of a semiconductor device. Figures 11B to 11D This is a cross-sectional view showing an example of a semiconductor device. Figure 12 This is a cross-sectional view showing an example of a semiconductor device. Figure 13A This is a plan view showing an example of a semiconductor device. Figures 13B to 13D This is a cross-sectional view showing an example of a semiconductor device. Figure 14A This is a plan view showing an example of a semiconductor device. Figures 14B to 14D This is a cross-sectional view showing an example of a semiconductor device. Figure 15A This is a plan view showing an example of a semiconductor device. Figures 15B to 15D This is a cross-sectional view showing an example of a semiconductor device. Figure 16A This is a plan view showing an example of a semiconductor device. Figures 16B to 16D This is a cross-sectional view showing an example of a semiconductor device. Figures 17A to 17C This is a cross-sectional view showing an example of a semiconductor device. Figures 18A to 18C This is a cross-sectional view showing an example of a semiconductor device. Figures 19A to 19C This is a cross-sectional view showing an example of a semiconductor device. Figures 20A to 20C This is a cross-sectional view showing an example of a semiconductor device. Figures 21A to 21C This is a cross-sectional view showing an example of a semiconductor device. Figures 22A to 22C This is a cross-sectional view showing an example of a semiconductor device. Figure 23A This is a plan view showing an example of a semiconductor device. Figures 23B to 23D This is a cross-sectional view showing an example of a semiconductor device. Figure 24A and Figure 24B This is a cross-sectional view showing an example of a semiconductor device. Figure 25AThis is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 25B to 25D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 26A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 26B to 26D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 27A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 27B to 27D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 28A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 28B to 28D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 29A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 29B to 29D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 30A1 to 30D2 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 31A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 31B to 31D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 32A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 32B to 32D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 33A This is a plan view illustrating an example of a method for manufacturing a semiconductor device. Figures 33B to 33D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 34A1 to 34B2 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 35A1 to 35B2 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 36 This is a block diagram illustrating an example of the structure of a semiconductor device. Figures 37A to 37H This is a diagram illustrating an example of the circuit structure of a memory cell. Figure 38 This is a cross-sectional view showing an example of a semiconductor device. Figure 39A and Figure 39B This is a three-dimensional diagram illustrating an example of the structure of a semiconductor device. Figure 40 This is a cross-sectional view showing an example of a semiconductor device. Figure 41 This is a cross-sectional view showing an example of a semiconductor device. Figure 42 This is a block diagram illustrating the CPU. Figure 43A and Figure 43B It is a 3D diagram of a semiconductor device. Figure 44A and Figure 44B It is a 3D diagram of a semiconductor device. Figure 45A and Figure 45B A diagram showing the various storage devices in a hierarchical manner. Figure 46A and Figure 46B This is a diagram illustrating an example of an electronic device. Figures 46C to 46E This is a diagram illustrating an example of a large computer. Figure 47 This is a diagram illustrating an example of a space device. Figure 48 This is a diagram illustrating an example of a storage system that can be used in a data center. Figure 49A and Figure 49B This is an example of the structure of a display device. Figure 50 This is an example of the structure of a display device. Figure 51 This is an example of the structure of a display device. Figure 52 This is an example of the structure of a display device. Figures 53A to 53D This is an example of the structure of a display device. Figure 54A and Figure 54B This is an example of the structure of a display device. Figure 55A and Figure 55B This is a diagram illustrating an example of the structure of a display device. Figures 56A to 56D This is a diagram illustrating an example of the structure of a display device. Figures 57A to 57D This is a diagram illustrating an example of the structure of a display device. Figure 58 This is a diagram illustrating an example of the structure of a display device. Figures 59A to 59F This is an example of the structure of an electronic device. Figures 60A to 60F This is an example of the structure of an electronic device. Figures 61A to 61G This is an example of the structure of an electronic device. Methods of implementing the invention

[0030] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0031] Note that in the structure of the invention described below, the same reference numerals are used in different figures to indicate the same parts or parts having the same function, and repeated descriptions are omitted. Furthermore, when indicating parts having the same function, the same shading lines are sometimes used without additional symbols.

[0032] Furthermore, for ease of understanding, the positions, sizes, and extents of the constituent elements shown in the accompanying drawings may not represent their actual positions, sizes, and extents. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the accompanying drawings.

[0033] In this specification and other documents, ordinal numbers such as "first" and "second" are used for convenience, but these do not limit the number of constituent elements or the order of the constituent elements (e.g., process sequence or stacking sequence). Furthermore, the ordinal numbers used for constituent elements in one part of this specification may sometimes differ from those used for the same constituent element in other parts of this specification or in the claims.

[0034] Furthermore, depending on the circumstances or conditions, the "film" and "layer" can be interchanged. For example, a "conductive layer" can be replaced with a "conductive film." Additionally, an "insulating film" can be replaced with an "insulating layer." Furthermore, an "oxide semiconductor film" can be replaced with an "oxide semiconductor layer." Additionally, depending on the circumstances or conditions, a "conductor" can be replaced with a "conductive layer" or a "conductive film." Additionally, depending on the circumstances or conditions, an "insulator" can be replaced with an "insulating layer" or an "insulating film." Additionally, depending on the circumstances or conditions, an "oxide semiconductor" can be replaced with an "oxide semiconductor layer" or an "oxide semiconductor film."

[0035] In this specification, "parallel" refers to a state where the angle formed by two straight lines is -10° or more and less than 10°. Therefore, it also includes a state where the angle is -5° or more and less than 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is -20° or more and less than 20°. Furthermore, "perpendicular" refers to a state where the angle between two straight lines is 80° or more and less than 100°. Therefore, it also includes a state where the angle is 85° or more and less than 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is 70° or more and less than 110°.

[0036] Openings include, for example, grooves and slits. Furthermore, the area where an opening is formed is sometimes referred to as an opening portion.

[0037] Furthermore, the accompanying drawings used in this specification and the like show the case where the sidewall of the insulator in the opening of the insulator is perpendicular or substantially perpendicular to the substrate surface or the surface to which it is formed, but the sidewall may also be tapered.

[0038] Note that in this specification, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region where the angle (hereinafter sometimes referred to as the cone angle) formed by the inclined side surface and the substrate surface or the surface to be formed is less than 90°. Note that the side surface of the constituent element and the substrate surface do not necessarily have to be completely flat; they may also be approximately planar with slight curvature or approximately planar with slight irregularities.

[0039] In this specification and the like, transistors that use oxide semiconductors or metal oxides as semiconductor layers, and transistors that contain oxide semiconductors or metal oxides in the channel formation region, are sometimes referred to as OS transistors. Furthermore, transistors that contain silicon in the channel formation region are sometimes referred to as Si transistors.

[0040] (Implementation Method 1) In this embodiment, refer to Figures 1A to 35B2 This describes a semiconductor device using oxide semiconductors and a method for manufacturing such a semiconductor device.

[0041] First, refer to Figure 1A The schematic diagram shown illustrates an OS transistor according to one aspect of the present invention. Figure 1A This is a schematic diagram showing the area near the channel formation region of the OS transistor. (See diagram below.) Figure 1A As shown, an insulator 250 is disposed between the oxide semiconductor 230 and the conductor 260. Furthermore, the insulator 224 is disposed opposite to the insulator 250 with the oxide semiconductor 230 separated from it.

[0042] The oxide semiconductor 230 has a region used as a channel formation region. The oxide semiconductor 230 preferably uses a metal oxide containing indium. For example, indium oxide (also known as In oxide, IO), In-Ga oxide, In-Zn oxide, or In-Ga-Zn oxide can be used. Furthermore, the conductor 260 is used as the gate electrode of the OS transistor. Furthermore, the insulator 250 is used as the gate insulator of the OS transistor. The insulator 224 is preferably used as the base film of the oxide semiconductor 230, and can be, for example, silicon oxide or silicon oxynitride. Note that detailed structures of the oxide semiconductor 230, conductor 260, insulator 250, and insulator 224 can be found in the description below.

[0043] like Figure 1A As shown, insulator 224 contains impurity 220. When insulator 224 contains silicon oxide or silicon oxynitride, impurity 220 preferably contains nitrogen; for example, nitrogen dioxide (NO2) can be used as impurity 220. That is, the silicon oxide film or silicon oxynitride film contains nitrogen dioxide.

[0044] Here, we present the results of calculations using a model with NO2 added to silicon oxide and first-principles calculations to determine the transition energy levels of the charge states of this model. For example... Figure 1B As shown, SiO2 (c-SiO2) with a low-temperature quartz (α-quartz) crystal structure is used for calculations. In this model, NO2 is introduced between the crystal lattices (hereinafter sometimes referred to as the NO2 model). Furthermore, for comparison, models introducing NO, N2O, O, and O2 between the crystal lattices are also calculated.

[0045] In the NO2 model, structural optimization calculations were performed for states with a system charge of +1, a system charge of 0, and a system charge of -1. Calculations showed that the structural changes of NO2 with varying charge are roughly equivalent to the changes in bond angles when the charge number of isolated molecules in the gas phase is changed. Therefore, the assumed charge is almost entirely NO2, and it can be inferred that NO2 in silicon dioxide (SiO2) exists in a near-isolated molecule state. That is, insulator 224 contains NO2 that is not bonded to SiO2. Alternatively, it can be said that the NO2 in insulator 224 is in a state where it is not bonded to SiO2. For example, sometimes the NO2 in insulator 224 is configured with the surrounding SiO2 at a distance equivalent to the covalent bond radius.

[0046] Figure 2 The results of first-principles calculations for each model are shown. Figure 2 The band structure diagram of c-SiO2 and the migration levels in the model incorporating NO2, NO, N2O, O, and O2 are shown. The band structure of c-SiO2 shows the conduction band bottom Ec and valence band top Ev relative to the vacuum level Evac. Furthermore, migration levels are shown for states with charges of +1 and 0 (+1 / 0), states with charges of 0 and -1 (0 / -1), and states with charges of 0 and -2 (0 / -2). The values ​​for each migration level are shown relative to Ev of SiO2 (0.0 eV) (unit: eV). Figure 2 Showing IGZO(111) and indium oxide (InO) xThe band structure diagram is shown below. Here, IGZO(111) refers to an In-Ga-Zn oxide with an In:Ga:Zn ratio of 1:1:1 [atomic ratio]. IGZO(111) and InO x Ec and Ev are experimental values.

[0047] like Figure 2 As shown, in IGZO (111) and InO x The band gap contains the NO2 model's transition energy level (0 / -1). Here, IGZO (111) or InO... x Considering that c-SiO2 is used as an oxide semiconductor 230, c-SiO2 is used as an insulator 224, and NO2 is used as an impurity 220. Figure 1A The model of the OS transistor is shown. At this point, it can be said that one of the migration energy levels of the impurity 220 in the insulator 224 is above Ev and below Ec of the oxide semiconductor 230.

[0048] When the OS transistor is turned on, electrons are injected into the oxide semiconductor 230 by supplying a potential to the conductor 260 of the gate electrode, but as Figure 2 As shown, a NO2 model migration level (0 / -1) exists at a position lower than Ec of oxide semiconductor 230, and thus this electron is captured by impurity 220 (NO2). The charge of impurity 220 (NO2) that captures this electron becomes -1, so impurity 220 becomes a negative fixed charge. Note that in the model introducing NO, N2O, O, O2, the migration level (0 / -1) or migration level (0 / -2) is higher than or too close to Ec of oxide semiconductor 230, so impurity 220 is difficult to be used as a negative fixed charge.

[0049] As described above, when the impurity 220 in the insulator 224 becomes a negative fixed charge, a larger potential needs to be supplied to the conductor 260 in order to turn the OS transistor on. In other words, by making the impurity 220 in the insulator 224 a negative fixed charge, the threshold voltage of the OS transistor can be shifted in the positive direction.

[0050] In an OS transistor, when oxygen vacancies (V0) exist in the channel formation region of the oxide semiconductor... O When impurities such as hydrogen are present, the electrical properties are easily altered. For example, V O Nearby hydrogen forms hydrogen that enters V O The defect in (hereinafter sometimes referred to as V) O H) may generate electrons that become charge carriers. Therefore, when V is included in the channel formation region of an oxide semiconductor... O At this time, OS transistors tend to have always-on characteristics.

[0051] However, as described above, by employing a structure where the impurities 220 in the insulator 224 have a negative fixed charge, the negative drift of the electrical characteristics of the OS transistor can be suppressed, thereby achieving normally-off characteristics. Therefore, a semiconductor device with good electrical characteristics can be provided.

[0052] Impurities 220 in insulator 224 can be evaluated by electron spin resonance (ESR) or thermal desorption spectroscopy (TDS) analysis.

[0053] For example, when silicon oxide is used as insulator 224 and nitrogen dioxide is added as impurity 220, evaluation can be performed using ESR measurements. Because neutral NO2 in silicon oxide contains isolated electrons, ESR measurements can be performed. The absorption peak originating from NO2 obtained by ESR measurements falls within the range of g values ​​greater than 1.94 and less than 2.05. Therefore, the spin density of insulator 224 corresponding to the absorption peak with g values ​​greater than 1.94 and less than 2.05 obtained by ESR measurements is 4.8 × 10⁻⁶. - 3 spins / nm 3 Above and 1.0×10 -2 spins / nm 3 The preferred value is 7.38 × 10⁻⁶. -3 spins / nm 3 Above and 1.0×10 - 2 spins / nm 3 The following applies. When the absorption peak of the ESR obtained from the insulator 224 containing impurity 220 reaches the aforementioned value, the threshold voltage of the OS transistor can be made to be 0V or higher. Furthermore, the addition process of impurity 220 can be performed efficiently to improve the productivity of semiconductor devices.

[0054] Note that the insulator 224 satisfying the above spin density is not limited to the vicinity of the oxide semiconductor 230. Preferably, the insulator 224 has the above spin density in the region surrounding the OS transistor, such as the region where a mark is formed or the region where an electrode pad is formed.

[0055] It is preferable to add impurity 220 to insulator 224 by plasma treatment with a nitrogen-containing gas. Nitrogen gas or nitrous oxide (N2O) gas can be used as the nitrogen-containing gas. By treating the silicon oxide insulator 224 with plasma-treated N2 or N2O, NO2 can be added to the insulator 224 as impurity 220.

[0056] In the plasma treatment described above, sputtering equipment, CVD equipment, dry etching equipment, CVD equipment using a high-density plasma source, or dry etching equipment using a high-density plasma source can be used. Therefore, when performing deposition or etching processes using these equipment before or after the plasma treatment, these processes and the plasma treatment can be performed continuously.

[0057] Furthermore, through the plasma treatment described above, oxygen (hereinafter sometimes referred to as excess oxygen) that has been removed by heating can be added to the insulator 224. In this case, oxygen gas can be used in addition to nitrogen-containing gas during the plasma treatment. By heating the insulator 224 with excess oxygen added, oxygen can diffuse from the insulator 224 into the oxide semiconductor 230, thereby reducing the oxygen vacancies (V0) in the oxide semiconductor 230. O This allows for improvements in the electrical characteristics and reliability of OS transistors containing oxide semiconductor 230.

[0058] Additionally, substrate heating can be performed during the plasma treatment described above. Furthermore, heating can be performed before or after the plasma treatment. The temperature for substrate heating or heating treatment can be, for example, 200°C or higher and 450°C or lower, preferably 350°C or higher and 400°C or lower. Thus, by heating or heating the substrate before forming the oxide semiconductor 230, excess oxygen contained in the insulator 224 can be reduced. This suppresses the presence of excessive oxygen in the insulator 224 and adjusts the oxygen content in the insulator 224 to an appropriate level. Therefore, it prevents excessive oxygen from being supplied to the oxide semiconductor 230, thus preventing the threshold voltage of the OS transistor from becoming too high. This improves the electrical characteristics of the OS transistor. Additionally, the reliability of the OS transistor can be improved. Furthermore, by setting the temperature for substrate heating or heating treatment to 450°C or lower, and more specifically 400°C or lower, the detachment of impurities 220 due to substrate heating or heating treatment can be suppressed.

[0059] <Examples of semiconductor device structures> Next, a structural example of a planar semiconductor device (transistor 200) will be described with reference to Figures 3 and 4. Figures 3A to 3D These are plan and cross-sectional views of a semiconductor device (transistor 200). Figure 3A This is a plan view of the semiconductor device. Additionally, Figures 3B to 3D This is a cross-sectional view of the semiconductor device. Here, Figure 3B It is along Figure 3A The cross-sectional view of the section marked with dotted lines A1-A2 is also a cross-sectional view along the channel length of transistor 200. Furthermore, Figure 3C It is along Figure 3AThe cross-sectional view of the section marked with dotted lines A3-A4 is also a cross-sectional view of the channel width direction of transistor 200. Additionally, Figure 3D It is along Figure 3A The cross-sectional view of the section marked with dashed lines A5-A6 is also a cross-sectional view of the channel width direction of transistor 200. Figure 3A In the plan view, some constituent elements have been omitted for clarity. Additionally, Figure 4A and Figure 4B This is an enlarged cross-sectional view of the transistor 200 along its channel length.

[0060] Transistor 200 includes a conductor 205 disposed in an insulator 216, an insulator 216, an insulator 221 on the conductor 205, an insulator 222 on the insulator 221, an insulator 224 on the insulator 222, an oxide semiconductor 230 on the insulator 224, conductors 242a and 242b on the oxide semiconductor 230, an insulator 271a on the conductor 242a, an insulator 271b on the conductor 242b, an insulator 250 on the oxide semiconductor 230, and a conductor 260 on the insulator 250. Here, oxide semiconductor 230 corresponds to... Figure 1A The oxide semiconductor 230 shown corresponds to the conductor 260. Figure 1A The conductor 260 and insulator 250 shown correspond to Figure 1A The insulator 250 and insulator 224 shown correspond to Figure 1A The insulator 224 is shown.

[0061] The oxide semiconductor 230 has a region serving as the channel formation region of the transistor 200. Furthermore, the conductor 260 has a region serving as the first gate electrode (also referred to as the upper gate electrode or top gate electrode) of the transistor 200. The insulator 250 has a region serving as the first gate insulator of the transistor 200. Furthermore, the conductor 205 has a region serving as the second gate electrode (also referred to as the lower gate electrode or bottom gate electrode) of the transistor 200. Insulators 224, 222, and 221 each have a region serving as the second gate insulator of the transistor 200. The conductor 242a has a region serving as one of the source and drain electrodes of the transistor 200. The conductor 242b has a region serving as the other of the source and drain electrodes of the transistor 200.

[0062] An insulator 275 is provided on insulators 271a and 271b, and an insulator 280 is provided on insulator 275. Openings are formed in insulators 280 and 275, reaching insulator 222 and oxide semiconductor 230, and these openings overlap with the area between conductors 242a and 242b. In plan view (also known as from a flat plane view), the side of insulator 280 in the opening is aligned or substantially aligned with the side of conductors 242a and 242b. Insulators 250 and 260 are disposed inside the openings provided in insulators 280 and 275. Furthermore, an insulator 282 is provided in contact with the top surface of insulator 280, the upper end of insulator 250, and the top surface of conductor 260. Insulator 283 is provided on insulator 282. Furthermore, an insulator 214 is provided below insulator 216 and conductor 205. In addition, an insulator 212 is provided below the insulator 214. Insulators 212, 214, 280, 282, 283 and 285 are used as interlayer membranes.

[0063] An opening is formed in insulators 285, 283, 282, 280, 275, and 271a to reach conductor 242a. Conductor 240a and insulator 241a are disposed within this opening. Insulator 241a is disposed in contact with the sidewall of this opening, and conductor 240a is disposed inside insulator 241a. Furthermore, an opening is formed in insulators 285, 283, 282, 280, 275, and 271b to reach conductor 242b. Conductor 240b and insulator 241b are disposed within this opening. Insulator 241b is disposed in contact with the sidewall of this opening, and conductor 240b is disposed inside insulator 241b. Conductors 240a and 240b are used as vias to connect wiring or other components disposed on transistor 200 to the source or drain of transistor 200. Furthermore, when viewed from above, conductors 240a and 240b can have shapes that are approximately circular, elliptical, or polygonal, or polygonal shapes with rounded corners.

[0064] The oxide semiconductor 230 has a channel formation region. The oxide semiconductor 230 also has a source region and a drain region. The source and drain regions are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region. The oxide semiconductor 230 can be a single-layer structure or a stacked structure of two or more layers.

[0065] There are no particular restrictions on the crystallinity of the semiconductor material used for oxide semiconductor 230; amorphous semiconductors, single-crystal semiconductors, or semiconductors with crystallinity other than single crystal (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with a portion of crystalline regions) can be used. Using single-crystal semiconductors or crystalline semiconductors can suppress the degradation of transistor characteristics, and is therefore preferred.

[0066] The bandgap of the metal oxide used as the semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wider bandgap in the oxide semiconductor 230, the off-state current of the transistor 200 can be reduced. The off-state current of the OS transistor is small, so the power consumption of the semiconductor device can be significantly reduced. In addition, the OS transistor has high frequency characteristics, so the semiconductor device can operate at high speed.

[0067] Regarding the oxide semiconductor layer that can be used as a transistor according to one aspect of the present invention, refer to the description of Embodiment 2. Detailed description is omitted here.

[0068] Furthermore, transistors using other semiconductor materials in the channel formation region can also be used in the semiconductor device of this embodiment. Examples of such other semiconductor materials include semiconductors or compound semiconductors composed of a single element.

[0069] Examples of semiconductors composed of a single element that can be used as semiconductor materials include silicon and germanium. Furthermore, examples of silicon that can be used as semiconductor materials include monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polycrystalline silicon (LTPS).

[0070] Examples of compound semiconductors that can be used as semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride, which can be used as a semiconductor layer, preferably has an amorphous structure. Boron arsenide, which can be used as a semiconductor layer, preferably comprises a crystal with a cubic structure. Furthermore, examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also types of compound semiconductors. These semiconductor materials may also contain impurities as dopants.

[0071] Here, the oxide semiconductor 230 for the semiconductor device preferably comprises indium oxide. For example, the oxide semiconductor 230 may use indium oxide, indium gallium oxide, indium zinc oxide, indium gallium zinc oxide, or indium gallium tin zinc oxide, etc. Furthermore, the oxide semiconductor 230 may have a stacked structure. For example, the oxide semiconductor 230 may have a stacked structure of indium oxide and indium gallium zinc oxide on indium oxide. Additionally, as... Figure 4AAs shown, the oxide semiconductor 230 may include oxide semiconductor 230a on insulator 224, oxide semiconductor 230b on oxide semiconductor 230a, and oxide semiconductor 230c on oxide semiconductor 230b. For example, indium oxide may be used for oxide semiconductor 230b, and indium gallium zinc oxide may be used for oxide semiconductor 230a and oxide semiconductor 230c. For example, oxide semiconductor 230a may have an In:Ga:Zn ratio of 1:3:2 or similar. Additionally, oxide semiconductor 230c may have an In:Ga:Zn ratio of 1:1:1 or similar. As described above, when oxide semiconductor 230 includes indium oxide, a semiconductor device with high field-effect mobility can be provided. Furthermore, a semiconductor device with good electrical characteristics, frequency characteristics, and reliability can be provided. Moreover, by employing this structure, an oxide semiconductor 230c containing indium gallium zinc oxide with low oxygen permeability can be disposed between oxide semiconductor 230b containing indium oxide with high oxygen permeability and conductor 242a (conductor 242b). Therefore, the amount of oxygen extracted from the oxide semiconductor 230b by the conductor 242a (conductor 242b) can be reduced, thereby reducing the possibility of increased contact resistance between the oxide semiconductor 230b and the conductor 242a (conductor 242b). Note that the detailed structure of the oxide semiconductor 230 can be found in Embodiment 2.

[0072] Note that in Figure 4A In the examples, oxide semiconductor 230 has a three-layer stacked structure of oxide semiconductor 230a to oxide semiconductor 230c, but the present invention is not limited thereto. For example, as... Figure 5A As shown, the oxide semiconductor 230 can also have a two-layer structure of oxide semiconductor 230a and oxide semiconductor 230b. In this case, the top surface of oxide semiconductor 230b is in contact with the bottom surface of insulator 250, the bottom surface of conductor 242a, and the bottom surface of conductor 242b. Furthermore, for example, as... Figure 5B As shown, the oxide semiconductor 230 can also have a single-layer structure of oxide semiconductor 230b. In this case, the bottom surface of oxide semiconductor 230b is in contact with the top surface of insulator 224.

[0073] In addition, such as Figure 5CAs shown, an oxide semiconductor 230c can be separated in the region overlapping with the insulator 250 to form oxide semiconductors 230ca and 230cb. Preferably, the top surface of oxide semiconductor 230ca contacts the bottom surface of conductor 242a, and in a top view, oxide semiconductor 230ca is aligned or substantially aligned with conductor 242a. Similarly, preferably, the top surface of oxide semiconductor 230cb contacts the bottom surface of conductor 242b, and in a top view, oxide semiconductor 230cb is aligned or substantially aligned with conductor 242b. Furthermore, a portion of the top surface of oxide semiconductor 230b contacts the insulator 250. By adopting this structure, it is possible to achieve a structure where oxide semiconductor 230ca (oxide semiconductor 230cb) is formed between conductor 242a (conductor 242b) and oxide semiconductor 230b, and the channel of transistor 200 is formed only in oxide semiconductor 230b. For example, when aluminum oxide is used as the insulator 250a and indium oxide is used as the oxide semiconductor 230b, the aluminum oxide and indium oxide are in contact at the interface between the insulator 250a and the oxide semiconductor 230b. By adopting this structure, the formation of impurity traps at this interface can be suppressed. As a result, the on-state current, carrier mobility, and frequency characteristics of the transistor 200 can be improved.

[0074] The oxide semiconductor 230b preferably contains indium (In), and more preferably, has a high In content. For example, the In content in the oxide semiconductor 230b is preferably higher than the In content of one or both of the oxide semiconductors 230a and 230c. By using a metal oxide with a high In content as the oxide semiconductor 230b, the on-state current can be increased, thereby improving the frequency characteristics.

[0075] For example, the oxide semiconductor 230b preferably comprises indium oxide. Furthermore, the oxide semiconductor 230b preferably uses high-purity indium oxide with reduced impurity concentration. When indium oxide is used as the oxide semiconductor 230b, high crystallinity is preferred, and it is preferable to have single-crystal or similar crystallinity.

[0076] When using high-purity indium oxide (INO) with reduced impurity concentration as the oxide semiconductor 230b, the concentration of the first element in the oxide semiconductor 230b is preferably low. Here, the first element is at least one of boron, aluminum, and gallium. The concentration of the first element in the oxide semiconductor 230b is preferably, for example, 1 atomic% or less, more preferably 0.1 atomic% or less, and even more preferably 0.01 atomic% (100 ppm) or less. By reducing the concentrations of boron and aluminum in the oxide semiconductor 230b, the crystallinity of the oxide semiconductor 230b can be improved. Furthermore, by reducing the gallium concentration in the oxide semiconductor 230b, the variation in threshold voltage during PBTS (Positive Bias Temperature Stress) testing can be reduced. Therefore, a transistor with high reliability for applying a positive bias voltage can be realized.

[0077] Furthermore, indium oxide (IO) has a small effective electron mass, for example, smaller than that of silicon. Therefore, by using IO, which has a small effective electron mass, in oxide semiconductor 230b, transistors with high on-state current, high field-effect mobility, and high frequency characteristics (also known as f-characteristics) can be realized. Conversely, indium oxide (IO) has a large effective hole mass, for example, greater than that of silicon. Therefore, by using IO, which has a large effective hole mass, in oxide semiconductor 230b, transistors with extremely small off-state current can be realized.

[0078] In addition, such as Figures 6A to 6D As shown, a layer 227 is preferably disposed between the oxide semiconductor 230 and the insulator 224. The bottom surface of layer 227 contacts the top surface of the insulator 224, and the top surface of layer 227 contacts the bottom surface of the oxide semiconductor 230. Furthermore, the side surfaces of layer 227 are preferably aligned with the side surfaces of the insulator 224 and the oxide semiconductor 230. Figures 6A to 6D Corresponding to Figures 3A to 3D Aside from the location with layer 227, it is connected to... Figures 3A to 3D Similarly.

[0079] The resistivity of layer 227 is preferably higher than that of oxide semiconductor 230. Alternatively, when oxide semiconductor 230 has a stacked structure, the resistivity of layer 227 is preferably higher than that of at least one of the layers constituting oxide semiconductor 230. For example, when oxide semiconductor 230 has a stacked structure of oxide semiconductors 230a to 230c, the resistivity of layer 227 is preferably higher than any one of oxide semiconductors 230a to 230c. Therefore, an insulator or a semiconductor is used as layer 227. For example, an oxide layer or a metal oxide layer can be used as layer 227. For example, an insulating material suitable for insulators described later or a metal oxide material suitable for oxide semiconductors described later can be used as layer 227. Furthermore, layer 227 can have a single-layer structure or a stacked structure. By providing such layer 227, the diffusion of impurities from the bottom surface of oxide semiconductor 230 into oxide semiconductor 230 can be suppressed. As a result, the electrical characteristics and reliability of transistor 200 using oxide semiconductor 230 can be improved.

[0080] Layer 227 preferably has crystallinity, and more preferably has single-crystal or single-crystal-like crystallinity. Here, the lattice constant of layer 227 is preferably the same as or substantially the same as the lattice constant of oxide semiconductor 230 (or lattice matching). By forming oxide semiconductor 230 on layer 227, the crystallinity of layer 227 can sometimes be reflected in oxide semiconductor 230 to form a well-crystallized oxide semiconductor 230.

[0081] For example, yttrium-stabilized zirconia (YSZ) can also be used as layer 227. Here, layer 227 contains yttrium and zirconium. When YSZ is used as layer 227, the crystallinity of YSZ is preferably high, and preferably has single-crystal or near-single-crystal crystallinity. By using highly crystalline YSZ as layer 227, the crystallinity of YSZ can sometimes be reflected in the oxide semiconductor 230. For example, by using indium oxide as oxide semiconductor 230, indium oxide with single-crystal or near-single-crystal crystallinity can be formed.

[0082] As described above, when using an oxide insulating material for layer 227, it is preferable to include at least one of gallium, aluminum, and zirconium. For example, aluminum oxide, gallium oxide, zirconium oxide, etc., may also be used.

[0083] Furthermore, for example, when using an oxide semiconductor material suitable for oxide semiconductor 230 as layer 227, layer 227 can be an In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:3:2 or similar, or an In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:1:1 or similar. Alternatively, structures using indium zinc oxide, gallium zinc oxide, or zinc oxide can be employed. The crystal structure of the oxide semiconductor used for layer 227 can adopt a CAAC (c-axis aligned crystalline) structure, as described later.

[0084] Note that layer 227 is not limited to this. For example, highly crystalline silicon, silicon carbide, gallium nitride, etc., can be used as layer 227.

[0085] In addition, such as Figure 7A As shown, a layer 227 can also be formed between the oxide semiconductor 230 and the insulator 224 in a two-layer structure of oxide semiconductor 230b and oxide semiconductor 230c. That is, in Figure 4B In the structure shown, layer 227 can be used instead of oxide semiconductor 230a. Here, the top surface of layer 227 is in contact with the bottom surface of oxide semiconductor 230b. For example, YSZ can be used for layer 227, indium oxide for oxide semiconductor 230b, and In-Ga-Zn oxide for oxide semiconductor 230c.

[0086] In addition, such as Figure 7B As shown, the oxide semiconductor 230 can have a single-layer structure of oxide semiconductor 230b, with a layer 227 formed between the oxide semiconductor 230b and the insulator 224. That is, in Figure 5A In the structure shown, layer 227 can be used instead of oxide semiconductor 230a. Here, the top surface of layer 227 is in contact with the bottom surface of oxide semiconductor 230b. For example, YSZ can be used for layer 227 and indium oxide can be used for oxide semiconductor 230b.

[0087] In addition, such as Figure 7C As shown, in Figure 7A In the structure shown, oxide semiconductor 230c can be separated in the region overlapping with insulator 250 to form oxide semiconductor 230ca and oxide semiconductor 230cb. That is, in Figure 5C In the structure shown, layer 227 can be used instead of oxide semiconductor 230a.

[0088] The oxide semiconductor 230 has a channel forming region for the transistor 200, as well as a source region and a drain region disposed in a manner that clamps the channel forming region. At least a portion of the channel forming region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can also be interchanged.

[0089] Because it has fewer oxygen vacancies or lower impurity concentrations compared to the source and drain regions, the channel formation region is a high-resistivity region with low carrier concentration. Therefore, the channel formation region can be considered an i-type (intrinsic) or essentially i-type region.

[0090] Furthermore, due to the abundance of oxygen vacancies or the high concentration of impurities such as hydrogen, nitrogen, and metal elements, the source and drain regions are low-resistance regions with high carrier concentration. In other words, the source and drain regions are n-type regions (low-resistance regions) with higher carrier concentration compared to the channel formation region.

[0091] The preferred carrier concentration in the channel formation region is 1×10⁻⁶. 18 cm -3 Below, less than 1×10 17 cm -3 Less than 1×10 16 cm -3 Less than 1×10 15 cm -3 Less than 1×10 14 cm -3 Less than 1×10 13 cm -3 Less than 1×10 12 cm -3 Less than 1×10 11 cm -3 Or less than 1×10 10 cm -3 Note that there is no specific limit to the lower limit of carrier concentration in the channel formation region; for example, it can be 1 × 10⁻⁶. -9 cm -3 .

[0092] When the purpose is to reduce the carrier concentration of the oxide semiconductor 230, the impurity concentration in the oxide semiconductor 230 can be reduced to reduce the defect state density. In this specification and the like, a state with low impurity concentration and low defect state density is referred to as high-purity intrinsic or substantially high-purity intrinsic. Furthermore, oxide semiconductors (or metal oxides) with low carrier concentration are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors (or metal oxides).

[0093] To stabilize the electrical characteristics of transistor 200, reducing the impurity concentration in the channel formation region of oxide semiconductor 230 is effective. To further reduce the impurity concentration in oxide semiconductor 230, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in oxide semiconductor 230 refer, for example, to elements other than the main components constituting oxide semiconductor 230. For example, elements with a concentration less than 0.1 atomic% can be considered impurities.

[0094] Furthermore, in oxide semiconductor 230, it is sometimes difficult to clearly observe the boundaries of each region. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region are not limited to varying in stages according to each region, but can also vary gradually in each region. That is to say, the closer to the channel formation region, the lower the concentration of metal elements and impurity elements such as hydrogen and nitrogen can be.

[0095] In transistors using oxide semiconductors, the presence of impurities and oxygen vacancies in the channel region of the oxide semiconductor can easily alter electrical characteristics, sometimes reducing reliability. Furthermore, hydrogen near the oxygen vacancy forms a defect where hydrogen enters the oxygen vacancy (sometimes referred to below as V). O H) may generate electrons that become charge carriers. Therefore, when oxygen vacancies are included in the channel formation region of an oxide semiconductor, the transistor tends to have always-on characteristics (the characteristic that current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of an oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V O H. In other words, preferably, the carrier concentration in the channel formation region of the oxide semiconductor is reduced and is i-typed (intrinsic) or substantially i-typed.

[0096] In contrast, by performing heat treatment with an insulator containing excess oxygen near the oxide semiconductor, oxygen can be supplied to the oxide semiconductor from the insulator, thereby reducing oxygen vacancies and V. O H. Note that supplying excessive oxygen to the source or drain regions may cause a decrease in the on-state current or field-effect mobility of the transistor 200. Furthermore, if the amount of oxygen supplied to the source or drain regions is uneven within the substrate surface, the characteristics of the semiconductor device, including the transistor, will become uneven. Additionally, excessive oxygen supplied from the insulator to the oxide semiconductor can sometimes negatively impact the electrical characteristics and reliability of the transistor. Moreover, there is the concern that oxygen diffuses into the gate, source, and drain electrodes, causing oxidation and a decrease in conductivity.

[0097] Preferably, an insulator with hydrogen-barrier properties is first formed near transistor 200 to reduce the channel formation region of oxide semiconductor 230 and its vicinity.O H.

[0098] At least one of insulators 212, 214, 221, 222, 275, 282, and 283 is preferably used as a hydrogen-barrier insulator. Furthermore, at least one of insulators 212, 214, 221, 222, 275, 282, and 283 is preferably used as an impurity-barrier insulator. Additionally, at least one of insulators 212, 214, 221, 222, 275, 282, and 283 is preferably used as an oxygen-barrier insulator. Note that it is not necessary to provide all of insulators 212, 214, 221, 222, 275, 282, and 283. As long as it provides sufficient barrier properties against hydrogen, impurities, oxygen, etc., it can be formed by appropriately selecting from insulators 212, 214, 221, 222, 275, 282, and 283. For example, it is also possible to form a structure where insulator 216 and conductor 205 are in contact with the top surface of insulator 212 without insulator 214.

[0099] Note that in this specification, etc., "barrier insulator" refers to an insulator that possesses barrier properties. In this specification, "barrier property" means the property that the corresponding substance does not easily diffuse (also referred to as the property that the corresponding substance is not easily permeable, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). Alternatively, it refers to the function of trapping or fixing the corresponding substance within the insulator (also called gettering). Furthermore, hydrogen, referred to as the corresponding substance, includes, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH-. - At least one of the following: substances bonded to hydrogen. Furthermore, unless otherwise specified, impurities referred to as corresponding substances refer to impurities in the channel-forming region or semiconductor layer, such as at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N₂O, NO, NO₂, etc.), copper atoms, etc. Additionally, oxygen referred to as corresponding substances refers to at least one of oxygen atoms, oxygen molecules, etc.

[0100] Silicon nitride or silicon oxynitride is preferred as an insulator that inhibits hydrogen diffusion. Other materials that may be used include, for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, and indium gallium zinc oxide.

[0101] Insulators 212, 221, 275, and 283 are preferably insulators that have the function of suppressing hydrogen diffusion. For example, silicon nitride with higher hydrogen barrier properties can be used for insulators 212, 221, 275, and 283.

[0102] A portion of an insulator that inhibits hydrogen diffusion also has the function of trapping or fixing hydrogen. As an insulator with the function of trapping or fixing hydrogen, metal oxides such as hafnium oxide, aluminum oxide, aluminum and hafnium oxide (hafnium aluminate), hafnium and zirconium oxide (hafnium zirconium oxide), or magnesium oxide are preferred. The insulator with the function of trapping or fixing hydrogen preferably has an amorphous structure. The aforementioned metal oxides with amorphous structures sometimes have the property that oxygen atoms have dangling bonds, which trap or fix hydrogen. In other words, metal oxides with amorphous structures have a high ability to trap or fix hydrogen. By adding silicon to the aforementioned metal oxides, polymorphism can be suppressed, making amorphization easier to achieve. Therefore, metal oxides with added silicon (e.g., hafnium silicate, aluminum silicate, etc.) are preferred.

[0103] Insulators 214, 222, and 282 are preferably insulators that have the function of trapping or fixing hydrogen. For example, aluminum oxide can be used as insulator 214 and insulator 282. For example, hafnium oxide, which is a high-k material, is preferably used as insulator 222, which is used as the second gate insulator.

[0104] In addition, inorganic insulators, which are insulators that have the function of inhibiting hydrogen diffusion and insulators that have the function of capturing or fixing hydrogen, also have oxygen barrier properties.

[0105] like Figure 4A As shown, it is preferable to provide an insulator 212 with the function of suppressing hydrogen diffusion and an insulator 214 with the function of trapping or fixing hydrogen under the transistor 200. By providing the insulator 212 under the transistor 200, hydrogen diffusion from the lower layer of the transistor 200 can be suppressed. Furthermore, by providing the insulator 214 on the insulator 212, hydrogen contained in the insulator 216, etc., can be trapped or fixed by the insulator 214. As a result, the hydrogen concentration in and around the oxide semiconductor 230 can be reduced.

[0106] In addition, such as Figure 4AAs shown, it is preferable to provide an insulator 221 with the function of suppressing hydrogen diffusion and an insulator 222 with the function of trapping or fixing hydrogen under the transistor 200. By providing the insulator 221 under the transistor 200, hydrogen diffusion from the lower layer of the transistor 200 can be suppressed. Furthermore, by providing the insulator 222 on the insulator 221, hydrogen contained in the insulator 224, etc., can be trapped or fixed by the insulator 222. As a result, the hydrogen concentration in and around the oxide semiconductor 230 can be reduced.

[0107] In addition, such as Figure 4A As shown, the insulator 275 is preferably provided in a manner that covers the oxide semiconductor 230, conductor 242a, and conductor 242b. By providing the insulator 275 in this way, the diffusion of hydrogen from the insulator 280 to the oxide semiconductor 230, conductor 242a, and conductor 242b can be suppressed.

[0108] In addition, such as Figure 4A As shown, preferably, an insulator 282 with the function of trapping or fixing hydrogen and an insulator 283 with the function of suppressing hydrogen diffusion are provided on the transistor 200. By providing the insulator 283 on the transistor 200, hydrogen diffusion from the upper layer of the transistor 200 can be suppressed. Furthermore, by providing the insulator 282 below the insulator 283, hydrogen contained in the insulator 280, etc., can be trapped or fixed by the insulator 282. As a result, the hydrogen concentration in and around the oxide semiconductor 230 can be reduced.

[0109] Thus, by employing a structure in which hydrogen barrier insulators surround the top and bottom of transistor 200, hydrogen diffusion into the oxide semiconductor can be reduced, thereby reducing Vc in the channel formation region. O H. This improves the electrical characteristics and reliability of transistor 200.

[0110] Furthermore, it is preferable that the insulator 280 contains oxygen that has been removed by heating. By supplying this oxygen to the oxide semiconductor 230 through the insulator 250 using a heat treatment, oxygen vacancies in the channel formation region can be reduced.

[0111] In addition, such as Figure 4A As shown, the insulator 282 may also have a stacked structure of insulator 282a and insulator 282b on insulator 282a.

[0112] At this time, oxygen can be added to the insulator 280 by sputtering deposition of insulator 282b in an atmosphere containing oxygen gas. Since oxygen is added through insulator 282a after insulator 282b has been deposited, the amount of oxygen added to the insulator 280 can be controlled. When the thickness of insulator 282a is large, the oxygen addition is easily hindered, resulting in a decrease in the amount of oxygen injected into the insulator 280. When the thickness of insulator 282a is small, the oxygen addition is less easily hindered, resulting in an increase in the amount of oxygen injected into the insulator 280. For example, by setting the thickness of insulator 282a to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, an appropriate amount of oxygen can be supplied to the insulator 280.

[0113] Furthermore, to prevent the addition of oxygen to the insulator 280 during the deposition of the insulator 282a, the insulator 282a is preferably deposited using atomic layer deposition (ALD). To reduce the thickness of the insulator 282a as described above, ALD deposition is preferred. ALD methods include thermal ALD, which uses only thermal energy to react the precursors and reactants, and plasma-enhanced ALD, which uses reactants excited by plasma.

[0114] The precursors used in the ALD method sometimes contain carbon and other impurities. Therefore, films deposited using the ALD method sometimes contain more carbon and other impurities compared to films deposited using other deposition methods. Consequently, the carbon concentration in insulator 282a is sometimes higher than that insulator 282b. Furthermore, impurity quantification can be performed using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0115] For example, when both insulator 282a and insulator 282b contain alumina, the carbon concentration of insulator 282a is sometimes higher than that of insulator 282b. In this case, the carbon concentration of insulator 282a in the SIMS analysis is preferably 1 × 10⁻⁶. 18 atoms / cm 3 Above and 1×10 21 atoms / cm 3 The following applies to insulator 282a, which sometimes has a carbon concentration of 1 × 10⁻⁶. 19 atoms / cm 3 Above and 1×10 21atoms / cm 3 The following region. Furthermore, the carbon concentration of insulator 282b in SIMS analysis is preferably above the detection limit and 1 × 10⁻⁶. 20 atoms / cm 3 The following is an example. Insulator 282b sometimes has a carbon concentration of 4.46 × 10⁻⁶. 17 atoms / cm 3 Above and 1×10 19 atoms / cm 3 The following areas.

[0116] As described above, by heating the insulator 280, which contains oxygen released through heating, an appropriate amount of oxygen can be supplied to the oxide semiconductor 230 via the insulator 250. During this heating process, since oxygen-barrier insulators 282 and 283 are formed on the insulator 280, excessive diffusion of oxygen contained in the insulator 280 from the insulator 280 is prevented. Furthermore, since an oxygen-barrier insulator 275 is formed between the insulator 280 and the oxide semiconductor 230, conductors 242a and 242b, excessive diffusion of oxygen contained in the insulator 280 from the insulator 280 is also prevented. Moreover, by performing this heating process with openings formed in a portion of the insulators 280, 282, and 283, a portion of the oxygen contained in the insulator 280 can diffuse outwards, thereby adjusting the amount of oxygen supplied from the insulator 280 to the oxide semiconductor 230.

[0117] Here, the insulator 250 preferably has a structure that allows oxygen to diffuse from the insulator 280 to the oxide semiconductor 230 and suppresses the oxidation of the conductors 242a, 242b and 260.

[0118] like Figure 3B and Figure 3C As shown, insulator 250 is disposed within an opening formed in insulator 280 and insulator 275. Within this opening, insulator 250 is formed in contact with the top surface of insulator 222, the side surface of insulator 224, the side surface and top surface of oxide semiconductor 230, the side surface of conductor 242a, the side surface of conductor 242b, the side surface of insulator 271a, the side surface of insulator 271b, the side surface of insulator 275, and the side surface of insulator 280. Furthermore, as... Figure 4A As shown, when the oxide semiconductor 230 includes oxide semiconductors 230a to 230c, the insulator 250 contacts the side surface of oxide semiconductor 230a, the side surface of oxide semiconductor 230b, and the top and side surfaces of oxide semiconductor 230c. Here, it is preferable to improve... Figure 4AThe oxide semiconductor 230c shown exhibits crystallinity. The oxide semiconductor 230c has a large contact area with the insulator 250, thus improving carrier mobility when the transistor 200 is in the on state.

[0119] Here, as Figure 4A , Figure 9A As shown, the insulator 250 preferably has a stacked structure of an insulator 250a in contact with the oxide semiconductor 230, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b.

[0120] The insulator 250b is preferably made of silicon oxide or silicon oxynitride, which have high dielectric strength. Furthermore, to improve the dielectric strength, the thickness of the insulator 250b can be greater than that of the insulator 250a. By using the aforementioned oxide insulator, oxygen can be diffused into the insulator 250b through a high-temperature heat treatment. Therefore, by performing a heat treatment, oxygen contained in the insulator 280 can be supplied to the oxide semiconductor 230 via the insulator 250b. Note that in this specification, "oxynitride" refers to a material in which the oxygen content is greater than the nitrogen content, while "oxygen oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when described as "silicon oxynitride," it refers to a material in which the oxygen content is greater than the nitrogen content, while when described as "silicon oxynitride," it refers to a material in which the nitrogen content is greater than the oxygen content.

[0121] Furthermore, in order to suppress the oxidation of conductors 242a, 242b, and 260, it is preferable to provide an oxygen barrier insulator near each of conductors 242a, 242b, and 260. For example, it is preferable to provide an oxygen barrier insulator as insulator 250a and insulator 250c.

[0122] Insulator 250a preferably has oxygen-barrier properties. Insulator 250a is preferably at least less permeable to oxygen than insulator 250b. Insulator 250a has regions that contact the sides of conductor 242a and the sides of conductor 242b. When insulator 250a has oxygen-barrier properties, oxidation of the sides of conductors 242a and 242b, resulting in the formation of an oxide film on those sides, can be suppressed. Therefore, a decrease in the on-state current or field-effect mobility of transistor 200 can be suppressed. Furthermore, by employing this structure, the amount of oxygen absorbed by conductors 242a and 242b in insulator 250b can be reduced. Therefore, an appropriate amount of oxygen can be supplied to oxide semiconductor 230 from insulator 250b, thereby reducing oxygen vacancies in the channel formation region of oxide semiconductor 230.

[0123] Furthermore, by providing insulator 250a between insulator 280 and insulator 250b, and between insulator 250b and oxide semiconductor 230, excessive oxygen supply from insulator 280 to oxide semiconductor 230 can be suppressed, and an appropriate amount of oxygen can be supplied to oxide semiconductor 230. Therefore, the oxygen content in and around the channel formation region of oxide semiconductor 230 can be controlled to an appropriate level, thus preventing excessive normally-off operation of transistor 200 and improving reliability. In addition, excessive oxidation of the source and drain regions can be suppressed, which could lead to a decrease in the on-state current or field-effect mobility of transistor 200.

[0124] Therefore, the thickness of the insulator 250a is preferably such that it does not excessively impede the diffusion of oxygen from the insulator 280 to the insulator 250b and from the insulator 250b to the oxide semiconductor 230. For example, the thickness of the insulator 250a is preferably 0.1 nm or more and 5.0 nm or less, more preferably 0.5 nm or more and 5.0 nm or less, further preferably 0.5 nm or more and less than 3.0 nm, and even more preferably 0.5 nm or more and 2.0 nm or less.

[0125] As described above, it is preferable to appropriately diffuse oxygen from insulator 280 to insulator 250b and from insulator 250b to oxide semiconductor 230, while suppressing oxygen diffusion from insulator 250b to conductors 242a and 242b as much as possible. Here, in the semiconductor device according to this embodiment, the contact area between insulator 250a and conductor 242a and the contact area between insulator 250a and conductor 242b are much smaller than the contact area between insulator 250a and oxide semiconductor 230. That is, it can be inferred that the amount of oxygen diffused from insulator 250b through insulator 250a to conductors 242a and 242b is less than the amount of oxygen diffused from insulator 250b through insulator 250a to oxide semiconductor 230. Therefore, by controlling the amount of oxygen contained in the insulator 280 to supply an appropriate amount of oxygen from the insulator 280 to the insulator 250b and the oxide semiconductor 230, the oxidation of the conductors 242a and 242b can be reduced.

[0126] The insulator 250a in contact with the channel formation region in the oxide semiconductor 230 preferably has the function of trapping or fixing hydrogen. This reduces the hydrogen concentration in the channel formation region of the oxide semiconductor 230. Therefore, the Vg in the channel formation region can be reduced. O H causes the channel to form an i-shaped region or essentially an i-shaped region.

[0127] Furthermore, the insulator 250a is preferably made of a high-k material. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. When a high-k material is used as the insulator 250a, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. Additionally, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0128] Therefore, as the insulator 250a, an oxide containing one or both of aluminum and hafnium is preferred, and an oxide having an amorphous structure and containing one or both of aluminum and hafnium is more preferred. Since alumina can be easily deposited into an amorphous film using the ALD method, alumina having an amorphous structure is further preferred. In this embodiment, an alumina film is used as the insulator 250a. Alumina has the function of trapping or fixing hydrogen and has oxygen-blocking properties, so it can be suitably used as the insulator 250a.

[0129] The insulator 250c preferably also has oxygen-barrier properties. The insulator 250c is disposed between the channel formation region of the oxide semiconductor 230 and the conductor 260, and between the insulator 280 and the conductor 260. By employing this structure, the diffusion of oxygen from the channel formation region of the oxide semiconductor 230 to the conductor 260, thus preventing the formation of oxygen vacancies in the channel formation region of the oxide semiconductor 230, can be suppressed. Furthermore, the diffusion of oxygen from the oxide semiconductor 230 and the insulator 280 to the conductor 260, thus preventing oxidation of the conductor 260, can be suppressed. The insulator 250c is preferably at least less permeable to oxygen than the insulator 250b. In addition, the insulator 250c preferably has the function of suppressing hydrogen diffusion. Thus, impurities such as hydrogen contained in the conductor 260 can be prevented from diffusing into the oxide semiconductor 230. For example, a silicon nitride film is preferably used as the insulator 250c.

[0130] In addition, such as Figure 9A As shown, when an oxide semiconductor 230ca is disposed between the oxide semiconductor 230b and the conductor 242a, and an oxide semiconductor 230cb is disposed between the oxide semiconductor 230b and the conductor 242b, with the insulator 250 in contact with the oxide semiconductor 230b, as follows: Figure 9A As shown, insulator 250 preferably has a three-layer stacked structure of insulator 250a, insulator 250b, and insulator 250c, and insulator 250a is preferably made of hafnium oxide. For example, insulator 250a can be a hafnium oxide film with a thickness of 2 nm, insulator 250b can be a silicon oxide film with a thickness of 2 nm, and insulator 250c can be a silicon nitride film with a thickness of 1 nm.

[0131] Thus, by employing a structure using hafnium oxide as the insulator 250a, the hafnium oxide-containing insulator 250a can be disposed near the channel formation region of the transistor 200 in contact with the indium oxide-containing oxide semiconductor 230b. With this structure, the insulator 250a can absorb impurities such as hydrogen and excess oxygen from the oxide semiconductor 230b. The hydrogen and oxygen absorbed by the insulator 250a can diffuse outwards as H2O through heating treatment. This reduces impurities such as hydrogen and excess oxygen in the oxide semiconductor 230b, thereby improving the electrical characteristics and reliability of the transistor 200.

[0132] Note that in Figure 9A The diagram shows a structure in which a layer 227 is disposed between the oxide semiconductor 230b and the insulator 224, but the present invention is not limited thereto. For example, as... Figure 9C As shown, layer 227 may not be provided between oxide semiconductor 230b and insulator 224. In this case, the top surface of insulator 224 can contact oxide semiconductor 230b.

[0133] In addition, such as Figure 4B As shown, a structure in which an insulator 250d is provided on an insulator 250b can also be adopted. In this case, the insulator 250d can be an insulator that can be used as an insulator 250a and has the function of trapping or fixing hydrogen. For example, an oxide containing hafnium is preferably used as the insulator 250d. As an oxide containing hafnium, hafnium oxide, hafnium aluminate, hafnium silicate, hafnium zirconium oxide, hafnium zirconium oxide containing yttrium, etc., can be used. In addition, hafnium zirconium oxide containing lanthanide elements such as lanthanum can also be used as the insulator 250d. Here, by providing an insulator 250d between the insulator 250c and the insulator 250b, hydrogen contained in the insulator 250b, etc., can be trapped and fixed more effectively. An oxide semiconductor 230 channel forming region, an insulator 250a, and an insulator 250d having the function of trapping and fixing hydrogen are provided under the insulator 250c, which has the function of suppressing hydrogen diffusion. In the region where insulator 250c blocks hydrogen diffusion from above, hydrogen contained in the channel formation region of oxide semiconductor 230 can be captured or fixed by insulators 250a and 250d. This reduces the hydrogen concentration in oxide semiconductor 230, thereby suppressing negative drift in the initial characteristics of transistor 200 and achieving normally-off characteristics. Furthermore, it suppresses negative drift degradation during +GBT (Gate Bias-Temperature) stress testing.

[0134] Alternatively, insulators 250a, 250b, and 250d can be provided instead of insulator 250c. In this case, it is preferable to provide an insulator (e.g., silicon nitride) that has the function of suppressing hydrogen diffusion as the insulator 283 on the insulator 250. By adopting this structure, an oxide semiconductor 230 and insulators 250a and 250d that have the function of trapping or fixing hydrogen are formed in the region covered by silicon nitride with high hydrogen barrier properties. Therefore, hydrogen contained in the channel formation region, etc., of the oxide semiconductor 230 can be trapped or fixed by insulators 250a and 250d.

[0135] By adopting the above structure, the channel formation region can be i-type or substantially i-type, and the source and drain regions can be n-type, providing a semiconductor device with excellent electrical characteristics. By adopting the above structure, even when the semiconductor device is miniaturized or highly integrated, it can still possess excellent electrical characteristics. Furthermore, miniaturizing the transistor 200 can improve frequency characteristics. Specifically, the cutoff frequency can be increased.

[0136] Furthermore, the hafnium-containing metal oxide used for the insulator 250d is preferably used as a high-k material. By employing this structure, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulator. Additionally, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0137] Furthermore, the insulator 250d preferably has ferroelectric properties. For example, ferroelectric hafnium zirconium oxide, yttrium-containing hafnium zirconium oxide, etc., can be used as the insulator 250d. Additionally, the insulator 250d may have a structure in which layers of hafnium zirconium oxide are stacked on top of a layer of yttrium-containing hafnium zirconium oxide. Note that when a ferroelectric material is used in the insulator 250d, the insulator 250d does not necessarily need to have the function of trapping or fixing hydrogen. For example, the insulator 250d can use a ferroelectric material as described in Embodiment 3.

[0138] Thus, by using a ferroelectric material as the insulator 250d, the transistor 200 can function as a FeFET (Ferroelectric Field Effect Transistor). The FeFET is used alone as a storage element. Therefore, compared to DRAM (Dynamic Random Access Memory) type storage elements that include transistors and capacitors, the structure of the storage element can be reduced. Therefore, miniaturization and high integration of storage devices including the transistor 200 can be achieved. Furthermore, the productivity of storage devices including the transistor 200 can be improved.

[0139] Insulators 250a to 250d are used as part of the first gate insulator. Insulators 250a to 250d are disposed together with conductor 260 in an opening formed in insulator 280, etc. To achieve miniaturization of transistor 200, the thickness of each of insulators 250a, 250c, and 250d is preferably small. The thickness of each of insulators 250a, 250c, and 250d is preferably 0.1 nm or more and 20 nm or less, more preferably 0.1 nm or more and 10 nm or less, further preferably 0.5 nm or more and 5.0 nm or less, even more preferably 1.0 nm or more and less than 5.0 nm, and even more preferably 1.0 nm or more and 3.0 nm or less. For example, aluminum oxide with a thickness of 1 nm can be used as insulator 250a, silicon oxide with a thickness of 2 nm can be used as insulator 250b, hafnium oxide, hafnium zirconium oxide, or yttrium-containing hafnium zirconium oxide with a thickness of 2 nm can be used as insulator 250d, and silicon nitride with a thickness of 1 nm can be used as insulator 250c. At least a portion of each of insulators 250a, 250c, and 250d may have a region whose thickness falls within the aforementioned range.

[0140] In order to reduce the thickness of insulators 250a to 250d as described above, it is preferable to perform deposition using the ALD method. Furthermore, in order to form insulators 250a to 250d with high coverage within the openings of insulators 280, etc., it is preferable to deposit insulators 250a to 250d using the ALD method.

[0141] Note that while the insulator 250 is described above as having a three-layer structure of insulators 250a to 250c or a four-layer structure of insulators 250a to 250d, the present invention is not limited thereto. The insulator 250 may have a single-layer structure, a two-layer structure, or a stacked structure of five or more layers. Furthermore, the insulator 250 may include at least one of insulators 250a to 250d. For example, the insulator 250 may also have a single-layer structure of insulator 250c. In this case, a single layer of hafnium zirconium oxide may be used to form the insulator 250. By having the insulator 250 consist of one, two, or three layers of insulators 250a to 250d, the manufacturing process of semiconductor devices can be simplified, thereby improving productivity.

[0142] In the case where the insulator 250 has a four-layer or five-layer structure, for example, it can have Figures 10A to 10E The layered structure shown. Here. Figures 10A to 10E It corresponds to Figure 4B An enlarged view of region A shown.

[0143] Figure 10AAn example is shown of an insulator 250 having a stacked structure of insulator 250a on oxide semiconductor 230, insulator 250d on insulator 250a, insulator 250b on insulator 250d, and insulator 250c on insulator 250b. In other words, Figure 10A The insulator 250 shown has Figure 4B The structure shown is formed by interchanged positions of insulators 250b and 250d in insulator 250. For example, insulator 250a can be made of aluminum oxide with a thickness of 1 nm, insulator 250d can be made of hafnium zirconium oxide or yttrium-containing hafnium zirconium oxide with a thickness of 2 nm, insulator 250b can be made of silicon oxide with a thickness of 2 nm, and insulator 250c can be made of silicon nitride with a thickness of 1 nm. Furthermore, insulator 250d can also have a structure formed by stacking a layer of hafnium zirconium oxide on a layer of yttrium-containing hafnium zirconium oxide. However, it is not limited to this; the above-mentioned insulating materials and the thickness of insulators 250a to 250d can be appropriately selected as insulators 250a to 250d. Through, as shown... Figure 10A The insulators 250a to 250d shown are stacked together. The insulators 250a and 250d, which have the function of capturing or fixing hydrogen, are arranged adjacent to each other, so that hydrogen can be captured and fixed more effectively.

[0144] In addition, such as Figure 10B As shown, a structure in which the positions of insulator 250c and insulator 250b are interchanged can also be adopted. In this case, the insulator 250 has a stacked structure of insulator 250a on oxide semiconductor 230, insulator 250d on insulator 250a, insulator 250c on insulator 250d, and insulator 250b on insulator 250c.

[0145] Alternatively, it can be used in Figure 10A The insulator 250c is configured to contact the top and bottom surfaces of the insulator 250b. In this case, such as Figure 10C As shown, the insulator 250 has a stacked structure of insulator 250a on oxide semiconductor 230, insulator 250d on insulator 250a, insulator 250c1 on insulator 250d, insulator 250b on insulator 250c1, and insulator 250c2 on insulator 250b. Here, insulators 250c1 and 250c2 can be any of the insulators described above that can be used in insulator 250c. For example, both insulators 250c1 and 250c2 can be made of silicon nitride with a thickness of 1 nm.

[0146] Figure 10DAn example is shown of an insulator 250 having a stacked structure of insulator 250a on oxide semiconductor 230, insulator 250b on insulator 250a, insulator 250d1 on insulator 250b, insulator 250c on insulator 250d1, and insulator 250d2 on insulator 250c. That is, Figure 10D The insulator 250 shown has in Figure 4B The insulator 250 shown has a structure formed by an insulator that can be used for insulator 250d, which is provided in contact with the top and bottom surfaces of insulator 250c. Here, insulator 250d1 can be an insulator with the function of trapping or fixing hydrogen (e.g., hafnium oxide), and insulator 250d2 can be an insulator with ferroelectric properties (e.g., hafnium zirconium oxide or yttrium-containing hafnium zirconium oxide). Furthermore, insulator 250d2 can also have a structure formed by stacking layers of hafnium zirconium oxide on a layer of yttrium-containing hafnium zirconium oxide. When this structure is adopted and a ferroelectric material is used in insulator 250d2, transistor 200 can function as a FeFET. Moreover, since hydrogen can be trapped or fixed by insulator 250d1, the electrical characteristics and reliability of transistor 200 can be improved.

[0147] Furthermore, in the case where ferroelectric materials such as hafnium zirconium oxide are used as insulators 250d2, such as Figure 10E As shown, the conductor 252 can also be provided in contact with the bottom surface of the insulator 250d2. As the conductor 252, a material that readily polarizes the insulator 250d2 is preferably used, such as titanium nitride. In this case, the portion of the conductor 260 that contacts the insulator 250d2 (e.g., conductor 260a) is also preferably made of titanium nitride. By adopting this structure, the insulator 250d2 can be a ferroelectric material, and the transistor 200 can function as a FeFET.

[0148] Insulators 224, 221 and 222 are used as the second gate insulator.

[0149] As the insulator 224 in contact with the oxide semiconductor 230, an insulating material described in <<Insulator>> can be used. The insulator 224 preferably comprises, for example, silicon oxide or silicon oxynitride. This allows oxygen to be supplied from the insulator 224 to the oxide semiconductor 230, reducing oxygen vacancies. Furthermore, the insulator 224 may also have a stacked structure of two or more layers. In this case, it is not limited to a stacked structure made of the same material; a stacked structure made of different materials may also be used.

[0150] like Figure 1AAs shown, insulator 224 contains impurity 220. When insulator 224 contains silicon oxide or silicon oxynitride, impurity 220 preferably contains nitrogen; for example, nitrogen dioxide can be used as impurity 220. At least a portion of impurity 220 preferably does not bond to insulator 224. For example, NO2 as impurity 220 is located in the inter-lattice of SiO2 contained in insulator 224.

[0151] Furthermore, one of the migration levels of the impurity 220 in the insulator 224 is preferably located above the valence band top and below the conduction band bottom of the oxide semiconductor 230. Here, this migration level is preferably a migration level with a zero charge state and a negative charge state. By providing such an impurity 220 in the insulator 224, electrons injected by the conductor 260, which serves as the gate electrode, can be captured by the impurity 220, thus using the impurity 220 as a negative fixed charge. Therefore, a negative fixed charge can be provided near the top surface of the insulator 224, that is, on the back channel side of the transistor 200.

[0152] When a negative fixed charge is applied to the back channel side of transistor 200, a larger potential needs to be supplied to conductor 260 to turn transistor 200 on. That is, by making the impurity 220 in insulator 224 a negative fixed charge, the threshold voltage of transistor 200 can be shifted in the positive direction. Therefore, a semiconductor device with good electrical characteristics and normally off properties can be provided.

[0153] Impurities 220 in insulator 224 can be evaluated using methods such as ESR measurement or TDS analysis. For example, when silicon oxide or silicon oxynitride is used as insulator 224 and nitrogen dioxide is added as impurity 220, evaluation can be performed using ESR measurement. The spin density of insulator 224 corresponding to the absorption peak with a g value of 1.94 or higher and 2.05 or lower obtained by ESR measurement is 4.8 × 10⁻⁶. -3 spins / nm 3 Above and 1.0×10 -2 spins / nm 3 The preferred value is 7.38 × 10⁻⁶. -3 spins / nm 3 Above and 1.0×10 -2 spins / nm 3 The following applies. When the absorption peak of the ESR obtained from the insulator 224 containing impurity 220 reaches the value described above, the threshold voltage of the transistor 200 can be made to be 0V or higher. Furthermore, the addition process of impurity 220 can be performed efficiently to improve the productivity of semiconductor devices.

[0154] Furthermore, the insulator 224 preferably contains excess oxygen. By performing heat treatment on the insulator 224 while it contains excess oxygen, oxygen can diffuse from the insulator 224 into the oxide semiconductor 230, thereby reducing the oxygen vacancies (V) in the oxide semiconductor 230. O ).

[0155] Note that when YSZ or similar materials are used for layer 227 as shown in Figure 6, a layer 227 with low oxygen permeability is sometimes provided between the insulator 224 and the oxide semiconductor 230. In this case, such as... Figure 8 As shown, oxygen can be supplied from insulator 224 to oxide semiconductor 230 through insulator 250. Here, Figure 8 This is a cross-sectional view of the channel formation region of transistor 200 along the A3-A4 direction. Figure 8 The arrows shown indicate the main diffusion direction of oxygen, with oxygen in insulator 224 diffusing to insulator 250 which is in contact with the side of insulator 224, and oxygen in insulator 250 diffusing from the top and side surfaces of oxide semiconductor 230 to oxide semiconductor 230.

[0156] Here, the insulator 250 is in contact with the channel formation region of the oxide semiconductor 230 and its vicinity. As a result, oxygen supplied from the insulator 250 is concentrated in and around the channel formation region of the oxide semiconductor 230, reducing the amount of oxygen supplied to the source and drain regions of the oxide semiconductor 230. Therefore, excessive oxidation of the source and drain regions of the oxide semiconductor 230 can be prevented, thus reducing the carrier concentration in the source or drain regions and preventing a decrease in the on-state current and field-effect mobility of the transistor 200.

[0157] Furthermore, indium oxide is preferably used in the oxide semiconductor 230 (especially oxide semiconductor 230b). Indium oxide has high oxygen permeability, for example, higher than that of indium gallium zinc oxide. Therefore, when indium oxide is used in the oxide semiconductor 230 (especially oxide semiconductor 230b) and oxygen vacancies in the oxide semiconductor 230 are reduced by oxygen supplied from the insulator 224, excess oxygen can diffuse out of the oxide semiconductor 230. This suppresses the presence of excess oxygen in the oxide semiconductor 230, thus preventing the threshold voltage of the transistor 200 from becoming excessive. Therefore, the electrical characteristics and reliability of the transistor 200 incorporating the oxide semiconductor 230 can be improved.

[0158] Furthermore, oxygen diffusing from the oxide semiconductor 230 is sometimes absorbed by the peripheral structures of the oxide semiconductor 230, such as the insulator 250, conductor 240, or conductor 260. For example, when the insulator 250d uses an oxide containing hafnium, or when the conductors 240a and 240b use metals such as tungsten, the oxygen is absorbed. Thus, by having the peripheral structures of the oxide semiconductor 230 absorb the oxygen diffusing from the oxide semiconductor 230, and preventing the oxygen from being reabsorbed by the oxide semiconductor 230, an excess of oxygen in the oxide semiconductor 230 can be prevented.

[0159] Furthermore, the insulator 224 is preferably processed into an island shape in the same way as the oxide semiconductor 230. Thus, when multiple transistors 200 are provided, each transistor 200 includes an insulator 224 of approximately the same size. Therefore, the amount of oxygen supplied from the insulator 224 to the oxide semiconductor 230 in each transistor 200 is approximately equal. This suppresses non-uniformity in the electrical characteristics of the transistors 200 within the substrate surface.

[0160] Note that insulator 224 does not necessarily have to be machined into an island shape. For example, as Figures 11A to 11D As shown, the insulator 224 can also be partially formed into an open shape instead of being an island. Here, Figures 11A to 11D Corresponding to Figures 3A to 3D Apart from the difference in shape of insulator 224, it is similar to Figures 3A to 3D Similarly.

[0161] exist Figures 11A to 11D In the insulator 224 shown, the thickness of the region that does not overlap with the oxide semiconductor 230 is smaller than the thickness of the region that overlaps with the oxide semiconductor 230. Furthermore, openings are formed in the region that does not overlap with the oxide semiconductor 230 but overlaps with the insulator 250. When multiple transistors are disposed on the same substrate, by forming the insulator 224 in this way, the oxide semiconductor 230 of each transistor is formed on the same insulator 224. This reduces the non-uniformity of oxygen supply from the insulator 224 to each transistor's oxide semiconductor 230. Therefore, it reduces the non-uniformity of the electrical characteristics of each transistor.

[0162] Note that in Figures 11A to 11D In the insulator 224 shown, an opening is formed in the region that does not overlap with the oxide semiconductor 230 but overlaps with the insulator 250; however, this opening may not be provided. For example, as... Figure 12 As shown, the insulator 224 can be formed in a manner that covers the insulator 222. Here, Figure 12 This is a cross-sectional view of the channel formation region of transistor 200 along the A3-A4 direction. Figure 12The arrows indicate the main diffusion direction of oxygen. Oxygen in insulator 224 diffuses to insulator 250, which is in contact with the side surface of insulator 224. Oxygen in insulator 250 diffuses from the top and side surfaces of oxide semiconductor 230 to oxide semiconductor 230. Figure 12 As shown, by forming insulator 224 in a manner that covers insulator 222, the contact area between insulator 224 and insulator 250 is increased, thereby increasing the amount of oxygen diffused.

[0163] Furthermore, the insulator 224 satisfying the above-mentioned spin density is not limited to the vicinity of the transistor 200. Preferably, the insulator 224 has the above-mentioned spin density in the region surrounding the transistor 200, such as the region where a mark is formed or the region where an electrode pad is formed.

[0164] Furthermore, the spin density is not necessarily uniform throughout the insulator 224. For example, sometimes there is a peak in spin density in the upper layer of insulator 224 (also known as near oxide semiconductor 230 or insulator 275), and the spin density decreases as it approaches the lower layer of insulator 224 (also known as near insulator 222). Additionally, for example, sometimes there is a peak in spin density in the lower layer of insulator 224, and the spin density decreases as it approaches the upper layer of insulator. Furthermore, for example, sometimes there is a peak in spin density between the upper and lower layers of insulator 224, and the spin density decreases as it approaches both the upper and lower layers of insulator 224.

[0165] In transistor 200, conductor 205 is arranged to overlap with oxide semiconductor 230 and conductor 260. Conductive materials described in <<Conductor>> can be used as conductor 205. Here, conductor 205 is preferably provided in a manner that embeds it in an opening formed in insulator 216. Furthermore, as... Figure 3A and Figure 3C As shown, the conductor 205 preferably extends in the channel width direction. By employing this structure, the conductor 205 is used as wiring when multiple transistors are arranged.

[0166] like Figure 4A As shown, conductor 205 preferably includes conductor 205a and conductor 205b. Conductor 205a is disposed in contact with the bottom surface and sidewall of the opening. Conductor 205b is disposed in a recess of conductor 205a formed along the opening. Here, the height of the top surface of conductor 205 is the same as or approximately the same as the height of the top surface of insulator 216.

[0167] Here, the conductor 205a preferably comprises a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to include a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0168] By using a conductive material that reduces hydrogen diffusion as conductor 205a, impurities such as hydrogen contained in conductor 205b can be prevented from diffusing to oxide semiconductor 230 via insulator 216, etc. Furthermore, by using a conductive material that inhibits oxygen diffusion as conductor 205a, oxidation of conductor 205b and subsequent decrease in conductivity can be prevented. Examples of conductive materials that inhibit oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Conductor 205a can have a single-layer structure or a multilayer structure of the aforementioned conductive materials. For example, conductor 205a preferably contains titanium nitride.

[0169] Furthermore, the conductor 205b preferably uses a conductive material whose main component is tungsten, copper, or aluminum. For example, the conductor 205b preferably contains tungsten.

[0170] Conductor 205 can be used as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by independently changing the potential applied to conductor 205 without linking it to the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205, the Vth of transistor 200 can be further increased, thereby reducing the off-state current. Thus, compared to not applying a negative potential to conductor 205, applying a negative potential to conductor 205 can reduce the drain current when the potential applied to conductor 260 is 0V.

[0171] Furthermore, as described above, it is preferable to add impurities 220 to the insulator 224 and form a negative fixed charge within the insulator 224. By employing this structure, the threshold voltage of the transistor 200 can be controlled by the conductor 205 and the insulator 224. Therefore, a semiconductor device with normally off characteristics can be provided.

[0172] Furthermore, the resistivity of the conductor 205 is designed taking into account the potential applied to the conductor 205 as described above, and the thickness of the conductor 205 is set according to this resistivity. Additionally, the thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to reduce the thickness of both the conductor 205 and the insulator 216 within the design limits of the conductor 205. By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thus suppressing the diffusion of these impurities into the oxide semiconductor 230.

[0173] Note that in Figure 4A The diagram shows a stacked structure of conductors 205a and 205b, but the invention is not limited to this. Conductor 205 can have a single-layer structure or a stacked structure of three or more layers. For example, conductor 205a can also have a two-layer structure of tantalum nitride and titanium nitride on tantalum nitride, and conductor 205b containing tungsten can be disposed on conductor 205a. By adopting this structure, the diffusion of impurities such as hydrogen and metallic impurities such as copper contained in the lower layer of transistor 200 to conductor 205 can be suppressed.

[0174] Note that when the threshold voltage of transistor 200 can be sufficiently controlled by the negative fixed charge of impurities 220 in insulator 224, such as Figures 13A to 13D As shown, a structure can also be adopted that does not include the conductor 205 used as the second gate electrode. In this case, as... Figures 13A to 13D As shown, a structure can also be adopted without insulators 216, 214, and 212. Here, Figures 13A to 13D Corresponding to Figures 3A to 3D Except for the areas where conductors 205, insulators 216, 214, and 212 are not provided, they are related to... Figures 3A to 3D Similarly, by adopting this structure, the structure of semiconductor devices can be simplified, thereby increasing the productivity of semiconductor devices.

[0175] Furthermore, in the structure described above where the conductor 205 is not provided, such as Figures 14A to 14D As shown, an insulator 224 can be provided in a manner that extends within the substrate surface. Alternatively, an oxide semiconductor 230 structure in which multiple transistors 200 are disposed on the insulator 224 can also be used. In this case, as... Figures 14A to 14D As shown, a structure can also be adopted without insulators 222 and 221. Here, Figures 14A to 14D Corresponding to Figures 13A to 13D , Figures 14A to 14D and Figures 13A to 13D The difference lies in that, in the former, the insulator 224 is provided in a manner that extends within the substrate surface; insulators 222 and 221 are not provided. By adopting this structure, the structure of the semiconductor device can be simplified, thereby improving the productivity of the semiconductor device.

[0176] Here, the flatness of the insulator 224 is preferably high. For example, the average surface roughness Ra of the surface of the insulator 224 is preferably 3 nm or less, more preferably 2 nm or less, and even more preferably 1 nm or less. By forming the oxide semiconductor 230 on such a surface, a highly crystalline oxide semiconductor can be formed. In addition, when using such a flat insulator 224, there are no particular limitations on the crystal structure of the insulator 224. For example, the insulator 224 can have a crystalline structure or an amorphous structure. Furthermore, the insulator 224 can also be used as a substrate for mounting a semiconductor device. Note that the average surface roughness Ra refers to the arithmetic mean roughness defined in JIS B 0601:2001 (ISO 4287:1997) extended to three dimensions to be applicable to curved surfaces. The average surface roughness Ra can be evaluated using an atomic force microscope (AFM).

[0177] Conductive materials described in <<Conductors>> can be used as conductors 242a, 242b, and 260. In particular, conductive materials that are not easily oxidized or that have the function of suppressing oxygen diffusion are preferably used as conductors 242a, 242b, and 260. Examples of such conductive materials include nitrogen-containing conductive materials and oxygen-containing conductive materials. This suppresses the decrease in conductivity of conductors 242a, 242b, and 260. When conductive materials containing metals and nitrogen are used as conductors 242a, 242b, and 260, conductors 242a, 242b, and 260 are conductors that contain at least metals and nitrogen.

[0178] Metal nitrides are preferably used as conductors 242a and 242b. For example, nitrides containing tantalum, titanium, molybdenum, tungsten, tantalum and aluminum, or titanium and aluminum are preferred. For instance, tantalum nitride can be used as conductors 242a and 242b. Furthermore, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel can also be used. These materials are preferred because they are conductive materials that are not easily oxidized or maintain conductivity even after absorbing oxygen.

[0179] Note that sometimes hydrogen contained in the oxide semiconductor 230, etc., diffuses into the conductor 242a or conductor 242b. In particular, when a tantalum-containing nitride is used as conductor 242a and conductor 242b, sometimes hydrogen contained in the oxide semiconductor 230, etc., readily diffuses into conductor 242a or conductor 242b, and sometimes this diffused hydrogen bonds with the nitrogen contained in conductor 242a or conductor 242b. That is, sometimes hydrogen contained in the oxide semiconductor 230, etc., is absorbed by conductor 242a or conductor 242b.

[0180] Furthermore, conductors 242a and 242b can also have a stacked structure. In this case, the aforementioned conductive material can be used as the lower layer of conductors 242a and 242b, while a conductive material with higher conductivity can be used as the upper layer. For example, tantalum nitride can be used as the lower layer, and tungsten can be used as the upper layer. Furthermore, for example, such as... Figure 9B As shown, conductor 242a can have a stacked structure of conductor 242a1 and conductor 242a2 on conductor 242a1, and conductor 242b can have a stacked structure of conductor 242b1 and conductor 242b2 on conductor 242b1. An oxide semiconductor 230ca can be disposed under conductor 242a1, and an oxide semiconductor 230cb can be disposed under conductor 242b1. Conductors 242a1 and 242b1 can be made of conductive materials that are not easily oxidized or conductive materials that have the function of suppressing oxygen diffusion. Furthermore, conductors 242a2 and 242b2 can be made of conductive materials whose conductivity is higher than that of conductors 242a1 and 242b1.

[0181] Insulators 271a and 271b are inorganic insulators used as etch stop layers to protect conductors 242a and 242b during the processing of conductors 242a and 242b. Furthermore, since they are in contact with conductors 242a and 242b, insulators 271a and 271b are preferably made of inorganic insulators that do not easily oxidize conductors 242a and 242b. Therefore, as... Figure 4A As shown, preferably, insulator 271a has a stacked structure of insulator 271a1 and insulator 271a2 on insulator 271a1, and insulator 271b has a stacked structure of insulator 271b1 and insulator 271b2 on insulator 271b1. Here, insulators 271a1 and 271b1 preferably use nitride insulators suitable for insulator 250c to prevent oxidation of conductors 242a and 242b. Furthermore, for use as an etch stop layer, insulators 271a2 and 271b2 preferably use oxide insulators suitable for insulator 250b.

[0182] Here, insulator 271a1 contacts the top surface of conductor 242a and a portion of insulator 275, and insulator 271b1 contacts the top surface of conductor 242b and a portion of insulator 275. Additionally, insulator 271a2 contacts the top surface of insulator 271a1 and the bottom surface of insulator 275, and insulator 271b2 contacts the top surface of insulator 271b1 and the bottom surface of insulator 275. For example, silicon nitride can be used as insulator 271a1 and insulator 271b1, and silicon oxide can be used as insulator 271a2 and insulator 271b2.

[0183] The insulators that will become insulators 271a and 271b are used as masks for conductors that will become conductors 242a and 242b, so as Figure 3D As shown, conductors 242a and 242b do not have curved surfaces between their side and top surfaces. Therefore, the ends where the side and top surfaces of conductors 242a and 242b intersect have sharp edges. When the ends where the side and top surfaces of conductors 242a and 242b intersect have sharp edges, the cross-sectional area of ​​conductors 242a and 242b increases compared to the case where the ends have curved surfaces. Furthermore, by using nitride insulators that are not prone to metal oxidation as insulators 271a1 and 271b1, excessive oxidation of conductors 242a and 242b can be prevented. As a result, the resistance of conductors 242a and 242b decreases, thus increasing the transistor's on-state current.

[0184] like Figure 3B and Figure 3C As shown, the conductor 260 is disposed in the openings formed in the insulators 280 and 275. The conductor 260 is disposed in the openings such that it covers the top surface of the insulator 222, the side surface of the insulator 224, and the side and top surfaces of the oxide semiconductor 230, separated by the insulator 250. Furthermore, the top surface of the conductor 260 is disposed at the same or substantially the same height as the upper end of the insulator 250 and the top surface of the insulator 280.

[0185] In the opening provided with conductor 260 and insulator 250, the sidewall of the opening can be perpendicular or substantially perpendicular to the top surface of insulator 222, or it can have a conical shape. By having a conical sidewall, the coverage of insulator 250 and the like provided in the opening of insulator 280 can be improved, thereby reducing defects such as voids.

[0186] Conductor 260 is used as the first gate electrode of transistor 200. Here, as... Figure 3A and Figure 3CAs shown, the conductor 260 preferably extends in the channel width direction. By employing this structure, the conductor 260 is used as wiring when multiple transistors are arranged.

[0187] When the above structure is adopted, such as Figure 3C As shown, when viewed in cross-section along the channel width direction of transistor 200, a curved surface may also be present between the side surface and the top surface of oxide semiconductor 230. That is, the ends of the side surface and the ends of the top surface may also be curved (hereinafter also referred to as circular).

[0188] The radius of curvature of the aforementioned curved surface is preferably greater than 0 nm and less than the thickness of the oxide semiconductor 230 in the region overlapping with the conductors 242a and 242b, or less than half the length of the region without the aforementioned curved surface. Specifically, the radius of curvature of the aforementioned curved surface is greater than 0 nm and less than 20 nm, preferably more than 1 nm and less than 15 nm, and more preferably more than 2 nm and less than 10 nm. By adopting the above shape, the coverage of the insulator 250 and the conductor 260 onto the oxide semiconductor 230 can be improved.

[0189] In this specification, the transistor structure in which at least the electric field of the first gate electrode forms a region surrounding the channel is referred to as a surrounded channel (S-channel) structure. Furthermore, the S-channel structure disclosed in this specification differs from Fin-type and planar structures. On the other hand, the S-channel structure disclosed in this specification can be considered a type of Fin-type structure. Additionally, in this specification, a Fin-type structure refers to a structure in which the gate electrode is arranged with at least two or more surfaces surrounding the channel (specifically, two, three, or four surfaces, etc.). By employing Fin-type and S-channel structures, tolerance to short-channel effects can be improved; in other words, transistors less prone to short-channel effects can be realized.

[0190] By employing the aforementioned S-channel structure as transistor 200, a region can be electrically formed around the channel. Since the S-channel structure is a structure that electrically forms a region around the channel, it can also be said that this structure is substantially the same as a GAA (Gate All Around) structure or a LGAA (Lateral Gate All Around) structure. By giving transistor 200 an S-channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the oxide semiconductor 230 and the gate insulator can be considered as the entire bulk of the oxide semiconductor 230. Therefore, the current density flowing through the transistor can be increased, and thus an increase in the transistor's on-state current or field-effect mobility can be expected.

[0191] This embodiment employs an island-shaped structure for the insulator 224. Therefore, as... Figure 3C As shown, at least a portion of the bottom surface of the conductor 260 can be disposed below the bottom surface of the oxide semiconductor 230. Therefore, the conductor 260 can be disposed opposite to the top and side surfaces of the oxide semiconductor 230, allowing the electric field of the conductor 260 to act on the top and side surfaces of the oxide semiconductor 230. Thus, by employing an island-shaped structure for the insulator 224, the transistor 200 can have an S-channel structure.

[0192] Note that, as Figure 3C The transistor 200 shown illustrates an S-channel structure, but the semiconductor device of one embodiment of the present invention is not limited thereto. For example, as a transistor structure that can be used in one embodiment of the present invention, one or more selected from planar structures, Fin structures, and GAA structures may also be employed.

[0193] like Figure 4A As shown, the conductor 260 preferably has a two-layer structure. Here, the conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, it is preferable that the conductor 260a is disposed in a manner that surrounds the bottom and side surfaces of the conductor 260b. In this case, as the conductor 260a, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting oxygen diffusion.

[0194] The conductor 260a preferably uses a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Furthermore, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0195] Furthermore, when the conductor 260a has the function of suppressing oxygen diffusion, it can prevent the oxygen contained in the insulator 280, etc., from oxidizing the conductor 260b and causing a decrease in conductivity. As a conductive material with the function of suppressing oxygen diffusion, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferred, for example.

[0196] Furthermore, the conductor 260b is preferably a conductor with high conductivity. For example, the conductor 260b can be a conductive material with tungsten, copper, or aluminum as the main component. In addition, the conductor 260b can have a laminated structure, for example, it can have a laminated structure of titanium or titanium nitride with the aforementioned conductive material.

[0197] Furthermore, in transistor 200, conductor 260 is formed in a self-aligned manner by embedding it into an opening formed in insulator 280, etc. By forming conductor 260 in this way, conductor 260 can be configured to overlap with the region between conductor 242a and conductor 242b without alignment.

[0198] The dielectric constants of insulators 216, 280, and 285 are preferably lower than those of insulator 222. By using materials with low dielectric constants for the interlayer films, parasitic capacitances generated between wirings can be reduced.

[0199] For example, insulators 216, 280, and 285 preferably comprise one or more of silicon oxide, silicon oxynitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, and porous silicon oxide.

[0200] In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability. They are also preferred because materials such as silicon oxide, silicon oxynitride, and porous silicon oxide readily form regions containing oxygen released during heating.

[0201] In addition, the top surfaces of insulators 216 and 280 can also be flattened.

[0202] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. For example, silicon oxides such as silicon oxynitride are preferably used as the insulator 280.

[0203] Conductors 240a and 240b can be made of conductive materials described in <<Conductors>>. Conductors 240a and 240b are preferably made of conductive materials with tungsten, copper, or aluminum as their main components. Furthermore, conductors 240a and 240b may also have a laminated structure.

[0204] For example, such as Figure 4AAs shown, conductors 240a and 240b may also have a two-layer stacked structure. Conductor 240a includes conductor 240a1 formed along the opening and conductor 240a2 formed inside conductor 240a1. Furthermore, conductor 240b includes conductor 240b1 formed along the opening and conductor 240b2 formed inside conductor 240b1.

[0205] Similar to conductor 205a, conductive materials that suppress the permeation of impurities such as water and hydrogen are preferably used as conductors 240a1 and 240b1. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide are preferred. Alternatively, a single layer or a stack of conductive materials that suppress the permeation of impurities such as water and hydrogen can be used. By providing conductors 240a1 and 240b1, impurities such as water and hydrogen can be prevented from entering the oxide semiconductor 230 through conductors 240a2 and 240b2. Furthermore, the conductive materials described above that can be used for conductors 240a and 240b can be used for conductors 240a and 240b2.

[0206] In addition, such as Figure 3B As shown, the top surfaces of conductors 240a and 240b can be formed in a manner that is flush with or substantially aligned with the top surface of insulator 285. Furthermore, as... Figure 4A As shown, the lower part of conductor 240a is sometimes formed in a manner that it is embedded in conductor 242a. Similarly, the lower part of conductor 240b is sometimes formed in a manner that it is embedded in conductor 242b.

[0207] As insulators 241a and 241b, barrier insulators suitable for insulators 275 and the like can be used. For example, silicon nitride can be used as insulators 241a and 241b. Insulators 241a and 241b are arranged in contact with insulators 285, 283, 282, 275, 271a, and 271b. This prevents impurities such as water and hydrogen contained in insulators 280 from being mixed into the oxide semiconductor 230 via conductors 240a and 240b. In particular, silicon nitride is preferred because it has high hydrogen barrier properties. Furthermore, it prevents oxygen contained in insulator 280 from being absorbed by conductors 240a and 240b.

[0208] Furthermore, insulators 241a and 241b may also have a laminated structure. In this case, an oxygen-barrier insulator and a hydrogen-barrier insulator are preferably used in combination as the first insulator that contacts the sidewall of the opening of the insulator 280, etc., and the second insulator inside it.

[0209] Note that in Figure 3AThe diagram shows a structure in which the top-view widths of conductors 240a and 240b are smaller than the top-view width of the channel formation region of the oxide semiconductor 230, but the present invention is not limited thereto. For example, as... Figures 15A to 15D As shown, a structure can also be adopted in which the widths of conductors 240a and 240b, when viewed from above, are greater than the width of the channel formation region of the oxide semiconductor 230. Note that... Figures 15A to 15D Corresponding to Figures 3A to 3D Aside from the differences in the top surface shape of insulator 224, oxide semiconductor 230, conductor 242a, conductor 242b, insulator 271a, insulator 271b, conductor 240a, and conductor 240b, they are similar to... Figures 3A to 3D Similarly.

[0210] like Figure 15A As shown, when viewed from above, the width L4 of the source region (drain region) of the oxide semiconductor 230 in the A5-A6 direction is preferably greater than the width L3 in the A3-A4 direction near the channel formation region of the oxide semiconductor 230. Furthermore, the width L3 can also be described as the width in the A3-A4 direction of the region where the oxide semiconductor 230 overlaps with the conductor 260 when viewed from above. Furthermore, the width L4 can also be described as the width in the A5-A6 direction near the region where the oxide semiconductor 230 overlaps with the conductor 240a (conductor 240b) when viewed from above. By adopting this structure, the space for forming an opening that embeds the wider conductors 240a and 240b can be increased. This improves the productivity of the semiconductor device. Furthermore, the contact area between the conductors 240a (conductor 240b) and 242a (conductor 242b) can be increased to reduce contact resistance. Furthermore, the contact area between conductor 242a (conductor 242b) and oxide semiconductor 230 can be increased to reduce contact resistance. This, in turn, can increase the on-state current of transistor 200 and improve the electrical characteristics of the semiconductor device.

[0211] Note that, as Figure 15A As shown, the insulator 224, conductor 242a, conductor 242b, insulator 271a and insulator 271b are preferably formed in a manner that overlaps the top surface shape of the oxide semiconductor 230.

[0212] <Example of Variation 1> exist Figure 3B In the example, in the opening provided in the insulator 280, the insulator 250 contacts the side of the insulator 280; however, the present invention is not limited to this structure. For example, in this opening, an insulator may also be provided between the insulator 250 and the insulator 280.

[0213] Reference Figures 16A to 17CThis section explains variations of the semiconductor device described in "Structural Examples of Semiconductor Devices". Figures 16A to 16D These are plan and cross-sectional views of a semiconductor device including transistor 200, respectively corresponding to... Figures 3A to 3D The plan view and cross-sectional view are shown. Additionally, Figures 17A to 17C This is a magnified cross-sectional view of the channel length of transistor 200, corresponding to... Figure 4B The enlarged cross-section shown.

[0214] Figures 16A to 16D The transistor 200 shown is Figures 3A to 3D The transistor 200 shown is a modified example. Specifically, Figures 16A to 16D The transistor 200 shown includes an insulator 255 between insulators 280 and 250, mainly in this respect... Figures 3A to 3D The transistor 200 shown is different. The following mainly describes the parts that differ from the description in the above <Example of Semiconductor Device Structure>, while repeating parts are described above, and sometimes omitted.

[0215] Furthermore, in Figure 16, both conductors 242a and 242b have a two-layer structure. Conductor 242a has a stacked structure of conductor 242a1 and conductor 242a2 on conductor 242a1. Conductor 242b has a stacked structure of conductor 242b1 and conductor 242b2 on conductor 242b1. Conductors 242a1 and 242b1 correspond to the lower layer of conductors 242a and 242b, and conductors 242a2 and 242b2 correspond to the upper layer of conductors 242a and 242b.

[0216] like Figure 16B and Figure 16C As shown, the insulator 255 is disposed inside the opening formed in the insulator 280, etc., and is in contact with the side surface of the insulator 280, the side surface of the conductor 242a2, the side surface of the conductor 242b2, the top surface of the conductor 242a1, the top surface of the conductor 242b1, and the top surface of the insulator 222 in the opening. In other words, the insulator 255 can be described as being formed in a sidewall shape in contact with the sidewall of the opening formed in the insulator 280, etc. Here, the sidewall of the opening corresponds, for example, to the side surface of the insulator 280, etc. in the opening.

[0217] In addition, insulator 250 is in side contact with insulator 255.

[0218] The insulator 255 preferably has oxygen-barrier properties. When the insulator 255 has oxygen-barrier properties, the oxidation of the sides of the conductors 242a and 242b, resulting in the formation of an oxide film on those sides, can be suppressed. Therefore, the decrease in the on-state current or the decrease in the field-effect mobility of the transistor 200 can be suppressed. As the insulator 255, a barrier insulator suitable for insulators 275, etc., can be used. For example, silicon nitride can be used as the insulator 255.

[0219] The opening in the insulator 280 overlaps with the area between conductors 242a2 and 242b2. In a top view, the side of the insulator 280 in the opening is aligned or substantially aligned with the side of conductors 242a2 and 242b2. Furthermore, portions of conductors 242a1 and 242b1 are formed to protrude inwards from the opening. In other words, in conductor 242a1, the portion on its top surface where the insulator 255 is formed (hereinafter, sometimes referred to as the protrusion of conductor 242a1) protrudes towards conductor 260 from conductor 242a2. Similarly, in conductor 242b1, the portion on its top surface where the insulator 255 is formed (hereinafter, sometimes referred to as the protrusion of conductor 242b1) protrudes towards conductor 260 from conductor 242b2.

[0220] Here, a portion of the top surface of conductor 242a1 contacts conductor 242a2, and a portion of the top surface of conductor 242b1 contacts conductor 242b2. Therefore, the insulator 255 contacts the remaining portion of the top surface of conductor 242a1, the remaining portion of the top surface of conductor 242b1, the side surface of conductor 242a2, and the side surface of conductor 242b2 on the inner side of the opening. Additionally, the insulator 250 contacts the top surface of oxide semiconductor 230, the side surface of conductor 242a1, the side surface of conductor 242b1, and the side surface of insulator 255.

[0221] After dividing the conductive layer into conductors 242a2 and 242b2, an insulator 255 is formed using anisotropic etching. The insulator 255 is formed in a sidewall shape, contacting the sidewall of the opening provided in the insulator 280. The insulator 255 is formed in contact with the sidewalls of both conductors 242a2 and 242b2, and functions to protect both conductors 242a2 and 242b2.

[0222] Furthermore, the insulator 255 is used as a mask when dividing the conductive layer into conductors 242a1 and conductors 242b1. Therefore, as Figure 17A As shown, when the transistor 200 is viewed in cross section, the side end of the insulator 255 is preferably aligned with the side end of the conductor 242a1 and the side end of the conductor 242b1.

[0223] After separating the conductors 242a1 and 242b1 and before depositing the insulator 250, heat treatment is preferably performed in an oxygen-containing atmosphere. At this time, since the insulator 255 is formed in contact with the sides of the conductors 242a2 and 242b2, excessive oxidation of the conductors 242a2 and 242b2 can be prevented. When microwave treatment is performed after separating the conductors 242a1 and 242b1, the formation of an oxide film on the sides of the conductors 242a1 and 242b2 can also be suppressed.

[0224] The insulators 255 and 250 and the conductor 260 are arranged to reflect the shape of the opening in the insulator 280. Therefore, the insulator 255 is arranged to cover the sidewall of the opening, the insulator 250 is arranged to cover the bottom of the opening and the insulator 255, and the conductor 260 is arranged to be embedded in the recess of the insulator 250.

[0225] Note that, similar to the above <Structure Example of a Semiconductor Device>, the insulator 250 can also have a stacked structure. For example, as shown... Figure 17A As shown, insulator 250 can also have a three-layer structure consisting of insulator 250a, insulator 250b, and insulator 250c. Furthermore, for example, as... Figure 17B As shown, insulator 250 can also have a four-layer structure consisting of insulator 250a, insulator 250b, insulator 250c, and insulator 250d. Furthermore, it is not limited to... Figure 17B The structure shown allows for the selection of one or more insulators 250a, 250b, 250c, and 250d to form insulator 250. For example, an insulator with... Figures 10A to 10D The insulator 250 of the structure shown.

[0226] Furthermore, the thickness of the insulator 255 is preferably 0.5 nm or more and 20 nm or less, more preferably 0.5 nm or more and 10 nm or less, and even more preferably 0.5 nm or more and 3 nm or less. When the insulator 255 has the above-mentioned thickness, excessive oxidation of the conductors 242a2 and 242b2 can be suppressed. Note that the insulator 255 only needs to have a region with the above-mentioned thickness in at least a portion of it. In addition, since the insulator 255 is provided in contact with the sidewall of the opening formed in the insulator 280, etc., it is preferable to use a deposition method such as ALD with good coverage. When the thickness of the insulator 255 is too large, the deposition time of the insulator 255 using the ALD method is long, resulting in a decrease in productivity. Therefore, it is preferable to set the thickness of the insulator 255 approximately within the above-mentioned range. Furthermore, the thickness of the insulator 255 is preferably a thickness that does not excessively block the diffusion of excess oxygen from the insulator 280 to the insulator 250b and from the insulator 250b to the oxide semiconductor 230.

[0227] like Figure 17A As shown, when viewed in cross-section along the channel length of transistor 200, the distance L1 between conductors 242a1 and 242b1 is smaller than the distance L2 between conductors 242a2 and 242b2. Here, distance L1 refers to the shortest distance between conductors 242a1 and 242b1, and distance L2 refers to the shortest distance between conductors 242a2 and 242b2. By adopting this structure, the distance between the source and drain can be further reduced, and the channel length can be reduced accordingly. Therefore, the frequency characteristics of transistor 200 can be improved. Thus, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0228] exist Figure 17A In the structure shown, the difference between distance L2 and distance L1 is equal to twice the thickness of insulator 255. In other words, distance L2 is equal to distance L1 plus twice the thickness of insulator 255. Here, the thickness of insulator 255 refers to the width of at least a portion of insulator 255 in the A1-A2 direction.

[0229] Alternatively, the insulator 255 may have a stacked structure with two or more layers. In this case, it is sufficient that at least one layer is an inorganic insulator that is not easily oxidized, as described above. For example, the first insulator of the insulator 255 may be an inorganic insulator that is not easily oxidized, and the second insulator on the first insulator of the insulator 255 may be an insulator suitable for the insulator 250b (e.g., silicon oxide). The dielectric constant of the second insulator of the insulator 255 is preferably lower than that of the first insulator of the insulator 255. In this way, by adopting a two-layer structure to increase the thickness of the insulator 255, the distance between the conductor 260 and the conductor 242a or the conductor 242b can be increased, thereby reducing parasitic capacitance.

[0230] Note that in Figure 17B In the examples, oxide semiconductor 230 has a three-layer stacked structure of oxide semiconductor 230a to oxide semiconductor 230c, but the present invention is not limited thereto. For example, as... Figure 18A As shown, the oxide semiconductor 230 can also have a two-layer structure of oxide semiconductor 230a and oxide semiconductor 230b. In this case, the top surface of oxide semiconductor 230b is in contact with the bottom surface of insulator 250, the bottom surface of conductor 242a1, and the bottom surface of conductor 242b1. Alternatively, the oxide semiconductor 230 can also have a single-layer structure of oxide semiconductor 230b.

[0231] In addition, such as Figure 18B As shown, an oxide semiconductor 230c can be separated in the region overlapping with the insulator 250 to form oxide semiconductors 230ca and 230cb. Preferably, the top surface of oxide semiconductor 230ca contacts the bottom surface of conductor 242a1, and in top view, oxide semiconductor 230ca and conductor 242a1 are aligned or substantially aligned. Similarly, preferably, the top surface of oxide semiconductor 230cb contacts the bottom surface of conductor 242b1, and in top view, oxide semiconductor 230cb and conductor 242b1 are aligned or substantially aligned. Furthermore, a portion of the top surface of oxide semiconductor 230b contacts the insulator 250. By adopting this structure, the channel of transistor 200 can be formed only in oxide semiconductor 230b and not in oxide semiconductor 230c. For example, when aluminum oxide is used as the insulator 250a and indium oxide is used as the oxide semiconductor 230b, the aluminum oxide and indium oxide are in contact at the interface between the insulator 250a and the oxide semiconductor 230b, thereby suppressing the formation of impurity traps at that interface. This improves the on-state current, carrier mobility, and frequency characteristics of the transistor 200.

[0232] In addition, Figures 16A to 16DIn the transistor 200 shown, a layer 227 may be disposed between the oxide semiconductor 230 and the insulator 224, as described above.

[0233] For example, such as Figure 19A As shown, a layer 227 can also be formed between the oxide semiconductor 230 and the insulator 224 in a two-layer structure of oxide semiconductor 230b and oxide semiconductor 230c. That is, in Figure 17B In the structure shown, layer 227 can also be used instead of oxide semiconductor 230a. Here, the top surface of layer 227 is in contact with the bottom surface of oxide semiconductor 230b. For example, YSZ can be used for layer 227, indium oxide for oxide semiconductor 230b, and In-Ga-Zn oxide for oxide semiconductor 230c.

[0234] In addition, such as Figure 19B As shown, the oxide semiconductor 230 can have a single-layer structure of oxide semiconductor 230b, with a layer 227 formed between the oxide semiconductor 230b and the insulator 224. That is, in Figure 18A In the structure shown, layer 227 can be used instead of oxide semiconductor 230a. Here, the top surface of layer 227 is in contact with the bottom surface of oxide semiconductor 230b. For example, YSZ can be used for layer 227 and indium oxide can be used for oxide semiconductor 230b.

[0235] In addition, such as Figure 19C As shown, in Figure 19A In the structure shown, oxide semiconductor 230c can be separated in the region overlapping with insulator 250 to form oxide semiconductor 230ca and oxide semiconductor 230cb. That is, in Figure 18B In the structure shown, layer 227 can be used instead of oxide semiconductor 230a.

[0236] In addition, Figure 19C In the structure shown, insulator 250 has a four-layer stacked structure of insulator 250a, insulator 250b, insulator 250c, and insulator 250d, but the present invention is not limited thereto. For example, as Figure 20A As shown, the insulator 250 can have a three-layer stacked structure of insulator 250a, insulator 250b, and insulator 250c. Here, hafnium oxide is preferably used for insulator 250a.

[0237] Thus, by employing a structure using hafnium oxide as the insulator 250a, and... Figure 9ASimilarly, the structure shown can also have an insulator 250a containing hafnium oxide disposed in contact with the oxide semiconductor 230b containing indium oxide near the channel formation region of the transistor 200. Therefore, impurities such as hydrogen and excess oxygen in the oxide semiconductor 230b can be reduced, thereby improving the electrical characteristics and reliability of the transistor 200.

[0238] In addition, such as Figure 20B As shown, sometimes a conductor 242a2 is provided on the oxide semiconductor 230ca, and a conductor 242b2 is provided on the oxide semiconductor 230cb, but conductors 242a1 and 242b1 are not provided. In this case, the bottom surface of the insulator 255 is in contact with the top surface of the oxide semiconductor 230ca and the top surface of the oxide semiconductor 230cb.

[0239] Note that in Figure 20A The diagram shows a structure in which a layer 227 is disposed between the oxide semiconductor 230b and the insulator 224, but the present invention is not limited thereto. For example, as... Figure 20C As shown, layer 227 may not be provided between oxide semiconductor 230b and insulator 224. In this case, the top surface of insulator 224 can contact oxide semiconductor 230b.

[0240] The above illustrates an example of forming the insulator 255 into a sidewall shape through anisotropic etching, but the invention is not limited thereto. Figure 17C As shown, the insulator 255 may also have a shape with an opening inside the opening formed in the insulator 280, etc. In this case, the opening of the insulator 255 can be formed by removing part of the insulating film that will become the insulator 255 using photolithography. The opening of the insulator 255 preferably overlaps with the area between the conductors 242a1 and 242b1.

[0241] like Figure 17C As shown in the cross-section, a protrusion is formed at the lower part of the insulator 255. The protrusion of the insulator 255 overlaps with the protrusions of the conductor 242a1 and the conductor 242b1.

[0242] Furthermore, such as Figure 18C As shown, oxide semiconductor 230c can be separated in the region overlapping with insulator 250 to form oxide semiconductor 230ca and oxide semiconductor 230cb. This can improve the on-state current, carrier mobility, and frequency characteristics of transistor 200.

[0243] In addition, Figure 17C In the transistor 200 shown, a layer 227 may be disposed between the oxide semiconductor 230 and the insulator 224, as described above.

[0244] For example, such as Figure 21A As shown, a layer 227 can also be formed between the oxide semiconductor 230 and the insulator 224 in a two-layer structure of oxide semiconductor 230b and oxide semiconductor 230c. That is, in Figure 17C In the structure shown, layer 227 can also be used instead of oxide semiconductor 230a. Here, the top surface of layer 227 is in contact with the bottom surface of oxide semiconductor 230b. For example, YSZ can be used for layer 227, indium oxide for oxide semiconductor 230b, and In-Ga-Zn oxide for oxide semiconductor 230c.

[0245] In addition, such as Figure 21B As shown, the oxide semiconductor 230 can have a single-layer structure of oxide semiconductor 230b, with a layer 227 formed between the oxide semiconductor 230b and the insulator 224. Here, the top surface of layer 227 is in contact with the bottom surface of oxide semiconductor 230b. For example, YSZ can be used for layer 227 and indium oxide can be used for oxide semiconductor 230b.

[0246] In addition, such as Figure 21C As shown, in Figure 21A In the structure shown, oxide semiconductor 230c can be separated in the region overlapping with insulator 250 to form oxide semiconductor 230ca and oxide semiconductor 230cb. That is, in Figure 18C In the structure shown, layer 227 can be used instead of oxide semiconductor 230a.

[0247] In addition, Figure 21C In the structure shown, insulator 250 has a four-layer stacked structure of insulator 250a, insulator 250b, insulator 250c, and insulator 250d, but the present invention is not limited thereto. For example, as Figure 22A As shown, the insulator 250 can have a three-layer stacked structure of insulator 250a, insulator 250b, and insulator 250c. Here, hafnium oxide is preferably used for insulator 250a.

[0248] Thus, by employing a structure using hafnium oxide as the insulator 250a, and... Figure 9A Similarly, the structure shown can also have an insulator 250a containing hafnium oxide disposed in contact with the oxide semiconductor 230b containing indium oxide near the channel formation region of the transistor 200. Therefore, impurities such as hydrogen and excess oxygen in the oxide semiconductor 230b can be reduced, thereby improving the electrical characteristics and reliability of the transistor 200.

[0249] In addition, such as Figure 22BAs shown, sometimes a conductor 242a2 is provided on the oxide semiconductor 230ca, and a conductor 242b2 is provided on the oxide semiconductor 230cb, but conductors 242a1 and 242b1 are not provided. In this case, the bottom surface of the insulator 255 is in contact with the top surface of the oxide semiconductor 230ca and the top surface of the oxide semiconductor 230cb.

[0250] Note that in Figure 22A The diagram shows a structure in which a layer 227 is disposed between the oxide semiconductor 230b and the insulator 224, but the present invention is not limited thereto. For example, as... Figure 22C As shown, layer 227 may not be provided between oxide semiconductor 230b and insulator 224. In this case, the top surface of insulator 224 can contact oxide semiconductor 230b.

[0251] <Example 2 of the variation> In Modified Example 1, a structure is described in which the insulator 255 is provided in such a way that it contacts the sidewall of the opening formed in the insulator 280, etc. However, the present invention is not limited to this structure. For example, the insulator 255 may not be provided in the opening.

[0252] Reference Figures 23A to 2 4. A modified example of the semiconductor device described in Modified Example 1. Figures 23A to 23D These are plan and cross-sectional views of a semiconductor device including transistor 200, respectively corresponding to... Figures 16A to 16D The plan view and cross-sectional view are shown. Additionally, Figure 24 is an enlarged cross-sectional view of the transistor 200 along its channel length, corresponding to... Figure 17C The enlarged cross-section shown.

[0253] Figures 23A to 23D The transistor 200 shown is Figures 16A to 16D The transistor 200 shown is a modified example. Specifically, Figures 23A to 23D The transistor 200 shown does not include the insulator 255, mainly in this respect compared to Figures 16A to 16D The transistor 200 shown is different. Hereinafter, the parts that differ from the descriptions in the above <Example of Semiconductor Device Structure> and <Modified Example 1> will be explained in detail. For parts that are repeated with these examples, the descriptions will sometimes be omitted with reference to those sections.

[0254] As shown in Figure 24, without the insulator 255, a portion of the insulator 250 is arranged to overlap with the protrusions of the conductors 242a1 and 242b1. Furthermore, a portion of the conductor 260 is sometimes arranged to overlap with the protrusions of the conductors 242a1 and 242b1. Here, the protrusions of the conductors 242a1 and 242b1 are in contact with the insulator 250. Additionally, the side surface of the insulator 250 is in contact with the side surfaces of the insulator 280, 275, 271a, 271b, 242a2, and 242b2.

[0255] The insulator 250 is configured to reflect the shape of the opening in the insulator 280. Therefore, the insulator 250 is formed to reflect the shape of the conductors 242a1 and 242b1 protruding into the opening.

[0256] As shown in Figure 24, when viewed in cross-section along the channel length of transistor 200, the distance L1 between conductors 242a1 and 242b1 is smaller than the distance L2 between conductors 242a2 and 242b2. By employing this structure, the distance between the source and drain can be further reduced, and the channel length can be correspondingly reduced. Therefore, the frequency characteristics of transistor 200 can be improved. Thus, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0257] Furthermore, by adopting the structure shown in Figure 24, the width of the upper part of the conductor 260 can be greater than the distance L1. This reduces the wiring resistance of the conductor 260, thereby reducing the power consumption of the semiconductor device.

[0258] Note that, similar to the above <Structure Example of a Semiconductor Device>, the insulator 250 can also have a stacked structure. For example, as shown... Figure 17A As shown, insulator 250 can also have a three-layer structure consisting of insulator 250a, insulator 250b, and insulator 250c. Furthermore, for example, as... Figure 17B As shown, insulator 250 can also have a four-layer structure consisting of insulator 250a, insulator 250b, insulator 250c, and insulator 250d. Furthermore, it is not limited to... Figure 17B The structure shown allows for the selection of one or more insulators 250a, 250b, 250c, and 250d to form insulator 250. For example, an insulator with... Figures 10A to 10D The insulator 250 of the structure shown.

[0259] Furthermore, such as Figure 24BAs shown, oxide semiconductor 230c can be separated in the region overlapping with insulator 250 to form oxide semiconductor 230ca and oxide semiconductor 230cb. This can improve the on-state current, carrier mobility, and frequency characteristics of transistor 200.

[0260] In addition, Figure 24A and Figure 24B In this embodiment, the oxide semiconductor 230 has a three-layer stacked structure of oxide semiconductors 230a to 230c, but the present invention is not limited thereto. Similar to the above-described <Structure Example of a Semiconductor Device>, the oxide semiconductor 230 may have a single-layer, two-layer, or four-layer or higher stacked structure. Furthermore, a layer 227 may be disposed between the oxide semiconductor 230 and the insulator 224.

[0261] Materials Constituting Semiconductor Devices The following describes the materials that can be used to construct semiconductor devices. Note that the layers constituting a semiconductor device can have either a single-layer structure or a multilayer structure.

[0262] <<Substrate>> Substrates for forming transistors can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconium oxide substrates (yttrium-stabilized zirconium oxide substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates can also be used, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Additionally, examples of substrates include substrates containing metal nitrides, substrates containing metal oxides, insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Alternatively, the aforementioned substrates with one or more elements can also be used. Examples of components disposed on a substrate include capacitors, resistors, switching elements, light-emitting elements, and storage elements.

[0263] <<Insulators>> The insulators 212, 214, 216, 221, 222, 224, 250, 275, 280, 282, 283, 285, 241a, 241b, 271a, 271b, and 255 shown in this embodiment can be any of the insulators shown below. Examples of insulators that possess insulating properties include oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides.

[0264] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulator. By using a high-k material as the insulator used as the gate insulator, low voltage can be achieved during transistor operation while maintaining the physical thickness. On the other hand, by using a material with a low relative permittivity as the insulator used as the interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulator.

[0265] Examples of insulators with relatively high permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0266] Examples of insulators with relatively low permittivity include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, and resins.

[0267] Furthermore, by surrounding a transistor using a metal oxide with an insulator that suppresses the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Examples of insulators that suppress the permeation of impurities such as hydrogen and oxygen include single layers or stacks of one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, examples of insulators that suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride.

[0268] Furthermore, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that has been removed by heating. For example, when a structure is used in which silicon oxide or silicon oxynitride having a region containing oxygen that has been removed by heating is contacted with the oxide semiconductor 230, the oxygen vacancies contained in the oxide semiconductor 230 can be filled.

[0269] <<Conductors>> As conductors 205, 242a, 242b, 260, 240a, and 240b shown in this embodiment, any conductor from the following descriptions can be used appropriately. Preferably, the conductor is a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the aforementioned metal elements, or an alloy combining the aforementioned metal elements. Examples of conductors include tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred materials as they are conductive materials that are not easily oxidized or maintain conductivity even after absorbing oxygen. Additionally, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicides can also be used.

[0270] When using a conductor with a multilayer structure, for example, a multilayer structure combining a material containing the aforementioned metal element and a conductive material containing oxygen, a multilayer structure combining a material containing the aforementioned metal element and a conductive material containing nitrogen, or a multilayer structure combining a material containing the aforementioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may also be used.

[0271] Furthermore, when using oxides in the channel formation region of a transistor, a stacked structure combining a material containing the aforementioned metallic elements and an oxygen-containing conductive material is preferably used as the conductor serving as the gate electrode. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from this conductive material can be easily supplied to the channel formation region.

[0272] In particular, as the conductor used as the gate electrode, a conductive material containing the metal element and oxygen contained in the metal oxide forming the channel is preferably used. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. For example, nitrogen-containing conductive materials such as titanium nitride and tantalum nitride can be used. Furthermore, one or more of the following can be used: indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon. Additionally, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Alternatively, hydrogen mixed in from external insulators or the like can sometimes be trapped.

[0273] <Examples of Semiconductor Device Manufacturing Methods> Reference Figures 25A to 33D An example of a method for manufacturing a semiconductor device according to one aspect of the present invention will be described. Here, manufacturing... Figures 3A to 3D The case of the semiconductor device shown will be used as an example for explanation.

[0274] Figures 25 to 29 and Figures 31 to 33, A, are plan views. Furthermore, Figures 25 to 29 and Figures 31 to 33, B, are cross-sectional views along the dashed lines A1-A2 in Figure A, corresponding to cross-sectional views along the channel length direction of transistor 200. Furthermore, Figures 25 to 29 and Figures 31 to 33, C, are cross-sectional views along the dashed lines A3-A4 in Figure A, corresponding to cross-sectional views along the channel width direction of transistor 200. Furthermore, Figures 25 to 29 and Figures 31 to 33, D, are cross-sectional views along the dashed lines A5-A6 in Figure A, corresponding to cross-sectional views along the channel width direction of transistor 200. Note that in the plan views of Figures 25 to 29 and Figures 31 to 33, A, some constituent elements are omitted for clarity. Additionally, Figures 30A1 to 30D1 It corresponds to Figure 3B A partial cross-sectional view, which corresponds to a cross-sectional view along the channel length of transistor 200. Additionally, Figures 30A2 to 30D2 yes Figure 3C A partial cross-sectional view, which corresponds to a cross-sectional view of the channel width direction of transistor 200.

[0275] The insulating materials used to form insulators, the conductive materials used to form conductors, or the semiconductor materials used to form semiconductors can be deposited using methods such as sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and ALD.

[0276] First, prepare a substrate (not shown), deposit an insulator 212 on the substrate, and then deposit an insulator 214 on the insulator 212 (see reference). Figures 25A to 25D Insulators 212 and 214 can use the aforementioned insulating materials. For example, insulators 212 and 214 can be deposited using sputtering, CVD, MBE, PLD, or ALD methods. Since sputtering does not require the use of hydrogen-containing molecules as the deposition gas, the hydrogen concentration in insulators 212 and 214 can be reduced, which is preferred.

[0277] In this embodiment, silicon nitride is deposited as insulator 212 using sputtering, and aluminum oxide is deposited as insulator 214 using sputtering. Thus, by using silicon nitride, which has the function of suppressing hydrogen diffusion, as insulator 212, hydrogen diffusion from the lower layer of transistor 200 can be suppressed. Furthermore, by using aluminum oxide, which has the function of trapping or fixing hydrogen, as insulator 214, hydrogen contained in insulator 216 and the like can be trapped or fixed by insulator 214. This reduces the hydrogen concentration in and around oxide semiconductor 230.

[0278] Furthermore, it is preferable to perform a heat treatment before depositing the insulator 212 to reduce the adsorption of water and hydrogen onto the substrate (including circuit elements and interlayer films formed on the substrate). In this embodiment, the heat treatment temperature is set to 400°C.

[0279] Next, insulator 216 is deposited on insulator 214. Insulator 216 is preferably deposited using a sputtering method. By using a sputtering method, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in insulator 216 can be reduced. Note that the deposition method for insulator 216 is not limited to sputtering; for example, CVD, MBE, PLD, ALD, etc., can also be appropriately used. In this embodiment, silicon oxide is deposited using a sputtering method as insulator 216.

[0280] Insulators 212, 214, and 216 are preferably deposited continuously without exposure to the atmosphere. For example, a multi-chamber deposition apparatus can be used. This allows for the deposition of insulators 212, 214, and 216 with reduced hydrogen content in the film, and also reduces hydrogen ingress into the film between deposition steps.

[0281] Next, an opening leading to insulator 214 is formed in insulator 216. The opening is formed in the region where conductor 205 will be formed. Wet etching can be used when forming the opening, but dry etching is preferred for microfabrication. As insulator 214, it is preferable to select an insulator that will serve as an etch stop film when etching insulator 216. For example, when silicon oxide or silicon oxynitride is used as insulator 216, silicon nitride, aluminum oxide, or hafnium oxide are preferably used as insulator 214.

[0282] After the opening is formed, a conductive film that will become conductor 205 is deposited until insulator 216 is exposed. CMP treatment is then performed to remove a portion of the conductive film that will become conductor 205. Thus, conductor 205 embedded in insulator 216 can be formed (see reference). Figures 25A to 25D ).

[0283] Here, the conductive film that will become the conductor 205 can be made of the aforementioned conductive material and deposited using methods such as sputtering, CVD, MBE, PLD, and ALD. For example, tantalum nitride films, titanium nitride films, and tungsten films can be deposited in layers using CVD. Thus, as... Figure 4A As shown, the conductor 205 may have a stacked structure of a conductor 205a with titanium nitride stacked on tantalum nitride and a conductor 205b with tungsten.

[0284] Next, insulator 221 is deposited on insulator 216 and conductor 205 (see reference). Figures 25A to 25D ).

[0285] The insulator 221 can be any insulator that blocks oxygen, hydrogen, and water as described above. The insulator 221 can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon nitride is deposited using the PEALD method as the insulator 221.

[0286] Next, insulator 222 is deposited on insulator 221 (see reference). Figures 25A to 25D ).

[0287] The insulator 222 is preferably deposited with an oxide containing one or both of aluminum and hafnium. For example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) are preferably used as the insulator. Alternatively, hafnium zirconium oxide is preferred. The insulator containing one or both of aluminum and hafnium oxide is a barrier to oxygen, hydrogen, and water. When the insulator 222 is a barrier to hydrogen and water, the diffusion of hydrogen and water contained in the surrounding structure of the transistor through the insulator 222 to the inside of the transistor can be suppressed, thereby suppressing the generation of oxygen vacancies in the oxide semiconductor 230.

[0288] The insulator 222 can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD. In this embodiment, hafnium oxide is deposited as the insulator 222 using thermal ALD.

[0289] In this embodiment, silicon nitride is deposited as insulator 221 using the PEALD method, and hafnium oxide is deposited as insulator 222 using the thermal ALD method. Thus, by using silicon nitride, which has the function of suppressing hydrogen diffusion, as insulator 221, hydrogen diffusion from the lower layer of transistor 200 can be suppressed. Furthermore, by using hafnium oxide, which has the function of trapping or fixing hydrogen, as insulator 222, hydrogen in insulator 224 and the like can be trapped or fixed by insulator 222. This reduces the hydrogen concentration in and around oxide semiconductor 230.

[0290] Next, an insulating film 224f is deposited on the insulator 222 (refer to...). Figures 25A to 25D As the insulating film 224f, an insulator corresponding to the aforementioned insulator 224 can be used. The insulating film 224f is formed in such a manner that it is parallel to or substantially parallel to the surface of the substrate.

[0291] The insulating film 224f can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon oxide is deposited as the insulating film 224f using sputtering. By using a sputtering method that does not require the use of hydrogen-containing molecules as a deposition gas, the hydrogen concentration in the insulating film 224f can be reduced. Since the insulating film 224f comes into contact with the oxide semiconductor 230 in a subsequent process, it is preferable to reduce the hydrogen concentration as described above.

[0292] Next, the insulating film 224f is subjected to plasma treatment and impurity 220 is added to the insulating film 224f (refer to...). Figures 25A to 25D The plasma treatment described above is performed using a nitrogen-containing gas. Nitrogen gas or nitrous oxide (N₂O) gas can be used as the nitrogen-containing gas. In addition to nitrogen-containing gases, oxygen gas can also be used. Note that... Figures 25B to 25DThe dashed arrows in the diagram represent plasma-enhanced gases. NO2 can be added as an impurity 220 by treating the insulating film 224f containing silicon oxide or silicon oxynitride with plasma-enhanced N2 or N2O.

[0293] In the above plasma processing, sputtering equipment, PECVD equipment, PEALD equipment, dry etching equipment, CVD equipment using a high-density plasma source, or dry etching equipment using a high-density plasma source can be used.

[0294] Additionally, substrate heating can be performed during the aforementioned plasma treatment. Furthermore, heating treatment can be performed before or after the aforementioned plasma treatment. The temperature for substrate heating or heating treatment is set, for example, to 200°C or higher and 450°C or lower, preferably 300°C or higher and 400°C or lower. By performing substrate heating or heating treatment, excess oxygen contained in the insulating film 224f can be reduced. This suppresses the presence of excessive oxygen in the insulating film 224f and adjusts the oxygen content in the insulating film 224f to an appropriate level. Therefore, it can prevent excessive oxygen from being supplied to the oxide semiconductor 230 and the threshold voltage of the OS transistor from becoming too high. This improves the electrical characteristics of the transistor 200. Furthermore, by setting the temperature for substrate heating or heating treatment to 450°C or lower, and more specifically to 400°C or lower, the detachment of impurities 220 due to substrate heating or heating treatment can be suppressed. Note that the conditions for heating treatment can be referred to in the following description.

[0295] Next, an oxide semiconductor film 230f (refer to) is deposited on the insulating film 224f. Figures 26A to 26D The oxide semiconductor film 230f can be deposited using the aforementioned oxide semiconductor materials via sputtering, CVD, MBE, PLD, or ALD methods. Furthermore, the oxide semiconductor film 230f can be deposited using the same method as the oxide semiconductor deposition described in Embodiment 2. Preferably, indium oxide (e.g., indium oxide, indium gallium oxide, indium zinc oxide, indium gallium zinc oxide, or indium gallium tin zinc oxide, etc.) is used for the oxide semiconductor film 230f. When the oxide semiconductor film 230f contains indium oxide, a semiconductor device with high field-effect mobility can be provided. Additionally, a semiconductor device with at least one good electrical characteristic, frequency characteristic, and reliability can be provided. When the oxide semiconductor film 230f is formed as described above, the oxide semiconductor film 230f is formed parallel to or substantially parallel to the substrate surface.

[0296] For example, such as Figure 4AAs shown, when the oxide semiconductor 230 has a three-layer structure of oxide semiconductor 230a to oxide semiconductor 230c, films that will become oxide semiconductor 230a and oxide semiconductor 230b can be deposited using the ALD method, and a film that will become oxide semiconductor 230c can be deposited using the sputtering method. Specifically, the film that will become oxide semiconductor 230a can be deposited with a composition having In:Ga:Zn = 1:3:2 [atomic ratio] or close to it. Alternatively, gallium oxide can be used for the film that will become oxide semiconductor 230a. In addition, indium oxide can be used to deposit the film that will become oxide semiconductor 230b. Alternatively, an oxide target with a composition having In:Ga:Zn = 1:1:1.2 [atomic ratio] or close to it can be used to deposit the film that will become oxide semiconductor 230c.

[0297] For example, in the structure described above, oxide semiconductor 230a can also be deposited using sputtering. Specifically, an oxide target with an In:Ga:Zn ratio of 1:3:2 or similar can be used to deposit the film that will become oxide semiconductor 230a.

[0298] In addition, such as Figures 6A to 6D As shown, when layer 227 is provided between insulator 224 and oxide semiconductor 230, a film becoming layer 227 is deposited before depositing oxide semiconductor film 230f. The method described above can be appropriately selected depending on the material used to deposit layer 227. For example, YSZ can be deposited as layer 227 using sputtering. Furthermore, for example, In-Ga-Zn oxide film can be deposited as layer 227 using sputtering. In this case, an oxide target with an In:Ga:Zn ratio of 1:3:2 or similar can be used. Furthermore, in manufacturing... Figure 7A In the case of the transistor 200 with the structure shown, a film that is an oxide semiconductor 230b and a film that is an oxide semiconductor 230c are deposited on the aforementioned layer 227. At this time, the films that are oxide semiconductor 230b and oxide semiconductor 230c can be deposited under the aforementioned conditions.

[0299] Next, a heat treatment is preferably performed. The heat treatment of the oxide semiconductor film 230f can be performed using the same method as the heat treatment described in Embodiment 2. For example, as a heat treatment, it can be performed at a temperature of 450°C for 1 hour with a nitrogen gas to oxygen gas flow ratio of 4:1.

[0300] By performing a heat treatment, the crystallinity of the oxide semiconductor 230 can be improved. This improves the on-state current, subthreshold swing value, field-effect mobility, and frequency characteristics of the transistor 200, resulting in a semiconductor device with excellent electrical characteristics. Furthermore, a highly reliable semiconductor device can be provided.

[0301] The heat treatment is carried out in a nitrogen atmosphere or an inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment can also be carried out under reduced pressure. Alternatively, the heat treatment can be carried out in a nitrogen atmosphere or an inert gas atmosphere, and then, to replenish the removed oxygen, it can be carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.

[0302] Furthermore, the gas used in the above-described heat treatment is preferably of high purity. For example, the water content in the gas used in the above-described heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By using a high-purity gas for heat treatment, the absorption of moisture and the like by the oxide semiconductor film 230f can be prevented as much as possible. In addition, the high-purity gas can also be used for heat treatment before and after this process.

[0303] Such heat treatment containing oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide semiconductor film 230f. By reducing impurities in the film, the crystallinity of the oxide semiconductor film 230f is improved, enabling a denser structure with higher density. Therefore, the crystalline region in the oxide semiconductor film 230f can be increased, and the in-plane inhomogeneity of the crystalline region can be reduced. Consequently, the in-plane inhomogeneity of the electrical characteristics of the transistor can be reduced.

[0304] Furthermore, by performing a heat treatment, oxygen can be supplied to the oxide semiconductor film 230f, thereby reducing oxygen vacancies in the oxide semiconductor film 230f. This improves the reliability of the transistor 200.

[0305] Furthermore, through heat treatment, hydrogen in insulator 216, insulating film 224f, and oxide semiconductor film 230f moves to insulator 222 and is absorbed by insulator 222. In other words, hydrogen in insulator 216, insulating film 224f, and oxide semiconductor film 230f diffuses to insulator 222. Therefore, although the hydrogen concentration in insulator 222 increases, the hydrogen concentration in insulator 216, insulating film 224f, and oxide semiconductor film 230f all decrease. Here, when insulator 221 is provided in contact with the bottom surface of insulator 222, impurities such as moisture or hydrogen can be prevented from entering from below insulator 221 due to the heat treatment.

[0306] In particular, the insulating film 224f (the rear insulator 224) is used as the second gate insulator of the transistor 200, and the oxide semiconductor film 230f (the rear oxide semiconductor 230) is used as the channel formation region of the transistor 200. The transistor 200 formed using the insulating film 224f and the oxide semiconductor film 230f with reduced hydrogen concentration has high reliability and is therefore preferred.

[0307] Next, a conductive film 242f is deposited on the oxide semiconductor film 230f (refer to...). Figures 26A to 26D The conductive film 242f can be any conductive material corresponding to the aforementioned conductive materials 242a and 242b. After depositing the oxide semiconductor film 230f, the conductive film 242f is deposited on and in contact with the oxide semiconductor film 230f without etching or other processes, thereby protecting the top surface of the oxide semiconductor film 230f. As a result, since the diffusion of impurities into the oxide semiconductor 230 constituting the transistor can be reduced, the electrical characteristics and reliability of the semiconductor device can be improved.

[0308] The conductive film 242f can be deposited using sputtering, CVD, MBE, PLD or ALD methods.

[0309] In this embodiment, tantalum nitride is deposited as a conductive film 242f using a sputtering method. Alternatively, a heat treatment can be performed before depositing the conductive film 242f. This heat treatment can be performed under reduced pressure, wherein the conductive film 242f is continuously deposited without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adsorbed on the surface of the oxide semiconductor 230 can be removed, and the moisture and hydrogen concentrations in the oxide semiconductor 230 can be reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower.

[0310] Here, when indium oxide is used as a film forming oxide semiconductor 230b and a conductive film 242f is formed in contact with the film forming oxide semiconductor 230b, due to the high oxygen permeability of indium oxide, oxygen in oxide semiconductor film 230f is sometimes drawn out by conductive film 242f, forming an oxide film at the interface between conductive film 242f and oxide semiconductor film 230f. Because of this oxide film, the contact resistance between conductors 242a and 242b of transistor 200 and oxide semiconductor 230 may increase. Furthermore, because this oxide film is not uniformly formed on the substrate surface, shape defects may occur when the conductive film 242f, oxide semiconductor film 230f, and insulating film 224f are processed into island shapes in subsequent processes.

[0311] In contrast, it is preferable to form an oxide semiconductor 230c film on the oxide semiconductor 230b film. Alternatively, an In-Ga-Zn oxide film with an In:Ga:Zn ratio of 1:1:1 or similar can be deposited to form the oxide semiconductor 230c film. By employing this structure, an oxide semiconductor 230c film with low oxygen permeability can be formed on the oxide semiconductor 230b film, thus reducing the extraction of oxygen from the oxide semiconductor film 230f by the conductive film 242f. This results in a transistor with excellent electrical characteristics and improves the productivity of semiconductor devices.

[0312] Next, an insulating film 271f is deposited on the conductive film 242f (refer to...). Figures 26A to 26D The insulating film 271f can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD. Preferably, the insulating film 271f is an insulating film that inhibits oxygen permeation. For example, the insulating film 271f can be a stack of a silicon nitride film and a silicon oxide film deposited on the silicon nitride film using sputtering. With this structure, the insulator 271a (insulator 271b) can have a stacked structure of an insulator 271a1 (insulator 271b1) made of silicon nitride and an insulator 271a2 (insulator 271b2) made of silicon oxide.

[0313] Here, when a multilayer film is used as the insulating film 271f, deposition is performed continuously without exposure to the atmospheric environment. By performing deposition without exposure to the atmosphere, the area near the interface of the multilayer film of the insulating film 271f can be kept clean. Furthermore, it is more preferable to continuously deposit the conductive film 242f onto the insulating film 271f without exposure to the atmosphere.

[0314] Alternatively, a heat treatment can be performed before depositing the insulating film 271f. This heat treatment can also be performed under reduced pressure, wherein the insulating film 271f is continuously deposited without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adsorbed on the surface of the conductive film 242f can be removed, and the moisture and hydrogen concentrations in the conductive film 242f can be reduced. The heat treatment temperature is preferably 100°C or higher and 400°C or lower.

[0315] Next, using photolithography, the insulating film 224f, oxide semiconductor film 230f, conductive film 242f, and insulating film 271f are processed into islands to form insulator 224, oxide semiconductor 230, conductor 242A, and insulator 271A (see reference). Figures 27A to 27D ).

[0316] The above processing can be performed using either dry etching or wet etching. Dry etching is suitable for microfabrication. Furthermore, the processing of the insulating film 224f, the oxide semiconductor film 230f, the conductive film 242f, and the insulating film 271f can also be performed under different conditions.

[0317] Here, it is preferable to process the insulator 224, oxide semiconductor 230, conductor 242A, and insulator 271A into an island shape in one step. In this case, the side end of conductor 242A is preferably aligned or substantially aligned with the side end of oxide semiconductor 230. Furthermore, the side end of insulator 224 is preferably aligned or substantially aligned with the side end of oxide semiconductor 230. Additionally, the side end of insulator 271A is preferably aligned or substantially aligned with the side end of conductor 242A. By adopting the above structure, the number of steps in the semiconductor device according to one aspect of the present invention can be reduced. Thus, a method for manufacturing a semiconductor device with high productivity can be provided.

[0318] Furthermore, insulator 224, oxide semiconductor 230, conductor 242A, and insulator 271A are formed such that at least a portion of them overlap with conductor 205. Additionally, in regions where they do not overlap with insulator 224, oxide semiconductor 230, conductor 242A, and insulator 271A, insulator 222 is exposed. However, this is not a limitation; a structure in which insulator 224 remains on insulator 222 in regions not overlapping with oxide semiconductor 230 may also be used. In this case, as... Figures 11A to 11D Like transistor 200, insulator 224 is partially formed in an open shape rather than in an island shape.

[0319] like Figures 27B to 27DAs shown, the side surfaces of insulator 224, oxide semiconductor 230, conductor 242A, and insulator 271A can also be conical. The cone angle of the side surfaces of insulator 224, oxide semiconductor 230, conductor 242A, and insulator 271A can, for example, be 60° or more and less than 90°. Thus, when the side surfaces are conical, the coverage of insulator 275 and the like is improved in subsequent processes, reducing defects such as voids.

[0320] Alternatively, the insulator 224, oxide semiconductor 230, conductor 242A, and insulator 271A can be arranged with their sides perpendicular to or substantially perpendicular to the top surface of insulator 222. This structure allows for smaller area and higher density when multiple transistors are arranged.

[0321] Note that in lithography, the photoresist is first exposed through a mask. Then, a developer is used to remove or leave the exposed areas, forming a photoresist mask. Next, an etching process is performed through this photoresist mask to process conductors, semiconductors, or insulators into the desired shape. For example, a KrF stimulated excimer laser, an ArF stimulated excimer laser, or EUV (Extreme Ultraviolet) light can be used to expose the photoresist mask to form it. Alternatively, immersion lithography can be used, where exposure is performed with a liquid (e.g., water) filling the space between the substrate and the projection lens. Furthermore, electron beams or ion beams can be used instead of the aforementioned light. In cases where electron beams or ion beams are used, a photomask may sometimes be omitted.

[0322] Unwanted resist masks after processing can be removed by dry etching (such as ashing with oxygen plasma, sometimes referred to as oxygen plasma treatment), wet etching, wet etching after dry etching, or dry etching after wet etching.

[0323] Furthermore, a hard mask made of an insulator or conductor can also be used under a photoresist mask. When using a hard mask, an insulating film or conductive film that serves as the hard mask material can be formed on the insulating film 271f, and a photoresist mask can be formed on it. Then, the hard mask material can be etched to form a hard mask of the desired shape. For example, tungsten can also be used as the hard mask material. The etching of the insulating film 271f, etc., can be performed either after removing the photoresist mask or without removing the photoresist mask. In the latter case, the photoresist mask may sometimes disappear during etching. The hard mask can also be removed by etching after etching the oxide semiconductor film 230f, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessary to remove the hard mask.

[0324] Alternatively, SOC (Spin On Carbon) films and SOG (Spin On Glass) films can be deposited between the workpiece and the resist mask. Using SOC and SOG films as masks improves the adhesion between the workpiece and the resist mask, thereby enhancing the durability of the mask pattern. For example, lithography can be performed by sequentially depositing an SOC film, an SOG film, and a resist mask on the workpiece.

[0325] As the etching gas for dry etching, halogen-containing etching gases can be used; specifically, etching gases containing one or more of fluorine, chlorine, and bromine can be used. Examples of etching gases include one or more mixtures of C4F6, C5F6, C4F8, CF4, SF6, CHF3, CH2F2, Cl2, BCl3, SiCl4, and BBr3. Additionally, oxygen, carbon dioxide, nitrogen, helium, argon, hydrogen, or hydrocarbon gases can be appropriately added to the above etching gases. Furthermore, depending on the material being dry-etched, gases containing hydrocarbons or hydrogen but not halogens can also be used as etching gases. Hydrocarbons used as etching gases include methane (CH4), ethane (C2H6), propane (C3H8), and butane (C4H4H6). 10 One or more of the following: ethylene (C2H4), propylene (C3H6), acetylene (C2H2), and propyne (C3H4). Etching conditions can be appropriately set according to the object being etched.

[0326] Alternatively, a capacitively coupled plasma (CCP) etching apparatus, including parallel planar electrodes, can be used as a dry etching apparatus. This type of CCP etching apparatus can also employ a structure where a high-frequency voltage is applied to one of the parallel planar electrodes. Alternatively, a structure where a high-frequency voltage of the same frequency is applied to each of the parallel planar electrodes can be used. Furthermore, a structure where multiple different high-frequency voltages are applied to the parallel planar electrodes can also be used. This type of CCP etching apparatus is called a dual-frequency capacitively coupled plasma (DF-CCP) etching apparatus. In a DF-CCP etching apparatus, high-frequency voltages of different frequencies can be applied to each of the parallel planar electrodes. Alternatively, a structure where multiple different high-frequency voltages are applied to one of the parallel planar electrodes can also be used. Alternatively, a dry etching apparatus with a high-density plasma source can be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus with a high-density plasma source. The etching apparatus can be appropriately configured according to the object being etched. Note that in the aforementioned dry etching apparatus, reactive ion etching can be performed by generating a self-biased potential by applying a high-frequency voltage to an electrode on one side of the substrate. In reactive ion etching, etching is performed by accelerating ions in the plasma to collide with the workpiece, thus enabling highly anisotropic etching processes.

[0327] Furthermore, in the aforementioned etching process, the insulator 271A can also be used as an etch stop layer to protect the conductor 242A. For example, when a metal hard mask is formed on the insulator 271A in the aforementioned etching process, it is sometimes difficult to obtain an etch selectivity ratio with the conductor 242A when the hard mask is removed. However, by forming the insulator 271A on the conductor 242A, the insulator 271A can be used as an etch stop layer to protect the conductor 242A during the etching process after removing the hard mask. This prevents the formation of a curved surface between the side and top surfaces of the conductor 242A, thus... Figure 3D The conductors 242a and 242b, which are formed laterally, have sharp edges at the ends where their sides and top surfaces intersect. When the ends where the sides and top surfaces of conductor 242A intersect have sharp edges, the cross-sectional area of ​​conductor 242A increases compared to the case where the ends have curved surfaces. Furthermore, by using a nitride insulator, which is less prone to metal oxidation, as the insulator 271A, excessive oxidation of conductor 242A can be prevented. As a result, the resistance of conductors 242a and 242b decreases, thus increasing the transistor's on-state current.

[0328] Furthermore, by processing insulator 224 into an island shape, insulator 275 can be disposed in a manner that contacts the side surface of insulator 224 and the top surface of insulator 222 in the later described process. That is, insulator 275 can separate insulator 224 from insulator 280. With this structure, excessive impurities such as oxygen and hydrogen can be prevented from mixing into oxide semiconductor 230 from insulator 280 through insulator 224.

[0329] Next, insulator 275 is deposited in a manner that covers insulator 224, oxide semiconductor 230, conductor 242A and insulator 271A, and insulator 280 is deposited on insulator 275 (see reference). Figures 28A to 28D The above-mentioned insulating materials can be used as insulators 275 and 280.

[0330] Here, insulator 275 is preferably in contact with the top surface of insulator 222.

[0331] As the insulator 280, it is preferable to form an insulating film that will become the insulator 280 by CMP treatment of the insulating film, thereby forming an insulator with a flat top surface. Alternatively, silicon nitride can be deposited on the insulator 280, for example, by sputtering, and CMP treatment can be performed on the silicon nitride until it reaches the insulator 280.

[0332] Insulators 275 and 280 can each be deposited, for example, by sputtering, CVD, MBE, PLD or ALD.

[0333] The insulator 275 is preferably an insulator that inhibits oxygen permeation. For example, silicon nitride is preferably deposited using the PEALD method as the insulator 275. Alternatively, aluminum oxide can be deposited using sputtering and silicon nitride can be deposited on it using the PEALD method. When the insulator 275 has the above-described structure, its ability to inhibit the diffusion of impurities such as water and hydrogen, as well as oxygen, can be improved.

[0334] Thus, the oxide semiconductor 230 and the conductor 242A can be covered by an insulator 275 that has the function of suppressing oxygen diffusion. As a result, oxygen can be prevented from diffusing directly from the insulator 280 and the like into the oxide semiconductor 230 and the conductor 242A in subsequent processes.

[0335] Furthermore, silicon oxide is preferably deposited using sputtering as the insulator 280. By depositing the insulating film that will become the insulator 280 using sputtering under an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 280 can be reduced. In addition, a heat treatment can be performed before depositing the insulating film. The heat treatment can also be performed under reduced pressure, wherein the insulating film is continuously deposited without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 can be removed. The heat treatment can be performed under the conditions described above.

[0336] Next, photolithography is used to process conductor 242A, insulator 271A, insulator 275, and insulator 280 to form openings reaching oxide semiconductor 230 and insulator 222 (see reference). Figures 29A to 29D Here, conductor 242A is divided to form conductor 242a and conductor 242b, and insulator 271A is divided to form insulator 271a and insulator 271b. The openings formed in insulator 280 and insulator 275 overlap with oxide semiconductor 230 and conductor 205.

[0337] Lithography can appropriately utilize the methods described above. For finely fabricating the openings in the insulator 280, lithography using short-wavelength light such as EUV light or electron beams is preferred. For example, using... Figures 30A1 to 30D2 The method shown involves forming an opening in the insulator 280 to form conductors 242a and 242b.

[0338] First, a coating film 277 is deposited on the insulator 280, and a coating film 278 is also deposited (see reference). Figure 30A1 and Figure 30A2 Coating films 277 and 278 can also improve the adhesion between the resist mask and the insulator 280 (described later). The deposition of coating films 277 and 278 can be achieved, for example, by spin coating. Non-photosensitive organic resins can be used as coating films 277 and 278.

[0339] Here, the coating film 278 is used as a mask in the etching process of the coating film 277. Therefore, under the etching conditions of the coating film 277, the etching rate of the coating film 278 is preferably lower than the etching rate of the coating film 277. For example, the coating film 277 can be a carbon-containing film, and the coating film 278 can be a silicon- and carbon-containing film. In this embodiment, an SOC film is deposited as the coating film 277, and an SOG film is deposited as the coating film 278.

[0340] Note that coating films 277 and 278 contain organic solvents such as alcohols during coating, but the organic matter may be reduced or removed in subsequent processes or when the semiconductor device is completed. Furthermore, the coating film can be provided as needed; a single-layer coating film may be provided, or no coating film may be provided if the resist mask described later is sufficient.

[0341] Next, a resist mask 279 with openings is formed on the coated film 278 using photolithography (see reference). Figure 30A1 and Figure 30A2 The photoresist mask 279 can be formed, for example, by exposing the photoresist to KrF stimulated excimer laser, ArF stimulated excimer laser, EUV (Extreme Ultraviolet) light, etc. Alternatively, immersion technology can be used, where exposure is performed with the substrate and projection lens filled with liquid (e.g., water). Furthermore, electron beams or ion beams can be used instead of the aforementioned light. In addition, when using electron beams or ion beams, sometimes a photomask is not required.

[0342] Below, according to Figures 30B1 to 30D2 In the process, dry etching is preferably used to process the workpiece. Dry etching allows for anisotropic etching, making it suitable for creating openings with high aspect ratios. When performing anisotropic etching, reactive ion etching is preferred, for example. Note that the dry etching conditions and apparatus can be found in the description above. Note that according to... Figures 30B1 to 30D2 The process is preferably carried out continuously without exposure to the atmosphere. For example, a multi-chamber etching apparatus can be used to carry out the process continuously without exposure to the atmosphere.

[0343] First, the coating film 278 is processed using a resist mask 279 to form a coating film 278 with openings. For example, when an SOG film is used for the coating film 278, an DF-CCP etching apparatus can be used and CF4 can be used as the etching gas for etching.

[0344] Next, the coating film 278 is used as a mask to process the coating film 277, forming a coating film 277 with openings (see reference). Figure 30B1 and Figure 30B2 For example, when using an SOG film as coating film 277, a DF-CCP etching apparatus can be used, and H2 and N2 can be used as etching gases for etching. Here, since an SOG film is used as coating film 278, it is possible to prevent the coating film 278 from disappearing during the etching process of coating film 277.

[0345] Furthermore, it is preferable to remove the resist mask 279 simultaneously during the processing of the coating film 277. Since a SOC film is used as the coating film 277, the resist mask 279 can be easily removed. In addition, if the resist mask 279 remains after the coating film 277 is formed, it is preferable to remove the resist mask 279.

[0346] Next, the coating film 277 is used as a mask to process the insulator 280 to form an insulator 280 with openings. For example, when a silicon oxide film is used for the insulator 280, an DF-CCP etching apparatus can be used and C4F8, C4F6, O2 and Ar can be used as etching gases for etching.

[0347] Furthermore, the coating film 277 is used as a mask to process the insulators 275 and 271A, forming insulators 275, 271a, and 271b with openings (see reference). Figure 30C1 and Figure 30C2 For example, when using silicon oxide and silicon nitride films for insulators 275 and 271A, a DF-CCP etching apparatus can be used, and CH2F2, O2, and Ar can be used as etching gases for etching. In this case, conductor 242A and insulator 222 can be used as etching stop layers. Furthermore, it is preferable to remove the coating film 278 simultaneously with the processing of insulators 275 and 271A.

[0348] Preferably, the coating film 277 is removed by a dry etching process, such as ashing with oxygen plasma, after the insulators 271a and 271b are formed. However, it is not limited to this, and the coating film 277 may also be removed after the conductors 242a and 242b are formed.

[0349] Next, the insulator 280 is preferably used as a mask to remove the surface oxide film of the conductor 242A. For example, when using a tantalum nitride film for the conductor 242A, an ICP etching apparatus can be used and BCl3 and Cl2 can be used as etching gases for etching.

[0350] Furthermore, the insulator 280 is used as a mask to process the conductor 242A to form conductors 242a and 242b (see reference). Figure 30D1 and Figure 30D2 For example, when using a tantalum nitride film for conductor 242A, an ICP etching apparatus can be used, and Cl2 and Ar can be used as etching gases for etching. In this case, oxide semiconductor 230 and insulator 222 can be used as etching stop layers. At this time, as... Figure 30D2As shown, when viewed in cross-section along the channel width direction of transistor 200, there is sometimes a curved surface between the side surface and the top surface of oxide semiconductor 230. That is, sometimes the ends of the side surface and the ends of the top surface are rounded.

[0351] Sometimes, a recess is formed in the portion of the oxide semiconductor 230 exposed from the conductors 242a and 242b. In other words, the height of the region on the top surface of the oxide semiconductor 230 sandwiched between the conductors 242a and 242b is sometimes smaller than the region overlapping with the conductors 242a and 242b.

[0352] Through the above steps, openings can be formed in insulators 275 and 280, and insulators 271a, 271b, conductors 242a and 242b can be formed.

[0353] Note that, as Figures 16A to 16D As shown, when conductors 242a and 242b have a two-layer structure and an insulator 255 is provided, the following process can be performed. At this time, conductor 242A has a stacked structure consisting of conductors 242a1 and 242b1 and conductors 242a2 and 242b2. Figure 30D1 and Figure 30D2 In the illustrated process, the etching process is stopped when conductors 242a2 and 242b2 are formed, exposing the conductors 242a1 and 242b1. Next, an insulating film is deposited to form insulator 255, and a portion of this insulating film is removed using anisotropic etching. This forms a sidewall-shaped insulator 255 that contacts the sides of conductors 242a2 and 242b2. Furthermore, at this time, as... Figure 17C As shown, an insulator 255 can be formed by photolithography, resulting in an insulator 255 having a protrusion at the bottom. Then, by removing the portion of the conductors 242a1 and 242b1 that are exposed from the insulator 255, the conductors 242a2 and 242b1 can be formed under the insulator 255, the conductors 242a2 and 242b2.

[0354] After processing the aforementioned conductor 242A, an ashing treatment using oxygen plasma can also be performed. This oxygen plasma treatment removes impurities that diffused into the oxide semiconductor 230 and the like during the etching process. Examples of such impurities include those originating from components in the workpiece subjected to the etching process and those originating from components in the gases used in the etching process. Examples include chlorine, fluorine, tantalum, silicon, and hafnium. By removing impurities adhering to the oxide semiconductor 230 in this way, the electrical characteristics and reliability of the transistor can be improved.

[0355] Furthermore, the processing of the conductor 242A and the oxygen plasma treatment can be performed continuously without exposure to the atmosphere. For example, this can be done continuously using a multi-chamber etching apparatus without exposure to the atmosphere.

[0356] Preferably, a washing process is performed to remove impurities and other contaminants that adhere to the surface of the oxide semiconductor 230 during the etching process described above. Washing methods include wet washing (also known as wet etching) using a washing solution, plasma treatment using plasma, and washing using heat treatment; combinations of these methods may also be appropriate. Note that this washing process may sometimes deepen the aforementioned recesses.

[0357] Wet washing can also be performed using an aqueous solution prepared by diluting one or more of oxalic acid, phosphoric acid, and hydrofluoric acid with carbonated water or pure water. Alternatively, wet washing can be performed using an aqueous solution prepared by diluting ammonia with carbonated water or pure water. Furthermore, wet washing can also be performed using pure water or carbonated water. Alternatively, ultrasonic washing can be performed using the aforementioned aqueous solutions, pure water, or carbonated water. Furthermore, the above washing methods can be appropriately combined.

[0358] Note that in this specification, the aqueous solution of hydrofluoric acid diluted with pure water is sometimes referred to as dilute hydrofluoric acid, and the aqueous solution of ammonia diluted with pure water is sometimes referred to as dilute ammonia. Furthermore, the concentration, temperature, etc., of this aqueous solution are appropriately adjusted according to the impurities to be removed and the structure of the semiconductor device being cleaned. The ammonia concentration of the dilute ammonia is preferably set to 0.01% or more and 5% or less, more preferably 0.1% or more and 0.5% or less. Furthermore, the hydrogen fluoride concentration of the dilute hydrofluoric acid is preferably set to 0.01 ppm or more and 100 ppm or less, more preferably 0.1 ppm or more and 10 ppm or less.

[0359] Furthermore, a frequency of 200 kHz or higher is preferably used for ultrasonic cleaning, and a frequency of 900 kHz or higher is more preferred. By using this frequency, damage to oxide semiconductors 230 and the like can be reduced.

[0360] Furthermore, the above washing process can be performed multiple times, or the washing solution can be changed for each washing process. For example, the first washing process can be performed using dilute hydrofluoric acid or dilute ammonia, and the second washing process can be performed using pure water or carbonated water.

[0361] In this embodiment, a wet wash is performed using carbonated water as the washing process described above. This washing process removes impurities adhering to the surface of the oxide semiconductor 230 or diffused into its interior. Furthermore, it also removes the surface layer of the oxide semiconductor 230 that was damaged during the etching process described above.

[0362] The heat treatment is preferably performed after the etching or washing described above. The temperature of the heat treatment is 100°C or higher and 650°C or lower, preferably 250°C or higher and 600°C or lower, more preferably 300°C or higher and 550°C or lower, and even more preferably 350°C or higher and 400°C or lower. The heat treatment is performed in an atmosphere containing nitrogen gas, an inactive gas, or an oxidizing gas containing 10 ppm or higher, 1% or higher, or 10% or higher. For example, it is preferable to perform the heat treatment in an oxygen-containing atmosphere, preferably at a nitrogen to oxygen gas flow ratio of 4:1 and at a temperature of 350°C for 1 hour. This supplies oxygen to the oxide semiconductor 230, thereby reducing oxygen vacancies. Furthermore, the crystallinity of the oxide semiconductor 230 can be improved by performing the above heat treatment. Moreover, when residual hydrogen in the oxide semiconductor 230 reacts with the supplied oxygen, the hydrogen can be removed in the form of H2O (dehydration). This suppresses the recombination of hydrogen and oxygen vacancies in the oxide semiconductor 230 to form V. O H. This improves the electrical characteristics of the transistor with the oxide semiconductor 230, thereby increasing reliability. Furthermore, it suppresses the inhomogeneity of electrical characteristics among multiple transistors formed on the same substrate. Additionally, the above-described heat treatment can be performed under reduced pressure. Alternatively, it can be performed in an oxygen atmosphere, followed by continuous heat treatment in a nitrogen atmosphere without exposure to the atmosphere. Moreover, the above-described heat treatment can also serve as a post-deposition heat treatment for the oxide semiconductor film 230f. Therefore, sometimes the crystalline region of the oxide semiconductor 230 is grown through the above-described heat treatment.

[0363] Here, as Figures 16A to 16D As shown, when both conductors 242a and 242b have a laminated structure, an insulator 255, which includes an inorganic insulator that is not easily oxidized, is provided in contact with the sides of conductors 242a2 and 242b2. Therefore, even if conductors 242a2 and 242b2 are made of materials such as tungsten films that are easily oxidized, excessive oxidation of conductors 242a2 and 242b2 due to the aforementioned heat treatment can be prevented.

[0364] Note that when heat treatment is performed with conductors 242a and 242b in contact with the oxide semiconductor 230, the sheet resistance of the regions of the oxide semiconductor 230 overlapping with conductors 242a and 242b sometimes decreases. Additionally, the carrier concentration sometimes increases. Therefore, it is possible to self-align and reduce the resistance of the regions of the oxide semiconductor 230 overlapping with conductors 242a and 242b.

[0365] For example, such as Figure 4A As shown, even if the oxide semiconductor 230 has a stacked structure and a metal oxide with low conductivity or a large band gap is used as the oxide semiconductor 230c, the resistance of the regions overlapping with conductor 242a and conductor 242b in the oxide semiconductor 230 can be reduced as described above. Therefore, source and drain regions can be formed in the oxide semiconductor 230c.

[0366] Next, an insulating film 250f, which will become the insulator 250, is deposited in a manner that covers the openings formed in the insulator 280, etc. (see reference). Figures 31A to 31D Here, insulating film 250f is deposited along the openings of insulator 280 and insulator 275. Insulating film 250f is in contact with insulator 280, conductor 242a, conductor 242b, insulator 222, insulator 224 and oxide semiconductor 230.

[0367] The insulating film 250f can be deposited using sputtering, CVD, MBE, PLD, or ALD methods. For example, the insulating film 250f is preferably deposited using the ALD method. The insulating film 250f is preferably formed thin, and thickness non-uniformity needs to be minimized. For this purpose, the ALD method is a deposition method that alternately introduces precursors and reactants (e.g., oxidants), and the thickness can be adjusted according to the number of cycles, thus allowing for precise thickness control. Furthermore, the insulating film 250f needs to be deposited with high coverage on the bottom and side surfaces of the opening. By using the ALD method, atomic layers can be deposited on the bottom and side surfaces of the opening, thereby forming the insulating film 250f with high coverage within the opening.

[0368] In addition, when depositing the insulating film 250f using the ALD method, ozone (O3), oxygen (O2), water (H2O), etc., can be used as oxidants. By using ozone (O3), oxygen (O2), etc., which do not contain hydrogen, as oxidants, the amount of hydrogen diffusing into the oxide semiconductor 230 can be reduced.

[0369] like Figure 4B As shown, the insulator 250 can have a multilayer structure. Below, we will discuss the insulator 250 and... Figure 4B Similarly, the deposition method of insulating film 250f when having a four-layer structure of insulator 250a, insulator 250b, insulator 250d and insulator 250c will be described.

[0370] First, a film that will become insulator 250a is deposited to cover the openings formed in insulator 280, etc., and then a film that will become insulator 250b is deposited on the film that will become insulator 250a. In this embodiment, aluminum oxide is deposited as the film that will become insulator 250a using the thermal ALD method, and silicon oxide is deposited as the film that will become insulator 250b using the PEALD method.

[0371] Next, microwave treatment (also known as microwave plasma treatment or microwave-excited high-density plasma treatment) is preferably performed in an oxygen-containing atmosphere. Here, microwave treatment refers, for example, to treatment using a device that includes a power supply for generating high-density plasma with microwaves. Furthermore, in this specification and the like, microwaves refer to electromagnetic waves with a frequency of 300 MHz or higher and 300 GHz or lower.

[0372] Microwave processing preferably utilizes a microwave processing apparatus, for example, that includes a power supply for generating high-density plasma using microwaves. Here, the frequency of the microwave processing apparatus is preferably set to 300 MHz or more and 300 GHz or less, more preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz. By using high-density plasma, a high density of oxygen free radicals can be generated. Furthermore, the power of the power supply for applying microwaves to the microwave processing apparatus is preferably 1000 W or more and 10000 W or less, more preferably 2000 W or more and 5000 W or less. Additionally, the microwave processing apparatus may also include a power supply that applies RF to one side of the substrate. Furthermore, by applying RF to one side of the substrate, oxygen ions generated by the high-density plasma can be efficiently introduced into the oxide semiconductor 230.

[0373] Furthermore, the aforementioned microwave treatment is preferably performed under reduced pressure, preferably between 10 Pa and 1000 Pa, more preferably between 300 Pa and 700 Pa. The treatment temperature is preferably below 750°C, more preferably below 500°C, for example, around 250°C. Alternatively, heating treatment can be performed continuously after oxygen plasma treatment without exposure to external air. The heating temperature is preferably between 100°C and 750°C, more preferably between 300°C and 500°C.

[0374] Alternatively, for example, the microwave processing described above can be performed using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O2 / (O2+Ar)) is greater than 0% and less than 100%. Preferably, the oxygen flow rate ratio (O2 / (O2+Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow rate ratio (O2 / (O2+Ar)) is more than 10% and less than 40%. Even more preferably, the oxygen flow rate ratio (O2 / (O2+Ar)) is more than 10% and less than 30%. In this way, by performing microwave processing in an oxygen-containing atmosphere, the carrier concentration in the region of the oxide semiconductor 230 exposed from the opening can be reduced. In addition, by preventing excessive oxygen from being introduced into the processing chamber during microwave processing, an excessive decrease in the carrier concentration in the oxide semiconductor 230 can be prevented.

[0375] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high frequencies such as RF, and this oxygen plasma can then act on the region between conductors 242a and 242b of the oxide semiconductor 230. Through the action of plasma, microwaves, etc., the V in this region can be increased. O H separates into oxygen vacancies and hydrogen, and hydrogen is removed from this region. Here, in the use of Figure 4B In the case of the structure shown, as the membrane that will become insulator 250a, it is preferable to use an insulating membrane (e.g., alumina, etc.) that has the function of trapping or fixing hydrogen. By adopting the above structure, the membrane that will become insulator 250a can trap or fix the hydrogen generated by microwave treatment. In this way, the V contained in the channel forming region can be reduced. O H. This can reduce oxygen vacancies and V in the channel formation region. O H reduces carrier concentration. Furthermore, by supplying oxygen free radicals generated in the aforementioned oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, thereby reducing carrier concentration.

[0376] The oxygen injected into the channel formation region can be in various forms, including oxygen atoms, oxygen molecules, oxygen ions, and oxygen free radicals (also known as O free radicals, which are atoms, molecules, or ions containing unpaired electrons). The oxygen injected into the channel formation region can be one or more of the above forms, and oxygen free radicals are particularly preferred. In addition, the reliability of the transistor is improved because the film quality of the insulator 250 can be improved.

[0377] On the other hand, the oxide semiconductor 230 has a region that overlaps with either conductor 242a or conductor 242b. This region can be used as a source region or a drain region. Here, conductor 242a and conductor 242b are preferably used as shielding films to protect against the effects of microwaves, RF, or oxygen plasma during microwave processing in an oxygen-containing atmosphere. Thus, conductor 242a and conductor 242b preferably have the function of shielding electromagnetic waves of 300 MHz or higher and 300 GHz or lower, for example, 2.4 GHz or higher and 2.5 GHz or lower.

[0378] Conductors 242a and 242b shield against the effects of high-frequency microwaves or RF, oxygen plasma, etc., and therefore do not act on the region of oxide semiconductor 230 that overlaps with either conductor 242a or conductor 242b. Thus, Vo does not occur in the source and drain regions during microwave processing. O The decrease in H and the excessive supply of oxygen can prevent the decrease in carrier concentration.

[0379] As described above, oxygen vacancies and V can be selectively removed in the channel formation region of an oxide semiconductor. O H makes the channel formation region i-type or substantially i-type. Furthermore, it can suppress the supply of excessive oxygen to the regions used as source or drain regions, maintaining the conductivity (low resistance region state) before microwave processing. Thus, it can suppress variations in the electrical characteristics of the transistor and suppress non-uniformity of the transistor's electrical characteristics within the substrate surface.

[0380] Furthermore, by modifying the film quality of the films that will become insulator 250a and insulator 250b through microwave treatment, the diffusion of hydrogen, water, impurities, etc., can be suppressed. This suppresses the diffusion of hydrogen, water, impurities, etc., through insulator 250 into oxide semiconductor 230 and the like, which may occur after subsequent processes such as deposition of the conductive film that will become conductor 260 or after heat treatment. Thus, by improving the film quality of insulator 250, the reliability of transistors can be improved.

[0381] Next, a film that will become insulator 250d is deposited on the film that will become insulator 250b. In this embodiment, hafnium oxide is deposited using a thermal ALD method as the film that will become insulator 250d. Alternatively, hafnium zirconium oxide can also be deposited using a thermal ALD method as the film that will become insulator 250d. Furthermore, microwave treatment can be performed again after depositing the film that will become insulator 250d.

[0382] Next, a film that will become insulator 250c is deposited on the film that will become insulator 250d. In this embodiment, silicon nitride is deposited using the PEALD method as the film that will become insulator 250c. In this way, an insulating film 250f comprising films that will become insulator 250a to films that will become insulator 250d can be formed.

[0383] Note that the above structure shows an example of microwave treatment performed after the deposition of the film that will become insulator 250b and after the deposition of the film that will become insulator 250d, but the present invention is not limited thereto. Microwave treatment may also be performed after the deposition of the film that will become insulator 250c. Alternatively, microwave treatment may be performed before the deposition of the film that will become insulator 250a. Furthermore, microwave treatment may be performed three or more times. In addition, the above-described microwave treatment can sometimes also be combined with the heat treatment shown in Embodiment 2. Therefore, sometimes a crystalline region of the oxide semiconductor 230 is grown through the above-described microwave treatment.

[0384] Alternatively, heating treatment can be performed while maintaining a reduced pressure after microwave treatment. This treatment efficiently removes hydrogen from the oxide semiconductor 230 within the insulating film. Furthermore, the step of performing heating treatment while maintaining a reduced pressure after microwave treatment can be repeated multiple times. Repeated heating treatment further efficiently removes hydrogen from the oxide semiconductor 230 within the insulating film. Note that the heating treatment temperature is preferably 300°C or higher and 500°C or lower. Moreover, the above-described heating treatment can also be performed as shown in Embodiment 2. Therefore, sometimes the crystalline region of the oxide semiconductor 230 grows through the above-described heating treatment.

[0385] Next, a conductive film 260f (refer to) will be deposited to become the conductor 260. Figures 31A to 31D The conductive film 260f can be made of the aforementioned conductive materials and deposited using sputtering, CVD, MBE, PLD, electroplating, or ALD methods. For example, titanium nitride and tungsten films can be deposited in layers using CVD. Figure 4A As shown, the conductor 260 can have a stacked structure of a titanium nitride conductor 260a and a tungsten conductor 260b. Alternatively, a conductive film 260f can be deposited simultaneously with heating the substrate. Substrate heating can also be performed as the heating process shown in Embodiment 2. Therefore, sometimes the crystalline region of the oxide semiconductor 230 is grown through the aforementioned substrate heating.

[0386] Next, the insulating film 250f and the conductive film 260f are polished using CMP until the insulator 280 is exposed. That is, a portion of the insulating film 250f and the conductive film 260f exposed from the opening is removed. Thus, the insulator 250 and the conductor 260 (conductor 260a and conductor 260b) are formed in the opening overlapping with the conductor 205 (see reference). Figures 32A to 32D ).

[0387] Thus, the insulator 250 is disposed in contact with the conductors 242a, 242b, oxide semiconductor 230, insulator 224, and insulator 222 within the aforementioned opening. Furthermore, the conductor 260 is disposed such that it is embedded in the aforementioned opening with the insulator 250 in between. This forms the transistor 200.

[0388] Next, insulator 282 is deposited on insulator 250, conductor 260 and insulator 280 (see reference). Figures 33A to 33D The insulator 282 can be deposited, for example, using sputtering, CVD, MBE, PLD, or ALD methods. Sputtering is preferred for depositing the insulator 282. By using sputtering, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0389] In addition, such as Figure 4A As shown, insulator 282 preferably has a stacked structure of insulator 282a and insulator 282b. Here, insulator 282a is preferably deposited using the ALD method, and insulator 282b is preferably deposited using the sputtering method.

[0390] In this embodiment, aluminum oxide can be deposited as the insulator 282a using the thermal ALD method. Here, the thickness of the insulator 282a is 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less.

[0391] By using the ALD method to deposit insulator 282a, insulator 282a can be deposited without causing excessive damage to the surface to be formed. Therefore, excessive damage to the upper end of insulator 250 and the top surface of conductor 260 can be prevented, thereby improving the electrical characteristics and reliability of transistor 200.

[0392] Furthermore, by using the ALD method to deposit insulator 282a, insulator 282a can be deposited without adding oxygen to insulator 280. This prevents the addition of excessive oxygen to insulator 280. Therefore, the electrical characteristics and reliability of transistor 200 can be improved.

[0393] In this embodiment, alumina can be deposited as the insulator 282b using a sputtering method. By using a sputtering method that does not require hydrogen-containing molecules to be used in the deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0394] Here, by depositing insulator 282b in an oxygen-containing atmosphere using sputtering, oxygen can be added to insulator 280 simultaneously with the deposition. This allows insulator 280 to contain excess oxygen. Preferably, insulator 282b is deposited while the substrate is heated. Since insulator 282b is deposited on insulator 282a and oxygen is added through insulator 282a, the amount of oxygen injected into insulator 280 can be controlled. When the thickness of insulator 282a is large, the aforementioned oxygen addition is easily hindered, resulting in a decrease in the amount of oxygen injected into insulator 280. When the thickness of insulator 282a is small, the aforementioned oxygen addition is not easily hindered, resulting in an increase in the amount of oxygen injected into insulator 280. For example, by setting the thickness of insulator 282a within the aforementioned range, a sufficient amount of oxygen can be supplied to oxide semiconductor 230, and excessive oxygen supply to oxide semiconductor 230 can be prevented. This improves the electrical characteristics and reliability of transistor 200. In addition, when depositing the insulator 282b, oxygen can be added not only to the insulator 280 but also to the upper end of the insulator 250.

[0395] Furthermore, by depositing insulator 282b on insulator 282a, the upper end of insulator 250 and the top surface of conductor 260 can be protected from the impact of ion collisions generated by the sputtering deposition of insulator 282b.

[0396] Alumina is deposited using an aluminum target in an atmosphere containing oxygen gas. The amount of oxygen injected into the insulator 280 can be controlled by the magnitude of the bias power applied to the substrate via sputtering. For example, a lower bias power results in less oxygen injected into the insulator 280, and the oxygen content can easily become saturated even if the thickness of the insulator 282b is small. Conversely, a higher bias power results in more oxygen injected into the insulator 280. By reducing the bias power, the amount of oxygen injected into the insulator 280 can be suppressed. Note that when applying a substrate bias using an RF power supply, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage to the substrate can be caused.

[0397] Furthermore, a heat treatment can be performed before depositing the insulator 282b. This heat treatment can also be performed under reduced pressure, wherein the insulator 282b is deposited continuously without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adsorbed on the surface of the insulator 280 can be captured or fixed by the insulator 282a, and the moisture and hydrogen concentrations in the insulator 280 are reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is set to 250°C.

[0398] Furthermore, by performing the aforementioned heat treatment, such as Figure 8 As shown, oxygen can diffuse from insulator 224 through insulator 250 to oxide semiconductor 230. Note that the heat treatment to supply oxygen to oxide semiconductor 230 can be appropriately performed after deposition of insulator 250.

[0399] Here, even though a layer 227 with low oxygen permeability is provided between the insulator 224 and the oxide semiconductor 230, excess oxygen contained in the insulator 224 can still be supplied to the oxide semiconductor 230 through the insulator 250. Furthermore, by supplying oxygen through the insulator 250, oxygen can be selectively supplied to the channel formation region of the oxide semiconductor 230 and its vicinity. Therefore, excessive oxidation of the source and drain regions of the oxide semiconductor 230 can be prevented, thus preventing a decrease in carrier concentration in the source or drain regions and preventing a decrease in the on-state current and field-effect mobility of the transistor 200.

[0400] Furthermore, by using indium oxide, which has high oxygen permeability, in the oxide semiconductor 230, and thus sufficiently reducing the oxygen vacancies in the oxide semiconductor 230, excess oxygen can diffuse from the oxide semiconductor 230. This suppresses the presence of excess oxygen in the oxide semiconductor 230, thereby preventing the threshold voltage of the transistor 200 from becoming excessive. Therefore, the electrical characteristics and reliability of the transistor 200 incorporating the oxide semiconductor 230 can be improved.

[0401] Next, insulator 283 is formed on insulator 282 (see reference). Figures 33A to 33D The insulator 283 can be deposited, for example, using sputtering, CVD, MBE, PLD, or ALD methods. Sputtering is preferred for depositing the insulator 283. By using sputtering, which does not require hydrogen-containing molecules to be used in the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. In this embodiment, silicon nitride is deposited as the insulator 283 using sputtering.

[0402] In this embodiment, silicon nitride is deposited as insulator 283 using sputtering, and aluminum oxide is deposited as insulator 282 using thermal ALD and sputtering. Thus, by using silicon nitride, which has the function of suppressing hydrogen diffusion, as insulator 283, hydrogen diffusion from the upper layer of transistor 200 can be suppressed. Furthermore, by using aluminum oxide, which has the function of trapping or fixing hydrogen, as insulator 282, hydrogen contained in insulator 280 and the like can be trapped or fixed by insulator 282. This reduces the hydrogen concentration in and around oxide semiconductor 230.

[0403] Next, insulator 285 is formed on insulator 283 (see reference). Figures 33A to 33D The insulator 285 can be deposited, for example, using sputtering, CVD, MBE, PLD, or ALD methods. Sputtering is preferred for depositing the insulator 285. By using sputtering, which does not require hydrogen-containing molecules to be used in the deposition gas, the hydrogen concentration in the insulator 285 can be reduced. In this embodiment, silicon oxide is deposited as the insulator 285 using sputtering.

[0404] Here, it is preferable to continuously deposit insulators 282, 283, and 285 using a sputtering method without exposing them to the atmospheric environment. By depositing in a manner that does not expose them to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to insulators 282, 283, and 285, thus keeping the area near the interface between insulators 282 and 283, and the area near the interface between insulators 283 and 285, clean.

[0405] Next, openings reaching the conductor 242a are formed in insulators 271a, 275, 280, 282, 283, and 285, and openings reaching the conductor 242b are formed in insulators 271b, 275, 280, 282, 283, and 285. These openings can be formed using lithography. When forming these openings, dry etching is preferably used on the workpiece. Dry etching allows for anisotropic etching, making it suitable for forming openings with high aspect ratios. When performing anisotropic etching, reactive ion etching is preferred, for example. Note that the dry etching conditions and apparatus can be referred to the above description. Furthermore, the shape of the opening when viewed from above can be a circle, an ellipse or other approximately circular shape, a polygonal shape such as a square, or a polygonal shape with rounded corners, etc.

[0406] Next, after forming the opening described above, a heat treatment is performed. The heat treatment temperature can be 100°C or higher and 600°C or lower, preferably 250°C or higher and 550°C or lower, more preferably 350°C or higher and 450°C or lower. The heat treatment is preferably performed in a nitrogen atmosphere or an inactive gas atmosphere. In addition, since this heat treatment is performed with the conductors 242a and 242b exposed, it is preferable to perform it in an atmosphere that does not contain oxidizing gases or oxygen gases. For example, it is preferable to perform the heat treatment at 400°C for 1 hour in a nitrogen atmosphere. In addition, the above heat treatment can also be performed under reduced pressure. Through the above heat treatment, oxygen contained in the insulator 280 can be supplied to the oxide semiconductor 230 through the insulator 250. As a result, oxygen vacancies in the channel formation region of the oxide semiconductor 230 can be reduced. Furthermore, the above heat treatment can also be used as the heat treatment shown in Embodiment 2. Therefore, sometimes the crystalline region of the oxide semiconductor 230 is grown through the above heat treatment.

[0407] Here, since the side of the insulator 280 is exposed in the aforementioned opening, the oxygen contained in the insulator 280 can be diffused outward by the aforementioned heat treatment, thereby controlling the amount of oxygen contained in the insulator 280. On the other hand, since the insulator 280 is provided with oxygen-barrier insulators 282 and 283, oxygen does not diffuse outward from the top surface of the insulator 280. Thus, excessive oxygen can be prevented from diffusing outward from the insulator 280 and forming oxygen vacancies in the insulator 280. Furthermore, the oxide semiconductor 230, conductors 242a and 242b are covered by the insulator 275. Thus, excessive oxygen can be prevented from directly diffusing from the insulator 280 to the oxide semiconductor 230, conductors 242a and 242b during the aforementioned heat treatment.

[0408] As described above, during the deposition of insulator 282b, the amount of oxygen added to insulator 280 can be controlled by adding oxygen through insulator 282a. Furthermore, when oxygen diffuses outward from the side of insulator 280 using the aforementioned heat treatment, the amount of oxygen in insulator 280 can be more appropriate. Thus, by supplying oxygen to oxide semiconductor 230 from insulator 280 with adjusted oxygen content, an appropriate amount of oxygen can be supplied to oxide semiconductor 230. This reduces oxygen vacancies in oxide semiconductor 230 and prevents excessive oxygen supply to oxide semiconductor 230. Therefore, the electrical characteristics and reliability of transistor 200 can be improved. In addition, the process of exposing the side of insulator 280 can also serve as the process of forming openings for embedding conductors 240a and 240b, thus simplifying the manufacturing process of the semiconductor device.

[0409] Furthermore, through the aforementioned heat treatment, hydrogen contained in insulators 280, 250, and oxide semiconductor 230 moves to insulator 282 and is captured by it. In other words, hydrogen in insulators 280, 250, and oxide semiconductor 230 diffuses into insulator 282. Therefore, although the hydrogen concentration in insulator 282 increases, the hydrogen concentrations in insulators 280, 250, and oxide semiconductor 230 all decrease. Moreover, when insulator 283 is provided in contact with the top surface of insulator 282, impurities such as moisture or hydrogen can be prevented from entering from above insulator 283 during the heat treatment. Additionally, through the heat treatment, hydrogen contained in insulators 216, 224, and oxide semiconductor 230 moves to insulator 222 and is captured by it. In other words, hydrogen in insulators 216, 224, and oxide semiconductor 230 diffuses into insulator 222. Therefore, although the hydrogen concentration in insulator 222 increases, the hydrogen concentrations in insulators 216, 224, and oxide semiconductor 230 all decrease. Here, when insulator 221 is provided in contact with the bottom surface of insulator 222, impurities such as moisture or hydrogen can be prevented from entering from below insulator 221 due to the heat treatment.

[0410] Next, insulating films that will become insulators 241a and 241b are deposited along the shape of the aforementioned openings. These insulating films can be deposited using methods such as sputtering, CVD, MBE, PLD, or ALD. Since the insulating films that will become insulators 241a and 241b are deposited in openings with high aspect ratios, ALD deposition is preferred. As the insulating films that will become insulators 241a and 241b, insulating films with oxygen-suppressing properties are preferred. For example, silicon nitride is preferably deposited using the PEALD method. Silicon nitride has high hydrogen barrier properties, so it is preferred.

[0411] Next, anisotropic etching is performed on the insulating film to form insulators 241a and 241b. Insulator 241a is formed to cover the sidewalls of the openings on conductor 242a, and insulator 241b is formed to cover the sidewalls of the openings on conductor 242b. Dry etching or similar methods can be used for the anisotropic etching of the insulating film that will become insulators 241a and 241b. For example, reactive ion etching is preferred. By providing insulators 241a and 241b on the sidewalls of the openings, oxygen permeation from the outside can be suppressed, and oxidation of the subsequently formed conductors 240a and 240b can be prevented. Furthermore, impurities such as water and hydrogen contained in insulator 280 can be prevented from diffusing into conductors 240a and 240b. Note that sometimes, due to this anisotropic etching, a recess is formed on a portion of the top surface of conductors 242a and 242b.

[0412] Next, a conductive film is deposited to become conductors 240a and 240b. This conductive film preferably has a multilayer structure including a conductor that inhibits the permeation of impurities such as water and hydrogen. For example, a multilayer of tantalum nitride, titanium nitride, etc., with tungsten, molybdenum, copper, etc., can be used. The conductive film to become conductors 240a and 240b can be deposited using sputtering, CVD, MBE, PLD, or ALD methods.

[0413] Next, by performing CMP processing, a portion of the conductive film that will become conductors 240a and 240b is removed, exposing the top surface of the insulator 285. As a result, the conductive film remains only at the opening, thereby forming conductors 240a and 240b with flat top surfaces (see reference). Figures 3A to 3D Note that sometimes a portion of the top surface of insulator 285 is removed due to this CMP process.

[0414] Alternatively, a heat treatment can be performed after the conductors 240a and 240b have been formed. This heat treatment can be performed under the same conditions as described above. By performing this heat treatment, the amount of oxygen supplied to the oxide semiconductor 230 can be adjusted. This, in turn, improves the electrical characteristics and reliability of the transistor 200.

[0415] Through the above steps, it is possible to manufacture Figures 3A to 3D The semiconductor device shown.

[0416] Furthermore, the process of providing oxide semiconductors 230ca and 230cb under conductors 242a and 242b will be described. As an example, the following refers to... Figures 34A1 to 35B2 illustrate Figure 9A The manufacturing process of the semiconductor device shown.

[0417] First, until Figures 28A to 28D The process shown is performed in the same manner as described above, forming insulator 280 (refer to...). Figure 34A1 and Figure 34A2 However, in Figure 34A1 and Figure 34A2In the structure shown, the oxide semiconductor 230 has a stacked structure of oxide semiconductor 230b and oxide semiconductor 230c on oxide semiconductor 230b. The oxide semiconductor 230c is further processed into oxide semiconductor 230ca and oxide semiconductor 230cb in subsequent processes. Furthermore, a layer 227 is formed between the oxide semiconductor 230b and the insulator 224. For example, indium oxide can be used as oxide semiconductor 230b, and In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:1:1 or similar can be used as oxide semiconductor 230c. Furthermore, for example, In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:3:2 or similar can be used as layer 227.

[0418] Next, through cooperation with... Figures 29A to 29D The same method is used to process conductor 242A, insulator 271A, insulator 275, and insulator 280 to form openings reaching oxide semiconductor 230 and insulator 222 (see reference). Figure 34B1 and Figure 34B2 Here, insulators 271a and 271b, conductors 242a and 242b are formed. At this time, sometimes a recess is formed in the portion of the oxide semiconductor 230c that is exposed from conductors 242a and 242b.

[0419] Next, an etching process is performed to remove the portions of the oxide semiconductor 230c exposed from the conductors 242a and 242b (see reference). Figure 35A1 and Figure 35A2 Therefore, the oxide semiconductor 230c can be separated into oxide semiconductor 230ca under conductor 242a and oxide semiconductor 230cb under conductor 242b. By adopting this structure, the channel of the transistor 200 can be formed only in oxide semiconductor 230b and not in oxide semiconductor 230c. This improves the on-state current, carrier mobility, and frequency characteristics of the transistor 200. The etching process described above can be performed using dry etching or wet etching. For example, wet etching is preferably performed using an etchant with a high selectivity for oxide semiconductor 230b.

[0420] For example, when indium oxide is used for oxide semiconductor 230b and In-Ga-Zn oxide with an In:Ga:Zn ratio of 1:1:1 [atomic ratio] is used for oxide semiconductor 230c, oxide semiconductor 230c can be selectively etched using a wet etching method. For example, one or more of oxalic acid, phosphoric acid, nitric acid, acetic acid, hydrochloric acid, and hydrogen fluoride can be used as the etchant. Furthermore, a mixed solution of the above acids or a mixed solution of the above acids with other acids can be used. For example, a mixed solution of phosphoric acid, hydrogen fluoride, and nitric acid can be used. Furthermore, for example, a mixed solution of nitric acid, acetic acid, and phosphoric acid can be used. Furthermore, for example, a mixed solution of nitric acid and hydrochloric acid can be used. Furthermore, an alkaline solution such as TMAH (Tetramethylammonium Hydroxide) solution can be used as the etchant. Furthermore, an aqueous solution diluted with pure water or the like can be used.

[0421] Furthermore, in the case of processing oxide semiconductor 230c using wet etching, such as Figure 35A1 As shown, sometimes the sides of oxide semiconductors 230ca and 230cb are etched. In this case, in transistor 200, the side of oxide semiconductor 230ca with conductor 260 is formed in a manner that is recessed from the side of conductor 260 of conductor 242a, and the side of oxide semiconductor 230cb with conductor 260 is formed in a manner that is recessed from the side of conductor 260 of conductor 242b. Therefore, the distance between the side of oxide semiconductor 230ca with conductor 260 and the side of oxide semiconductor 230cb with conductor 260 is longer than the distance between the side of conductor 260 of conductor 242a and the side of conductor 260 of conductor 242b.

[0422] Note that, as Figure 20A As shown, when conductors 242a and 242b have a two-layer structure and an insulator 255 is provided, in transistor 200, the side of oxide semiconductor 230ca with conductor 260 side is formed in a manner that is recessed from the side of oxide semiconductor 242a1 with conductor 260 side, and the side of oxide semiconductor 230cb with conductor 260 side is formed in a manner that is recessed from the side of oxide semiconductor 242b1 with conductor 260 side. Therefore, the distance between the side of oxide semiconductor 230ca with conductor 260 side and the side of oxide semiconductor 230cb with conductor 260 side is longer than the distance between the side of oxide semiconductor 242a1 with conductor 260 side and the side of oxide semiconductor 242b1 with conductor 260 side.

[0423] In addition, such as Figure 35A2As shown, sometimes the sidewalls of layer 227 are etched. In this case, in the region of transistor 200 that overlaps with conductor 260, the sidewalls of layer 227 in the channel width direction are formed in a manner that they are recessed from the sidewalls of insulator 224 in the channel width direction.

[0424] Next, insulator 250 is deposited in a manner that covers insulator 280, oxide semiconductor 230b, layer 227, insulator 224, and insulator 222 (see reference). Figure 35B1 and Figure 35B2 Regarding the deposition method for insulator 250, please refer to [reference needed]. Figures 31A to 31D According to the record, by using deposition methods with good coverage such as ALD, a portion of the insulator 250 can sometimes be embedded in the recesses on the side of the oxide semiconductor 230ca, the side of the oxide semiconductor 230cb, and the side of the layer 227.

[0425] like Figure 9A As shown, the insulator 250 can have a stacked structure of insulator 250a, insulator 250b on insulator 250a, and insulator 250c on insulator 250b. For example, insulator 250a can be made of hafnium oxide with a thickness of 2 nm, insulator 250b can be made of silicon oxide with a thickness of 2 nm, and insulator 250c can be made of silicon nitride with a thickness of 1 nm. Thus, by using a structure in which hafnium oxide is used as insulator 250a, an insulator 250a containing hafnium oxide can be disposed in contact with an oxide semiconductor 230b containing indium oxide near the channel formation region of transistor 200. By adopting this structure, impurities such as hydrogen and excess oxygen in oxide semiconductor 230b can be absorbed by insulator 250a. The hydrogen and oxygen absorbed by insulator 250a can diffuse outward from insulator 250a as H2O by heat treatment in a subsequent process. In this way, impurities such as hydrogen and excess oxygen in the oxide semiconductor 230b can be reduced, thereby improving the electrical characteristics and reliability of the transistor 200.

[0426] The processes following the formation of insulator 250 can be carried out in accordance with... Figures 31A to 31D The same process is performed after the formation of the conductor 260. Note that... Figures 34A1 to 35B2 The process shown is related to Figure 9A Similarly, a layer 227 can be disposed between the insulator 224 and the oxide semiconductor 230b, but this is not a limitation. For example, as... Figure 9C As shown, the transistor 200 can be manufactured by the above method even without a layer 227 between the insulator 224 and the oxide semiconductor 230b.

[0427] The semiconductor device according to this embodiment includes an OS transistor. In this embodiment, by employing a structure in which the impurity 220 in the insulator 224 becomes a negative fixed charge, the negative drift of the electrical characteristics of the OS transistor can be suppressed, thereby achieving normally-off characteristics. Therefore, a semiconductor device with good electrical characteristics can be provided.

[0428] This embodiment can be appropriately combined with other embodiments. Furthermore, in this specification, where multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0429] (Implementation Method 2) In this embodiment, an oxide semiconductor that can be used as a semiconductor layer for a transistor is described. The oxide semiconductor described in this embodiment can be used as the oxide semiconductor 230 shown in Embodiment 1, etc. As an example of the present invention, an oxide semiconductor can be a single layer or a stack of layers containing metal oxides. Note that in oxide semiconductors with a stacked structure, as described later, it is sometimes difficult to determine the boundaries between the stacked films.

[0430] [Metal Oxides] According to one aspect of the invention, the metal oxide preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Furthermore, the metal oxide preferably contains two or three selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide may contain indium and zinc as main components, and may also contain element M. Note that element M is a metallic or half-metallic element with a high bond energy with oxygen, for example, a metallic or half-metallic element with a higher bond energy with oxygen than indium. Specifically, examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the invention preferably contains one or more elements selected from indium, gallium, and zinc. In this specification and the like, metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the term "metallic element" as used in this specification and the like sometimes includes half-metallic elements.

[0431] As one embodiment of the metal oxide according to the present invention, for example, indium zinc oxide (In-Zn oxide, also known as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also known as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also known as IGTO), indium aluminum zinc oxide (In-Al-Zn oxide, also known as IAZO), indium tin zinc oxide (also known as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also known as IGZO), indium tin oxide containing silicon oxide (ITSO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also known as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also known as IGAZO or IAGZO), etc. Alternatively, gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc., can be used. Furthermore, as a metal oxide according to one aspect of the present invention, indium oxide can be used. Additionally, as a metal oxide according to one aspect of the present invention, gallium oxide, zinc oxide, etc., can be used.

[0432] By increasing the indium content of metal oxides, transistors can achieve large on-state current and high frequency characteristics.

[0433] Note that metal oxides can also contain one or more metals with high period numbers in the periodic table to replace indium. Alternatively, metal oxides can also contain one or more metals with high period numbers in the periodic table in addition to indium. The greater the overlap of the orbitals of a metal element, the greater the carrier conduction in the metal oxide. Therefore, by including metals with high period numbers in the periodic table, the field-effect mobility of transistors can sometimes be improved. Examples of metals with high period numbers in the periodic table include metals belonging to period 5 and period 6. Specifically, examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0434] Furthermore, metal oxides can also contain one or more non-metallic elements. The inclusion of non-metallic elements in metal oxides can sometimes improve the field-effect mobility of transistors. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0435] Furthermore, by increasing the zinc content in the metal oxide, the metal oxide becomes highly crystallizable, thus suppressing the diffusion of impurities within the metal oxide. Consequently, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0436] Furthermore, by increasing the content of element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, thereby enabling transistors with low off-state current. In addition, variations in the transistor's electrical characteristics are suppressed, thus improving reliability.

[0437] Examples of oxide semiconductor structures that can improve the field-effect mobility of transistors will be described. For example, a stacked structure of indium oxide and IGZO is preferred. Specifically, the oxide semiconductor preferably includes indium oxide and IGZO on indium oxide. Furthermore, nitrogen-containing IGZO is preferably used as the oxide semiconductor. For example, nitrogen-containing IGZO can be formed by performing N2O plasma treatment during or after deposition. In addition, at least one of indium oxide, In-Ga oxide, In-Zn oxide, and IGZTO is preferably used as the oxide semiconductor.

[0438] In this embodiment, In-M-Zn oxide is sometimes used as an example of a metal oxide.

[0439] One aspect of the oxide semiconductor of the present invention preferably comprises a crystalline metal oxide. Examples of structures comprising a crystalline metal oxide include a CAAC (c-axis aligned crystalline) structure, a polycrystalline structure, and a nanocrystalline structure. By using a crystalline metal oxide in the oxide semiconductor, the defect state density in the oxide semiconductor can be reduced. Therefore, the reliability of transistors using an oxide semiconductor according to one aspect of the present invention can be improved, and the reliability of semiconductor devices in which transistors are mounted can be improved.

[0440] Note that there are no particular restrictions on the crystallinity of the metal oxides included in oxide semiconductors. For example, oxide semiconductors sometimes include more than one of the following: amorphous semiconductors (semiconductors with an amorphous structure), single-crystal semiconductors (semiconductors with a single-crystal structure), and semiconductors with crystallinity other than single crystal (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors in which a portion has crystalline regions). When oxide semiconductors are crystallinous, it can sometimes suppress the degradation of transistor characteristics.

[0441] The crystallinity of oxide semiconductors can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods can be used for analysis.

[0442] One embodiment of the present invention preferably comprises a metal oxide having a CAAC structure. A CAAC structure is a crystal structure in which multiple microcrystals (typically multiple microcrystals with a hexagonal crystal structure) are c-axis oriented and connected without orientation on the ab plane. Furthermore, when a cross-section of an oxide semiconductor having a CAAC structure is observed using a high-resolution TEM image (also known as a multibeam interferometry image), it can be confirmed that the metal atoms are arranged in layers within the crystalline region. Therefore, it can also be said that an oxide semiconductor having a CAAC structure has layered crystalline regions.

[0443] The CAAC structure is formed, for example, with the c-axis perpendicular or substantially perpendicular to the surface or plane of the oxide semiconductor. In the CAAC structure, metal atoms are arranged in layers in a direction parallel or substantially parallel to the surface to be formed. In the region having the CAAC structure, the angle of the c-axis relative to the surface to be formed is preferably within 90° ± 20° (70° or more and 110° or less), more preferably within 90° ± 15° (75° or more and 105° or less), further preferably within 90° ± 10° (80° or more and 100° or less), and even more preferably within 90° ± 5° (85° or more and 95° or less).

[0444] When an oxide semiconductor has a CAAC structure, clusters of bright spots reflecting the layered arrangement of metal atoms (specifically, bright spots arranged in layers) are observed in the cross-section of the oxide semiconductor when viewed using TEM images. Specifically, the bright spots are observed to be arranged in layers parallel to or approximately parallel to the surface in which they are formed.

[0445] When performing electron diffraction on an oxide semiconductor with a CAAC structure, spots (bright spots) indicating c-axis orientation are observed in the electron diffraction pattern.

[0446] Furthermore, the FFT pattern obtained by processing the TEM image with Fast Fourier Transform (FFT) reflects the same reciprocal space information as the electron diffraction pattern.

[0447] A cross-sectional TEM image of an oxide semiconductor with a CAAC structure is obtained. An FFT pattern is formed by performing FFT processing on each region of the cross-sectional TEM image. The direction of the crystal axis of each region can be calculated based on the fabricated FFT pattern. Specifically, the direction of the line segment connecting two spots with high brightness and approximately equal distances from the center observed in the fabricated FFT pattern is the crystal axis direction. Regions where the angle of the crystal axis direction calculated from the FFT pattern relative to the formed surface is preferably 70° or more and 110° or less (within 90° ± 20°), more preferably 75° or more and 105° or less (within 90° ± 15°), more preferably 80° or more and 100° or less (within 90° ± 10°), and even more preferably 85° or more and 95° or less (within 90° ± 5°) can be considered as CAAC structures.

[0448] When an oxide semiconductor with a CAAC structure is observed using TEM images from a direction perpendicular to the formed surface, triangular or hexagonal atomic arrangements are observed on the ab surface, exhibiting crystallinity.

[0449] [Composition of the Metal Oxide] According to one aspect of the invention, the metal oxide preferably contains indium (In), and more preferably, has a high In content. By using a metal oxide with a high In content as an oxide semiconductor, the on-state current of the transistor can be increased, thereby improving the frequency characteristics. For example, indium oxide is preferably used as the oxide semiconductor.

[0450] Additionally, the metal oxide according to one aspect of the invention may contain zinc. When the metal oxide contains zinc, it is a highly crystalline metal oxide, for example, a metal oxide having a CAAC structure. For example, In-Zn oxides can be used as oxide semiconductors. Specifically, metal oxides having an In:Zn ratio of 1:1 or closer, an In:Zn ratio of 2:1 or closer, or an In:Zn ratio of 4:1 or closer can be used. Note that "closely related" includes a range of ±30% of the desired atomic ratio.

[0451] Furthermore, the metal oxide according to one embodiment of the present invention may contain element M. When the metal oxide contains element M, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the reliability of transistors using oxide semiconductors can be improved.

[0452] For example, In-Zn oxides containing trace amounts of element M can be used as oxide semiconductors. Specifically, metal oxides with an In:Ga:Zn ratio of 4:0.1:1 or similar, an In:Ga:Zn ratio of 2:0.1:1 or similar, or an In:Ga:Zn ratio of 1:0.1:1 or similar can be used. Furthermore, metal oxides with an In:Sn:Zn ratio of 4:0.1:1 or similar, an In:Sn:Zn ratio of 2:0.1:1 or similar, or an In:Sn:Zn ratio of 1:0.1:1 or similar can be used.

[0453] Furthermore, In-Zn oxides containing element M can be used as oxide semiconductors. Specifically, metal oxides with compositions having an In:M:Zn ratio of 1:1:1 or similar, an In:M:Zn ratio of 1:1:1.2 or similar, an In:M:Zn ratio of 1:1:0.5 or similar, an In:M:Zn ratio of 1:1:2 or similar, an In:M:Zn ratio of 4:2:3 or similar, an In:M:Zn ratio of 1:3:2 or similar, or an In:M:Zn ratio of 1:3:4 or similar can be used.

[0454] Note that when metal oxides are formed using sputtering, the composition of the resulting metal oxide sometimes differs from that of the sputtering target. In particular, the zinc content of the resulting metal oxide can sometimes be reduced to about 50% of the zinc content of the sputtering target.

[0455] Furthermore, when depositing metal oxides containing multiple metal elements, such as In-Ga-Zn oxides, using the ALD method, the cycle ratio of the precursors containing each metal element can be set according to the target composition. For example, when depositing In-Ga-Zn oxides with an In:Ga:Zn ratio of 1:3:2 (atomic number ratio), one cycle of depositing the In-containing precursor and treating with an oxidant can be performed, three cycles of depositing the Ga-containing precursor and treating with an oxidant can be performed, and two cycles of depositing the Zn-containing precursor and treating with an oxidant can be performed. Note that sometimes the cycle ratio of the precursors containing each metal element is not consistent with the atomic number ratio of each metal element in the deposited metal oxide.

[0456] Compositional analysis of metal oxides used in oxide semiconductors can be performed using methods such as EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, multiple methods can be combined. Note that the actual content of elements with low concentrations may differ from the analytically obtained content due to variations in analytical precision. For example, when the content of element M is low, the analytically obtained content of element M may sometimes be lower than the actual content.

[0457] The oxide semiconductor of one embodiment of the present invention may also have a stacked structure of two or more layers. When the oxide semiconductor has a two-layer structure of a first layer and a second layer on the first layer, the composition of the second layer is preferably different from that of the first layer. Furthermore, when the oxide semiconductor has a three-layer structure of a first layer, a second layer on the first layer, and a third layer on the second layer, the composition of the second layer is preferably different from that of the first and third layers. Alternatively, the composition of the first layer may be the same as that of the third layer. Or, the compositions of the first and third layers may be different from each other. Moreover, the first to third layers can be used in the oxide semiconductors 230a to 230c shown in Embodiment 1.

[0458] The first to third layers can each use the aforementioned metal oxides.

[0459] The second layer can be made of materials such as indium oxide, In-Zn oxide, or In-Zn oxide containing trace amounts of element M. By increasing the In content of the second layer, the on-state current can be increased and the frequency characteristics can be improved.

[0460] The conduction band bottoms of the first and third layers are preferably closer to the vacuum level than the conduction band bottom of the second layer. In other words, the energies of the conduction band bottoms of the first and third layers are preferably lower than the energies of the conduction band bottom of the second layer. In this case, the second layer is sandwiched between the first and third layers, with the conduction band bottoms closer to the vacuum level, and can be primarily used as a current path (channel).

[0461] When the second layer is sandwiched between the first and third layers, the number of carriers trapped at and near the interface of the second layer can be reduced. Additionally, the channel can be moved away from the surface of the gate insulating layer, reducing the effects of surface scattering. This allows for the realization of embedded-channel transistors with the channel away from the insulating layer interface, thereby improving field-effect mobility. Furthermore, the influence of the interface energy level that can be formed on the back channel side is reduced, suppressing transistor optical degradation (e.g., optical negative bias degradation), thus improving transistor reliability.

[0462] Based on the constituent elements and composition of the first, second, and third layers, the first and third layers, with their conduction band bottom closer to the vacuum level side compared to the second layer, sandwich the second layer. This structure allows for the embedding of a channel. In other words, this structure creates a path for more current to flow through the second layer. Therefore, it enables the increase of on-state current or the improvement of reliability.

[0463] When using the first to third layers to form the embedded channel, for example, metal oxides with a higher Ga content than the second layer can be used as the first and third layers. Specifically, for each of the first and third layers, a metal oxide with an In:Ga:Zn ratio of 1:1:1 or similar, an In:Ga:Zn ratio of 1:3:2 or similar, or an In:Ga:Zn ratio of 1:3:4 or similar can be used. Alternatively, Ga-Zn oxide or gallium oxide can be used. When the Ga content of the first and third layers is increased, sometimes the conduction band bottom of each of the first and third layers is closer to the vacuum level than the conduction band bottom of the second layer.

[0464] Furthermore, by increasing the Ga content in the first and third layers, the hydrogen barrier properties of the first and third layers can be improved. Therefore, hydrogen diffusion from below the first layer or above the third layer to the second layer can be suppressed. Additionally, by increasing the Ga content in the first and third layers, impurities such as hydrogen or water contained in the oxide semiconductor can be reduced by utilizing heat applied after the oxide semiconductor is formed.

[0465] Furthermore, by increasing the Ga content in the first and third layers, the oxygen barrier properties of the first and third layers can be improved. Therefore, the release of oxygen from the second layer forming the channel can be suppressed, thereby inhibiting the formation of oxygen vacancies in the second layer or the increase in the amount of oxygen vacancies in the second layer. This, in turn, improves the electrical characteristics of the transistor.

[0466] Furthermore, increasing the Ga content in the first layer can sometimes make the resistivity of the first layer higher than that of the second layer. When the first layer is placed on the back channel side, by using a layer with high resistivity as the first layer, negative shift of the threshold voltage or decrease in the on-state current can be suppressed. Therefore, the threshold voltage of the transistor shifts to the positive direction, thereby enabling the transistor to be normally off. This results in better electrical characteristics of the transistor and improved transistor reliability.

[0467] When evaluating the band gap of metal oxides, optical evaluation using a spectrophotometer, spectral ellipsometry, photoluminescence, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS) can be used. Furthermore, multiple methods can be combined for analysis. The electron affinity or conduction band bottom can be determined from the ionization potential and band gap, which is the energy difference between the vacuum level and the valence band top. For example, ultraviolet photoelectron spectroscopy (UPS) can be used to evaluate the ionization potential.

[0468] Alternatively, the first and third layers can also use metal oxides with a higher In content than the second layer. Furthermore, one of the first and third layers can respectively use a metal oxide with a higher In content than the second layer, and a metal oxide with a higher Ga content than the second layer.

[0469] Furthermore, the first, second, and third layers may each comprise a stack of multiple layers having the aforementioned composition. For example, the first layer may have a structure in which a metal oxide with a high Ga content is stacked on a metal oxide with a high Ga content. Similarly, the third layer may have a structure in which a metal oxide with a high Ga content is stacked on a metal oxide with a high In content.

[0470] [Manufacturing methods for oxide semiconductors] The oxide semiconductor of one aspect of the present invention can be formed by sputtering, CVD, vacuum evaporation, MBE, PLD or ALD.

[0471] Furthermore, an oxide semiconductor according to one aspect of the present invention can be manufactured by forming a metal oxide using two deposition methods. For example, an oxide semiconductor according to one aspect of the present invention can be manufactured by forming a metal oxide using a first deposition method and a second deposition method.

[0472] In one aspect of the present invention, the oxide semiconductor may have a two-layer structure comprising a first layer and a second layer thereon. When the oxide semiconductor has a two-layer structure, it can be manufactured by forming a first layer on the surface to be formed using a first deposition method, and then forming a second layer thereon using a second deposition method.

[0473] As the first deposition method, it is preferable to use a deposition method that causes less damage to the surface to be formed compared to the second deposition method. This suppresses the formation of a mixed layer at the interface between the oxide semiconductor and the layer formed on the surface of the oxide semiconductor. Furthermore, since the incorporation of impurities such as silicon into the second layer formed on the first layer can be suppressed, the crystallinity of the oxide semiconductor can sometimes be further improved.

[0474] Examples of primary deposition methods include ALD, CVD, and MBE. Furthermore, examples of CVD methods include Plasma Enhanced CVD (PECVD), thermal CVD, photochemical CVD, and MOCVD. MBE is a deposition method that grows thin films with a crystal structure reflecting the crystal system of the substrate; it is considered one of the deposition methods that causes minimal damage to the surface being formed. Additionally, wet deposition methods can be used as primary deposition methods. Wet deposition methods are among the deposition methods that cause minimal damage to the surface being formed. Examples of wet deposition methods include spray coating.

[0475] As a second deposition method, a method capable of depositing crystalline metal oxides is preferred. The deposited metal oxide in this case particularly preferably has a CAAC structure. Examples of second deposition methods include sputtering and PLD. Metal oxides deposited by sputtering tend to be crystalline, therefore sputtering is suitable as a second deposition method.

[0476] Furthermore, when a metal oxide is formed on the surface to be formed using a second deposition method, damage to the surface can sometimes lead to alloying between the components contained in the metal oxide and the components contained in the layer of the surface to be formed. When alloying occurs, a mixed layer may sometimes form at the interface between the metal oxide and the layer of the surface to be formed. This mixed layer can also be referred to as an alloyed region. Additionally, the formation of the mixed layer can also be described as alloying.

[0477] For example, when sputtering is used as a second deposition method, a mixed layer may sometimes form due to particles released from the target (also called sputtered particles) or energy supplied to the substrate side by the sputtered particles. Specifically, when a metal oxide is deposited using a silicon-containing insulating layer, such as a silicon oxide film, as the surface to be formed, there is a concern that silicon may be mixed into the metal oxide. When impurities such as silicon are mixed into the metal oxide, the crystallization of the metal oxide may be hindered. Furthermore, when using oxide semiconductors mixed with impurities in transistors, there are concerns that it may negatively affect the initial characteristics or reliability of the transistor. In addition, it is difficult to improve the crystallinity of the alloyed region when performing the heat treatment described later.

[0478] Therefore, as described above, by forming the metal oxide using the first deposition method before forming it using the second deposition method, the incorporation of impurities into the oxide semiconductor can be suppressed. Furthermore, alloying with the layer on the formed surface can be suppressed. Thus, the initial characteristics and reliability of the transistor can be improved. In addition, the crystallinity of the oxide semiconductor can be further improved.

[0479] Note that a hybrid layer is sometimes formed at the interface between the first and second layers. The hybrid layer contains the components of both the first and second layers. For example, if gallium oxide is used as the first layer and an indium-containing metal oxide is used as the second layer, the hybrid layer contains both gallium and indium. For instance, if the indium content of the second layer is higher than that of the first layer, the indium content of the hybrid layer is higher than that of the first layer and lower than that of the second layer.

[0480] Compared to sputtering, ALD (Alternating Deposition) can suppress damage to the surface being formed, making it suitable as a first deposition method. Furthermore, ALD offers higher coverage than sputtering; by using ALD as the first layer, the coverage of the oxide semiconductor can be improved. Therefore, oxide semiconductors can effectively cover high aspect ratio steps, openings, and other similar areas.

[0481] As the first layer, a metal oxide with a microcrystalline or amorphous structure, for example, is sometimes formed, exhibiting a lower crystallinity than the CAAC structure. The crystallinity of the first layer, with the second layer as its core, is sometimes improved by forming a second layer with higher crystallinity on top of the low-crystallinity first layer, or by performing heat treatment after forming the second layer. This can sometimes improve the overall crystallinity of the oxide semiconductor, including the area near the interface with the formed surface.

[0482] The layer to be formed can be, for example, an insulating film such as silicon oxide film, silicon oxynitride film, silicon nitride film, silicon oxynitride film, aluminum oxide film, or hafnium oxide film. Alternatively, depending on the transistor structure, the layer to be formed can be a conductive film such as titanium nitride film, tungsten film, or ITSO film. Furthermore, the layer to be formed may not be crystalline. In addition, if the layer is crystalline, it may have a crystal structure with low lattice matching to the metal oxide contained in the oxide semiconductor.

[0483] The first layer is preferably formed using the ALD method. Here, the method for forming In-M-Zn oxide as the first layer using the ALD method will be described.

[0484] First, a source gas containing an indium precursor is introduced into a reaction chamber (also called a processing chamber), causing the precursor to adsorb onto the surface to be formed. Next, an oxidant is introduced into the reaction chamber as a reactant, reacting with the adsorbed precursor. While the indium is adsorbed onto the substrate, components other than indium are desorbed, thereby forming a layer bonded to indium and oxygen.

[0485] Next, a source gas containing a precursor of element M is introduced into the reaction chamber, causing it to adsorb onto the layer formed by indium and oxygen bonding. Then, an oxidant is introduced into the reaction chamber as a reactant, reacting with the adsorbed precursor to desorb components other than element M while element M is adsorbed onto the substrate, thereby forming a layer formed by element M and oxygen bonding.

[0486] Next, a source gas containing a zinc precursor is introduced into the reaction chamber and adsorbed onto the layer formed by the bonding of element M and oxygen. Then, an oxidant is introduced into the reaction chamber as a reactant to react with the adsorbed precursor, thereby desorbing components other than zinc while zinc is adsorbed onto the substrate, thus forming a layer formed by the bonding of zinc and oxygen.

[0487] By repeating the above method, In-M-Zn oxide can be formed on the layer of the formed surface as an oxide semiconductor using the ALD method.

[0488] When forming oxide semiconductors using the ALD method, ozone (O3), oxygen (O2), water (H2O), etc., can be used as oxidants. By using ozone (O3) or oxygen (O2), which do not contain hydrogen, as oxidants, the amount of hydrogen mixed into the oxide semiconductor can be reduced.

[0489] In the above embodiments, preferably, after the precursor is adsorbed, the introduction of the source gas including the precursor is stopped, the reaction chamber is purged, and then the remaining precursor and reaction products are discharged from the reaction chamber. Alternatively, preferably, after the adsorbed precursor reacts with the oxidant, the introduction of the oxidant is stopped, the reaction chamber is purged, and then the remaining reactants and reaction products are discharged from the reaction chamber.

[0490] Furthermore, in the descriptions in this specification and other documents, unless otherwise specified, when ozone, oxygen, and water are used as reactants or oxidants, they also include plasma states, free radical states, and ionic states, and are not limited to gaseous states or molecular states.

[0491] The second layer is preferably formed using a sputtering method.

[0492] In-M-Zn oxides can be used as the target material for sputtering. For example, when forming metal oxides using sputtering, oxygen or a mixture of oxygen and rare gases can be used as the sputtering gas. Furthermore, by increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the deposited oxide film can be increased.

[0493] In addition, sometimes the higher the oxygen flow rate ratio relative to the overall deposit gas used during formation (hereinafter also referred to as the oxygen flow ratio), the more crystalline metal oxides can be formed.

[0494] When forming metal oxides using sputtering, oxygen-excess metal oxides can sometimes be formed by depositing under conditions where the proportion of oxygen contained in the sputtering gas is higher than 30% and lower than 100%, preferably higher than 70% and lower than 100%. Transistors using oxygen-excess metal oxides in the channel formation region can achieve higher reliability. Note that one aspect of the invention is not limited to this. Oxygen-deficient metal oxides can be formed by depositing under conditions where the proportion of oxygen contained in the sputtering gas is higher than 1% and lower than 30%, preferably higher than 5% and lower than 20%. Transistors using oxygen-deficient metal oxides in the channel formation region can have higher field-effect mobility.

[0495] When forming metal oxides using sputtering, it is preferable to heat the substrate. By increasing the substrate temperature (stage temperature) during metal oxide formation, highly crystalline metal oxides can sometimes be formed. When forming metal oxides using sputtering, the substrate heating temperature is preferably 100°C or higher and 400°C or lower, more preferably 200°C or higher and 300°C or lower.

[0496] By employing the above manufacturing method, the thickness of the mixed layer formed at the interface between the layer and the metal oxide on the formed surface can be reduced, or the alloyed region formed at the interface between the layer and the metal oxide on the formed surface can be thinned to an unobservable degree. For example, the thickness of the alloyed region can be 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0497] In addition, the thickness of the alloyed region can sometimes be calculated by performing a linear analysis of the composition of the region and its surroundings using SIMS or Energy Dispersive X-ray Spectroscopy (EDX).

[0498] For example, using the direction perpendicular to the surface to be formed of the first layer as the depth direction, EDX line analysis is performed on the alloyed region and its surroundings. Then, in the distribution of quantitative values ​​of each element relative to the depth direction obtained through this analysis, the depth (location) of the interface between the aforementioned region and the first layer is defined as the depth where the quantitative value of the metal that will be the main component of the first layer, but not the main component of the layer to be formed (In if the first layer contains In), reaches half its value. Similarly, the depth (location) of the interface between the aforementioned region and the layer to be formed is defined as the depth where the quantitative value of the element that will be the main component of the layer to be formed, but not the main component of the first layer (e.g., Si), reaches half its value. Through these steps, the thickness of the alloyed region can be calculated.

[0499] When observing the thickness of the alloyed region in the oxide semiconductor of one aspect of the present invention using EDX analysis, for example, its thickness is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0500] Additionally, for example, when performing SIMS analysis on an oxide semiconductor formed on a silicon oxide film on the formed surface, the interface is defined as the depth at which the silicon concentration reaches 50% of the maximum concentration of the silicon oxide film, and the interface is defined as the depth at which the silicon concentration decreases to 1.0 × 10⁻⁶. 21 atoms / cm 3 The optimal reduction is 5.0 × 10. 20 atoms / cm 3 More preferably, reduced to 1.0 × 10 20 atoms / cm 3 The distance between the depth and the interface is the thickness t. The thickness t is preferably less than 3 nm, and more preferably less than 2 nm.

[0501] By reducing the thickness of the alloyed region, the thickness t can be set to a value within the range mentioned above.

[0502] Furthermore, by reducing the alloying region, a CAAC structure can be formed near the surface to be formed. Here, "near the surface to be formed" refers, for example, to a region greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, and more preferably greater than 1 nm and less than 2 nm, in a direction substantially perpendicular to the surface to be formed of the oxide semiconductor.

[0503] Note that CAAC structures near the formed surface can sometimes be identified during TEM observation. For example, when observing a cross-section of an oxide semiconductor using high-resolution TEM, bright spots arranged in layers in a direction parallel to the formed surface can be identified near the formed surface.

[0504] In addition, one embodiment of the present invention, an oxide semiconductor, may have a three-layer structure consisting of a first layer, a second layer on the first layer, and a third layer on the second layer.

[0505] In the case of an oxide semiconductor having a three-layer structure, the oxide semiconductor can be manufactured by the following steps: after forming a first layer on the surface to be formed using a first deposition method, forming a second layer using a second deposition method, and forming a third layer using the first deposition method.

[0506] In the aforementioned oxide semiconductor, even if it is not easy to form a CAAC structure by forming a single layer when used as the first and third layers, since the crystal growth is generated with the second layer as the nucleus, the oxide semiconductor including the first and third layers can have a CAAC structure as a whole. Alternatively, the region including at least a portion of each of the first and third layers to the region including the second layer can have a CAAC structure.

[0507] In particular, compositions with high In content in the first and third layers can also possess suitable crystallinity for use as semiconductor layers in transistors. In an oxide semiconductor according to one aspect of the present invention, a highly crystalline CAAC structure can be used to improve reliability while increasing the In content to improve the transistor's turn-on characteristics.

[0508] Alternatively, the first and third layers can also use metal oxides with the same composition as the second layer. By using the same composition, it is sometimes easy to achieve CAAC formation after heat treatment.

[0509] Because the second layer has high crystallinity, the third layer can be grown using the crystals of the second layer as nuclei or seeds. Therefore, the third layer can be crystallized even without using a deposition method that easily imparts crystallinity as the deposition method for the third layer. Here, for example, by using a deposition method with higher coverage than the second layer to form the third layer, the oxide semiconductor can have both high crystallinity and high coverage throughout the layer.

[0510] Furthermore, by setting a first layer to reduce the influence of the formed surface, the crystallinity of the second layer is improved, resulting in extremely excellent crystallinity. Therefore, it is expected that an extremely crystallinity layer will also be formed in the third layer, which crystallizes with the second layer as the nucleus or seed.

[0511] Note that when oxide semiconductors are used as the semiconductor layer of a transistor, sometimes the third layer of the topmost oxide semiconductor layer is in contact with the gate insulating layer. By increasing the crystallinity of the layer in contact with the gate insulating layer, the carrier mobility of the transistor in the on state can be improved.

[0512] The crystallinity of the first and third layers is enhanced by using the highly crystalline second layer as a nucleus or seed. Specifically, the crystallinity of the first layer is sometimes enhanced by heat treatment during or after the deposition of the second or third layer. Similarly, the crystallinity of the third layer is sometimes enhanced by heat treatment during or after the deposition of the third layer. Furthermore, the aforementioned heat treatment plays an auxiliary role in enhancing crystallinity.

[0513] Thus, in one aspect of the oxide semiconductor manufacturing method of the present invention, the crystallinity of the metal oxides above and below it (here, the first and third layers) can be improved by using a second layer containing a highly crystalline metal oxide (i.e., CAAC) as a nucleus or seed. This improves the overall crystallinity of the oxide semiconductor. In other words, by using the second layer as a nucleus or seed and allowing the metal oxides above and below it to grow in a solid phase, a highly crystalline oxide semiconductor can be formed. The oxide semiconductor formed using the above deposition method, in this case, the CAAC film can be referred to as axially grown CAAC (AGCAAC).

[0514] In oxide semiconductors, regions with CAAC structures are preferably widely distributed throughout the entire layer. The CAAC-structured regions of the first layer are crystal-bonded with the CAAC-structured regions of the second layer. The CAAC-structured regions of the third layer are crystal-bonded with the CAAC-structured regions of the second layer. Therefore, sometimes the boundary between the first and second layers is not observable. Additionally, sometimes the boundary between the second and third layers is not observable. Sometimes it can be expressed as an oxide semiconductor being a single layer with no clearly observable interface. Sometimes it can be expressed as an oxide semiconductor being a monolayer.

[0515] In each of the first to third layers, for example, when cross-sectional observation is performed using a high-resolution TEM, bright spots arranged parallel to or substantially parallel to the surface being formed are identified in the region having the CAAC structure. Furthermore, the c-axis of the CAAC structure in each of the first to third layers is preferably parallel to or substantially parallel to the normal direction of the surface or plane of the oxide semiconductor being formed.

[0516] In addition, a portion of the first or third layer is sometimes not crystallized.

[0517] Alternatively, when the oxide semiconductor has a three-layer structure, the oxide semiconductor can also be manufactured by the following steps: after forming a first layer on the surface to be formed using a first deposition method, forming a second layer using a first deposition method, and forming a third layer using a second deposition method.

[0518] As described above, using metal oxides with high In content in transistors can improve the field-effect mobility of transistors. On the other hand, metal oxides with high In content tend to have a cubic crystal structure. Therefore, by using metal oxides with high In content in the second layer that is in contact with the third layer, a crystal reflecting the orientation of the crystal contained in the third layer can be formed.

[0519] Furthermore, the lattice mismatch between the crystals contained in the third layer and those contained in the second layer is preferably small. Therefore, crystals reflecting the orientation of the crystals contained in the third layer can be formed in the second layer. At this time, for example, when observing a cross-section of an oxide semiconductor using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the surface to which they are formed are observed in the second layer.

[0520] As long as the lattice mismatch between the crystals contained in the third layer and the crystals contained in the second layer is small, there are no particular restrictions on the crystal structure of the second layer. The crystal structure of the second layer can be cubic, tetragonal, orthorhombic, hexagonal, monoclinic, or trigonal.

[0521] In the above structure, typically, the first layer can be a metal oxide or gallium oxide layer containing an In:Ga:Zn ratio of 1:3:2 or similar; the second layer can be a metal oxide or indium oxide layer containing trace amounts of element M; and the third layer can be a metal oxide layer containing an In:Ga:Zn ratio of 1:1:1 or similar. In this case, the first layer contains gallium. Furthermore, when the first layer contains a metal oxide with an In:Ga:Zn ratio of 1:3:2 or similar, the indium content in the first layer is lower than the gallium content. Conversely, the indium content in the second layer is higher than that in the third layer.

[0522] When forming the first and second layers using the first deposition method, it is preferable to deposit the first and second layers continuously without exposure to the atmosphere. By continuously depositing the first and second layers without exposure to the atmosphere, productivity can be improved. Furthermore, impurities (typically moisture) introduced into and near the interface between the first and second layers can be reduced.

[0523] Alternatively, one or more of the first to third layers may be stacked to include multiple layers with different compositions. For example, the first layer may also be manufactured by the following steps: after forming a layer containing a metal oxide with a high Ga content using a first deposition method, forming a layer containing a metal oxide with an In content high...

Claims

1. A semiconductor device, comprising: First insulator; Oxide semiconductor on the first insulator; The first and second conductors on the oxide semiconductor are separated from each other; A second insulator disposed on the first conductor and the second conductor and having an opening that overlaps the region between the first conductor and the second conductor; A third insulator disposed within the opening and in contact with the top surface of the oxide semiconductor, the side surface of the first conductor, the side surface of the second conductor, and the side surface of the second insulator; as well as A third conductor is disposed within the opening on the third insulator and has a region that overlaps with the oxide semiconductor across the third insulator. The oxide semiconductor contains indium. The first insulator comprises a silicon oxide film. Furthermore, the silicon oxide film contains nitrogen dioxide.

2. The semiconductor device according to claim 1, The nitrogen dioxide thereon is not bonded to the silicon dioxide contained in the silicon oxide film.

3. The semiconductor device according to claim 1, One of the migration energy levels of nitrogen dioxide in the first insulator is above the valence band top and below the conduction band bottom of the oxide semiconductor.

4. The semiconductor device according to any one of claims 1 to 3, The oxide semiconductor includes a first layer and a second layer on the first layer. The first layer contains indium. The second layer contains indium, gallium, zinc, and oxygen. Furthermore, the indium content in the first layer is higher than that in the second layer.

5. The semiconductor device according to claim 4, The second layer is divided into a third layer located under the first conductor and a fourth layer located under the second conductor.

6. The semiconductor device according to claim 5, The side of the third conductor in the third layer is configured to be recessed from the side of the third conductor in the first conductor. Furthermore, the side of the third conductor of the fourth layer is arranged in a manner that is set back from the side of the third conductor of the second conductor.

7. The semiconductor device according to claim 5, The third insulator has a stacked structure. Furthermore, the layer of the third insulator in contact with the oxide semiconductor contains hafnium oxide.

8. The semiconductor device according to claim 4, An oxide layer is included between the oxide semiconductor and the first insulator. Furthermore, the oxide layer contains yttrium, zirconium, and oxygen.

9. A semiconductor device, comprising: First insulator; Oxide semiconductor on the first insulator; The first and second conductors on the oxide semiconductor are separated from each other; A second insulator disposed on the first conductor and the second conductor and having an opening that overlaps the region between the first conductor and the second conductor; A third insulator disposed within the opening and in contact with the top surface of the oxide semiconductor, the side surface of the first conductor, and the side surface of the second conductor; A fourth insulator is disposed within the opening between the second insulator and the third insulator; as well as A third conductor is disposed within the opening on the third insulator and has a region that overlaps with the oxide semiconductor across the third insulator. The oxide semiconductor contains indium. The first insulator comprises a silicon oxide film. The silicon oxide film contains nitrogen dioxide. The first conductor and the second conductor each include a first conductive layer and a second conductive layer on the first conductive layer. The shortest distance between the first conductive layer of the first conductor and the first conductive layer of the second conductor is less than the shortest distance between the second conductive layers of the first conductor and the second conductive layers of the second conductor. Furthermore, the fourth insulator is in contact with the top surface of the first conductive layer of the first conductor, the side surface of the second conductive layer of the first conductor, the top surface of the first conductive layer of the second conductor, and the side surface of the second conductive layer of the second conductor.

10. The semiconductor device according to claim 9, The nitrogen dioxide thereon is not bonded to the silicon dioxide contained in the silicon oxide film.

11. The semiconductor device according to claim 9, One of the migration energy levels of nitrogen dioxide in the first insulator is above the valence band top and below the conduction band bottom of the oxide semiconductor.

12. The semiconductor device according to any one of claims 9 to 11, The oxide semiconductor includes a first layer and a second layer on the first layer. The first layer contains indium. The second layer contains indium, gallium, zinc, and oxygen. Furthermore, the indium content in the first layer is higher than that in the second layer.

13. The semiconductor device according to claim 12, The second layer is divided into a third layer located under the first conductive layer of the first conductor and a fourth layer located under the first conductive layer of the second conductor.

14. The semiconductor device according to claim 13, The side of the third conductor in the third layer is configured to be recessed from the side of the first conductive layer of the first conductor. Furthermore, the side of the third conductor of the fourth layer is arranged in a manner that is recessed from the side of the third conductor of the first conductive layer of the second conductor.

15. The semiconductor device according to claim 13, The third insulator has a stacked structure. Furthermore, the layer in the third insulator that contacts the oxide semiconductor contains hafnium oxide.

16. The semiconductor device according to claim 12, An oxide layer is included between the oxide semiconductor and the first insulator. Furthermore, the oxide layer contains yttrium, zirconium, and oxygen.

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