Complementary field effect transistor source-drain isolation

Abstract

A method for isolating source-drains of a complementary field effect transistor (CFET) stack incorporates a bottom-up fill process to form an isolation layer between vertical structures. The method can include forming an opening to expose a material of a bottom stack of a CFET structure, the CFET structure including a top stack vertically positioned above the bottom stack, where an aspect ratio of a width to a depth of the opening is about 15 or greater. A source-drain isolation (SDI) layer is then formed on the material of the bottom stack of the CFET structure using a bottom-up fill process, the process including depositing a SDI material and etching the SDI material to enable formation of the SDI layer. The SDI layer is positioned to electrically isolate source-drains of the bottom stack from source-drains of the top stack.

Description

Technical Field

[0001] The implementation of this principle generally involves semiconductor processing of semiconductor substrates. Background Technology

[0002] Complementary metal-oxide-semiconductor (CMOS) transistors are constantly being developed or “scaled” to deliver higher performance in smaller packages. Planar CMOS transistors have given way to FinFETs, which have been replaced by gate-all-around (GAA) transistors. GAA transistors can comprise stacks of PMOS and NMOS transistors. However, the side-by-side configuration of GAA transistors occupies valuable area on the device. To reduce the area of ​​GAA transistors, monolithically integrated complementary field-effect transistors (CFETs) are being considered. Monolithically integrated CFETs can have NMOS transistor stacks positioned above PMOS transistor stacks, or PMOS transistor stacks positioned above NMOS transistor stacks. The vertical stacking of monolithically integrated CFETs substantially reduces the transistor area. However, the inventors have observed that the practical fabrication of monolithically integrated CFETs presents processing challenges due to the very high aspect ratio of the vertical stack.

[0003] Therefore, the inventors provided an improved CFET manufacturing method. Summary of the Invention

[0004] This article provides a method for isolating the source and drain of a CFET structure.

[0005] In some embodiments, a method for isolating the source-drain of a complementary field-effect transistor (CFET) structure may include: forming an opening for access to a bottom stack of the CFET structure, the CFET structure further including a top stack vertically positioned above the bottom stack, wherein the aspect ratio of the width to depth of the opening is about 15 or greater, and forming a source-drain isolation (SDI) layer on the material of the bottom stack of the CFET structure using a bottom-up fill process, the process including depositing SDI material and etching SDI material to achieve the formation of the SDI layer, wherein the SDI layer is positioned to electrically isolate the source-drain of the bottom stack from the source-drain of the top stack.

[0006] In some embodiments, the method may further include: the bottom stack of the CFET structure being a metal contact material or a dummy contact material, and wherein the SDI layer is formed on the metal contact material or the dummy contact material; the bottom stack being a P-type metal-oxide-semiconductor (MOS) stack and the top stack being an N-type MOS stack, or wherein the bottom stack being an N-type MOS stack and the top stack being a P-type MOS stack; the SDI layer being formed in situ in a chamber for performing SDI material deposition and etching; the SDI layer being formed using plasma-enhanced chemical vapor deposition (PECVD) or plasma-enhanced atomic layer deposition (PEALD); the SDI layer being formed of silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, or aluminum oxide; a second source-drain electrode being formed on the top stack using epitaxial deposition; the thickness variation rate of the SDI layer being approximately 10% of the target thickness of the SDI layer; the aperture depth being approximately 400 nm; and the thickness of the SDI layer being approximately 5 nm to approximately 50 nm. nm; Etching of SDI material includes etching deposited material from the sidewalls of the opening using chlorine-based or fluorine-based gases; The number of cycles for depositing and etching SDI material is adjusted based on the aspect ratio of the opening; and / or multiple cycles for depositing SDI material are performed before performing multiple cycles for etching SDI material.

[0007] In some embodiments, a method for isolating the source-drain of a complementary field-effect transistor (CFET) structure may include: forming an opening for access to a first source-drain of a bottom stack of the CFET structure, the CFET structure further including a top stack vertically positioned above the bottom stack, wherein the aspect ratio of the width to depth of the opening is about 15 or greater; forming a metal contact layer or dummy contact layer on the first source-drain of the bottom stack of the CFET structure; and forming a source-drain isolation (SDI) layer on the metal contact layer or dummy contact layer using a bottom-up fill process, the process including depositing SDI material and etching SDI material to achieve the formation of the SDI layer, wherein the SDI layer electrically isolates the source-drain of the bottom stack from the source-drain of the top stack, wherein the SDI layer is formed using a plasma-enhanced chemical vapor deposition (PECVD) process or a plasma-enhanced atomic layer deposition (PEALD) process, and wherein the formation of the SDI layer is performed in situ in a chamber where the deposition and etching of the SDI material are performed.

[0008] In some embodiments, the method further includes: a bottom stack being a P-type metal-oxide-semiconductor (MOS) stack and a top stack being an N-type MOS stack, or wherein the bottom stack is an N-type MOS stack and the top stack is a P-type MOS stack; the SDI layer is formed of silicon dioxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or aluminum oxide; a second source-drain electrode of the top stack is formed on the SDI layer using epitaxial deposition; the thickness variation rate of the SDI layer is approximately 10% of the target thickness of the SDI layer; and / or the thickness of the SDI layer is approximately 5 nm to approximately 50 nm.

[0009] In some embodiments, a non-transitory computer-readable medium storing instructions that, when executed, cause to perform a method for isolating the source-drain of a complementary field-effect transistor (CFET) structure, the method comprising: forming an opening for access to a bottom stack of the CFET structure, the CFET structure further comprising a top stack vertically positioned above the bottom stack, wherein the aspect ratio of the width to depth of the opening is about 15 or greater, and forming a source-drain isolation (SDI) layer on the material of the bottom stack of the CFET structure using a bottom-up fill process, the process comprising depositing SDI material and etching SDI material to achieve the formation of the SDI layer, wherein the SDI layer is positioned to electrically isolate the source-drain of the bottom stack from the source-drain of the top stack.

[0010] Other and further implementation methods are disclosed below. Attached Figure Description

[0011] The embodiments of this principle, which have been briefly summarized above and discussed in more detail below, can be understood by referring to the illustrative embodiments of this principle depicted in the accompanying drawings. However, the drawings only illustrate common embodiments of this principle and should therefore not be considered as limiting the scope, as other equally effective embodiments of this principle are permissible.

[0012] Figure 1 Based on some implementations of this principle, a simplified cross-sectional view of a complementary field-effect transistor (CFET) is depicted.

[0013] Figure 2 According to some implementations of this principle, a method for forming a source-drain isolation (SDI) layer for a CFET is described.

[0014] Figure 3 According to some embodiments of this principle, equidistant cross-sectional views of the formed CFET structure are depicted.

[0015] Figure 4 According to some embodiments of this principle, isometric cross-sectional views are depicted of openings formed for exposing the material of the bottom stack of the CFET structure.

[0016] Figure 5 According to some embodiments of this principle, isometric cross-sectional views are depicted of optional metal or dummy contacts formed on the source-drain stack at the bottom of a CFET structure.

[0017] Figure 6 According to some embodiments of this principle, isometric cross-sectional views of an SDI layer formed on a material stacked at the bottom of a CFET structure are depicted.

[0018] Figure 7 According to some embodiments of this principle, an equidistant cross-sectional view of the top stacked source-drain electrodes of a CFET structure formed on an SDI layer is depicted.

[0019] For ease of understanding, the same reference numerals are used as much as possible to indicate common elements in the figures. The figures are not drawn to scale and have been simplified for clarity. Elements and features of one embodiment may be beneficially incorporated into other embodiments without further detail. Detailed Implementation

[0020] This method provides an improved process for forming source-drain isolation layers in vertical stacks of complementary field-effect transistor (CFET) structures. This principle achieves device isolation through source-drain contact formation, thereby substantially improving process tolerance to meet the stringent requirements of fabricating vertical CFET structures. The technique overcomes the shortcomings of conventional gap-filling and etch-back processes when used in high aspect ratio structures, allowing for the efficient fabrication of CFETs with tight tolerances. This technique significantly reduces the rate of change in isolation layer thickness, the number of processes required to form the isolation layer, and the cost of isolation layer formation.

[0021] The CFET structure is a recently developed architecture in which NP elements are vertically separated, rather than horizontally separated as in a gate-all-around (GAA) device. To achieve the vertical stacking of GAA devices, methods for isolating the elements are required at several points in the processing. Specifically, a processing sequence is used to isolate the source-drain trench contacts of the bottom elements (e.g., PMOS or NMOS stacks) and the top elements (e.g., NMOS or PMOS stacks). For quasi-planar GAA structures, the bottom and top elements of the CFET structure are placed laterally and thus lithographically separated and isolated. However, due to the vertical stacking of the CFET structure, CFETs require a processing sequence for isolation formation compatible with high aspect ratios. Conventional processing uses full gap filling to form the isolation material, followed by planarization using chemical mechanical polishing (CMP) and recessing using etch-back processing to significantly thin the gap fill and form the isolation. However, the inventors found that conventional GAA processing cannot achieve tight tolerances in isolation layer thickness because most of the gap fill is removed due to the high aspect ratio (HAR) characteristics of vertical stacking.

[0022] This method achieves source-drain contact device isolation, providing substantial improvements in processing tolerance and cost savings to meet the requirements of CFET structures. An NP device isolation (referred to herein as source-drain isolation (SDI)) is formed on the bottom element's source-drain contact, exposing the top element for source-drain epitaxy. Since the total bottom-up deposition height is a fraction of the total gate height already achieved using gap-filling methods, the proposed processing tolerance is substantially improved compared to conventional methods. Therefore, the total processing tolerance is only a fraction of that of conventional methods using gap-filling. To achieve this improved performance, in short, this method employs a bottom-up deposition process where the dielectric material of the SDI layer is deposited in situ within a single chamber using a deposition-etch-deposition process.

[0023] Figure 1A simplified cross-sectional view depicting a single CFET structure 100 is shown. The CFET structure 100 with a gate 108 is formed on a working substrate 106 or similar to isolate the CFET structure 100 from other structures. The bottom stack 102 includes nanosheets with channels 110 and source-drain electrodes 114. In some embodiments, the bottom stack 102 may form a P-type CMOS structure. In some embodiments, the bottom stack 102 may form an N-type CMOS structure. The top stack 104 includes nanosheets with channels 112 and source-drain electrodes 116. In some embodiments, the top stack 104 may form an N-type CMOS structure. In some embodiments, the top stack 104 may form a P-type CMOS structure. During fabrication, multiple CFET structures may be formed adjacent to each other to produce a monolithically integrated CFET having more than one CFET structure 100. As part of the fabrication process, the source-drain electrodes 114 of the bottom stack 102 may be connected together to form a unified bottom stack source-drain electrode 120. Similarly, the source-drain 116 of the top stack 104 can be connected together to form a unified top stack source-drain 122. Since the CFET structure 100 is a vertical structure, the unified top stack source-drain 122 is built directly above the unified bottom stack source-drain 120. To electrically isolate the unified bottom stack source-drain 120 and the unified top stack source-drain 122, an isolation layer or source-drain isolation (SDI) layer 118 is formed therebetween. The vertical nature of the CFET structure 100 presents manufacturing challenges that must be overcome to successfully form the CFET structure 100. As discussed below, this method provides technical solutions to these manufacturing challenges, such as, but not limited to, high aspect ratio handling when forming the SDI layer, while achieving tight handling tolerances.

[0024] Figure 2 It is used for isolation, such as Figure 3 The source-drain method 200 of the CFET structure 302 depicted in view 300. Reference will also be made to method 200 in the discussion of method 200. Figures 4 to 7Additional isometric cross-sectional views are provided. The examples used in the depiction of method 200 are not intended to limit the formation technique of the source-drain isolation (SDI) layer. For simplicity, in some embodiments, examples include a bottom stack material (such as a metal or dummy contact layer) on which the SDI layer is formed. However, the SDI layer can be formed on any material of the bottom stack at the bottom of the opening. View 300 depicts a portion of a plurality of CFET structures 308 formed on a substrate 310. The CFET structure 302 includes a bottom stack 304 and a top stack 306. The bottom stack 304 and the top stack 306 have nanosheets 314 and dummy gates 312 formed in a previous process. In the example (but not limited to), a first source-drain 316 and an interlayer dielectric filler 318 of the bottom stack 304 have also been formed in a previous process. In block 202 of method 200, an opening 402 is formed (e.g., a portion of the interlayer dielectric filler 318 is removed; dashed box 420 indicates the dimensional boundary of an exemplary opening) to access a portion 404 of the material of the bottom stack 304, such as, for example, Figure 4 View 400 depicts the first source-drain 316 of the bottom stack 304 of the CFET structure 302. In some embodiments, the material entering and exiting may be a previously formed layer of the bottom stack 304, such as contacts and the like. In some embodiments, the height (or depth, for example, see...) of the opening 402... Figure 5 The height of 504 can be approximately 400 nm.

[0025] In optional box 204, such as Figure 5 As depicted in view 500, a metal or dummy contact layer 502 or other material layer of the bottom stack 304 may be formed on the first source-drain 316. In some embodiments, the metal or dummy contact layer 502 may be formed prior, and the metal or dummy contact layer 502 will be the material of the bottom stack, on which an SDI layer is formed. The dummy contact layer is a placeholder or sacrificial layer that may be removed in a later stage of processing and replaced with other materials to form the metal contact layer and the like. Since the material of the bottom stack 304 on which the SDI layer will be formed may be formed prior, forming contacts and the like is not necessary for method 200 and is therefore optional. The height 504 of the opening 402 is much greater than the width 506 of the opening 402. In some embodiments, method 200 may be used for a high aspect ratio (height to width) greater than about 15. In some embodiments, method 200 may be used for an aspect ratio of about 20 to about 30.

[0026] In box 206, the material stacked at the bottom (such as, for example, ...) Figure 6A source-drain isolation (SDI) layer 602 is formed on the metal or dummy contact layer 502 depicted in view 600. In some embodiments, the thickness 604 or height of the SDI layer 602 can be from about 5 nm to about 50 nm. The SDI layer 602 is located in the CFET structure and is used to connect the first source-drain 316 of the bottom stack 304 with the second source-drain 702 of the top stack 306 (see [reference]). Figure 7 Electrical isolation. The SDI layer 602 can be formed in situ in a single chamber where SDI material deposition and etching are performed. In some embodiments, the SDI layer 602 can be formed of silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, and / or aluminum oxide, and / or other oxide and nitride materials and the like. Compared to conventional processes that attempt to form an SDI layer using gap filling, CMP, and etch-back processes, method 200 offers the advantage of a shorter SDI layer formation process. Regardless of the introduced structural variations, this method can achieve the target SDI layer height, thereby maintaining isolation between the top and bottom stacks of the CFET structure.

[0027] In some embodiments, the bottom-up fill process includes depositing and etching SDI material to form the SDI layer 602. The deposition portion of the bottom-up fill process can be performed using plasma-enhanced chemical vapor deposition (PECVD) and / or plasma-enhanced atomic layer deposition (PEALD). PECVD deposition is preferred because the deposition rate is higher than PEALD deposition. However, PECVD deposition can result in overhangs at the opening 402, requiring periodic etching to prevent closure of the opening 402. The PEALD deposition process and cycle number can be adjusted to avoid overhangs at the opening 402. The etching portion of the bottom-up fill process can use chlorine-based and / or fluorine-based gases to etch the deposited SDI material from the opening 402's opening and sidewalls, while retaining the deposits at the bottom of the opening 402, which form the SDI layer 602. The etching process is an anisotropic etching process used to remove the deposits (overhangs) at the opening 402's opening, which can cause blockage of the deposition process at the bottom of the opening 402. In some embodiments, deposition and etching processes can be performed alternately for a given number of cycles to complete the formation of the SDI layer 602. In some embodiments, multiple deposition cycles can be performed before one or more etching cycles, and the entire deposition / etching cycle can be repeated to complete the formation of the SDI layer 602. In some embodiments, the total number of cycles and the number of cycles for each deposition and etching process can be adjusted based on the aspect ratio of the opening 402.

[0028] By employing a bottom-up fill process, the thickness or height variation of the SDI layer 602 can be less than approximately 10% of the target thickness of the SDI layer 602. The tolerance for conventional gap-fill and etch-back processes is a percentage of the total depth (height) of the exposed material in the bottom stack, such as (but not limited to) metal or dummy contact layers (in some cases, approximately 400 nm) from the top of the gate. Furthermore, conventional processes consist of gap-fill steps and recess or etch-back steps, both of which have processing variations. For example, a nominal SDI layer height variation of 10% of 400 nm = 40 nm is greater than the final target SDI layer thickness. In contrast, the tolerance for bottom-up fill in this method is a percentage of the target SDI layer thickness, approximately 5 nm or less. The nominal SDI layer height variation in this method is 10% of 5 nm = 0.05 nm, which is within the expected tolerance for the SDI layer thickness. Furthermore, assuming a 10% change in the nominal processing target, the expected change in conventional processing is four times the total height of the SDI layer. This is because almost the entire gap filler in the opening must be removed to form the SDI layer, resulting in a much larger tolerance error compared to our method. Therefore, our method significantly reduces the rate of change, processing volume, and cost.

[0029] In box 208, as Figure 7 As depicted in view 700, a second source-drain 702 of the top stack 306 of the CFET structure 302 is formed on the SDI layer 602. The second source-drain 702 can be formed using an epitaxial deposition process. The SDI layer 602 provides electrical isolation between the first source-drain 316 of the bottom stack 304 of the CFET structure 302 and the top stack 306, while confining the epitaxial growth to the top stack source-drain.

[0030] Implementations based on this principle can be carried out in hardware, firmware, software, or any combination thereof. Implementations can also be carried out using instructions stored on one or more computer-readable media, which can be read and executed by one or more processors. Computer-readable media can include any mechanism for storing or transferring information in a machine-readable form (e.g., a computing platform or a “virtual machine” running on one or more computing platforms). For example, computer-readable media can include any suitable form of volatile or non-volatile memory. In some implementations, computer-readable media can include non-transitory computer-readable media.

[0031] Although the foregoing describes an implementation of this principle, other and further implementations of this principle can be designed without departing from its basic scope.

Claims

1. A method for isolating the source and drain of a complementary field-effect transistor (CFET) structure, the method comprising: An opening is formed for access to and from a bottom stack of a CFET structure, the CFET structure further comprising a top stack vertically positioned on the bottom stack; and A source-drain isolation (SDI) layer is formed on the bottom stack of material of the CFET structure using a bottom-up fill process, the process including depositing SDI material and etching the SDI material to achieve the formation of the SDI layer, wherein the SDI layer is positioned to electrically isolate the source-drain of the bottom stack from the source-drain of the top stack.

2. The method of claim 1, wherein the material of the bottom stack of the CFET structure is a metal contact material or a virtual contact material, and wherein the SDI layer is formed on the metal contact material or the virtual contact material.

3. The method of claim 1, wherein the bottom stack is a P-type metal-oxide-semiconductor (MOS) stack and the top stack is an N-type MOS stack, or wherein the bottom stack is an N-type MOS stack and the top stack is a P-type MOS stack.

4. The method of claim 1, wherein the formation of the SDI layer is performed in situ within a chamber where the deposition and etching of the SDI material are carried out.

5. The method of claim 1, wherein the SDI layer is formed using plasma-enhanced chemical vapor deposition (PECVD) or plasma-enhanced atomic layer deposition (PEALD).

6. The method of claim 1, wherein the SDI layer is formed of silicon dioxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or aluminum oxide.

7. The method of claim 1, wherein an epitaxial deposition process is used to form the second source-drain electrode of the top stack on the SDI layer.

8. The method of claim 1, wherein the thickness variation rate of the SDI layer is approximately 10% of the target thickness of the SDI layer.

9. The method of claim 1, wherein the depth of the opening is approximately 400 nm.

10. The method of claim 1, wherein the thickness of the SDI layer is from about 5 nm to about 50 nm.

11. The method of claim 1, wherein the etching of the SDI material comprises etching deposited material from the sidewall of the opening using a chlorine-based gas or a fluorine-based gas.

12. The method of claim 1, wherein the number of cycles of depositing SDI material and etching SDI material is adjusted based on the aspect ratio of the opening.

13. The method of claim 1, wherein multiple cycles of depositing SDI material are performed prior to performing multiple cycles of etching SDI material.

14. A method for isolating the source and drain of a complementary field-effect transistor (CFET) structure, the method comprising: An opening is formed to allow access to and from the first source-drain of the bottom stack of the CFET structure, which also includes a top stack positioned vertically above the bottom stack; A metal contact layer or a virtual contact layer is formed on the first source-drain electrode stacked at the bottom of the CFET structure; and A source-drain isolation (SDI) layer is formed on the metal contact layer or the virtual contact layer using a bottom-up filling process. The process includes depositing an SDI material and etching the SDI material to achieve the formation of the SDI layer, wherein the SDI layer electrically isolates the bottom stacked source-drain from the top stacked source-drain. The SDI layer is formed using plasma-enhanced chemical vapor deposition (PECVD) or plasma-enhanced atomic layer deposition (PEALD) processes, and wherein the formation of the SDI layer is performed in situ in a chamber where the deposition and etching of the SDI material are performed.

15. The method of claim 14, wherein the bottom stack is a P-type metal-oxide-semiconductor (MOS) stack and the top stack is an N-type MOS stack, or wherein the bottom stack is an N-type MOS stack and the top stack is a P-type MOS stack.

16. The method of claim 14, wherein the SDI layer is formed of a silicon dioxide material, a silicon nitride material, silicon oxynitride, silicon oxycarbide, or aluminum oxide.

17. The method of claim 14, wherein an epitaxial deposition process is used to form the second source-drain electrode of the top stack on the SDI layer.

18. The method of claim 14, wherein the thickness variation rate of the SDI layer is approximately 10% of the target thickness of the SDI layer.

19. The method of claim 14, wherein the thickness of the SDI layer is from about 5 nm to about 50 nm.

20. A non-transitory computer-readable medium storing instructions thereon, which, when executed, cause to perform a method for isolating the source-drain of a complementary field-effect transistor (CFET) structure, the method comprising: An opening is formed for access to and from a bottom stack of a CFET structure, the CFET structure further comprising a top stack vertically positioned above the bottom stack; and A source-drain isolation (SDI) layer is formed on the bottom stack of material of the CFET structure using a bottom-up fill process, the process including depositing SDI material and etching the SDI material to achieve the formation of the SDI layer, wherein the SDI layer is positioned to electrically isolate the source-drain of the bottom stack from the source-drain of the top stack.

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