Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes: a substrate; a signal line layer located on the substrate and including a plurality of signal lines; a planarization layer located on a side of the signal line layer away from the substrate; a passivation layer located on a side of the planarization layer away from the substrate; an anode layer located on a side of the passivation layer away from the substrate; a pixel defining layer located on a side of the anode layer away from the substrate; a plurality of recesses extending through the pixel defining layer; a plurality of first recesses extending into the planarization layer; and a plurality of second recesses extending into the passivation layer.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] Display technologies have made significant progress to meet the increasing demands for high resolution, power efficiency, and enhanced image quality in various applications, including smartphones, tablets, wearable devices, and large displays. Among these technologies, organic light-emitting diode (OLED) displays are widely used due to their self-emissive properties, high contrast, and wide color gamut. Summary of the Invention

[0003] In one aspect, this disclosure provides an array substrate comprising: a substrate; a signal line layer located on the substrate and including a plurality of signal lines; a planarization layer located on a side of the signal line layer away from the substrate; a passivation layer located on a side of the planarization layer away from the substrate; an anode layer located on a side of the passivation layer away from the substrate; a pixel defining layer located on a side of the anode layer away from the substrate; a plurality of recesses extending through the pixel defining layer; a plurality of first recesses extending into the planarization layer; and a plurality of second recesses extending into the passivation layer.

[0004] Optionally, the orthographic projection of each of the plurality of grooves on the substrate at least partially overlaps with the orthographic projection of the corresponding first recess of the plurality of first recesses on the substrate; and at least partially overlaps with the orthographic projection of the corresponding second recess of the plurality of second recesses on the substrate.

[0005] Optionally, two of the plurality of first recesses partially surround the sub-pixel opening on opposite sides; two of the plurality of second recesses partially surround the sub-pixel opening on opposite sides; and two of the plurality of grooves partially surround the sub-pixel opening on opposite sides.

[0006] Optionally, the array substrate includes a plurality of pixels; wherein each of the plurality of pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; the sub-pixels of the array substrate are arranged in a plurality of first columns and a plurality of second columns; the plurality of first columns and the plurality of second columns are arranged alternately; the first sub-pixel and the second sub-pixel are located in the first column of the plurality of first columns; and the third sub-pixel is located in the second column of the plurality of second columns.

[0007] Optionally, the plurality of first recesses, the plurality of second recesses, and the plurality of grooves exist in the plurality of first columns but not in the plurality of second columns.

[0008] Optionally, the second passivation layer includes a plurality of first strips and a plurality of second strips; the plurality of first strips are respectively located in a plurality of first columns; and the plurality of second strips are respectively located in a plurality of second columns.

[0009] Optionally, the anode layer includes a plurality of anodes arranged in a plurality of first columns and a plurality of second columns; the orthographic projection of a corresponding first strip among the plurality of first strips on the substrate at least partially overlaps with the orthographic projection of the anode in the corresponding first column among the plurality of first columns; and the orthographic projection of a corresponding second strip among the plurality of second strips on the substrate at least partially overlaps with the orthographic projection of the anode in the corresponding second column among the plurality of second columns.

[0010] Optionally, the array substrate includes a plurality of pixels; wherein each of the plurality of pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; each pixel includes a first anode in the first sub-pixel, a second anode in the second sub-pixel, and a third anode in the third sub-pixel; the orthographic projection of a corresponding first strip in the plurality of first strips on the substrate at least partially overlaps with the orthographic projection of the first anode and the second anode in the corresponding first column in the plurality of first columns; and the orthographic projection of a corresponding second strip in the plurality of second strips on the substrate at least partially overlaps with the orthographic projection of the third anode in the corresponding second column in the plurality of second columns.

[0011] Optionally, the plurality of second recesses are present in the plurality of first strips but not in the plurality of second strips.

[0012] Optionally, two of the plurality of first recesses partially surround two of the plurality of second recesses.

[0013] Optionally, the orthographic projection of a corresponding groove in the plurality of grooves on the substrate covers the orthographic projection of a corresponding first recess in the plurality of first recesses on the substrate; and covers the orthographic projection of a corresponding second recess in the plurality of second recesses on the substrate; and the orthographic projections of the corresponding first recesses on the substrate and the corresponding second recesses on the substrate do not overlap.

[0014] Optionally, two of the plurality of grooves partially surrounding the sub-pixel opening have a partially annular shape; two of the plurality of first recesses partially surrounding the sub-pixel opening have a partially annular shape; and two of the plurality of second recesses partially surrounding the sub-pixel opening have a partially annular shape.

[0015] Optionally, the plurality of first strips and the plurality of second strips are arranged along a first direction; the plurality of first strips and the plurality of second strips extend along a second direction; two of the plurality of grooves that partially surround the sub-pixel opening are arranged along the first direction; two of the plurality of first recesses that partially surround the sub-pixel opening are arranged along the first direction; and two of the plurality of second recesses that partially surround the sub-pixel opening are arranged along the first direction.

[0016] Optionally, the array substrate includes a plurality of pixels; wherein each of the plurality of pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; the sub-pixels of the array substrate are arranged in a plurality of first columns and a plurality of second columns; the plurality of first columns and the plurality of second columns are arranged alternately; the first sub-pixel and the second sub-pixel are located in the first column of the plurality of first columns; and the third sub-pixel is located in the second column of the plurality of second columns; wherein the plurality of first strips and the plurality of second strips are arranged along a first direction; the plurality of first strips and the plurality of second strips extend along a second direction; two grooves in the plurality of grooves that partially surround the sub-pixel opening of the first sub-pixel are arranged along the first direction; two grooves in the plurality of grooves that partially surround the sub-pixel opening of the second sub-pixel are arranged along a third direction; and the third direction is different from the first direction and different from the second direction.

[0017] Optionally, the orthographic projection of at least two of the plurality of recesses partially surrounding the sub-pixel opening of the second sub-pixel on the substrate at least partially overlaps with the orthographic projection of the anode connection pad among the plurality of anode connection pads connected to the first anode in the first sub-pixel on the substrate; the orthographic projection of at least two of the plurality of first recesses partially surrounding the sub-pixel opening of the second sub-pixel on the substrate at least partially overlaps with the orthographic projection of the anode connection pad among the plurality of anode connection pads connected to the first anode in the first sub-pixel on the substrate; and the orthographic projection of at least two of the plurality of second recesses partially surrounding the sub-pixel opening of the second sub-pixel on the substrate at least partially overlaps with the orthographic projection of the anode connection pad among the plurality of anode connection pads connected to the first anode in the first sub-pixel on the substrate.

[0018] Optionally, a groove partially surrounding the sub-pixel opening of the first sub-pixel is interconnected with a groove partially surrounding the sub-pixel opening of the second sub-pixel; and a first recess partially surrounding the sub-pixel opening of the first sub-pixel is interconnected with a first recess partially surrounding the sub-pixel opening of the second sub-pixel.

[0019] Optionally, the second recesses that partially surround the sub-pixel opening of the first sub-pixel are spaced apart from the second recesses that partially surround the sub-pixel opening of the second sub-pixel.

[0020] Optionally, each of the plurality of grooves has a rectangular shape; each of the plurality of first recesses has a rectangular shape; and each of the plurality of second recesses has a rectangular shape.

[0021] Optionally, each of the plurality of grooves has an L-shaped shape; each of the plurality of first recesses has an L-shaped shape; and each of the plurality of second recesses has an L-shaped shape.

[0022] In another aspect, this disclosure provides a display device including the array substrate described herein and one or more integrated circuits connected to the array substrate. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0025] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0026] Figure 2B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0027] Figure 3A This is a schematic diagram illustrating the arrangement of pixel driving circuits in an array substrate according to some embodiments of the present disclosure.

[0028] Figure 3B It is shown Figure 3A A schematic diagram of the structure of the first semiconductor material layer in the array substrate shown.

[0029] Figure 3C It is shown Figure 3A The diagram shows the structure of the first semiconductor material layer and the first gate metal layer in the array substrate.

[0030] Figure 3D It is shown Figure 3A The diagram shows the structure of the first semiconductor material layer, the first gate metal layer, and the second gate metal layer in the array substrate.

[0031] Figure 3E It is shown Figure 3A The diagram shows the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, and the second semiconductor material layer in the array substrate.

[0032] Figure 3F It is shown Figure 3A The diagram shows the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the second semiconductor material layer, and the third gate metal layer in the array substrate.

[0033] Figure 3G It is shown Figure 3A The diagram shows a schematic representation of the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the second semiconductor material layer, the third gate metal layer, and the passivation layer in the array substrate.

[0034] Figure 3H It is shown Figure 3A The diagram shows a schematic representation of the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the second semiconductor material layer, the third gate metal layer, the first planarization layer, and the first signal line layer in the array substrate.

[0035] Figure 3I It is shown Figure 3A The diagram shows a schematic representation of the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the second semiconductor material layer, the third gate metal layer, the first planarization layer, the first signal line layer, and the second signal line layer in the array substrate shown.

[0036] Figure 3J It is shown Figure 3A The diagram shows a schematic representation of the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the second semiconductor material layer, the third gate metal layer, the first planarization layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate.

[0037] Figure 4A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0038] Figure 4BThis is a schematic diagram illustrating the structure of a third signal line layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0039] Figure 4C This is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0040] Figure 4D This is a schematic diagram illustrating the structure of a second passivation layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0041] Figure 4E This is a schematic diagram illustrating the structure of the anode layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0042] Figure 4F This is a schematic diagram illustrating the structure of a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0043] Figure 4G This is a schematic diagram illustrating the structure of a plurality of recesses in a portion of an array substrate according to some embodiments of the present disclosure.

[0044] Figure 5 This is a cross-sectional view of a portion of an array substrate according to some embodiments of the present disclosure.

[0045] Figure 6A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0046] Figure 6B This is a schematic diagram illustrating the structure of a third signal line layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0047] Figure 6C This is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0048] Figure 6D This is a schematic diagram illustrating the structure of a second passivation layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0049] Figure 6E This is a schematic diagram illustrating the structure of the anode layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0050] Figure 6F This is a schematic diagram illustrating the structure of a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0051] Figure 6GThis is a schematic diagram illustrating the structure of a plurality of recesses in a portion of an array substrate according to some embodiments of the present disclosure.

[0052] Figure 7A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0053] Figure 7B This is a schematic diagram illustrating the structure of a third signal line layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0054] Figure 7C This is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0055] Figure 7D This is a schematic diagram illustrating the structure of a second passivation layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0056] Figure 7E This is a schematic diagram illustrating the structure of the anode layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0057] Figure 7F This is a schematic diagram illustrating the structure of a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0058] Figure 7G This is a schematic diagram illustrating the structure of a plurality of recesses in a portion of an array substrate according to some embodiments of the present disclosure.

[0059] Figure 8A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0060] Figure 8B This is a schematic diagram illustrating the structure of a third signal line layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0061] Figure 8C This is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0062] Figure 8D This is a schematic diagram illustrating the structure of a second passivation layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0063] Figure 8E This is a schematic diagram illustrating the structure of the anode layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0064] Figure 8FThis is a schematic diagram illustrating the structure of a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0065] Figure 8G This is a schematic diagram illustrating the structure of a plurality of recesses in a portion of an array substrate according to some embodiments of the present disclosure.

[0066] Figure 9A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0067] Figure 9B This is a schematic diagram illustrating the structure of a third signal line layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0068] Figure 9C This is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0069] Figure 9D This is a schematic diagram illustrating the structure of a second passivation layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0070] Figure 9E This is a schematic diagram illustrating the structure of the anode layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0071] Figure 9F This is a schematic diagram illustrating the structure of a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure.

[0072] Figure 9G This is a schematic diagram illustrating the structure of a plurality of recesses in a portion of an array substrate according to some embodiments of the present disclosure. Detailed Implementation

[0073] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0074] Currently, the AMOLED pixel structure used in mobile phone panels is mainly based on subpixel rendering (SPR), which is widely used in handheld display designs. In contrast, wearable smartwatches, large-screen tablets, and computers typically use true RGB pixel structures, but true RGB displays generally have lower PPIs, ranging between 185 and 326.

[0075] Currently, with the increasing demand for higher image quality, the required PPI for true RGB displays is also increasing. However, true RGB designs based on LTPO remain relatively limited. Because each full pixel in a true RGB arrangement consists of three subpixels, the horizontal layout space per subpixel is more constrained compared to an SPR arrangement with the same PPI. As a result, achieving higher PPI presents challenges for layout design.

[0076] Therefore, this disclosure particularly provides an array substrate and a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a substrate; a signal line layer comprising a plurality of signal lines located on the substrate; a planarization layer located on the side of the signal line layer away from the substrate; a passivation layer located on the side of the planarization layer away from the substrate; an anode layer located on the side of the passivation layer away from the substrate; a pixel defining layer located on the side of the anode layer away from the substrate; a plurality of recesses extending through the pixel defining layer; a plurality of first recesses extending into the planarization layer; and a plurality of second recesses extending into the passivation layer.

[0077] Various suitable pixel driving circuits can be used in the array substrate described in this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in a plurality of pixel driving circuits is an 8T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0078] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1The array substrate comprises an array of subpixels Sp. Each subpixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of first gate lines (e.g., a corresponding first gate line GL1), a plurality of second gate lines (e.g., a corresponding second gate line GL2), a plurality of data lines (e.g., a corresponding data line DL), a plurality of power lines (e.g., a corresponding power line Vdd), and a plurality of voltage supply lines (e.g., a corresponding voltage supply line Vss). Each subpixel Sp emits light driven by its corresponding pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via a corresponding power line Vdd among the plurality of power lines; a low voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element via the voltage supply line. The voltage difference between the high voltage signal (e.g., the VDD signal) and the low voltage signal (e.g., the VSS signal) is the driving voltage ΔV, which drives the light-emitting element to emit light.

[0079] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2AIn some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to a first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to a first electrode of the driving transistor Td; and a second transistor T2 having a gate connected to a corresponding second gate line among a plurality of second gate lines. The transistor comprises: a gate of gate line GL2; a first electrode connected to the first capacitor electrode Ce1 of storage capacitor Cst and the gate of driving transistor Td; and a second electrode connected to the second electrode of driving transistor Td; a third transistor T3 having a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines; a first electrode connected to a corresponding power line Vdd among a plurality of power lines; and a second electrode connected to the first electrode of driving transistor Td and the second electrode of first transistor T1; a fourth transistor T4 having a gate connected to a corresponding light-emitting control signal line em among a plurality of light-emitting control signal lines; a first electrode connected to the second electrode of driving transistor Td and second transistor T2; and a second electrode connected to the anode of light-emitting element LE; and a first reset transistor Tr1 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines; a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines; and a second electrode connected to the second electrode of fourth transistor T4 and the anode of light-emitting element LE. A second capacitor electrode Ce2 is connected to the corresponding power line and the first electrode of third transistor T3.

[0080] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a first transistor T1), a compensation transistor (e.g., a second transistor T2), two light-emitting control transistors (e.g., a third transistor T3 and a fourth transistor T4), and three reset transistors (e.g., a first reset transistor Tr1, a second reset transistor Tr2, and a third reset transistor Tr3).

[0081] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, both of which are connected to the active layer of the transistor. The direction of current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0082] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0083] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, a corresponding pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3, wherein S1 represents a corresponding first sub-pixel, S2 represents a corresponding second sub-pixel, and S3 represents a corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents a corresponding first sub-pixel of a first color, C2 represents a corresponding second sub-pixel of a second color, and C3 represents a corresponding third sub-pixel of a third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0084] In another example, the array of multiple subpixels includes a repeating array in the format S1-S2-S3-S4, where S1 represents the corresponding first subpixel, S2 represents the corresponding second subpixel, S3 represents the corresponding third subpixel, and S4 represents the corresponding fourth subpixel. In another example, the S1-S2-S3-S4 format is C1-C2-C3-C4, where C1 represents the corresponding first subpixel of the first color, C2 represents the corresponding second subpixel of the second color, C3 represents the corresponding third subpixel of the third color, and C4 represents the corresponding fourth subpixel of the fourth color. In yet another example, the S1-S2-S3-S4 format is C1-C2-C3-C2', where C1 represents the corresponding first subpixel of the first color, C2 represents the corresponding second subpixel of the second color, C3 represents the corresponding third subpixel of the third color, and C2' represents the corresponding fourth subpixel of the second color. In another example, the C1-C2-C3-C2' format is RGBG format, where the corresponding first subpixel is a red subpixel, the corresponding second subpixel is a green subpixel, the corresponding third subpixel is a blue subpixel, and the corresponding fourth subpixel is a green subpixel.

[0085] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, and a storage capacitor Cst.

[0086] In an alternative embodiment, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, and a storage capacitor Cst.

[0087] This disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. (See also...) Figure 2AThe second transistor T2 is an n-type transistor, such as a metal-oxide-semiconductor (MOS) transistor, while the other transistors are p-type transistors, such as polysilicon transistors. For p-type transistors, the active control signal (e.g., the turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., the turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., the turn-off control signal) is a low-voltage signal.

[0088] Figure 2B This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2A and Figure 2B During one frame of an image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light emission sub-stage t3. In the initial sub-stage t0, a cutoff reset control signal is provided to the second reset transistor Tr2 via the corresponding second reset control signal line rst2 to turn off the second reset transistor Tr2. A cutoff reset control signal is provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1 to turn off the first reset transistor Tr1 and the third reset transistor Tr3. In the initial sub-stage t0, a cutoff signal is provided to the corresponding first gate line GL1, therefore the first transistor T1 is turned off.

[0089] In reset phase t1, the turn-on reset control signal is provided to the gate of the first reset transistor Tr1 via the corresponding first reset control signal line rst1 to turn on the first reset transistor Tr1; allowing the initialization voltage signal from the corresponding first reset signal line Vint1 to pass from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1; and sequentially to node N4. The anode of the light-emitting element LE is initialized. The turn-on reset control signal is provided to the gate of the third reset transistor Tr3 via the corresponding first reset control signal line rst1 to turn on the third reset transistor Tr3; allowing the initialization voltage signal from the corresponding third reset signal line Vint3 to pass from the first electrode of the third reset transistor Tr3 to the second electrode of the third reset transistor Tr3; and sequentially to node N2. Node N2 is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding power supply line Vdd. Due to the increased voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2, the first capacitor electrode Ce1 is charged in reset phase t1. During the reset phase t1, the corresponding first gate line GL1 is provided with a cutoff signal, thus turning off the first transistor T1. The corresponding light-emitting control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4.

[0090] During the data writing sub-stage t2, a turn-on reset control signal is provided to the gate of the second reset transistor Tr2 via the second reset control signal line rst2 to turn on the second reset transistor Tr2; this allows the initialization voltage signal from the corresponding second reset signal line Vint2 to be transmitted from the first electrode of the second reset transistor Tr2 to the second electrode of the second reset transistor Tr2, and then sequentially to the second electrode of the driving transistor Td. The second electrode of the driving transistor Td is then initialized.

[0091] During the data write sub-stage t2, the cutoff reset control signal is again provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1, thus turning off the first reset transistor Tr1 and the third reset transistor Tr3. The corresponding first gate line GL1 and the corresponding second gate line GL2 are provided with conduction signals, therefore the first transistor T1 and the second transistor T2 are turned on. The first electrode of the driving transistor Td is connected to the second electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the first electrode of the second transistor T2. Since the second transistor T2 is turned on during the data write sub-stage t2, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thus putting the driving transistor Td in diode connection mode. The first transistor T1 is turned on during the data write sub-stage t2. The data voltage signal transmitted via the corresponding data line DL is received by the first electrode of the first transistor T1 and sequentially transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. Node N2, connected to the first electrode of the driving transistor Td, has a data voltage signal level. Since only the PN junction between the gate of the driving transistor Td and the first electrode is active, during the data write sub-stage t2, the voltage level of node N1 gradually rises to (Vdata + Vth), where Vdata is the data voltage signal level and Vth is the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. The corresponding light-emitting control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4.

[0092] In the light-emitting stage t3, a cutoff reset control signal is provided to the gate of the second reset transistor Tr2 via the corresponding second reset control signal line rst2 to turn off the second reset transistor Tr2. A cutoff reset control signal is also provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 via the corresponding first reset control signal line rst1 to turn off the first reset transistor Tr1 and the third reset transistor Tr3. Cutoff signals are provided to the corresponding first gate line GL1 and the corresponding second gate line GL2, turning off the first transistor T1 and the second transistor T2. A low voltage signal is provided to the corresponding light-emitting control signal line em to turn on the third transistor T3 and the fourth transistor T4. In the light-emitting stage t3, the voltage level at node N1 is maintained at (Vdata + Vth), and the driving transistor Td is turned on by this voltage level, operating in the saturation region. A path is formed through the third transistor T3, the driving transistor Td, and the fourth transistor T4 to the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at node N3, connected to the second electrode of the driving transistor Td, is equal to the emission voltage of the light-emitting element LE.

[0093] Figure 3A This is a schematic diagram illustrating the arrangement of pixel driving circuits in an array substrate according to some embodiments of the present disclosure. Figure 3B It is shown Figure 3A A schematic diagram of the structure of the first semiconductor material layer in the array substrate shown. Figure 3C It is shown Figure 3A The diagram shows the structure of the first semiconductor material layer and the first gate metal layer in the array substrate. Figure 3D It is shown Figure 3A The diagram shows the structure of the first semiconductor material layer, the first gate metal layer, and the second gate metal layer in the array substrate. Figure 3E It is shown Figure 3A The diagram shows the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, and the second semiconductor material layer in the array substrate. Figure 3F It is shown Figure 3A The diagram shows the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the second semiconductor material layer, and the third gate metal layer in the array substrate. Figure 3G It is shown Figure 3A The diagram shows a schematic representation of the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the second semiconductor material layer, the third gate metal layer, and the passivation layer in the array substrate. Figure 3H It is shown Figure 3AThe diagram shows a schematic representation of the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the second semiconductor material layer, the third gate metal layer, the first planarization layer, and the first signal line layer in the array substrate. Figure 3I It is shown Figure 3A The diagram shows a schematic representation of the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the second semiconductor material layer, the third gate metal layer, the first planarization layer, the first signal line layer, and the second signal line layer in the array substrate shown. Figure 3J It is shown Figure 3A The diagram shows a schematic representation of the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the second semiconductor material layer, the third gate metal layer, the first planarization layer, the first signal line layer, the second signal line layer, and the third signal line layer in the array substrate. Figures 3A to 3J A portion of an array substrate is shown, comprising twelve adjacent pixel driving circuits (including PDC1, PDC2, PDC3, PDC4, PDC5, PDC6, PDC7, PDC8, PDC9, PDC10, PDC11, and PDC12). The twelve adjacent pixel driving circuits are arranged in four columns and two rows.

[0094] Reference Figure 2A , Figure 3J , Figure 3A and Figure 3BIn some embodiments, the first semiconductor material layer includes at least an active layer of the plurality of transistors (including first transistor T1, third transistor T3, fourth transistor T4, first reset transistor Tr1, second reset transistor Tr2, third reset transistor Tr3, and driving transistor Td) of the pixel driving circuit. Optionally, the first semiconductor material layer also includes at least corresponding portions of the first electrodes of the plurality of transistors (including first transistor T1, third transistor T3, fourth transistor T4, first reset transistor Tr1, second reset transistor Tr2, third reset transistor Tr3, and driving transistor Td) of the pixel driving circuit. Optionally, the first semiconductor material layer also includes at least corresponding portions of the second electrodes of the plurality of transistors (including first transistor T1, third transistor T3, fourth transistor T4, first reset transistor Tr1, second reset transistor Tr2, third reset transistor Tr3, and driving transistor Td) of the pixel driving circuit. Optionally, the first semiconductor material layer includes an active layer, a first electrode, and a second electrode for a plurality of transistors (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td) of the pixel driving circuit. Various suitable semiconductor materials can be used to fabricate the first semiconductor material layer. Examples of semiconductor materials used to fabricate the first semiconductor material layer include silicon-based semiconductor materials, such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0095] exist Figure 3B In, corresponding to Figure 3A The pixel driving circuit of PDC1 is indicated by a label that indicates the components of each of the multiple transistors (T1, T3, T4, Tr1, Tr2, Tr3, and Td) in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode, and a second electrode. The third transistor T3 includes an active layer ACT3, a first electrode, and a second electrode. The fourth transistor T4 includes an active layer ACT4, a first electrode, and a second electrode. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode, and a second electrode. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode, and a second electrode. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode, and a second electrode. The driving transistor Td includes an active layer ACTd, a first electrode, and a second electrode.

[0096] Optionally, the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr2, Tr3 and Td), the first electrode and the second electrode of each transistor (T1, T3, T4, Tr1, Tr2, Tr3 and Td) are located on the same layer.

[0097] In some embodiments, the active layers (ACT1, ACT3, ACT4, ACTr1, and ACTd) of the plurality of transistors (T1, T3, T4, Tr1, and Td) in the pixel driving circuit, at least a portion of the first electrode, and at least a portion of the second electrode are part of the overall structure. Optionally, in the same pixel driving circuit, a portion of the second reset transistor Tr2 located in the first semiconductor material layer is spaced apart from the overall structure (T1, T3, T4, Tr1, and Td). Optionally, in the same pixel driving circuit, a portion of the second reset transistor Tr3 located in the first semiconductor material layer is spaced apart from the overall structure (T1, T3, T4, Tr1, and Td). Figure 3B As shown, in some embodiments, the active layers (ACT1, ACT3, ACT4, ACTr1 and ACTd) of multiple transistors (T1, T3, T4, Tr1 and Td) in two adjacent pixel driving circuits, at least a portion of the first electrode and at least a portion of the second electrode are part of the overall structure.

[0098] Reference Figure 2A , Figure 3J , Figure 3C In some embodiments, the first gate metal layer includes a plurality of first gate lines (e.g., a corresponding first gate line GL1), a plurality of light emission control signal lines (e.g., a corresponding light emission control signal line em), a plurality of first reset control signal lines (e.g., a corresponding first reset control signal line rst1), a plurality of second reset control signal lines (e.g., a corresponding second reset control signal line rst2), and a first capacitor electrode Ce1 of the storage capacitor Cst in the pixel driving circuit.

[0099] Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first gate metal layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first gate metal layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, a plurality of first gate lines (e.g., corresponding first gate line GL1), a plurality of light emission control signal lines (e.g., corresponding light emission control signal line em), a plurality of first reset control signal lines (e.g., corresponding first reset control signal line rst1), a plurality of second reset control signal lines (e.g., corresponding second reset control signal line rst2), and the first capacitor electrode Ce1 of the storage capacitor Cst in the pixel driving circuit are located in the same layer.

[0100] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, multiple first gate lines and first capacitor electrodes Ce1 are located in the same layer when they are formed due to one or more steps of the same patterning process performed in the same material layer. In another example, multiple first gate lines and first capacitor electrodes Ce1 can be formed in the same layer by simultaneously performing the steps of forming multiple first gate lines and the step of forming first capacitor electrodes Ce1. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0101] Reference Figure 2A , Figure 3J , Figure 3D In some embodiments, the second gate metal layer includes at least a portion of a plurality of second gate lines (e.g., a corresponding first branch GL2-1 of the second gate lines) and a second capacitor electrode Ce2 of the storage capacitor Cst in the pixel driving circuit. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the second gate metal layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second gate metal layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, at least a portion of the plurality of second gate lines (e.g., a corresponding first branch GL2-1 of the second gate lines) and the second capacitor electrode Ce2 of the storage capacitor Cst in the pixel driving circuit are located in the same layer.

[0102] Reference Figure 2A , Figure 3J , Figure 3E In some embodiments, the second semiconductor material layer includes at least the active layer ACT2 of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer also includes at least a portion of the first electrode of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer also includes at least a portion of the second electrode of the second transistor T2 in the pixel driving circuit. Optionally, the second semiconductor material layer includes the active layer ACT2 of the second transistor T2, the first electrode, and the second electrode. In this array substrate, the at least active layer ACT2 of the second transistor T2 is located on a different layer from the at least active layers of other transistors in the pixel driving circuit. Various suitable semiconductor materials can be used to fabricate the second semiconductor material layer. Examples of semiconductor materials used to fabricate the second semiconductor material layer include metal oxide-based semiconductor materials (e.g., indium gallium zinc oxide) and metal oxynitride-based semiconductor materials (e.g., zinc oxynitride).

[0103] exist Figure 3EIn, corresponding to Figure 3A The pixel driving circuit of PDC1 is indicated by a label, which indicates the components of the second transistor in the pixel driving circuit. For example, the second transistor T2 includes an active layer ACT2, a first electrode, and a second electrode. Optionally, the active layer ACT2, the first electrode, and the second electrode of the second transistor T2 are located on the same layer.

[0104] refer to Figure 2A , Figure 3J , Figure 3F In some embodiments, the third gate metal layer includes at least portions of a plurality of second gate lines (e.g., corresponding second branches of the second gate lines GL2-2), a plurality of first reset signal lines (e.g., corresponding first reset signal line Vint1), a plurality of second reset signal lines (e.g., corresponding second reset signal line Vint2), and a plurality of third reset signal lines (e.g., corresponding third reset signal line Vint3). Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the third gate metal layer. For example, conductive materials can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the third gate metal layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc.

[0105] Figure 3G Show Figure 3A The vias extending through the passivation layer in the array substrate shown.

[0106] refer to Figure 2A , Figure 3J , Figure 3H In some embodiments, the first signal line layer includes a first node connection line Cln1; a second node connection line Cln2; and a third node connection line Cln3.

[0107] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In some embodiments, the first signal line layer comprises multiple sublayers stacked together. In one example, the first signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, the first node connection line Cln1, the second node connection line Cln2, and the third node connection line Cln3 are located in the same layer.

[0108] In some embodiments, the first node connection line Cln1 connects multiple components of the pixel driving circuit to the first node N1. In some embodiments, the first node connection line Cln1 is connected to the first capacitor electrode Ce1 through a first via and to the second transistor T2 (e.g., connected to the first electrode of the second transistor T2) through a second via. Optionally, the first node connection line Cln1 corresponds to Figure 2A The node N1 described in the text.

[0109] In some embodiments, the first node connection line Cln1 intersects with a corresponding second gate line among a plurality of second gate lines. In some embodiments, the first node connection line Cln1 intersects with a first branch GL2-1 of a corresponding second gate line located in the second gate metal layer and a second branch GL2-2 of a corresponding second gate line located in the third gate metal layer.

[0110] In some embodiments, the second node connection line Cln2 connects multiple components of the pixel driving circuit to the second node N2. In some embodiments, the second node connection line Cln2 is connected to the second electrode of the third reset transistor Tr3, to the second electrode of the third transistor T3, and to the first electrode of the driving transistor Td.

[0111] In some embodiments, the third node connection line Cln3 is connected to the second electrode of the driving transistor Td, the second electrode of the second reset transistor Tr2, and the first electrode of the fourth transistor T4.

[0112] refer to Figure 2A , Figure 3J , Figure 3I In some embodiments, the second signal line layer includes multiple voltage supply lines (e.g., corresponding voltage supply lines Vdd).

[0113] In some embodiments, the corresponding voltage supply line Vdd is configured to provide a first reference voltage signal. Optionally, the first reference voltage signal (e.g., a high voltage signal) is a constant voltage signal.

[0114] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the second signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the second signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In one example, the second signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure.

[0115] refer to Figure 2A , Figure 3J Figure 3N shows that in some embodiments, the third signal line layer includes multiple data lines (e.g., corresponding data lines DL).

[0116] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the third signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the third signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. In one example, the second signal line layer comprises a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer comprises a stacked molybdenum / aluminum / molybdenum multilayer structure.

[0117] In some embodiments, reference Figures 3A to 3J The first pixel driving circuits that are directly adjacent to each other and in the same level (e.g., in the same row) (e.g.) Figure 3A The corresponding layer of PDC1 and the second pixel driving circuit (e.g., Figure 3A The corresponding layer of PDC2 in the array, for example, with respect to a plane that is perpendicular to the main surface of the array substrate and substantially parallel to the multiple data lines, has a basic (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or completely symmetrical) mirror symmetry with respect to each other.

[0118] As used herein, the term "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" is not intended to include layers that are not part of the pixel driving circuit. For example, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include an anode layer or a pixel defining layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a third signal line layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a second signal line layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a first signal line layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a third gate metal layer. In some embodiments, "corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit" does not include a second gate metal layer.

[0119] In one example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" refers to at least one conductive layer of the first pixel driving circuit and at least one conductive layer of the second pixel driving circuit. In a specific example, "corresponding layer" includes at least one of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, a second signal line layer, or a third signal line layer. In another specific example, "corresponding layer" further includes at least one of a gate insulating layer, an insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a passivation layer, a first planarization layer, or a second planarization layer. In another specific example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" includes a first semiconductor material layer. In another specific example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" includes a first gate metal layer. In another specific example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" includes a second semiconductor material layer.

[0120] The inventors of this disclosure have discovered that a major challenge in true RGB pixel circuits combining tandem and COE technologies is the problem of tandem crosstalk. The inventors of this disclosure have discovered that isolation pillars can be used to prevent interference between adjacent pixels. The inventors of this disclosure have discovered that true RGB pixels have a denser subpixel aperture distribution compared to GRB arrangements, further complicating the layout. Due to the subpixel arrangement in true RGB, it is difficult to achieve a perfectly mirrored pixel structure. Otherwise, parasitic differences between pixels of the same color with different orientations can lead to the Mura problem. This compromises the effectiveness of COE, as COE requires a perfectly symmetrical metal layer beneath the pixels. Taking these factors into consideration, the inventors of this disclosure have discovered a novel and inventive array substrate that addresses the COE symmetry, tandem isolation requirements, and inherent asymmetry of true RGB structures.

[0121] Figure 4A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 4B This is a schematic diagram illustrating the structure of a third signal line layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 4C This is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 4D This is a schematic diagram illustrating the structure of a second passivation layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 4E This is a schematic diagram illustrating the structure of the anode layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 4FThis is a schematic diagram illustrating the structure of a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 4G This is a schematic diagram illustrating the structure of a plurality of recesses in a portion of an array substrate according to some embodiments of the present disclosure. Figure 5 This is a cross-sectional view of a portion of an array substrate according to some embodiments of the present disclosure. For example, Figure 5 It can be along Figure 4A A cross-sectional view of line A-A' in the diagram.

[0122] In some embodiments, the array substrate includes a substrate BS; a third signal line layer SL3 located on the substrate BS; a planarization layer PLN located on the side of the third signal line layer SL3 away from the substrate BS; a second passivation layer PVX2 located on the side of the planarization layer PLN away from the substrate BS; an anode layer ADL located on the side of the second passivation layer PVX2 away from the substrate BS; and a pixel defining layer PDL located on the side of the anode layer ADL away from the substrate BS.

[0123] In some embodiments, the third signal line layer includes multiple power lines (e.g., corresponding power lines Vdd), multiple data lines (e.g., corresponding data lines DL), and multiple anode connection pads (e.g., corresponding anode connection pads ACP).

[0124] In some embodiments, the array substrate includes a plurality of first recesses RES1 extending into the planarization layer PLN. A first recess of the plurality of first recesses RES1 partially surrounds a sub-pixel opening in a plurality of sub-pixel openings SA. In one example, two first recesses of the plurality of first recesses RES1 partially surround a sub-pixel opening on opposite sides.

[0125] In some embodiments, the array substrate includes a plurality of pixels. In some embodiments, each of the plurality of pixels includes a first sub-pixel Sp1, a second sub-pixel Sp2, and a third sub-pixel Sp3. Optionally, the first sub-pixel Sp1, the second sub-pixel Sp2, and the third sub-pixel Sp3 are sub-pixels of different colors.

[0126] In some embodiments, the subpixels of the array substrate are arranged in a plurality of first columns and a plurality of second columns. The plurality of first columns and the plurality of second columns are arranged alternately. In some embodiments, a first subpixel Sp1 and a second subpixel Sp2 are located in the first column of the plurality of first columns, and a third subpixel Sp3 is located in the second column of the plurality of second columns. In some embodiments, a plurality of first recesses RES1 are present in the plurality of first columns but not in the plurality of second columns.

[0127] In some embodiments, the plurality of first recesses RES1 extend partially into the planarization layer PLN, for example, the plurality of first recesses RES1 do not extend through the planarization layer PLN.

[0128] In some embodiments, the second passivation layer PVX2 includes a plurality of first strips BA1 and a plurality of second strips BA2. The plurality of first strips BA1 are respectively located in a plurality of first columns; and the plurality of second strips BA2 are respectively located in a plurality of second columns.

[0129] In some embodiments, the anode layer ADL includes a plurality of anodes arranged in a plurality of first columns and a plurality of second columns. Each pixel in the plurality of pixels includes a first anode AD1 in a first sub-pixel Sp1, a second anode AD2 in a second sub-pixel Sp2, and a third anode AD3 in a third sub-pixel Sp3.

[0130] In some embodiments, the orthographic projection of each of the plurality of first strips BA1 on the substrate BS at least partially overlaps with the orthographic projection of the anode (e.g., first anode AD1 and second anode AD2) in the corresponding first column of the plurality of first columns. In some embodiments, the orthographic projection of each of the plurality of second strips BA2 on the substrate BS at least partially overlaps with the orthographic projection of the anode (e.g., third anode AD3) in the corresponding second column of the plurality of second columns.

[0131] In some embodiments, the orthographic projection of each of the plurality of first strips BA1 onto the substrate BS overlaps the orthographic projection of the anode (e.g., first anode AD1 and second anode AD2) in the corresponding first column of the plurality of first columns. In some embodiments, the orthographic projection of each of the plurality of second strips BA2 onto the substrate BS overlaps the orthographic projection of the anode (e.g., third anode AD3) in the corresponding second column of the plurality of second columns.

[0132] In some embodiments, the array substrate includes a plurality of second recesses RES2 extending into the second passivation layer PVX2. The second recesses of the plurality of second recesses RES2 partially surround sub-pixel openings in a plurality of sub-pixel openings SA. In one example, two second recesses of the plurality of second recesses RES2 partially surround a sub-pixel opening on opposite sides.

[0133] In some embodiments, a first recess in a plurality of first recesses RES1 partially surrounds a second recess in a plurality of second recesses RES2. In one example, two first recesses in a plurality of first recesses RES1 partially surround two second recesses in a plurality of second recesses RES2.

[0134] In some embodiments, a plurality of second recesses RES2 are present in a plurality of first strips BA1 but not in a plurality of second strips BA2.

[0135] In some embodiments, the array substrate includes a plurality of sub-pixel openings SA extending through the pixel defining layer PDL and a plurality of grooves extending through the pixel defining layer PDL. In some embodiments, the orthographic projection of each groove in the plurality of grooves GV onto the substrate BS at least partially overlaps with the orthographic projection of a corresponding first recess in the plurality of first recesses RES1 onto the substrate BS; and at least partially overlaps with the orthographic projection of a corresponding second recess in the plurality of second recesses RES2 onto the substrate BS.

[0136] In some embodiments, the orthographic projection of each of the plurality of grooves GV onto the substrate BS covers the orthographic projection of the corresponding first recess in the plurality of first recesses RES1 onto the substrate BS; and covers the orthographic projection of the corresponding second recess in the plurality of second recesses RES2 onto the substrate BS.

[0137] In some embodiments, the grooves in the plurality of grooves GV partially surround the sub-pixel openings in the plurality of sub-pixel openings SA. In one example, two grooves in the plurality of grooves GV partially surround the sub-pixel openings on opposite sides.

[0138] Reference Figure 4A and Figure 4G In some embodiments, the array substrate includes a plurality of recesses RES. Each recess in the plurality of recesses RES includes a corresponding first recess in a plurality of first recesses RES1 and a corresponding second recess in a plurality of second recesses RES2. In some embodiments, the orthographic projections of each first recess on the substrate do not overlap with the orthographic projections of each second recess on the substrate.

[0139] The inventors of this disclosure have discovered that, by having a plurality of grooves GV, a plurality of first recesses RES1 and a plurality of second recesses RES2, when an organic material layer (e.g., a common layer such as a hole transport layer or an electron transport layer) is deposited on an array substrate, the plurality of grooves GV, the plurality of first recesses RES1 and the plurality of second recesses RES2 at least partially isolate the organic material layer into discontinuous segments, thereby defining a plurality of sub-pixels.

[0140] exist Figures 4A to 4G as well as Figure 5 In the example shown, two of the multiple grooves GV that partially surround the sub-pixel opening have a partially annular shape; two of the multiple first recesses RES1 that partially surround the sub-pixel opening have a partially annular shape; and two of the multiple second recesses RES2 that partially surround the sub-pixel opening have a partially annular shape.

[0141] In some embodiments, a plurality of first strips BA1 and a plurality of second strips BA2 are arranged along a first direction DR1, and the plurality of first strips BA1 and the plurality of second strips BA2 extend along a second direction DR2. In some embodiments, two recesses in a plurality of recesses GV that partially surround the sub-pixel opening are arranged along the first direction DR1. In some embodiments, two first recesses in a plurality of first recesses RES1 that partially surround the sub-pixel opening are arranged along the first direction DR1. In some embodiments, two second recesses in a plurality of second recesses RES2 that partially surround the sub-pixel opening are arranged along the first direction DR1.

[0142] Figure 6A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 6B This is a schematic diagram illustrating the structure of a third signal line layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 6C This is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 6D This is a schematic diagram illustrating the structure of a second passivation layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 6E This is a schematic diagram illustrating the structure of the anode layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 6F This is a schematic diagram illustrating the structure of a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 6G This is a schematic diagram illustrating the structure of a plurality of recesses in a portion of an array substrate according to some embodiments of the present disclosure. In one example, Figure 5 It can be along Figure 6A A cross-sectional view of line B-B' in the diagram.

[0143] In some embodiments, the array substrate includes a substrate BS; a third signal line layer SL3 located on the substrate BS; a planarization layer PLN located on the side of the third signal line layer SL3 away from the substrate BS; a second passivation layer PVX2 located on the side of the planarization layer PLN away from the substrate BS; an anode layer ADL located on the side of the second passivation layer PVX2 away from the substrate BS; and a pixel defining layer PDL located on the side of the anode layer ADL away from the substrate BS.

[0144] In some embodiments, the third signal line layer includes multiple power lines (e.g., corresponding power lines Vdd), multiple data lines (e.g., corresponding data lines DL), and multiple anode connection pads (e.g., corresponding anode connection pads ACP).

[0145] In some embodiments, the array substrate includes a plurality of first recesses RES1 extending into the planarization layer PLN. A first recess of the plurality of first recesses RES1 partially surrounds a sub-pixel opening in a plurality of sub-pixel openings SA. In one example, two first recesses of the plurality of first recesses RES1 partially surround a sub-pixel opening on opposite sides.

[0146] In some embodiments, the array substrate includes a plurality of pixels. In some embodiments, each of the plurality of pixels includes a first sub-pixel Sp1, a second sub-pixel Sp2, and a third sub-pixel Sp3. Optionally, the first sub-pixel Sp1, the second sub-pixel Sp2, and the third sub-pixel Sp3 are sub-pixels of different colors.

[0147] In some embodiments, the subpixels of the array substrate are arranged in a plurality of first columns and a plurality of second columns. The plurality of first columns and the plurality of second columns are arranged alternately. In some embodiments, a first subpixel Sp1 and a second subpixel Sp2 are located in the first column of the plurality of first columns, and a third subpixel Sp3 is located in the second column of the plurality of second columns. In some embodiments, a plurality of first recesses RES1 are present in the plurality of first columns but not in the plurality of second columns.

[0148] In some embodiments, the plurality of first recesses RES1 extend partially into the planarization layer PLN, for example, the plurality of first recesses RES1 do not extend through the planarization layer PLN.

[0149] In some embodiments, the second passivation layer PVX2 includes a plurality of first strips BA1 and a plurality of second strips BA2. The plurality of first strips BA1 are respectively located in a plurality of first columns; and the plurality of second strips BA2 are respectively located in a plurality of second columns.

[0150] In some embodiments, the anode layer ADL includes a plurality of anodes arranged in a plurality of first columns and a plurality of second columns. Each pixel in the plurality of pixels includes a first anode AD1 in a first sub-pixel Sp1, a second anode AD2 in a second sub-pixel Sp2, and a third anode AD3 in a third sub-pixel Sp3.

[0151] In some embodiments, the orthographic projection of each of the plurality of first strips BA1 on the substrate BS at least partially overlaps with the orthographic projection of the anode (e.g., first anode AD1 and second anode AD2) in the corresponding first column of the plurality of first columns. In some embodiments, the orthographic projection of each of the plurality of second strips BA2 on the substrate BS at least partially overlaps with the orthographic projection of the anode (e.g., third anode AD3) in the corresponding second column of the plurality of second columns.

[0152] In some embodiments, the orthographic projection of each of the plurality of first strips BA1 onto the substrate BS overlaps the orthographic projection of the anode (e.g., first anode AD1 and second anode AD2) in the corresponding first column of the plurality of first columns. In some embodiments, the orthographic projection of each of the plurality of second strips BA2 onto the substrate BS overlaps the orthographic projection of the anode (e.g., third anode AD3) in the corresponding second column of the plurality of second columns.

[0153] In some embodiments, the array substrate includes a plurality of second recesses RES2 extending into the second passivation layer PVX2. The second recesses of the plurality of second recesses RES2 partially surround sub-pixel openings in a plurality of sub-pixel openings SA. In one example, two second recesses of the plurality of second recesses RES2 partially surround a sub-pixel opening on opposite sides.

[0154] In some embodiments, a first recess in a plurality of first recesses RES1 partially surrounds a second recess in a plurality of second recesses RES2. In one example, two first recesses in a plurality of first recesses RES1 partially surround two second recesses in a plurality of second recesses RES2.

[0155] In some embodiments, a plurality of second recesses RES2 are present in a plurality of first strips BA1 but not in a plurality of second strips BA2.

[0156] In some embodiments, the array substrate includes a plurality of sub-pixel openings SA extending through the pixel defining layer PDL and a plurality of grooves extending through the pixel defining layer PDL. In some embodiments, the orthographic projection of each groove in the plurality of grooves GV onto the substrate BS at least partially overlaps with the orthographic projection of a corresponding first recess in the plurality of first recesses RES1 onto the substrate BS; and at least partially overlaps with the orthographic projection of a corresponding second recess in the plurality of second recesses RES2 onto the substrate BS.

[0157] In some embodiments, the orthographic projection of each of the plurality of grooves GV onto the substrate BS covers the orthographic projection of the corresponding first recess in the plurality of first recesses RES1 onto the substrate BS; and covers the orthographic projection of the corresponding second recess in the plurality of second recesses RES2 onto the substrate BS.

[0158] In some embodiments, the grooves in the plurality of grooves GV partially surround the sub-pixel openings in the plurality of sub-pixel openings SA. In one example, two grooves in the plurality of grooves GV partially surround the sub-pixel openings on opposite sides.

[0159] Reference Figure 6A and Figure 6GIn some embodiments, the array substrate includes a plurality of recesses RES. Each recess in the plurality of recesses RES includes a corresponding first recess in a plurality of first recesses RES1 and a corresponding second recess in a plurality of second recesses RES2. In some embodiments, the orthographic projections of each first recess on the substrate do not overlap with the orthographic projections of each second recess on the substrate.

[0160] The inventors of this disclosure have discovered that, by having a plurality of grooves GV, a plurality of first recesses RES1 and a plurality of second recesses RES2, when an organic material layer (e.g., a common layer such as a hole transport layer or an electron transport layer) is deposited on an array substrate, the plurality of grooves GV, the plurality of first recesses RES1 and the plurality of second recesses RES2 at least partially isolate the organic material layer into discontinuous segments, thereby defining a plurality of sub-pixels.

[0161] exist Figures 6A to 6G as well as Figure 5 In the example shown, two of the multiple grooves GV that partially surround the sub-pixel opening have a partially annular shape; two of the multiple first recesses RES1 that partially surround the sub-pixel opening have a partially annular shape; and two of the multiple second recesses RES2 that partially surround the sub-pixel opening have a partially annular shape.

[0162] In some embodiments, a plurality of first strips BA1 and a plurality of second strips BA2 are arranged along a first direction DR1, and the plurality of first strips BA1 and the plurality of second strips BA2 extend along a second direction DR2. In some embodiments, two grooves in a plurality of grooves GV that partially surround the subpixel opening of a first subpixel Sp1 are arranged along the first direction DR1. In some embodiments, two grooves in a plurality of grooves GV that partially surround the subpixel opening of a second subpixel Sp2 are arranged along a third direction DR3, wherein the third direction DR3 is different from the first direction DR1 and different from the second direction DR2.

[0163] In some embodiments, two first recesses of the plurality of first recesses RES1 that partially surround the subpixel opening of the first subpixel Sp1 are arranged along a first direction DR1. In some embodiments, two first recesses of the plurality of first recesses RES1 that partially surround the subpixel opening of the second subpixel Sp2 are arranged along a third direction DR3, wherein the third direction DR3 is different from the first direction DR1 and different from the second direction DR2.

[0164] In some embodiments, two second recesses of the plurality of second recesses RES2 that partially surround the subpixel opening of the first subpixel Sp1 are arranged along a first direction DR1. In some embodiments, two second recesses of the plurality of second recesses RES2 that partially surround the subpixel opening of the second subpixel Sp2 are arranged along a third direction DR3, wherein the third direction DR3 is different from the first direction DR1 and different from the second direction DR2.

[0165] In some embodiments, the orthographic projection of at least two of the two grooves in the plurality of grooves GV that partially surround the subpixel opening of the second subpixel Sp2 on the substrate at least partially overlaps with the orthographic projection of the anode connection pads in the plurality of anode connection pads ACP connected to the first anode AD1 in the first subpixel Sp1 on the substrate. The inventors of this disclosure have found that this structure can better isolate the organic material layer when it is deposited on the array substrate.

[0166] In some embodiments, the orthographic projection of at least one of the two first recesses in the plurality of first recesses RES1 that partially surround the subpixel opening of the second subpixel Sp2 on the substrate at least partially overlaps with the orthographic projection of the anode connection pads in the plurality of anode connection pads ACP connected to the first anode AD1 in the first subpixel Sp1 on the substrate. The inventors of this disclosure have found that this structure can better isolate the organic material layer when it is deposited on the array substrate.

[0167] In some embodiments, the orthographic projection of at least one of the two second recesses RES2 that partially surround the subpixel opening of the second subpixel Sp2 on the substrate at least partially overlaps with the orthographic projection of the anode connection pads ACP of the plurality of anode connection pads ACP connected to the first anode AD1 in the first subpixel Sp1 on the substrate. The inventors of this disclosure have found that this structure can better isolate the organic material layer when it is deposited on the array substrate.

[0168] Figure 7A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 7B This is a schematic diagram illustrating the structure of a third signal line layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 7C This is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 7D This is a schematic diagram illustrating the structure of a second passivation layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 7E This is a schematic diagram illustrating the structure of the anode layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 7FThis is a schematic diagram illustrating the structure of a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 7G This is a schematic diagram illustrating the structure of a plurality of recesses in a portion of an array substrate according to some embodiments of the present disclosure. In one example, Figure 5 It can be along Figure 7A A cross-sectional view of line C-C' in the diagram.

[0169] In some embodiments, the array substrate includes a substrate BS; a third signal line layer SL3 located on the substrate BS; a planarization layer PLN located on the side of the third signal line layer SL3 away from the substrate BS; a second passivation layer PVX2 located on the side of the planarization layer PLN away from the substrate BS; an anode layer ADL located on the side of the second passivation layer PVX2 away from the substrate BS; and a pixel defining layer PDL located on the side of the anode layer ADL away from the substrate BS.

[0170] In some embodiments, the third signal line layer includes multiple power lines (e.g., corresponding power lines Vdd), multiple data lines (e.g., corresponding data lines DL), and multiple anode connection pads (e.g., corresponding anode connection pads ACP).

[0171] In some embodiments, the array substrate includes a plurality of first recesses RES1 extending into the planarization layer PLN. A first recess of the plurality of first recesses RES1 partially surrounds a sub-pixel opening in a plurality of sub-pixel openings SA. In one example, two first recesses of the plurality of first recesses RES1 partially surround a sub-pixel opening on opposite sides.

[0172] In some embodiments, the array substrate includes a plurality of pixels. In some embodiments, each of the plurality of pixels includes a first sub-pixel Sp1, a second sub-pixel Sp2, and a third sub-pixel Sp3. Optionally, the first sub-pixel Sp1, the second sub-pixel Sp2, and the third sub-pixel Sp3 are sub-pixels of different colors.

[0173] In some embodiments, the subpixels of the array substrate are arranged in a plurality of first columns and a plurality of second columns. The plurality of first columns and the plurality of second columns are arranged alternately. In some embodiments, a first subpixel Sp1 and a second subpixel Sp2 are located in the first column of the plurality of first columns, and a third subpixel Sp3 is located in the second column of the plurality of second columns. In some embodiments, a plurality of first recesses RES1 are present in the plurality of first columns but not in the plurality of second columns.

[0174] In some embodiments, the plurality of first recesses RES1 extend partially into the planarization layer PLN, for example, the plurality of first recesses RES1 do not extend through the planarization layer PLN.

[0175] In some embodiments, the second passivation layer PVX2 includes a plurality of first strips BA1 and a plurality of second strips BA2. The plurality of first strips BA1 are respectively located in a plurality of first columns; and the plurality of second strips BA2 are respectively located in a plurality of second columns.

[0176] In some embodiments, the anode layer ADL includes a plurality of anodes arranged in a plurality of first columns and a plurality of second columns. Each pixel in the plurality of pixels includes a first anode AD1 in a first sub-pixel Sp1, a second anode AD2 in a second sub-pixel Sp2, and a third anode AD3 in a third sub-pixel Sp3.

[0177] In some embodiments, the orthographic projection of each of the plurality of first strips BA1 on the substrate BS at least partially overlaps with the orthographic projection of the anode (e.g., first anode AD1 and second anode AD2) in the corresponding first column of the plurality of first columns. In some embodiments, the orthographic projection of each of the plurality of second strips BA2 on the substrate BS at least partially overlaps with the orthographic projection of the anode (e.g., third anode AD3) in the corresponding second column of the plurality of second columns.

[0178] In some embodiments, the orthographic projection of each of the plurality of first strips BA1 onto the substrate BS overlaps the orthographic projection of the anode (e.g., first anode AD1 and second anode AD2) in the corresponding first column of the plurality of first columns. In some embodiments, the orthographic projection of each of the plurality of second strips BA2 onto the substrate BS overlaps the orthographic projection of the anode (e.g., third anode AD3) in the corresponding second column of the plurality of second columns.

[0179] In some embodiments, the array substrate includes a plurality of second recesses RES2 extending into the second passivation layer PVX2. The second recesses of the plurality of second recesses RES2 partially surround sub-pixel openings in a plurality of sub-pixel openings SA. In one example, two second recesses of the plurality of second recesses RES2 partially surround a sub-pixel opening on opposite sides.

[0180] In some embodiments, a first recess in a plurality of first recesses RES1 partially surrounds a second recess in a plurality of second recesses RES2. In one example, two first recesses in a plurality of first recesses RES1 partially surround two second recesses in a plurality of second recesses RES2.

[0181] In some embodiments, a plurality of second recesses RES2 are present in a plurality of first strips BA1 but not in a plurality of second strips BA2.

[0182] In some embodiments, the array substrate includes a plurality of sub-pixel openings SA extending through the pixel defining layer PDL and a plurality of grooves extending through the pixel defining layer PDL. In some embodiments, the orthographic projection of each groove in the plurality of grooves GV onto the substrate BS at least partially overlaps with the orthographic projection of a corresponding first recess in the plurality of first recesses RES1 onto the substrate BS; and at least partially overlaps with the orthographic projection of a corresponding second recess in the plurality of second recesses RES2 onto the substrate BS.

[0183] In some embodiments, the orthographic projection of each of the plurality of grooves GV onto the substrate BS covers the orthographic projection of the corresponding first recess in the plurality of first recesses RES1 onto the substrate BS; and covers the orthographic projection of the corresponding second recess in the plurality of second recesses RES2 onto the substrate BS.

[0184] In some embodiments, the grooves in the plurality of grooves GV partially surround the sub-pixel openings in the plurality of sub-pixel openings SA. In one example, two grooves in the plurality of grooves GV partially surround the sub-pixel openings on opposite sides.

[0185] Reference Figure 7A and Figure 7G In some embodiments, the array substrate includes a plurality of recesses RES. Each recess in the plurality of recesses RES includes a corresponding first recess in a plurality of first recesses RES1 and a corresponding second recess in a plurality of second recesses RES2. In some embodiments, the orthographic projections of each first recess on the substrate do not overlap with the orthographic projections of each second recess on the substrate.

[0186] The inventors of this disclosure have discovered that, by having a plurality of grooves GV, a plurality of first recesses RES1 and a plurality of second recesses RES2, when an organic material layer (e.g., a common layer such as a hole transport layer or an electron transport layer) is deposited on an array substrate, the plurality of grooves GV, the plurality of first recesses RES1 and the plurality of second recesses RES2 at least partially isolate the organic material layer into discontinuous segments, thereby defining a plurality of sub-pixels.

[0187] exist Figures 7A to 7G as well as Figure 5 In the example shown, two of the multiple grooves GV that partially surround the sub-pixel opening have a partially annular shape; two of the multiple first recesses RES1 that partially surround the sub-pixel opening have a partially annular shape; and two of the multiple second recesses RES2 that partially surround the sub-pixel opening have a partially annular shape.

[0188] In some embodiments, a plurality of first strips BA1 and a plurality of second strips BA2 are arranged along a first direction DR1, and the plurality of first strips BA1 and the plurality of second strips BA2 extend along a second direction DR2. In some embodiments, two grooves in a plurality of grooves GV that partially surround the subpixel opening of a first subpixel Sp1 are arranged along the first direction DR1. In some embodiments, two grooves in a plurality of grooves GV that partially surround the subpixel opening of a second subpixel Sp2 are arranged along a third direction DR3, wherein the third direction DR3 is different from the first direction DR1 and different from the second direction DR2.

[0189] In some embodiments, two first recesses of the plurality of first recesses RES1 that partially surround the subpixel opening of the first subpixel Sp1 are arranged along a first direction DR1. In some embodiments, two first recesses of the plurality of first recesses RES1 that partially surround the subpixel opening of the second subpixel Sp2 are arranged along a third direction DR3, wherein the third direction DR3 is different from the first direction DR1 and different from the second direction DR2.

[0190] In some embodiments, two second recesses of the plurality of second recesses RES2 that partially surround the subpixel opening of the first subpixel Sp1 are arranged along a first direction DR1. In some embodiments, two second recesses of the plurality of second recesses RES2 that partially surround the subpixel opening of the second subpixel Sp2 are arranged along a third direction DR3, wherein the third direction DR3 is different from the first direction DR1 and different from the second direction DR2.

[0191] In some embodiments, the orthographic projection of at least two of the two grooves in the plurality of grooves GV that partially surround the subpixel opening of the second subpixel Sp2 on the substrate at least partially overlaps with the orthographic projection of the anode connection pads in the plurality of anode connection pads ACP connected to the first anode AD1 in the first subpixel Sp1 on the substrate. The inventors of this disclosure have found that this structure can better isolate the organic material layer when it is deposited on the array substrate.

[0192] In some embodiments, the orthographic projection of at least one of the two first recesses in the plurality of first recesses RES1 that partially surround the subpixel opening of the second subpixel Sp2 on the substrate at least partially overlaps with the orthographic projection of the anode connection pads in the plurality of anode connection pads ACP connected to the first anode AD1 in the first subpixel Sp1 on the substrate. The inventors of this disclosure have found that this structure can better isolate the organic material layer when it is deposited on the array substrate.

[0193] In some embodiments, the orthographic projection of at least one of the two second recesses RES2 that partially surround the subpixel opening of the second subpixel Sp2 on the substrate at least partially overlaps with the orthographic projection of the anode connection pads ACP of the plurality of anode connection pads ACP connected to the first anode AD1 in the first subpixel Sp1 on the substrate. The inventors of this disclosure have found that this structure can better isolate the organic material layer when it is deposited on the array substrate.

[0194] In some embodiments, the grooves in the plurality of grooves GV that partially surround the subpixel opening of the first subpixel Sp1 and the grooves in the plurality of grooves GV that partially surround the subpixel opening of the second subpixel Sp2 are interconnected. The inventors of this disclosure have found that this structure produces lower crosstalk.

[0195] In some embodiments, a first recess in a plurality of first recesses RES1 that partially surrounds a subpixel opening of a first subpixel Sp1 and a first recess in a plurality of first recesses RES1 that partially surrounds a subpixel opening of a second subpixel Sp2 are interconnected. The inventors of this disclosure have found that this structure produces lower crosstalk.

[0196] In some embodiments, the second recesses in the plurality of second recesses RES2 that partially surround the subpixel opening of the first subpixel Sp1 and the second recesses in the plurality of second recesses RES2 that partially surround the subpixel opening of the second subpixel Sp2 are spaced apart from each other.

[0197] Figure 8A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 8B This is a schematic diagram illustrating the structure of a third signal line layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 8C This is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 8D This is a schematic diagram illustrating the structure of a second passivation layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 8E This is a schematic diagram illustrating the structure of the anode layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 8F This is a schematic diagram illustrating the structure of a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 8G This is a schematic diagram illustrating the structure of a plurality of recesses in a portion of an array substrate according to some embodiments of the present disclosure. In one example, Figure 5 It can be along Figure 8A A cross-sectional view of the D-D' line in the diagram.

[0198] In some embodiments, the array substrate includes a substrate BS; a third signal line layer SL3 located on the substrate BS; a planarization layer PLN located on the side of the third signal line layer SL3 away from the substrate BS; a second passivation layer PVX2 located on the side of the planarization layer PLN away from the substrate BS; an anode layer ADL located on the side of the second passivation layer PVX2 away from the substrate BS; and a pixel defining layer PDL located on the side of the anode layer ADL away from the substrate BS.

[0199] In some embodiments, the third signal line layer includes multiple power lines (e.g., corresponding power lines Vdd), multiple data lines (e.g., corresponding data lines DL), and multiple anode connection pads (e.g., corresponding anode connection pads ACP).

[0200] In some embodiments, the array substrate includes a plurality of first recesses RES1 extending into the planarization layer PLN. A first recess of the plurality of first recesses RES1 partially surrounds a sub-pixel opening in a plurality of sub-pixel openings SA. In one example, two first recesses of the plurality of first recesses RES1 partially surround a sub-pixel opening on opposite sides.

[0201] In some embodiments, the array substrate includes a plurality of pixels. In some embodiments, each of the plurality of pixels includes a first sub-pixel Sp1, a second sub-pixel Sp2, and a third sub-pixel Sp3. Optionally, the first sub-pixel Sp1, the second sub-pixel Sp2, and the third sub-pixel Sp3 are sub-pixels of different colors.

[0202] In some embodiments, the subpixels of the array substrate are arranged in a plurality of first columns and a plurality of second columns. The plurality of first columns and the plurality of second columns are arranged alternately. In some embodiments, a first subpixel Sp1 and a second subpixel Sp2 are located in the first column of the plurality of first columns, and a third subpixel Sp3 is located in the second column of the plurality of second columns. In some embodiments, a plurality of first recesses RES1 are present in the plurality of first columns but not in the plurality of second columns.

[0203] In some embodiments, the plurality of first recesses RES1 extend partially into the planarization layer PLN, for example, the plurality of first recesses RES1 do not extend through the planarization layer PLN.

[0204] In some embodiments, the second passivation layer PVX2 includes a plurality of first strips BA1 and a plurality of second strips BA2. The plurality of first strips BA1 are respectively located in a plurality of first columns; and the plurality of second strips BA2 are respectively located in a plurality of second columns.

[0205] In some embodiments, the anode layer ADL includes a plurality of anodes arranged in a plurality of first columns and a plurality of second columns. Each pixel in the plurality of pixels includes a first anode AD1 in a first sub-pixel Sp1, a second anode AD2 in a second sub-pixel Sp2, and a third anode AD3 in a third sub-pixel Sp3.

[0206] In some embodiments, the orthographic projection of each of the plurality of first strips BA1 on the substrate BS at least partially overlaps with the orthographic projection of the anode (e.g., first anode AD1 and second anode AD2) in the corresponding first column of the plurality of first columns. In some embodiments, the orthographic projection of each of the plurality of second strips BA2 on the substrate BS at least partially overlaps with the orthographic projection of the anode (e.g., third anode AD3) in the corresponding second column of the plurality of second columns.

[0207] In some embodiments, the orthographic projection of each of the plurality of first strips BA1 onto the substrate BS overlaps the orthographic projection of the anode (e.g., first anode AD1 and second anode AD2) in the corresponding first column of the plurality of first columns. In some embodiments, the orthographic projection of each of the plurality of second strips BA2 onto the substrate BS overlaps the orthographic projection of the anode (e.g., third anode AD3) in the corresponding second column of the plurality of second columns.

[0208] In some embodiments, the array substrate includes a plurality of second recesses RES2 extending into the second passivation layer PVX2. The second recesses of the plurality of second recesses RES2 partially surround sub-pixel openings in a plurality of sub-pixel openings SA. In one example, two second recesses of the plurality of second recesses RES2 partially surround a sub-pixel opening on opposite sides.

[0209] In some embodiments, a first recess in a plurality of first recesses RES1 partially surrounds a second recess in a plurality of second recesses RES2. In one example, two first recesses in a plurality of first recesses RES1 partially surround two second recesses in a plurality of second recesses RES2.

[0210] In some embodiments, a plurality of second recesses RES2 are present in a plurality of first strips BA1 but not in a plurality of second strips BA2.

[0211] In some embodiments, the array substrate includes a plurality of sub-pixel openings SA extending through the pixel defining layer PDL and a plurality of grooves extending through the pixel defining layer PDL. In some embodiments, the orthographic projection of each groove in the plurality of grooves GV onto the substrate BS at least partially overlaps with the orthographic projection of a corresponding first recess in the plurality of first recesses RES1 onto the substrate BS; and at least partially overlaps with the orthographic projection of a corresponding second recess in the plurality of second recesses RES2 onto the substrate BS.

[0212] In some embodiments, the orthographic projection of each of the plurality of grooves GV on the substrate BS covers the orthographic projection of the corresponding first recess in the plurality of first recesses RES1 on the substrate BS; and covers the orthographic projection of the corresponding second recess in the plurality of second recesses RES2 on the substrate BS.

[0213] In some embodiments, the grooves in the plurality of grooves GV partially surround the sub-pixel openings in the plurality of sub-pixel openings SA. In one example, two grooves in the plurality of grooves GV partially surround the sub-pixel openings on opposite sides.

[0214] Reference Figure 8A and Figure 8G In some embodiments, the array substrate includes a plurality of recesses RES. Each of the plurality of recesses RES includes a corresponding first recess in a plurality of first recesses RES1 and a corresponding second recess in a plurality of second recesses RES2. In some embodiments, the orthographic projections of each first recess on the substrate do not overlap with the orthographic projections of each second recess on the substrate.

[0215] The inventors of this disclosure have discovered that, by having a plurality of grooves GV, a plurality of first recesses RES1 and a plurality of second recesses RES2, when an organic material layer (e.g., a common layer such as a hole transport layer or an electron transport layer) is deposited on an array substrate, the plurality of grooves GV, the plurality of first recesses RES1 and the plurality of second recesses RES2 at least partially isolate the organic material layer into discontinuous segments, thereby defining a plurality of sub-pixels.

[0216] exist Figures 8A to 8G as well as Figure 5 In the example shown, each of the plurality of grooves GV has a rectangular shape; each of the plurality of first recesses RES1 has a rectangular shape; and each of the plurality of second recesses RES2 has a rectangular shape. Optionally, the longitudinal side of the rectangular shape extends along the second direction DR2.

[0217] In some embodiments, a plurality of first strips BA1 and a plurality of second strips BA2 are arranged along a first direction DR1, and the plurality of first strips BA1 and the plurality of second strips BA2 extend along a second direction DR2. In some embodiments, two recesses in a plurality of recesses GV that partially surround the sub-pixel opening are arranged along the first direction DR1. In some embodiments, two first recesses in a plurality of first recesses RES1 that partially surround the sub-pixel opening are arranged along the first direction DR1. In some embodiments, two second recesses in a plurality of second recesses RES2 that partially surround the sub-pixel opening are arranged along the first direction DR1.

[0218] Figure 9A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 9B This is a schematic diagram illustrating the structure of a third signal line layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 9C This is a schematic diagram illustrating the structure of a planarization layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 9D This is a schematic diagram illustrating the structure of a second passivation layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 9E This is a schematic diagram illustrating the structure of the anode layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 9F This is a schematic diagram illustrating the structure of a pixel defining layer in a portion of an array substrate according to some embodiments of the present disclosure. Figure 9G This is a schematic diagram illustrating the structure of a plurality of recesses in a portion of an array substrate according to some embodiments of the present disclosure. In one example, Figure 5 It can be along Figure 9A A cross-sectional view of the E-E' line in the diagram.

[0219] In some embodiments, the array substrate includes a substrate BS; a third signal line layer SL3 located on the substrate BS; a planarization layer PLN located on the side of the third signal line layer SL3 away from the substrate BS; a second passivation layer PVX2 located on the side of the planarization layer PLN away from the substrate BS; an anode layer ADL located on the side of the second passivation layer PVX2 away from the substrate BS; and a pixel defining layer PDL located on the side of the anode layer ADL away from the substrate BS.

[0220] In some embodiments, the third signal line layer includes multiple power lines (e.g., corresponding power lines Vdd), multiple data lines (e.g., corresponding data lines DL), and multiple anode connection pads (e.g., corresponding anode connection pads ACP).

[0221] In some embodiments, the array substrate includes a plurality of first recesses RES1 extending into the planarization layer PLN. A first recess of the plurality of first recesses RES1 partially surrounds a sub-pixel opening in a plurality of sub-pixel openings SA. In one example, two first recesses of the plurality of first recesses RES1 partially surround a sub-pixel opening on opposite sides.

[0222] In some embodiments, the array substrate includes a plurality of pixels. In some embodiments, each of the plurality of pixels includes a first sub-pixel Sp1, a second sub-pixel Sp2, and a third sub-pixel Sp3. Optionally, the first sub-pixel Sp1, the second sub-pixel Sp2, and the third sub-pixel Sp3 are sub-pixels of different colors.

[0223] In some embodiments, the subpixels of the array substrate are arranged in a plurality of first columns and a plurality of second columns. The plurality of first columns and the plurality of second columns are arranged alternately. In some embodiments, a first subpixel Sp1 and a second subpixel Sp2 are located in the first column of the plurality of first columns, and a third subpixel Sp3 is located in the second column of the plurality of second columns. In some embodiments, a plurality of first recesses RES1 are present in the plurality of first columns but not in the plurality of second columns.

[0224] In some embodiments, the plurality of first recesses RES1 extend partially into the planarization layer PLN, for example, the plurality of first recesses RES1 do not extend through the planarization layer PLN.

[0225] In some embodiments, the second passivation layer PVX2 includes a plurality of first strips BA1 and a plurality of second strips BA2. The plurality of first strips BA1 are respectively located in a plurality of first columns; and the plurality of second strips BA2 are respectively located in a plurality of second columns.

[0226] In some embodiments, the anode layer ADL includes a plurality of anodes arranged in a plurality of first columns and a plurality of second columns. Each pixel in the plurality of pixels includes a first anode AD1 in a first sub-pixel Sp1, a second anode AD2 in a second sub-pixel Sp2, and a third anode AD3 in a third sub-pixel Sp3.

[0227] In some embodiments, the orthographic projection of each of the plurality of first strips BA1 on the substrate BS at least partially overlaps with the orthographic projection of the anode (e.g., first anode AD1 and second anode AD2) in the corresponding first column of the plurality of first columns. In some embodiments, the orthographic projection of each of the plurality of second strips BA2 on the substrate BS at least partially overlaps with the orthographic projection of the anode (e.g., third anode AD3) in the corresponding second column of the plurality of second columns.

[0228] In some embodiments, the orthographic projection of each of the plurality of first strips BA1 onto the substrate BS overlaps the orthographic projection of the anode (e.g., first anode AD1 and second anode AD2) in the corresponding first column of the plurality of first columns. In some embodiments, the orthographic projection of each of the plurality of second strips BA2 onto the substrate BS overlaps the orthographic projection of the anode (e.g., third anode AD3) in the corresponding second column of the plurality of second columns.

[0229] In some embodiments, the array substrate includes a plurality of second recesses RES2 extending into the second passivation layer PVX2. The second recesses of the plurality of second recesses RES2 partially surround sub-pixel openings in a plurality of sub-pixel openings SA. In one example, two second recesses of the plurality of second recesses RES2 partially surround a sub-pixel opening on opposite sides.

[0230] In some embodiments, a first recess in a plurality of first recesses RES1 partially surrounds a second recess in a plurality of second recesses RES2. In one example, two first recesses in a plurality of first recesses RES1 partially surround two second recesses in a plurality of second recesses RES2.

[0231] In some embodiments, a plurality of second recesses RES2 are present in a plurality of first strips BA1 but not in a plurality of second strips BA2.

[0232] In some embodiments, the array substrate includes a plurality of sub-pixel openings SA extending through the pixel defining layer PDL and a plurality of grooves extending through the pixel defining layer PDL. In some embodiments, the orthographic projection of each groove in the plurality of grooves GV onto the substrate BS at least partially overlaps with the orthographic projection of a corresponding first recess in the plurality of first recesses RES1 onto the substrate BS; and at least partially overlaps with the orthographic projection of a corresponding second recess in the plurality of second recesses RES2 onto the substrate BS.

[0233] In some embodiments, the orthographic projection of each of the plurality of grooves GV on the substrate BS covers the orthographic projection of the corresponding first recess in the plurality of first recesses RES1 on the substrate BS; and covers the orthographic projection of the corresponding second recess in the plurality of second recesses RES2 on the substrate BS.

[0234] In some embodiments, the grooves in the plurality of grooves GV partially surround the sub-pixel openings in the plurality of sub-pixel openings SA. In one example, two grooves in the plurality of grooves GV partially surround the sub-pixel openings on opposite sides.

[0235] Reference Figure 9A and Figure 9GIn some embodiments, the array substrate includes a plurality of recesses RES. Each of the plurality of recesses RES includes a corresponding first recess in a plurality of first recesses RES1 and a corresponding second recess in a plurality of second recesses RES2. In some embodiments, the orthographic projections of each first recess on the substrate do not overlap with the orthographic projections of each second recess on the substrate.

[0236] The inventors of this disclosure have discovered that, by having a plurality of grooves GV, a plurality of first recesses RES1 and a plurality of second recesses RES2, when an organic material layer (e.g., a common layer such as a hole transport layer or an electron transport layer) is deposited on an array substrate, the plurality of grooves GV, the plurality of first recesses RES1 and the plurality of second recesses RES2 at least partially isolate the organic material layer into discontinuous segments, thereby defining a plurality of sub-pixels.

[0237] exist Figures 9A to 9G as well as Figure 5 In the example shown, each of the multiple grooves GV has an L-shaped shape; each of the multiple first recesses RES1 has an L-shaped shape; and each of the multiple second recesses RES2 has an L-shaped shape.

[0238] In another aspect, the present invention provides a display device comprising an array substrate manufactured as described herein or by means of the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device.

[0239] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate, comprising: Substrate; A signal line layer, which is located on the substrate and includes a plurality of signal lines; A planarization layer is located on the side of the signal line layer away from the substrate. A passivation layer is located on the side of the planarization layer away from the substrate. An anode layer is located on the side of the passivation layer away from the substrate. A pixel defining layer is located on the side of the anode layer away from the substrate. Multiple grooves extending through the pixel-defining layer; Multiple first recesses extend into the planarization layer; as well as Multiple second recesses extend into the passivation layer.

2. The array substrate according to claim 1, wherein, The orthographic projection of each of the plurality of grooves on the substrate at least partially overlaps with the orthographic projection of the corresponding first recess of the plurality of first recesses on the substrate; and at least partially overlaps with the orthographic projection of the corresponding second recess of the plurality of second recesses on the substrate.

3. The array substrate according to claim 1, wherein, Two of the plurality of first recesses partially surround the sub-pixel opening on opposite sides; Two of the plurality of second recesses partially surround the sub-pixel opening on opposite sides; and Two of the plurality of grooves partially surround the sub-pixel opening on opposite sides.

4. The array substrate according to any one of claims 1 to 3, comprising a plurality of pixels; in, Each of the plurality of pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; The subpixels of the array substrate are arranged in a plurality of first columns and a plurality of second columns; The plurality of first columns and the plurality of second columns are arranged alternately; The first sub-pixel and the second sub-pixel are located in the first column of the plurality of first columns; as well as The third sub-pixel is located in the second column of the plurality of second columns.

5. The array substrate according to claim 4, wherein, The plurality of first recesses, the plurality of second recesses, and the plurality of grooves are present in the plurality of first columns but not in the plurality of second columns.

6. The array substrate according to any one of claims 1 to 5, wherein, The second passivation layer includes a plurality of first strips and a plurality of second strips; The plurality of first strips are respectively located in a plurality of first columns; and The plurality of second strips are located in the plurality of second columns.

7. The array substrate according to claim 6, wherein, The anode layer includes a plurality of anodes arranged in a plurality of first columns and a plurality of second columns; The orthographic projection of a corresponding first strip among the plurality of first strips on the substrate at least partially overlaps with the orthographic projection of the anode in the corresponding first column among the plurality of first columns; as well as The orthographic projection of a corresponding second strip among the plurality of second strips on the substrate at least partially overlaps with the orthographic projection of the anode in the corresponding second column among the plurality of second columns.

8. The array substrate according to claim 7, comprising a plurality of pixels; in, Each of the plurality of pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; Each pixel includes a first anode in a first sub-pixel, a second anode in a second sub-pixel, and a third anode in a third sub-pixel; The orthographic projection of a corresponding first strip among the plurality of first strips on the substrate at least partially overlaps with the orthographic projection of the first anode and the second anode in the corresponding first column among the plurality of first columns; as well as The orthographic projection of a corresponding second strip among the plurality of second strips on the substrate at least partially overlaps with the orthographic projection of the third anode in a corresponding second column among the plurality of second columns.

9. The array substrate according to claim 6, wherein, The plurality of second recesses are present in the plurality of first strips, but not in the plurality of second strips.

10. The array substrate according to any one of claims 1 to 9, wherein, Two of the plurality of first recesses partially surround two of the plurality of second recesses.

11. The array substrate according to any one of claims 1 to 10, wherein, The orthographic projection of a corresponding groove in the plurality of grooves on the substrate covers the orthographic projection of a corresponding first recess in the plurality of first recesses on the substrate; and covers the orthographic projection of a corresponding second recess in the plurality of second recesses on the substrate; as well as The orthographic projection of the corresponding first recess on the substrate does not overlap with the orthographic projection of the corresponding second recess on the substrate.

12. The array substrate according to any one of claims 1 to 11, wherein, Two of the plurality of grooves that partially surround the sub-pixel opening have a partially annular shape; Two of the plurality of first recesses, partially surrounding the sub-pixel opening, have a partially annular shape; and Two of the plurality of second recesses that partially surround the sub-pixel opening have a partially annular shape.

13. The array substrate according to claim 6, wherein, The plurality of first strips and the plurality of second strips are arranged along a first direction; The plurality of first strips and the plurality of second strips extend along a second direction; Two of the plurality of grooves that partially surround the sub-pixel opening are arranged along the first direction; Two of the plurality of first recesses that partially surround the sub-pixel opening are arranged along the first direction; as well as Two of the plurality of second recesses, which partially surround the sub-pixel opening, are arranged along the first direction.

14. The array substrate according to claim 6, comprising a plurality of pixels; in, Each of the plurality of pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; The subpixels of the array substrate are arranged in a plurality of first columns and a plurality of second columns; The plurality of first columns and the plurality of second columns are arranged alternately; The first sub-pixel and the second sub-pixel are located in the first column of the plurality of first columns; as well as The third sub-pixel is located in the second column of the plurality of second columns; The plurality of first strips and the plurality of second strips are arranged along a first direction; The plurality of first strips and the plurality of second strips extend along a second direction; Two of the plurality of grooves that partially surround the sub-pixel opening of the first sub-pixel are arranged along the first direction; Two of the plurality of grooves, partially surrounding the sub-pixel opening of the second sub-pixel, are arranged along a third direction; and The third direction is different from the first direction and different from the second direction.

15. The array substrate according to claim 4, wherein, At least one of the two grooves that partially surround the sub-pixel opening of the second sub-pixel has its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the anode connection pad of the plurality of anode connection pads connected to the first anode in the first sub-pixel on the substrate. At least one of the two first recesses that partially surround the sub-pixel opening of the second sub-pixel has its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the anode connection pad of the plurality of anode connection pads connected to the first anode in the first sub-pixel on the substrate. as well as At least one of the two second recesses that partially surround the sub-pixel opening of the second sub-pixel has its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the anode connection pad of the plurality of anode connection pads connected to the first anode in the first sub-pixel on the substrate.

16. The array substrate according to claim 4, wherein, The groove that partially surrounds the sub-pixel opening of the first sub-pixel is interconnected with the groove that partially surrounds the sub-pixel opening of the second sub-pixel. as well as A first recess that partially surrounds the sub-pixel opening of the first sub-pixel is interconnected with a first recess that partially surrounds the sub-pixel opening of the second sub-pixel.

17. The array substrate according to claim 16, wherein, The second recesses that partially surround the sub-pixel opening of the first sub-pixel are spaced apart from the second recesses that partially surround the sub-pixel opening of the second sub-pixel.

18. The array substrate according to any one of claims 1 to 11, wherein, Each of the plurality of grooves has a rectangular shape; Each of the plurality of first recesses has a rectangular shape; and Each of the plurality of second recesses has a rectangular shape.

19. The array substrate according to any one of claims 1 to 11, wherein, Each of the plurality of grooves has an L-shaped shape; Each of the plurality of first recesses has an L-shaped shape; as well as Each of the plurality of second recesses has an L-shaped form.

20. A display device comprising an array substrate according to any one of claims 1 to 19, and one or more integrated circuits connected to the array substrate.

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