Display substrate, display device, and display motherboard

Abstract

A display substrate is provided, comprising: a substrate (100), a first type of contact pad (51) located in a first signal access area (251), a second type of contact pad (52) and a first type of test unit (31), and a third type of contact pad (53) located in a second signal access area (252). The first type of test unit (31) is located between the first type of contact pad (51) and the second type of contact pad (52). The first type of contact pad (51) comprises: a plurality of data contact pads (511) and a plurality of first control contact pads (512), and the first type of test unit (31) is connected with at least part of the plurality of data contact pads (511). The third type of contact pad (53) comprises: a plurality of second control contact pads (531) and a plurality of third control contact pads (532), the plurality of third control contact pads (532) are connected with some of the second type of contact pad (52), and the plurality of second control contact pads (531) are connected with the plurality of first control contact pads (512).

Description

Display substrate, display device and display motherboard TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the technical field of display, and in particular to a display substrate, a display device and a display motherboard. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility and low cost. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0004] The embodiments of the present disclosure provide a display substrate, a display device and a display motherboard.

[0005] In one aspect, the embodiments provide a display substrate, comprising: a substrate, a first type of contact pad, a second type of contact pad, a third type of contact pad and a first type of test unit. The substrate comprises a display area and a first frame area located on one side of the display area, the first frame area comprising: at least one first signal access area and at least one second signal access area, the second signal access area being located on the side of the first signal access area away from the display area. The first type of contact pad, the second type of contact pad and the first type of test unit are located in the first signal access area, the second type of contact pad is located on the side of the first type of contact pad close to the second signal access area, and the first type of test unit is located between the first type of contact pad and the second type of contact pad; the first type of contact pad comprises: a plurality of data contact pads and a plurality of first control contact pads, the first type of test unit is connected with at least part of the plurality of data contact pads and is configured to transmit test data signals to at least part of the plurality of data contact pads in a first test stage. The third type of contact pad is located in the second signal access area, and the third type of contact pad comprises: a plurality of second control contact pads and a plurality of third control contact pads, the plurality of third control contact pads are connected with some of the second type of contact pads, and the plurality of second control contact pads are connected with the plurality of first control contact pads and are configured to transmit a first type of test control signal in the first test stage.

[0006] In some example embodiments, the first type of test unit comprises: a plurality of first test contact pads, and a single first test contact pad is connected with one data contact pad.

[0007] In some example embodiments, the first type of test unit includes a plurality of first test contact pads and a plurality of first multiplexing circuits, the plurality of first multiplexing circuits are located on a side of the plurality of first test contact pads close to the first type of contact pads, and are connected with the plurality of data contact pads and the plurality of first test contact pads. At least one of the plurality of first multiplexing circuits is configured to provide a test data signal transmitted by at least one of the plurality of first test contact pads to the connected plurality of data contact pads.

[0008] In some example embodiments, the display substrate further includes a first insulating protective layer located at the first signal access area, the first insulating protective layer covers the orthographic projection of the plurality of first multiplexing circuits on the orthographic projection of the base.

[0009] In some example embodiments, the plurality of first multiplexing circuits includes a plurality of vias, and a minimum distance between an edge via of the plurality of vias and an edge of the first insulating protective layer is greater than or equal to 10 microns.

[0010] In some example embodiments, the first type of test unit further includes a plurality of multiplexing control lines and a plurality of multiplexing control contact pads, the plurality of multiplexing control contact pads are connected with the plurality of multiplexing control lines one by one, and the plurality of multiplexing control contact pads are located on at least one side of the plurality of first test contact pads in one direction.

[0011] In some example embodiments, the first type of test unit further includes a plurality of first invalid contact pads, at least one of the plurality of first invalid contact pads is located between two adjacent multiplexing control contact pads of the plurality of multiplexing control contact pads, or between the plurality of multiplexing control contact pads and an adjacent first test contact pad.

[0012] In some example embodiments, the display substrate further includes a plurality of first resistance strips located at the first signal access area, one end of the first resistance strip is connected with one multiplexing control contact pad and one multiplexing control line, the other end of the first resistance strip is configured to receive a stabilized voltage signal, and the resistivity of the first resistance strip is greater than the resistivity of the multiplexing control line.

[0013] In some example embodiments, the display substrate further includes a second insulating protective layer located at the first signal access area, the second insulating protective layer covers the orthographic projection of the plurality of first resistance strips on the orthographic projection of the base.

[0014] In another aspect, the present embodiment provides a display device including the display substrate as described above.

[0015] In another aspect, the present embodiments provide a display mother board, comprising: a plurality of substrate regions and a cutting region surrounding the substrate regions; the substrate regions comprising: a display region and a first bezel region located at a side of the display region, the first bezel region comprising: at least one first signal access region and at least one second signal access region, the second signal access region located at a side of the first signal access region away from the display region. The display mother board comprising: a first type of contact pad, a second type of contact pad, a third type of contact pad, a first type of test unit and a second type of test unit. The first type of contact pad, the second type of contact pad and the first type of test unit are located in the first signal access region, the second type of contact pad is located at a side of the first type of contact pad close to the second signal access region, and the first type of test unit is located between the first type of contact pad and the second type of contact pad; the first type of contact pad comprising: a plurality of data contact pads and a plurality of first control contact pads, the first type of test unit being connected to at least part of the plurality of data contact pads and configured to transmit a test data signal to at least part of the plurality of data contact pads in a first test stage. The third type of contact pad is located in the second signal access region, the third type of contact pad comprising: a plurality of second control contact pads and a plurality of third control contact pads, the plurality of third control contact pads being connected to some of the second type of contact pad, and the plurality of second control contact pads being connected to the plurality of first control contact pads. The second type of test unit is located in the cutting region, the second type of test unit being connected to the plurality of second control contact pads and configured to provide a first type of test control signal to the plurality of second control contact pads in the first test stage.

[0016] In some example embodiments, the first bezel region is located at a side of the display region along a first direction, and the first signal access region has a first center line extending along the first direction; and the second type of test unit is close to the first center line.

[0017] In some example embodiments, the display mother board further comprises: a third type of test unit located in the cutting region, the third type of test unit being configured to provide a second type of test control signal to the plurality of second control contact pads in a second test stage.

[0018] In some example embodiments, the display mother board further comprises: a plurality of first connection lines and a plurality of second connection lines located in the cutting region, the second type of test unit being connected to the plurality of second connection lines through the plurality of first connection lines, and the third type of test unit being connected to the plurality of second control contact pads through the plurality of second connection lines.

[0019] In some example embodiments, the second type of test unit is close to the plurality of second connection lines.

[0020] In some example embodiments, the display mother substrate further comprises: a plurality of second resistive strips located in the cutting region; the second type of test unit comprises: a plurality of second test contact pads, at least one second test contact pad in the plurality of second test contact pads is connected with the first connection line through at least one second resistive strip, the resistivity of the second resistive strip is greater than the resistivity of the first connection line.

[0021] In some example embodiments, the second test contact pad connected with the second resistive strip is configured to provide a start signal to the gate driving circuit.

[0022] In some example embodiments, the display mother substrate further comprises: a first transfer electrode and a second transfer electrode located in the cutting region; the first connection line is connected with the second resistive strip through the first transfer electrode, the first transfer electrode is located on the side of the first connection line and the second resistive strip away from the substrate, the second transfer electrode is located on the side of the first transfer electrode away from the substrate and is connected with the first transfer electrode, the second transfer electrode covers the projection of the first transfer electrode on the substrate.

[0023] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description.

[0024] SUMMARY

[0025] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0026] FIG. 1 is a schematic diagram of a display mother substrate according to at least one embodiment of the present disclosure;

[0027] FIG. 2A is a schematic diagram of a partial cross-section of a display region according to at least one embodiment of the present disclosure;

[0028] FIG. 2B is another schematic diagram of a partial cross-section of a display region of a display substrate according to at least one embodiment of the present disclosure;

[0029] FIG. 3 is a schematic diagram of a display mother substrate according to at least one embodiment of the present disclosure;

[0030] FIG. 4 is a schematic diagram of a partial cross-section of a contact pad of a first type of test unit according to at least one embodiment of the present disclosure;

[0031] FIG. 5 is a schematic diagram of a connection relationship between a first type of test unit and a first type of contact pad in a first signal access region according to at least one embodiment of the present disclosure;

[0032] FIG. 6 is a partial enlarged view of a second sub-region and a cutting region according to at least one embodiment of the present disclosure;

[0033] FIG. 7 is a partial enlarged view of a first signal access region of the second sub-region according to at least one embodiment of the present disclosure;

[0034] FIG. 8A is a partial schematic view of a plurality of first multiplexing circuits according to at least one embodiment of the present disclosure;

[0035] FIG. 8B is a schematic view of the semiconductor layer, the first gate metal layer, the second gate metal layer and the first source-drain metal layer in FIG. 8A;

[0036] FIG. 8C is a schematic view of the semiconductor layer, the first gate metal layer and the second gate metal layer in FIG. 8A;

[0037] FIG. 9A is a schematic view of the connection between a multiplexing control contact pad and a multiplexing control line according to at least one embodiment of the present disclosure;

[0038] FIG. 9B is a schematic view of the semiconductor layer, the first gate metal layer and the second gate metal layer in FIG. 9A;

[0039] FIG. 9C is a schematic view of the semiconductor layer, the first gate metal layer, the second gate metal layer and the first source-drain metal layer in FIG. 9A;

[0040] FIG. 10 is a partial schematic view of a second type of test unit according to at least one embodiment of the present disclosure;

[0041] FIG. 11 is a partial enlarged view of region U1 in FIG. 10;

[0042] FIG. 12 is a partial enlarged view of FIG. 10 along the direction of QQ';

[0043] FIG. 13 is another partial enlarged view of FIG. 10 along the direction of QQ';

[0044] FIG. 14 is another partial schematic view of a second sub-region and a cutting region according to at least one embodiment of the present disclosure;

[0045] FIG. 15 is a schematic view of a display device according to at least one embodiment of the present disclosure.

[0046] Detailed Description

[0047] Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. Embodiments can be implemented in various forms. One of ordinary skill in the art can easily understand that the manner and content can be changed into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. Embodiments in the present disclosure and features in the embodiments can be arbitrarily combined with each other without conflict.

[0048] In the drawings, the size, the thickness, or the region of one or a plurality of components is sometimes exaggerated, and the shape, the relative size, or the like of one or a plurality of components is sometimes schematically illustrated for the purpose of clarity. Thus, one embodiment of the present disclosure is not necessarily limited to that illustrated in the drawings. The present disclosure is not necessarily limited to the shape, the numerical value, or the like illustrated in the drawings.

[0049] The ordinal numbers such as "first", "second", and "third" in this specification are used for the purpose of distinguishing components of the same kind from one another only, and does not limit the number of components. The "plurality of" in the present disclosure means two or more.

[0050] In this specification, terms of "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the orientation or positional relationship are used to describe the positional relationship of components with reference to the drawings only for convenience of explanation of the specification and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be construed as limiting the present disclosure. The positional relationship of components is appropriately changed according to the direction of the components described. Thus, the terms described in the specification are not limited, and can be appropriately replaced according to the situation.

[0051] In this specification, unless explicitly stated and limited otherwise, the terms "mount", "connected", "connected" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. The above terms in the present disclosure can be understood according to the situation by those skilled in the art.

[0052] In this specification, the connection includes "electrical connection". The "electrical connection" includes the case where the components are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transmit electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having multiple functions, and the like.

[0053] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0054] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control terminal.

[0055] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0056] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0057] In this disclosure, "about" and "approximately" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "same" can include cases where index values ​​differ by no more than 10%.

[0058] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this disclosure, "A extends along direction B" refers to "the main part of A extends along direction B".

[0059] In this specification, "A and B are of the same layer structure" and "A and B are arranged in the same layer" mean that A and B are formed simultaneously through the same patterning process, or that the surfaces of A and B closest to the substrate are substantially the same distance from the substrate, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. "Same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection area of ​​A, or the orthographic projection of A covers the orthographic projection of B. The "shape of A" in this disclosure refers to the shape of the orthographic projection of A onto the substrate.

[0060] In some implementations, during the design verification (DV) phase before mass production of display products, reliability testing is conducted on the display products under high temperature and high humidity conditions. Because the driver chip is bonded to the driver chip area of ​​the display substrate, this area is subject to high pressure, which can cause microcracks to form in some vias. During reliability testing in high temperature and high humidity environments, moisture can easily penetrate through these microcracks, causing electrochemical corrosion on some pins and leading to abnormalities.

[0061] This embodiment provides a display substrate, a display device, and a display motherboard, which can improve the reliability of the display substrate under high temperature and high humidity environments, including the corrosion of vias.

[0062] This embodiment provides a display substrate, including: a substrate, a first type of contact pad, a second type of contact pad, a third type of contact pad, and a first type of test unit. The substrate includes a display area and a first border area located on one side of the display area. The first border area includes: at least one first signal access area and at least one second signal access area. The second signal access area is located on the side of the first signal access area away from the display area. The first type of contact pad, the second type of contact pad, and the first type of test unit are located in the first signal access area. The second type of contact pad is located on the side of the first type of contact pad closer to the second signal access area. The first type of test unit is located between the first type of contact pad and the second type of contact pad. The first type of contact pad includes: a plurality of data contact pads and a plurality of first control contact pads. The first type of test unit is connected to at least a portion of the plurality of data contact pads and configured to transmit test data signals to at least a portion of the plurality of data contact pads during a first test phase. The third type of contact pad is located in the second signal access area. This third type of contact pad includes multiple second control contact pads and multiple third control contact pads. The multiple third control contact pads are connected to some of the second type of contact pads, and the multiple second control contact pads are connected to the multiple first control contact pads. This configuration is for transmitting a first type of test control signal during a first test phase. The first test phase can be an array test phase.

[0063] The display substrate provided in this embodiment provides a first type of test control signal by a plurality of second control contact pads disposed in the second signal access area. A first type of test unit for transmitting test data signals is disposed in the first signal access area, and there is no voltage difference between the test data signals transmitted by the first type of test unit. This can improve the reliability of the via corrosion in the first signal access area under high temperature and high humidity conditions.

[0064] In some exemplary embodiments, the first type of test unit may include: a plurality of first test contact pads, each first test contact pad being connected to a data contact pad. In this example, the first test contact pad can directly transmit test data signals to the data contact pad. For example, the number of first test contact pads may be less than the number of data contact pads, with one data contact pad connected to one first test contact pad out of every four data contact pads. One of every four data contact pads can receive test data signals.

[0065] In some exemplary embodiments, the first type of test unit may further include: a plurality of first test contact pads and a plurality of first multiplexing circuits, the plurality of first multiplexing circuits being located on the side of the plurality of first test contact pads near the first type of contact pads and connected to the plurality of data contact pads and the plurality of first test contact pads; at least one first multiplexing circuit is configured to provide test data signals provided by at least one first test contact pad to the connected plurality of data contact pads. In this example, the plurality of first test contact pads can transmit test data signals to the plurality of data contact pads through the plurality of first multiplexing circuits. Each data contact pad can receive the test data signal.

[0066] In some exemplary embodiments, the display substrate may further include a first insulating protective layer located in the first signal access area, wherein the orthographic projection of the first insulating protective layer onto the substrate can cover the orthographic projection of the plurality of first multiplexed circuits onto the substrate. In some examples, the plurality of first multiplexed circuits include a plurality of vias, and the minimum distance between the edge of the first insulating protective layer and the edge vias among the plurality of vias can be greater than or equal to 10 micrometers. This example, by providing a first insulating protective layer to cover the plurality of first multiplexed circuits, can effectively avoid the corrosion of reliable vias that may occur when the first multiplexed circuits are provided.

[0067] In some exemplary embodiments, the first type of test unit may further include: multiple multiplexed control lines and multiple multiplexed control contact pads, wherein the multiple multiplexed control contact pads are connected one-to-one with the multiple multiplexed control lines, and the multiple multiplexed control contact pads may be located on at least one side of the multiple first test contact pads in one direction. For example, the multiple multiplexed control contact pads may be located on both sides of the multiple first test contact pads in one direction. In some examples, the display substrate may further include: multiple first resistor strips located in the first signal access area, one end of the first resistor strip being connected to a multiplexed control contact pad and a multiplexed control line, and the other end of the first resistor strip being configured to receive a regulated signal. The conductivity of the first resistor strip may be less than the conductivity of the multiplexed control line. This example, by setting the first resistor strips connected to the multiplexed control contact pads and multiplexed control lines, can avoid the potential risks to the display substrate caused by the floating connection of the multiplexed control lines.

[0068] The following examples illustrate the solution of this embodiment.

[0069] In some examples, during the fabrication of the display substrate, a display motherboard is first fabricated, and then the display motherboard is divided into multiple display substrates, each of which can be used to form a single display device. Figure 1 is a schematic diagram of a display motherboard according to at least one embodiment of the present disclosure. Figure 1 is a schematic diagram of the arrangement of four display substrates in the display motherboard. As shown in Figure 1, the multiple substrate regions 200 on the display motherboard 10 can be arranged periodically and regularly, and the cutting region 210 can be located outside the substrate regions 200. The substrate regions 200 may include: a border region surrounding the display region 201. The display region 201 may include a pixel array. The border region may include: a first border region 202 located on one side of the display region 201 along a first direction D1, and a second border region located on the remaining sides of the display region 201.

[0070] In some examples, a first cutting track 701 and a second cutting track 702 may be provided within the cutting area 210. After all the film layers of the display motherboard are prepared, the cutting equipment can perform coarse cutting along the first cutting track 701 and fine cutting along the second cutting track 702 to cut off the substrate area 200 to form the display substrate. The first cutting track 701 may also be called the coarse cutting track, and the second cutting track 702 may also be called the fine cutting track.

[0071] In some examples, the display area 201 may be a flat area, which may include multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL forming a pixel array. The multiple sub-pixels PX can be configured to display dynamic or still images. The multiple gate lines GL may extend along a second direction D2 and be arranged along a first direction D1; the multiple data lines DL may extend along the first direction D1 and be arranged along the second direction D2. The orthographic projections of the multiple gate lines GL and the multiple data lines DL onto the substrate may intersect to form multiple sub-pixel regions, each of which may contain one sub-pixel PX. The multiple data lines DL may be electrically connected to the multiple sub-pixels PX, and the multiple data lines DL may be configured to provide data signals or test data signals to the multiple sub-pixels PX. The multiple gate lines GL may be electrically connected to the multiple sub-pixels PX, and the multiple gate lines GL may be configured to provide pixel control signals to the multiple sub-pixels PX. In some examples, the pixel control signals may include scan signals and emission control signals, or may include scan signals, or may include scan signals, reset control signals, and emission control signals.

[0072] In some examples, as shown in Figure 1, the second direction D2 can be the extension direction of the grid line GL in the display area 201 (e.g., the row direction), and the first direction D1 can be the extension direction of the data line DL in the display area 201 (e.g., the column direction). The first direction D1 and the second direction D2 can intersect each other, for example, they can be perpendicular to each other.

[0073] In some examples, a pixel unit of display area 201 may include three sub-pixels, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, namely a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0074] In some examples, a sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, 8T2C, or 9T2C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit simplifies the process flow, reduces the processing difficulty of the display substrate, and improves product yield. In other examples, the multiple transistors in the pixel circuit may include both P-type and N-type transistors.

[0075] In some examples, the multiple transistors in the pixel circuit can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OPTs offer advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate—an LTPS+Oxide (LTPO) display substrate—leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0076] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0077] In some examples, the orthographic projection of the light-emitting element of a sub-pixel onto the substrate can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0078] Figure 2A is a partial cross-sectional schematic diagram of a display area according to at least one embodiment of the present disclosure. Figure 2A illustrates the structure of a sub-pixel of the display area as an example. In this example, it is described that multiple transistors in the pixel circuit are of the same type; for example, the multiple transistors in the pixel circuit may all be low-temperature polysilicon thin-film transistors (LTPS) or all be oxide thin-film transistors (OPS). In other examples, the multiple transistors in the pixel circuit may be both LPS and OPS. Furthermore, this example illustrates the integration of a mutual capacitance touch structure into the display substrate to form an FMLOC structure.

[0079] In some examples, as shown in FIG2A, the display substrate may include a substrate 100 and a circuit structure layer 120, a light-emitting structure layer 130, an encapsulation structure layer 140, and a touch structure layer 150 sequentially disposed on the substrate 100. The circuit structure layer 120 may include pixel circuits for multiple sub-pixels located in the display area, each pixel circuit including multiple transistors and at least one capacitor. The light-emitting structure layer 130 may be located in the display area and may include light-emitting elements for multiple sub-pixels. The touch structure layer 150 uses the encapsulation structure layer 140 as a substrate. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited in this embodiment.

[0080] In some examples, substrate 100 can be a flexible substrate, for example, made of an insulating material such as resin. In other examples, the substrate can be a single-layer structure or a multi-layer structure. When the substrate is a multi-layer structure, inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride can be placed in single or multiple layers between the layers.

[0081] In some examples, Figure 2A illustrates a transistor 16 and a capacitor 17 for each sub-pixel. The circuit structure layer 120 may include a semiconductor layer disposed on the substrate 100, a gate metal layer (e.g., including a first gate metal layer and a second gate metal layer), and a source / drain metal layer (e.g., including a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer). A first insulating layer (also referred to as a first gate insulating layer) 101 may be disposed between the semiconductor layer and the first gate metal layer; a second insulating layer (also referred to as a second gate insulating layer) 102 may be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer (also referred to as an interlayer insulating layer) 103 may be disposed between the second gate metal layer and the first source / drain metal layer; a fourth insulating layer (also referred to as a passivation layer) 104 and a fifth insulating layer (also referred to as a first planarization layer) 105 may be disposed between the first source / drain metal layer and the second source / drain metal layer; a sixth insulating layer (also referred to as a second planarization layer) 106 may be disposed between the second source / drain metal layer and the third source / drain metal layer; and a seventh insulating layer (also referred to as a third planarization layer) 107 may be disposed on the side of the third source / drain metal layer away from the substrate 100. The first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 may be inorganic insulating layers, while the fifth insulating layer 105, the sixth insulating layer 106, and the seventh insulating layer 107 may be organic insulating layers. However, this embodiment is not limited thereto. In other examples, a buffer layer may be provided on the side of the semiconductor layer near the substrate. The buffer layer can prevent harmful substances in the substrate from penetrating into the interior of the display substrate and can also increase the adhesion of the film layers in the display substrate to the substrate. In other examples, a bottom shielding metal layer (BSM) may be provided on the side of the buffer layer near the substrate. The bottom shielding metal layer may be configured to at least partially cover the active layer of the thin-film transistor of the pixel circuit to avoid external light affecting the performance of the thin-film transistor. In other examples, the passivation layer may be omitted between the first source / drain metal layer and the second source / drain metal layer, and only a first planarization layer may be provided between the first source / drain metal layer and the second source / drain metal layer.

[0082] In some examples, the first gate metal layer, the second gate metal layer, the first source / drain metal layer, the second source / drain metal layer, and the third source / drain metal layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). These can be single-layer structures or multi-layer composite structures, such as Ti / Al / Ti. The semiconductor layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc. That is, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, or organic technology.

[0083] In some examples, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The semiconductor layer material may, for example, include polysilicon. The channel region may be undoped and possess semiconductor properties. The first and second regions may be doped regions on either side of the channel region and are doped with impurities, thus possessing conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped regions of the active layer may be interpreted as the source or drain electrodes of the transistor. The portion of the active layer between transistors may be interpreted as doped wiring that can be used to electrically connect the transistors. This embodiment is not limited in this respect.

[0084] In some examples, as shown in FIG2A, the semiconductor layer of the display area may include at least the active layer 160 of transistor 16. The active layer 160 of transistor 16 may include a first region 1601, a second region 1602, and a channel region 1600 located between the first region 1601 and the second region 1602. The first gate metal layer may include at least the gate 163 of transistor 16 and the first electrode 171 of capacitor 17. The orthographic projection of the gate 163 of transistor 16 onto the substrate 100 may cover the orthographic projection of the channel region 1600 of the active layer 160 onto the substrate 100. The second gate metal layer may include at least the second electrode 172 of capacitor 17. The orthographic projections of the second electrode 172 and the first electrode 171 of capacitor 17 onto the substrate 100 may at least partially overlap, for example, they may coincide. The first source-drain metal layer may include at least the source 161 and the drain 162 of transistor 16. The third insulating layer 103 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 1601 of the active layer 160. The third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the second pixel via can also be removed, exposing at least a portion of the surface of the second region 1602 of the active layer 160. The source 161 of the transistor 16 can be electrically connected to the first region 1601 of the active layer 160 through the first pixel via, and the drain 162 can be electrically connected to the second region 1602 of the active layer 160 through the second pixel via. The second source-drain metal layer may include a first anode transition electrode 181. The third source-drain metal layer may include a second anode transition electrode 182. The first anode transition electrode 181 can be electrically connected to the drain 162 of the transistor 16 of the pixel circuit through a third pixel via formed by the fourth insulating layer 104 and the fifth insulating layer 105. The second anode transition electrode 182 can be electrically connected to the first anode transition electrode 181 through a fourth pixel via formed by the sixth insulating layer 106. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the first anode transition electrode 181 and the second anode transition electrode 182.

[0085] In some examples, the gate lines of the display area may be located, for example, in the first gate metal layer; the data lines of the display area may be located, for example, in the second or third source-drain metal layer; and the high-potential power lines of the display area may be located, for example, in the second or third source-drain metal layer. This embodiment is not limited in this respect. The circuit structure layer of this example may include three source-drain metal layers, which can avoid arranging too many traces in a single source-drain metal layer, thereby facilitating the realization of a narrow bezel structure.

[0086] In some examples, as shown in Figure 2A, the light-emitting structure layer 130 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element can be an anode, and the first electrode 131 can be disposed on the sixth insulating layer 106 and electrically connected to the anode transition electrode 181 through a third pixel via formed in the sixth insulating layer 106. The pixel definition layer 134 is disposed on the first electrode 131 and the sixth insulating layer 106, and the pixel definition layer 134 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 can be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 can be a cathode, and can be disposed on and in contact with the organic light-emitting layer 132. The organic light-emitting layer 132 can emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133. An isolation pillar layer can also be set on the side of the pixel definition layer 134 away from the substrate 100. The isolation pillar layer can include multiple isolation pillars (PS).

[0087] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML) and one or more films selected from the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0088] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0089] In some examples, as shown in Figure 2A, the encapsulation structure layer 140 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked together. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, while the second encapsulation layer 142 may be made of organic materials. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to prevent external moisture from entering the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may employ a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0090] In some examples, as shown in Figure 2A, the touch structure layer 150 of the display area may include: a touch barrier layer (TBL) 151, a first touch conductive layer (TMA) 154, a touch interlayer insulating layer (TLD) 152, a second touch conductive layer (TMB) 155, and a touch protective layer (OC) 153, arranged sequentially.

[0091] In some examples, the first touch conductive layer 154 may include a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of first connecting portions; the plurality of first touch electrodes, the plurality of second touch electrodes, and the plurality of first connecting portions may be formed in the same patterning process, and the first touch electrodes and the first connecting portions may be an integral structure interconnected with each other. The second touch conductive layer 155 may include a plurality of second connecting portions; the second connecting portions may be interconnected with adjacent second touch electrodes through vias formed in the interlayer insulating layer 152. In other examples, the first touch conductive layer may include the aforementioned first touch electrodes, second touch electrodes, and first connecting portions, and the second touch conductive layer may include the aforementioned second connecting portions.

[0092] In some examples, the first touch electrode can be a drive (Tx) electrode and the second touch electrode can be a sensing (Rx) electrode. Alternatively, the first touch electrode can be a sensing (Rx) electrode and the second touch electrode can be a drive (Tx) electrode.

[0093] In some examples, the touch barrier layer 151 and the interlayer insulating layer 152 can be inorganic insulating layers, while the touch protective layer 153 can be an organic insulating layer. For example, the touch barrier layer 151 and the interlayer insulating layer 152 can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or composite layers. The touch protective layer 153 can be made of polyimide (PI), etc.

[0094] In some examples, the first touch conductive layer 154 and the second touch conductive layer 155 can be made of any one or more of the following metal materials: silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Ti / Al / Ti, ITO / Ag / ITO, etc.

[0095] Figure 2B is another partial cross-sectional schematic diagram of the display area of ​​a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 2B, the circuit structure layer 120 may include: a semiconductor layer, a gate metal layer (e.g., including a first gate metal layer and a second gate metal layer), and a source / drain metal layer (e.g., including a first source / drain metal layer and a second source / drain metal layer) disposed on the substrate 100. The first electrode 131 of the light-emitting element can be electrically connected to the drain 162 of the transistor 16 through a first anode connection electrode 181 located in the second source / drain metal layer. Further descriptions of the display substrate of this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0096] In some examples, as shown in FIG1, the first border region 202 of the substrate region 200 may include a first sub-region 203, a bent region 204, and a second sub-region 205 sequentially disposed along a direction away from the display region 201. The first sub-region 203 may be connected to the display region 201 and the second border region. The bent region 204 may be connected between the first sub-region 203 and the second sub-region 205. The bent region 204 may be configured such that the second sub-region 205 bends to the back side of the display region 201.

[0097] In some examples, the second sub-region 205 may include at least one first signal access region 251 and at least one second signal access region 252. Figure 1 illustrates an example with one first signal access region 251 and one second signal access region 252. The first signal access region 251 may be located on the side of the second signal access region 252 closer to the bending region 204. The second signal access region 252 is located on the side of the first signal access region 251 away from the display region 201. The first signal access region 251 is configured to house a driver chip and may also be referred to as a driver chip housing area; the second signal access region 252 is configured to bond an external circuit board, such as a flexible printed circuit board (FPC), and may also be referred to as a circuit bonding area.

[0098] Figure 3 is a partial schematic diagram of a display motherboard according to at least one embodiment of the present disclosure. Figure 3 illustrates a partial area of ​​the first border region 202 and a partial area of ​​the cutting region 210 of the display substrate. In this example, the second border region 202 may include two first signal access regions 251 aligned along the second direction D2. Figure 3 illustrates one of the first signal access regions 251 as an example. In some examples, as shown in Figure 3, the first signal access region 251 may be provided with a first type of contact pad 51, a second type of contact pad 52, and a first type of test unit 31. The first type of contact pad 51 may be located on the side of the second type of contact pad 52 near the bending region 204, and the first type of test unit 31 may be located between the first type of contact pad 51 and the second type of contact pad 52. The first type of contact pad 51 may include a plurality of data contact pads 511 and a plurality of first control contact pads 512. The plurality of first control contact pads 512 may be located on both sides of the plurality of data contact pads 511 along the second direction D2. For example, the first type of contact pad 51 may include two sets of data contact pads 51a and 51b and two sets of first control contact pads 51c and 51d. The first set of first control contact pads 51c, the first set of data contact pads 51a, the second set of data contact pads 51b, and the second set of first control contact pads 51d may be arranged sequentially along the second direction D2. Each set of data contact pads may include multiple data contact pads 511, and each set of first control contact pads may include multiple first control contact pads 512.

[0099] In some examples, multiple data contact pads 511 can be configured to transmit data signals or test data signals; multiple first control contact pads 512 can be configured to transmit control signals or test control signals, such as clock signals, start signals, and power signals provided to the gate driving circuit. The gate driving circuit can be located in the second frame region of the display substrate; for example, the gate driving circuit can be located in the left and right frame regions on both sides of the display area along the second direction D2. The gate driving circuit can be configured to provide pixel control signals to the pixel circuits of multiple sub-pixels through multiple gate lines. In this example, data signals and control signals refer to signals provided during the normal display process of the display substrate; test data signals and test control signals refer to signals provided during the testing phase of the display substrate.

[0100] In some examples, the first type of test unit 31 can be divided into two groups. The first group can be located on the side of the first group data contact pad 51a near the second type of contact pad 52 and connected to the first group data contact pad 51a, configured to provide test data signals to the first group data contact pad 51a. The second group can be located on the side of the second group data contact pad 51b near the second type of contact pad 52 and connected to the second group data contact pad 51b, configured to provide test data signals to the second group data contact pad 51b. The two groups of first type test units 31 can be aligned along the second direction D2.

[0101] In some examples, the first type of test unit 31 may include a plurality of first test contact pads. A single first test contact pad may be connected to a data contact pad 511. In other examples, the first type of test unit 31 may include a plurality of first test contact pads and a plurality of first multiplexing circuits, the plurality of first multiplexing circuits being located on the side of the plurality of first test contact pads close to the plurality of data contact pads 511, the first multiplexing circuits being connected to at least one first test contact pad and the plurality of data contact pads 511, configured to provide test data signals provided by at least one first test contact pad to the connected plurality of data contact pads 511.

[0102] In some examples, the second sub-region 205 may further include a circuit setting area 253 located on the side of the first signal access area 251 near the bend area 204. The circuit setting area 253 may be configured with multiple second multiplexing circuits and multiple electrostatic discharge circuits.

[0103] In some examples, the second sub-region 205 may also be provided with multiple first data leads 431 and multiple second data leads 432. The multiple first data leads 431 may be located on the side of the circuit setup area 253 near the bend area 204, and the multiple second data leads 432 may be located between the circuit setup area 253 and the first signal access area 251. Multiple data contact pads 511 within the first signal access area 251 may be connected to the multiple second data leads 432, and the multiple second data leads 432 and multiple first data leads 431 may be connected to multiple second multiplexing circuits and multiple electrostatic discharge circuits within the circuit setup area 253. The second multiplexing circuit may be connected to at least one second data lead 432 and multiple first data leads 431, configured to transmit data signals provided by at least one second data lead 432 to the connected multiple first data leads 431. Multiple first data leads 431 and multiple second data leads 432 can be located in the gate metal layer. For example, the multiple first data leads 431 can be alternately arranged in the first gate metal layer and the second gate metal layer, and the multiple second data leads 432 can be alternately arranged in the first gate metal layer and the second gate metal layer, or the multiple second data leads 432 can be located in the first gate metal layer. The multiple first data leads 431 can be connected to multiple data lines in the display area through the routing in the bending area 204 and the first sub-area, thereby realizing the transmission of data signals or test data signals from the second sub-area 205 to the display area.

[0104] In some examples, the second sub-region 205 may also be provided with multiple first control leads 441 and multiple second control leads 442. The multiple first control leads 441 can be connected to multiple first control contact pads 512 within the first signal access region 251. The multiple first control leads 441 can also be connected to the gate drive circuit within the second frame region via a bend region 204 and traces within the first sub-region, thereby enabling the transmission of control signals or test control signals from the second sub-region 205 to the display region. The multiple first control leads 441 can be connected to multiple second control leads 442, and the multiple second control leads 442 can extend to the second signal access region 252. For example, the multiple first control leads 441 can be formed by connecting traces located in the second gate metal layer and the first gate metal layer, and the multiple second control leads 442 can be located in the first source / drain metal layer.

[0105] In some examples, the second signal access area 252 may be provided with a third type of contact pad 53. The third type of contact pad 53 may include a plurality of second control contact pads 531 and a plurality of third control contact pads 532. The plurality of second control contact pads 531 may be connected to a plurality of second control leads 442. The plurality of third control contact pads 532 may be connected to some of the second type of contact pads 52 in the first signal access area 251 via a plurality of ILB (Inner Lead Bonding) traces 49.

[0106] In some examples, the second sub-region 205 may also be provided with a first power lead 41 and a second power lead 42. The first power lead 41 can be connected to a third-type contact pad 53 within the second signal access region 252 that transmits a first power signal. The second power lead 42 can be connected to a third-type contact pad 53 within the second signal access region 252 that transmits a second power signal. The second power lead 42 can be located on the side of the first power lead 41 away from the first signal access region 251.

[0107] In some examples, the first power lead 41 may include a main body extending along a first direction D1 and a first extension and a second extension extending along a second direction D2. The first extension and the second extension may be located on opposite sides of the first signal access area 251 along the second direction D2, and the main body may be located on the side of the circuit setting area 253 near the bending area 204. The orthographic projection of the main body onto the substrate may overlap with the orthographic projection of the plurality of first data leads 431 onto the substrate. The first power lead 41 and the second power lead 42 may be disposed in the same layer, for example, both located in the first source-drain metal layer.

[0108] In some examples, the second sub-region 205 may also be provided with multiple touch leads 45. The multiple touch leads 45 may be located on the side of the second power lead 42 away from the substrate, for example, in the touch structure layer. The multiple touch leads 45 may extend to the second signal access area 252 and connect to the third type of contact pad 53 that transmits touch signals within the second signal access area 252.

[0109] In some examples, the cutting area 210 can be configured with a second type of test unit 32 and multiple first connection lines 461. The second type of test unit 32 can be positioned adjacent to the second cutting track 702. The first signal access area 251 can have a first center line O1 extending along a first direction D1. The second type of test unit 32 can be positioned close to the first center line O1. For example, the second type of test unit 32 can be divided into two groups, and the two groups of second type of test units 32 can be aligned along a second direction D2, with the minimum distance between the two groups of second type of test units 32 and the first center line O1 being the same. For example, the two groups of second type of test units 32 can be symmetrically positioned about the first center line O1. The second type of test unit 32 can include multiple second test pins, which can be connected to multiple first connection lines 461. The placement of the second type of test unit 32 in this example facilitates the application of the test equipment to the testing process of different types of display substrates, enabling the sharing of test equipment and thus saving costs.

[0110] In some examples, the cutting area 210 may also include a third type of test unit 33, multiple second connecting lines 462, multiple third connecting lines 463, and multiple fourth connecting lines 464. The third type of test unit 33 may be located on the side of the second type of test unit 32 away from the second cutting track 702. The third type of test unit 33 may include multiple third test pins. The multiple third test pins may be divided into two groups, and the two groups of third test pins may be aligned along the second direction D2. The multiple third test pins may be connected to multiple second connecting lines 462, and the multiple second connecting lines 462 may be connected to multiple first connecting lines 461 in the cutting area 210. The multiple second connecting lines 462 may extend to the second sub-area 205 and connect to multiple second control contact pads 531 in the second signal access area 252. Third test pins transmitting the same signal in the two groups of third test pins may be connected via third connecting lines 463. Multiple third test pins that transmit touch test signals can be connected to the corresponding third type contact pads 53 in the second signal access area 252 via multiple fourth connection lines 464 to achieve connection with the touch lead-out line 45.

[0111] In some examples, the third type of test unit 33 is used for electrical testing (ET). Electrical testing focuses on the electrical characteristics of the display substrate, such as voltage, current, and power consumption, and can evaluate the electrical performance of the display substrate under different operating conditions, thereby ensuring the stability and reliability of the display substrate in practical applications. The third type of test unit 33 can be configured to provide second type of test control signals (such as start signals, clock signals, and voltage signals provided to the gate drive circuit) through multiple second connection lines 462 during the electrical testing phase.

[0112] In some examples, the first type of test unit 31 and the second type of test unit 32 are used for array testing (AT). The first type of test unit 31 is configured to provide test data signals during the array testing phase, and the second type of test unit 32 is configured to provide first type of test control signals (such as start signals, clock signals, and voltage signals provided to the gate drive circuit) during the array testing phase. Array testing is mainly used to inspect the pixel units of the display substrate and provide feedback signals such as the type, quantity, and location of defects, thereby monitoring the manufacturing process of the display substrate to continuously improve the manufacturing process and achieve the goal of increasing product yield. During the array testing phase, the testing equipment can perform comprehensive functional tests on the display substrate through the first type of test unit 31 and the second type of test unit 32, including brightness, color accuracy, and response time.

[0113] Figure 4 is a partial cross-sectional schematic diagram of the contact pads of a first type of test unit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 4, the contact pads of the first type of test unit may include: a first contact pad layer 311-1, a second contact pad layer 311-2, and a third contact pad layer 311-3 stacked sequentially. The first contact pad layer 311-1 may be located in a first source / drain metal layer, the second contact pad layer 311-2 may be located in a second source / drain metal layer, and the third contact pad layer 311-3 may be located in a third source / drain metal layer. The third contact pad layer 311-3 may contact the second contact pad layer 311-2, and the second contact pad layer 311-2 may contact the first contact pad layer 311-1 through vias formed in the fifth insulating layer 105 and the fourth insulating layer 104.

[0114] As shown in Figure 4, a single contact pad of the first type of test unit 31 is equivalent to a large via. Although corrosion is prone to occur at the via location in the first signal access area 251, the first type of test unit 31 is configured to transmit test data signals. There is no voltage difference between adjacent first test contact pads transmitting test data signals, and there is no electrochemical corrosion caused by moisture affecting the contact pads. The second type of test unit 32 is configured to transmit first type of test control signals. The signals transmitted by the second test contact pads are mostly transition signals, and there will be a voltage difference between adjacent second test contact pads. At the via location, it is prone to electrochemical corrosion caused by moisture. Compared to placing the second type of test unit in the first signal access area 251, this example, by placing the first type of test unit 31 in the first signal access area 251 and placing the second type of test unit 32 in the cutting area 210, can avoid the risk of electrochemical corrosion caused by the second type of test unit in the first signal access area, thereby improving the reliability of the via corrosion in the first signal access area.

[0115] In this example, during the array testing phase, the first type of test control signal transmitted by the second type of test unit 32 can be transmitted to the gate drive circuit sequentially through the first connecting line 461, the second connecting line 462, the second control contact pad 531, the second control lead 442, and the first control lead 441. During the electrical testing phase, the second type of test control signal transmitted by the third type of test unit 33 can be transmitted to the gate drive circuit through the second connecting line 462, the second control contact pad 531, the second control lead 442, and the first control lead 441. It is evident that during the array testing phase, the first type of test control signal received by the multiple first control contact pads 512 within the first signal access area 251 does not originate from the first signal access area 251, but rather from the cutting area 210. The second type of test unit 32 is located in the cutting area 210 and can reuse the signal transmission path of the third type of test unit 33 to transmit the first type of test control signal, enabling shared routing and thus saving costs.

[0116] Figure 5 is a schematic diagram illustrating a connection relationship between a first type of test unit and a first type of contact pad within a first signal access area according to at least one embodiment of this disclosure. In some examples, as shown in Figure 5, multiple data contact pads 511 can be arranged in three rows, each row including multiple data contact pads 511 aligned along a second direction D2. Each data contact pad 511 can include multiple contact pad layers stacked sequentially. A data contact pad 511 can be connected to a second data lead 432. For example, the second data lead 432 and one of the contact pad layers of the connected data contact pad 511 can be an integral structure.

[0117] In some examples, the first type of test unit 31 may include a plurality of first test contact pads 311 aligned along a second direction D2. One first test contact pad 311 may be connected to a data contact pad 511 via a first internal connection line 341. The number of the plurality of first test contact pads 311 may be less than the number of the plurality of data contact pads 511. For example, one first test contact pad 311 may be connected to one of four data contact pads 511 via a first internal connection line 341. For example, three data contact pads 511 arranged along the inclined direction of the data contact pads form a row of data contact pads. In Figure 5, the data contact pad 511 in the first row of data contact pads from the left, closest to the first type of test unit 31, is connected to a first test contact pad 311. The middle data contact pad 511 in the second row of data contact pads from the left is connected to another first test contact pad 311. The data contact pad 511 in the third row of data contact pads from the left, furthest from the first type of test unit 31, is connected to another first test contact pad 311. The remaining data contact pads in the three rows of data contact pads may not be connected to the first test contact pads. The first internal connecting line 341 and one contact pad layer of the connected data contact pad 511 can be an integral structure, and the first internal connecting line 341 and one contact pad layer of the connected first test contact pad 311 can be an integral structure.

[0118] Figure 6 is a partially enlarged schematic diagram of the second sub-region and the cutting region according to at least one embodiment of the present disclosure. Figure 7 is a partially enlarged schematic diagram of the first signal access region of the second sub-region according to at least one embodiment of the present disclosure. In some examples, as shown in Figures 6 and 7, the first type of test unit 31 may include: a plurality of first test contact pads 311 and a plurality of first multiplexing circuits 315. The plurality of first test contact pads 311 may be located on the side of the plurality of first multiplexing circuits 315 close to the second type of contact pads 52. Some of the second type of contact pads 52 may be connected to a plurality of third control contact pads 532 in the third type of contact pads 53 via a plurality of ILB traces 49. The plurality of ILB traces 49 may be of the same layer structure.

[0119] In some examples, as shown in Figure 7, the first type of test unit 31 may further include: a plurality of multiplexed control contact pads 312, a plurality of first invalid contact pads 313, and at least one power contact pad 314. The plurality of first test contact pads 311, multiple multiplexed control contact pads 312, a plurality of first invalid contact pads 313, and at least one power contact pad 314 may be arranged in a row, with the plurality of multiplexed control contact pads 312 located on at least one side of the plurality of first test contact pads 311 along the second direction D2. A first invalid contact pad 313 may be disposed between adjacent multiplexed control contact pads 312, and at least one first invalid contact pad 313 (e.g., two first invalid contact pads 313) may be disposed between a multiplexed control contact pad 312 and an adjacent first test contact pad 311. The power contact pad 314 may be located on the side of the plurality of multiplexed control contact pads 312 away from the plurality of first contact pads 311, and at least one first invalid contact pad 313 (e.g., two first invalid contact pads 313) may be disposed between a power contact pad 314 and an adjacent multiplexed control contact pad 312.

[0120] In some examples, as shown in Figure 7, multiple first multiplexing circuits 315 can be arranged in a row, aligned sequentially along the second direction D2. Multiple first multiplexing circuits 315 can be connected to multiple multiplexing control lines ML (e.g., first multiplexing control line ML1, second multiplexing control line ML2, third multiplexing control line ML3, and fourth multiplexing control line ML4). A first test pin 311 can be connected to a first multiplexing circuit 315 via a second internal trace 342, and a first multiplexing circuit 315 can be connected to multiple data contact pads 511 via multiple third internal traces 343. For example, a first multiplexing circuit 315 can be connected to one first test pin 311 via one second internal trace 342, and can also be connected to four data contact pads 511 via four third internal traces 343. In this example, the first multiplexing circuit 315 can provide one test data signal to four data contact pads 511.

[0121] In some examples, as shown in Figure 6, the second type of test unit 32 located in the cutting area 210 may include: a plurality of second test contact pads 321 and a plurality of second invalid contact pads 322. The second invalid contact pads 322 may be disposed between at least two adjacent second test contact pads 321. The plurality of second test contact pads 321 may be connected to a plurality of first connection lines 461 to achieve signal transmission. The second type of test unit 32 may include two sets: the first set may be configured to provide first type of test control signals to a plurality of first control leads 441 on one side of the first signal access area 251 along the second direction D2; the second set may be configured to provide first type of test control signals to a plurality of first control leads 441 on the other side of the first signal access area 251 along the second direction D2.

[0122] In some examples, as shown in Figure 7, the first signal access area may also be provided with multiple bumps 61. The multiple bumps 61 may be arranged in a row along the second direction D2, for example, between multiple first test pins 311 and multiple first multiplexer circuits 315. The multiple bumps 61 can provide support when the driver chip is located within the first signal access area.

[0123] Figure 8A is a partial schematic diagram of a plurality of first multiplexing circuits according to at least one embodiment of the present disclosure; Figure 8B is a schematic diagram of the semiconductor layer, the first gate metal layer, the second gate metal layer, and the first source / drain metal layer in Figure 8A; Figure 8C is a schematic diagram of the semiconductor layer, the first gate metal layer, and the second gate metal layer in Figure 8A. In some examples, as shown in Figures 8A to 8C, the plurality of first multiplexing circuits may include: a plurality of active multiplexing circuits 315a and a plurality of inactive multiplexing circuits 315b. The inactive multiplexing circuits 315b may be located on one or both sides of the plurality of active multiplexing circuits 315a along the second direction D2.

[0124] In some examples, each first multiplexing circuit may include: a first multiplexing control transistor M1, a second multiplexing control transistor M2, a third multiplexing control transistor M3, and a fourth multiplexing control transistor M4. The gate of the first multiplexing control transistor M1 is connected to the first multiplexing control line ML1, the gate of the second multiplexing control transistor M2 is connected to the second multiplexing control line ML2, the gate of the third multiplexing control transistor M3 is connected to the third multiplexing control line ML3, and the gate of the fourth multiplexing control transistor M4 is connected to the fourth multiplexing control line ML4.

[0125] In some examples, the first multiplexing control transistors M1 of multiple first multiplexing circuits can be aligned and arranged along the second direction D2; the second multiplexing control transistors M2 of multiple first multiplexing circuits can be aligned and arranged along the second direction D2; the third multiplexing control transistors M3 of multiple first multiplexing circuits can be aligned and arranged along the second direction D2; and the fourth multiplexing control transistors M4 of multiple first multiplexing circuits can be aligned and arranged along the second direction D2. The first multiplexing control line ML1 can be multiplexed as the gate of multiple first multiplexing control transistors M1, the second multiplexing control line ML2 can be multiplexed as the gate of multiple second multiplexing control transistors M2, the third multiplexing control line ML3 can be multiplexed as the gate of multiple third multiplexing control transistors M3, and the fourth multiplexing control line ML4 can be multiplexed as the gate of multiple fourth multiplexing control transistors M4. The first multiplexing control line ML1, the second multiplexing control line ML2, the third multiplexing control line ML3, and the fourth multiplexing control line ML4 can be disposed on the same layer, for example, located in the first gate metal layer.

[0126] In some examples, the active layers M10 of the first multiplexing control transistor M1, M20 of the second multiplexing control transistor M2, M30 of the third multiplexing control transistor M3, and M40 of the fourth multiplexing control transistor M4 in a single first multiplexing circuit can be arranged in a stepped manner along the second direction D2. The active layers M10 of the first multiplexing control transistor M1, M20 of the second multiplexing control transistor M2, M30 of the third multiplexing control transistor M3, and M40 of the fourth multiplexing control transistor M4 can be located in the aforementioned semiconductor layers.

[0127] In some examples, the first terminal M11 of the first multiplexed control transistor M1, the first terminal M21 of the second multiplexed control transistor M2, the first terminal M31 of the third multiplexed control transistor M3, and the first terminal M41 of the fourth multiplexed control transistor M4 can be a single structure and connected to a second internal connection line (such as a second internal connection line 342a or 342b). Multiple second internal connection lines may include a second internal connection line 342a located in the first gate metal layer and a second internal connection line 342b located in the second gate metal layer. The second internal connection lines 342a and 342b can be arranged alternately, and their orthographic projections onto the substrate may not overlap.

[0128] In some examples, the second terminals M12 of the first multiplexing control transistor M1, M22 of the second multiplexing control transistor M2, M32 of the third multiplexing control transistor M3, and M42 of the fourth multiplexing control transistor M4 of the effective multiplexing circuit 315a can each be connected to a third internal connection line 343. A third internal connection line 343 can be connected to a data contact pad. Multiple third internal connection lines 343 can be in the same layer, for example, they can be located in the first gate metal layer.

[0129] In some examples, the first pole M11 and the second pole M12 of the first multiplexed control transistor M1, the first pole M21 and the second pole M22 of the second multiplexed control transistor M2, the first pole M31 and the second pole M32 of the third multiplexed control transistor M3, and the first pole M41 and the second pole M42 of the fourth multiplexed control transistor M4 can be in the same layer, for example, located in the first source-drain metal layer.

[0130] In some examples, the first multiplexing circuit may further include multiple vias, through which the first and second terminals of the multiplexing transistor can be connected to corresponding interconnects or semiconductor layers. For example, the first terminal of the multiplexing transistor can be connected to a second internal interconnect through a via formed in the third insulating layer or the third and second insulating layers, and the second terminal of the multiplexing transistor can be connected to a third internal interconnect through a via formed in the third and second insulating layers. The first and second terminals of the multiplexing transistor can also be connected to an active layer located in the semiconductor layer through multiple vias formed in the third, second, and first insulating layers.

[0131] In some examples, as shown in Figure 8A, a first insulating protective layer 55 may also be provided in the first signal access area. The first insulating protective layer 55 may be located on the side of the plurality of first multiplexed circuits away from the substrate. The orthographic projection of the first insulating protective layer 55 onto the substrate may cover the orthographic projection of the plurality of first multiplexed circuits onto the substrate. The minimum distance between the edge of the first insulating protective layer 55 and the edge vias among the plurality of vias may be greater than or equal to 10 micrometers. For example, the minimum distance between the left edge of the first insulating protective layer 55 and the left edge via of the plurality of vias (e.g., the connection via between the first electrode of the first multiplexed control transistor of the multiplexed transistor in the invalid multiplexing circuit 315b and the active layer) is L1; the minimum distance between the upper edge of the first insulating protective layer 55 and the upper edge via of the plurality of vias (e.g., the connection via between the first electrode of the multiplexed transistor in the effective multiplexing circuit 315a and the third internal connection line) is L2; ​​and the minimum distance between the lower edge of the first insulating protective layer 55 and the lower edge via of the plurality of vias (e.g., the connection via between the first electrode of the multiplexed transistor in the effective multiplexing circuit 315a and the second internal connection line) is L3. L1, L2, and L3 can all be greater than or equal to 10 micrometers.

[0132] In some examples, the first insulating protective layer 55 can be a single-layer structure, for example, it can be a co-layer structure with the aforementioned fifth insulating layer 105. In some examples, a first auxiliary insulating protective layer can be disposed on the side of the first insulating protective layer 55 near the substrate. The orthographic projection of the first auxiliary insulating protective layer onto the substrate can cover the orthographic projection of the first insulating protective layer 55 onto the substrate. For example, the first auxiliary insulating protective layer can be an inorganic insulating layer, and the first insulating protective layer 55 can be an organic insulating layer. The first auxiliary insulating protective layer can be a co-layer structure with the aforementioned fourth insulating layer 104, and the first insulating protective layer 55 can be a co-layer structure with the aforementioned fifth insulating layer 105. In this example, by providing a first insulating protective layer, the risk of reliability via corrosion in the area where the first multiplexing circuit is located can be effectively avoided.

[0133] Figure 9A is a schematic diagram of the connection between the multiplexing control contact pad and the multiplexing control line according to at least one embodiment of the present disclosure; Figure 9B is a schematic diagram of the semiconductor layer, the first gate metal layer and the second gate metal layer in Figure 9A; Figure 9C is a schematic diagram of the semiconductor layer, the first gate metal layer, the second gate metal layer and the first source / drain metal layer in Figure 9A.

[0134] In some examples, as shown in Figures 9A to 9C, the first signal access area may also be provided with multiple first resistor strips 351. The first resistor strips 351 may extend along the second direction D2, for example, as a serpentine trace extending along the second direction D2. The serpentine trace is a curved path. For example, one end of the trace extends a certain distance in one direction, then bends and extends a certain distance in the opposite direction, then bends and extends in the same direction again, repeating this bending and twisting several times to form a serpentine trace.

[0135] In some examples, a plurality of first resistor strips 351 may be located on the side of a plurality of multiplexing control contact pads 312 near a plurality of first multiplexing circuits in the first direction D1. The plurality of first resistor strips 351 may be aligned along the second direction D2. The minimum distance between the plurality of first resistor strips 351 and the plurality of multiplexing control contact pads 312 in the first direction D1 may be less than the minimum distance between the plurality of first resistor strips 351 and the plurality of first multiplexing circuits in the first direction D1. In other words, the plurality of first resistor strips 351 may be positioned near the multiplexing control contact pads 312.

[0136] In some examples, the first resistor strip 351 connected to the first multiplexed control line ML1 is used as an example. A first end of the first resistor strip 351 and a first end of the first multiplexed control line ML1 can be connected to a third connection electrode 363, which can be connected to a multiplexed control contact pad 312. A second end of the first resistor strip 351 can be connected to the first connection electrode 361 via a second connection electrode 362. The first connection electrode 361 can be connected to a power contact pad 314 via a fourth connection electrode 364. The first connection electrode 361 can be located in the first gate metal layer and extend along the second direction D2, and is located on the side of the plurality of first resistor strips 351 near the multiplexed control contact pad 312. The second connection electrode 362, the third connection electrode 363, and the fourth connection electrode 364 can be a co-layer structure, for example, located in the first source / drain metal layer. The multiplexed control contact pad 312, the power contact pad 314, and the first invalid contact pad 313 can be located in the second source / drain metal layer, or can include a dual-layer structure located in the second and third source / drain metal layers.

[0137] In some examples, the resistivity of the first resistor strip 351 can be greater than the resistivity of the multiplexed control line. Resistivity refers to the resistance coefficient; the resistivity of a material is numerically equal to the resistance per unit length and unit cross-section of that material. For example, the resistance of the first resistor strip 351 can be greater than 500KΩ to ensure display quality. Multiple first resistor strips 351 can be in the same layer, for example, located in a semiconductor layer. The power contact pad 314 can be configured to transmit regulated signals, such as high-potential signals.

[0138] In some examples, the multiplexing control contact pad 312 is configured to provide a multiplexing control signal during the array detection phase. Because the first resistor strip has a high resistance, during the array detection phase, the first resistor strip 351 acts as an open circuit, disconnecting the connection between the multiplexing control contact pad 312 and the power contact pad 314. During the normal display phase, the multiplexing control contact pad 312 is in a floating state, and the first resistor strip 351 acts as a capacitor, allowing the multiplexing control contact pad 312 to maintain the potential provided by the power contact pad 314. This ensures that the normal display of the display substrate is not affected and avoids the potential risks associated with floating contact pads.

[0139] In some examples, a second insulating protective layer 56 may also be provided in the first signal access area. The orthographic projection of the second insulating protective layer 56 onto the substrate can cover the orthographic projections of the multiple first resistor strips 351 and the multiple contact pads of the first type of test unit onto the substrate. Since the transition between the first resistor strip 351 and the connecting electrode requires the opening of a transition hole, the coverage of the transition hole by providing the second insulating protective layer can improve the reliability via corrosion situation in the first signal access area.

[0140] In some examples, the second insulating protective layer 56 can be a single-layer structure, for example, it can be a co-layer structure with the aforementioned seventh insulating layer 107. In some examples, a second auxiliary insulating protective layer can be disposed on the side of the second insulating protective layer 56 near the substrate. The orthographic projection of the second auxiliary insulating protective layer onto the substrate can cover the orthographic projection of the second insulating protective layer 56 onto the substrate. For example, the second auxiliary insulating protective layer can be an inorganic insulating layer, and the second insulating protective layer 56 can be an organic insulating layer. The second auxiliary insulating protective layer can be a co-layer structure with the aforementioned fourth insulating layer 104, and the second insulating protective layer 56 can be a co-layer structure with the aforementioned seventh insulating layer 107. For example, the second auxiliary insulating protective layer and the aforementioned first auxiliary insulating protective layer can be an integral structure. In some examples, the second insulating protective layer 56 can be prepared after the array test is completed, so that the second insulating protective layer 56 can cover multiple contact pads of the first type of test cell, thereby effectively avoiding the risk of corrosion of the reliability vias in the first signal access area.

[0141] Figure 10 is a partial schematic diagram of a second type of test unit according to at least one embodiment of the present disclosure. Figure 11 is a partially enlarged schematic diagram of region U1 in Figure 10. Figure 12 is a partially enlarged schematic diagram along the QQ' direction in Figure 10.

[0142] In some examples, as shown in Figure 10, the second type of test unit 32 may include a plurality of second test contact pads 321 and a plurality of second invalid contact pads 322 arranged aligned along a second direction D2. The second test contact pads 321 may be connected to the first connection line 461. At least one second test contact pad 321 may be connected to a second resistor strip 352. The resistivity of the second resistor strip 352 is greater than the resistivity of the first connection line 461. The second test contact pads 321 connected to the second resistor strip 352 may be configured to transmit a start signal provided to the gate drive circuit, such as a scan start signal, a light emission start signal, etc. By connecting a second resistor strip 352 to the output terminal of the second test contact pad 321 transmitting the start signal, the risk of signal abrupt changes can be reduced.

[0143] In some examples, as shown in Figures 11 and 12, the second test contact pad 321 may include a first contact pad layer 321-1 and a second contact pad layer 321-2 stacked sequentially. The second contact pad layer 321-2 contacts the first contact pad layer 321-1. The first contact pad layer 321-1 can be connected to the third adapter electrode 372 through a through-hole in the fourth insulating layer 104. The third adapter electrode 372 can be connected to one end of the second resistance strip 352 through through-holes in the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103. The orthographic projections of the second contact pad layer 321-2 and the first contact pad layer 321-1 onto the substrate can cover the orthographic projection of the third adapter electrode 372 onto the substrate. The other end of the second resistance strip 352 can be connected to the first adapter electrode 371 through through-holes in the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103. The first transition electrode 371 and the third transition electrode 372 can be in the same layer, for example, located in the first source / drain metal layer. The first transition electrode 371 can also be connected to the first connecting line 461 through vias formed in the second insulating layer 102 and the third insulating layer 103. The first transition electrode 371 can also be connected to the second transition electrodes 381 and 382 through vias formed in the fourth insulating layer 104. The second transition electrode 381 can be located in the second source / drain metal layer, and the second transition electrode 382 can be located in the third source / drain metal layer. The orthographic projections of the second transition electrodes 381 and 382 onto the substrate can cover the orthographic projection of the first transition electrode 381 onto the substrate.

[0144] This example demonstrates how by providing at least one second transition electrode covering the first transition electrode located above the first transition electrode in the first source / drain metal layer, and by having the third transition electrode located above the first source / drain metal layer covered by the contact pad layer of the second test contact pad, over-etching can be prevented during wet etching of the anode layer, thus protecting the transition electrode located in the first source / drain metal layer.

[0145] Figure 13 is another partially enlarged schematic diagram along the QQ' direction in Figure 10. In some examples, as shown in Figure 13, the second adapter electrode may not cover the first adapter electrode 381. The first adapter electrode 381 is used to connect the first connecting line 461 and the second resistor strip 352.

[0146] Figure 14 is another partial schematic diagram of the second sub-region and the cutting region according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 14, the second type of test unit 32 is located in the cutting region 210 and may be located near the second connecting line 462. For example, the second type of test unit 32 may be located on the side of the multiple second connecting lines 462 away from the edge of the display substrate along the second direction D2. For example, the multiple second test contact pads of the second type of test unit 32 may be divided into two groups, one group of second test contact pads may be close to the second connecting line 462 connected to a group of third type test units 33, and the other group of second test contact pads may be close to the second connecting line 462 connected to another group of third type test units 33. In this example, by arranging the second type of test unit 32 adjacent to the second connecting line 462, the length of the first connecting trace 461 can be reduced, thereby helping to reduce the impedance of the first connecting trace. The remaining description of the display substrate and display motherboard of this example can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0147] This embodiment also provides a display motherboard, including: multiple substrate regions and a cut area surrounding the substrate regions; the substrate regions include: a display region and a first frame region located on one side of the display region, the first frame region including: at least one first signal access region and at least one second signal access region, the second signal access region being located on the side of the first signal access region away from the display region. The display motherboard includes: a first type of contact pad, a second type of contact pad, a third type of contact pad, a first type of test unit, and a second type of test unit. The first type of contact pad, the second type of contact pad, and the first type of test unit are located in the first signal access region, the second type of contact pad is located on the side of the first type of contact pad close to the second signal access region, and the first type of test unit is located between the first type of contact pad and the second type of contact pad; the first type of contact pad includes: multiple data contact pads and multiple first control contact pads, the first type of test unit is connected to at least a portion of the multiple data contact pads, and configured to transmit test data signals to at least a portion of the multiple data contact pads during a first test phase. A third type of contact pad, located in the second signal access area, includes multiple second control contact pads and multiple third control contact pads. The multiple third control contact pads are connected to some of the second type of contact pads, and the multiple second control contact pads are connected to the multiple first control contact pads. A second type of test unit, located in the cutting area, is connected to the multiple second control contact pads and configured to provide a first type of test control signal to the multiple second control contact pads during the first test phase.

[0148] The display motherboard provided in this embodiment provides a first type of test control signal by a second type of test unit set in the cutting area. A first type of test unit is set in the first signal access area to transmit test data signals, and there is no voltage difference between the test data signals transmitted by the first type of test unit. This can improve the reliability of the via corrosion in the first signal access area of ​​the display substrate formed by the display motherboard under high temperature and high humidity environment.

[0149] In some exemplary embodiments, the first border region is located on one side of the display area along a first direction, and the first signal access region has a first center line extending along the first direction; the second type of test unit is located near the first center line. The placement of the second type of test unit in this example can facilitate the adaptation of the test equipment to various types of display substrates.

[0150] In some exemplary embodiments, the display motherboard further includes a third type of test unit located in the cut area, the third type of test unit being configured to provide a second type of test control signal to the plurality of second control contact pads during a second test phase (e.g., the aforementioned electrical test phase). In some examples, the display motherboard further includes a plurality of first connecting lines and a plurality of second connecting lines located in the cut area, the second type of test unit being connected to the plurality of second connecting lines via the plurality of first connecting lines, and the third type of test unit being connected to the plurality of second control contact pads via the plurality of second connecting lines. In some examples, the second type of test unit is located close to the plurality of second connecting lines. The placement of the second type of test unit in this example can help reduce the impedance of the first connecting lines.

[0151] In some exemplary embodiments, the display motherboard further includes: a plurality of second resistance strips located in the cut area; the second type of test unit includes: a plurality of second test contact pads, at least one of the plurality of second test contact pads being connected to the first connecting line via at least one second resistance strip, the resistivity of the second resistance strip being greater than the resistivity of the first connecting line. In some examples, the second test contact pad connected to the second resistance strip is configured to provide a start signal to the gate drive circuit. This example reduces the risk of abrupt changes in the start signal by providing the second resistance strip.

[0152] In some exemplary embodiments, the display motherboard further includes: a first adapter electrode and a second adapter electrode located in the cutting area; the first connecting line and the second resistance strip are connected through the first adapter electrode, the first adapter electrode is located on the side of the first connecting line and the second resistance strip away from the substrate, the second adapter electrode is located on the side of the first adapter electrode away from the substrate and is connected to the first adapter electrode, and the orthographic projection of the second adapter electrode on the substrate covers the orthographic projection of the first adapter electrode on the substrate. This example, by providing a second adapter electrode that covers the first adapter electrode, ensures that over-etching is avoided during wet etching of the anode layer, thus protecting the first adapter electrode.

[0153] The description of the display motherboard in this embodiment can be found in the description of the foregoing embodiments, and therefore will not be repeated here.

[0154] Figure 15 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 15, the display device 91 may include a display substrate 910. The display substrate 910 may be an OLED display substrate. The display device 91 may be any product or component with display function, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited thereto.

[0155] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0156] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, comprising: The substrate includes a display area and a first border area located on one side of the display area. The first border area includes at least one first signal access area and at least one second signal access area, wherein the second signal access area is located on the side of the first signal access area away from the display area. A first type of contact pad, a second type of contact pad, and a first type of test unit are located in the first signal access area. The second type of contact pad is located on the side of the first type of contact pad closer to the second signal access area. The first type of test unit is located between the first type of contact pad and the second type of contact pad. The first type of contact pad includes: a plurality of data contact pads and a plurality of first control contact pads. The first type of test unit is connected to at least a portion of the plurality of data contact pads and is configured to transmit test data signals to at least a portion of the plurality of data contact pads during a first test phase. The third type of contact pad is located in the second signal access area. The third type of contact pad includes: a plurality of second control contact pads and a plurality of third control contact pads. The plurality of third control contact pads are connected to some of the second type of contact pads. The plurality of second control contact pads are connected to the plurality of first control contact pads. The third type of contact pads are configured to transmit a first type of test control signal during the first test phase.

2. The display substrate according to claim 1, wherein, The first type of test unit includes: a plurality of first test contact pads, each of which is connected to a data contact pad.

3. The display substrate according to claim 1, wherein, The first type of test unit includes: a plurality of first test contact pads and a plurality of first multiplexing circuits, wherein the plurality of first multiplexing circuits are located on the side of the plurality of first test contact pads close to the first type of contact pads and are connected to the plurality of data contact pads and the plurality of first test contact pads; At least one of the plurality of first multiplexing circuits is configured to provide test data signals transmitted by at least one of the plurality of first test contact pads to the plurality of connected data contact pads.

4. The display substrate according to claim 3, further comprising: A first insulating protective layer located in the first signal access area, the orthographic projection of the first insulating protective layer on the substrate covers the orthographic projection of the plurality of first multiplexing circuits on the substrate.

5. The display substrate according to claim 4, wherein, The plurality of first multiplexing circuits include a plurality of vias, wherein the minimum distance between the edge of the first insulating protective layer and the edge vias of the plurality of vias is greater than or equal to 10 micrometers.

6. The display substrate according to claim 3, wherein, The first type of test unit further includes: multiple multiplexed control lines and multiple multiplexed control contact pads, wherein the multiple multiplexed control contact pads are connected one-to-one with the multiple multiplexed control lines, and the multiple multiplexed control contact pads are located on at least one side of the multiple first test contact pads in one direction.

7. The display substrate according to claim 6, wherein, The first type of test unit further includes: a plurality of first invalid contact pads, wherein at least one of the plurality of first invalid contact pads is located between two adjacent multiplex control contact pads among the plurality of multiplex control contact pads, or is located between the plurality of multiplex control contact pads and an adjacent first test contact pad.

8. The display substrate according to claim 6, further comprising: A plurality of first resistor strips are located in the first signal access area. One end of the first resistor strip is connected to a multiplexing control contact pad and a multiplexing control line. The other end of the first resistor strip is configured to receive a regulated signal. The resistivity of the first resistor strip is greater than the resistivity of the multiplexing control line.

9. The display substrate according to claim 8, further comprising: A second insulating protective layer is located in the first signal access area, and the orthographic projection of the second insulating protective layer on the substrate covers the orthographic projection of the plurality of first resistor strips on the substrate.

10. A display device comprising a display substrate as claimed in any one of claims 1 to 9.

11. A display motherboard, comprising: Multiple substrate regions and a cut area surrounding the substrate regions; The substrate region includes: a display region and a first border region located on one side of the display region. The first border region includes: at least one first signal access region and at least one second signal access region. The second signal access region is located on the side of the first signal access region away from the display region. The display motherboard includes: A first type of contact pad, a second type of contact pad, and a first type of test unit are located in the first signal access area. The second type of contact pad is located on the side of the first type of contact pad closer to the second signal access area. The first type of test unit is located between the first type of contact pad and the second type of contact pad. The first type of contact pad includes: a plurality of data contact pads and a plurality of first control contact pads. The first type of test unit is connected to at least a portion of the plurality of data contact pads and is configured to transmit test data signals to at least a portion of the plurality of data contact pads during a first test phase. The third type of contact pad is located in the second signal access area. The third type of contact pad includes: a plurality of second control contact pads and a plurality of third control contact pads. The plurality of third control contact pads are connected to some of the second type of contact pads. The plurality of second control contact pads are connected to the plurality of first control contact pads. The second type of test unit is located in the cutting area. The second type of test unit is connected to the plurality of second control contact pads and is configured to provide a first type of test control signal to the plurality of second control contact pads during the first test phase.

12. The display motherboard according to claim 11, wherein, The first border area is located on one side of the display area along a first direction, and the first signal access area has a first center line extending along the first direction; The second type of test unit is located near the first center line.

13. The display motherboard according to claim 11, further comprising: A third type of test unit located in the cutting area is configured to provide a second type of test control signal to the plurality of second control contact pads during the second test phase.

14. The display motherboard according to claim 13, further comprising: The cutting area contains multiple first connecting lines and multiple second connecting lines. The second type of test unit is connected to the multiple first connecting lines and the multiple second connecting lines. The third type of test unit is connected to the multiple second control contact pads through the multiple second connecting lines.

15. The display motherboard according to claim 14, wherein, The second type of test unit is located near the plurality of second connection lines.

16. The display motherboard according to claim 14, further comprising: Multiple second resistance strips located in the cutting area; The second type of test unit includes: a plurality of second test contact pads, at least one of the plurality of second test contact pads being connected to the first connecting line via at least one second resistance strip, wherein the resistivity of the second resistance strip is greater than the resistivity of the first connecting line.

17. The display motherboard according to claim 16, wherein, The second test contact pad, connected to the second resistor strip, is configured to provide a start signal to the gate drive circuit.

18. The display motherboard according to claim 16, further comprising: The first and second transfer electrodes are located in the cutting area; The first connecting line and the second resistor strip are connected through the first adapter electrode. The first adapter electrode is located on the side of the first connecting line and the second resistor strip away from the substrate. The second adapter electrode is located on the side of the first adapter electrode away from the substrate and is connected to the first adapter electrode. The orthographic projection of the second adapter electrode on the substrate covers the orthographic projection of the first adapter electrode on the substrate.

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