Thermally confined phase change cell

Abstract

A device includes a first electrode (110), a second electrode (120), a node (130) between the first electrode and the second electrode, and a thermal confinement structure (155) adjacent to the node, wherein the thermal confinement structure includes a textured phase change material (170).

Description

Technical Field

[0001] This invention relates generally to the fields of electrical, electronic and computer technology, and more specifically to a technique for thermally isolating phase change units, etc. Background Technology

[0002] Phase change units (PCMs) can be advantageously incorporated into a wide variety of electronic devices, such as switches, memories, and storage elements, because PCMs can reversibly transition between an amorphous state with high resistivity (RESET) and a crystalline state with low resistivity (SET) by applying heat-generating current pulses. Rapid (tens of nanoseconds) high-temperature current pulses are used to amorphize the PCM into a high-resistivity reset state, while longer (hundreds of nanoseconds to tens of microseconds) medium-temperature pulses above the crystallization temperature are used to crystallize the PCM into a low-resistivity set state.

[0003] Figure 1A and Figure 1B These are cross-sectional views of various aspects of a confined phase change unit and a mushroom-shaped phase change unit, respectively. In both cases, unit 100 includes a top electrode 110, a bottom electrode 120, and nodes 130 of the phase change material. Adjacent units are separated by a dielectric material 150 that electrically isolates these units from each other. Figure 1B The mushroom-shaped unit also includes a heater that connects the bottom electrode 120 and the phase change material 130. Summary of the Invention

[0004] The principles of this invention provide a technique for thermal confinement structures for adjacent phase change units. In one aspect, an exemplary semiconductor structure includes a top electrode, a bottom electrode, a node between the top electrode and the bottom electrode, and a thermal confinement structure in contact with the node, wherein the node includes a phase change material, and wherein the thermal confinement structure includes a dielectric layer and textured components.

[0005] Optionally, the textured components of the device include superlattices.

[0006] Alternatively, the van der Waals gaps of the superlattice are parallel to the current flow in the device.

[0007] Optionally, the top electrode, bottom electrode, and nodes of the device have the same width.

[0008] Optionally, the node width of the device is smaller than the width of the first electrode.

[0009] Optionally, the textured component of the device includes alternating layers of a first layer and a second layer, wherein the first layer contacts the dielectric layer and includes Sb2Te3, and the second layer contacts the first layer and includes GeTe.

[0010] Optionally, the device may further include a second top electrode, a second bottom electrode, and a second node between the second top electrode and the second bottom electrode, wherein the thermal confinement structure is in contact with the second node, and wherein the dielectric layer is U-shaped.

[0011] In another aspect, an exemplary device includes a top electrode, a bottom electrode, a node between the top electrode and the bottom electrode, and a thermal confinement structure in contact with and located above the node, wherein the node includes a phase change material, and wherein the thermal confinement structure includes a first layer and a second layer.

[0012] Optionally, the thermal confinement structure of the device includes a superlattice.

[0013] Alternatively, the van der Waals gaps of the superlattice are perpendicular to the current flow in the device.

[0014] Optionally, the top electrode and the node have the same width, which is greater than the width of the bottom electrode.

[0015] In another aspect, an exemplary device includes a first phase change unit, a second phase change unit, and a thermal confinement structure between the first phase change unit and the second phase change unit, wherein the thermal confinement structure includes a dielectric layer and a textured phase change material.

[0016] Optionally, the dielectric layer conforms to the bottom surface, the sidewalls of the first phase change unit, and the sidewalls of the second phase change unit.

[0017] Optionally, the entire sidewall of each of the first and second phase change units is straight and parallel to each other.

[0018] Optionally, the first phase change unit and the second phase change unit include a top electrode, a bottom electrode, and a node between the top electrode and the bottom electrode, wherein the node width is smaller than the electrode width.

[0019] In another aspect, an exemplary device includes a first electrode, a second electrode, a node between the first electrode and the second electrode, and a thermal confinement structure adjacent to the node, wherein the thermal confinement structure includes a textured phase change material.

[0020] Optionally, the thermal confinement structure of the device also includes a dielectric material in contact with the node, wherein a portion of the textured phase change material is configured parallel to the device current direction. Adding a dielectric layer further enhances thermal resistance.

[0021] Optionally, the second portion of the textured phase change material is configured to be perpendicular to the current direction of the device.

[0022] Optionally, the first electrode and the node do not have a common width.

[0023] Optionally, the thermal confinement structure of the device is located between the node and the first electrode, and the thermal confinement structure also includes a seed layer in contact with the node, and at least a portion of the textured phase change material is configured to be perpendicular to the current direction of the device.

[0024] In another aspect, an exemplary method of forming a device includes forming a first electrode, forming a second electrode, forming a node between the first electrode and the second electrode, and forming a thermally confined structure adjacent to the node, wherein the thermally confined structure includes a textured phase change material.

[0025] Optionally, the thermal confinement structure also includes a dielectric material in contact with the node, wherein a portion of the textured phase change material is configured to be parallel to the device current direction.

[0026] Optionally, a portion of the textured phase change material is configured to be perpendicular to the device current direction.

[0027] Optionally, the first electrode and the node do not have a common width.

[0028] Optionally, a thermal confinement structure is located between the node and the first electrode, wherein the thermal confinement structure further includes a seed layer in contact with the node, and at least a portion of the textured phase change material is configured perpendicular to the programming current direction.

[0029] As used herein, "facilitating" an action includes performing an action, making an action easier, assisting in the implementation of an action, or causing an action to be performed. Therefore, by way of example and not limitation, instructions executed on a processor can facilitate an action performed by a semiconductor manufacturing device by sending appropriate data or commands to cause or assist in the execution of an action. When an agent facilitates an action in a manner other than performing the action, the action is still performed by an entity or group of entities.

[0030] The techniques disclosed herein can provide significantly beneficial technical effects. Some embodiments may not have these potential advantages, and not all embodiments necessarily require these potential advantages. As examples only and not limitations, one or more embodiments may provide one or more of the following:

[0031] • By reducing heat loss, it allows for a reduction in programming current;

[0032] • By reducing heat loss and limiting thermal crosstalk between adjacent devices, reliability can be improved;

[0033] • Allows for smaller cell size, thus contributing to high integration density;

[0034] • Allows for easy manufacturing in back-end processes; and

[0035] • By reducing the electrical power requirements for programming, the device's cycle capability can be improved.

[0036] These and other features and advantages will become apparent from the following detailed description of exemplary embodiments, which are read in conjunction with the accompanying drawings. Attached Figure Description

[0037] The following figures are given by way of example only and not by way of limitation, wherein the same reference numerals (when used) denote corresponding elements in the various views, and wherein:

[0038] Figure 1A It is a cross-sectional view depicting various aspects of a conventional confined phase transition unit;

[0039] Figure 1B It is a cross-sectional view depicting various aspects of the existing mushroom-shaped phase change unit;

[0040] Figure 2 This is a cross-sectional view depicting a confined phase transition unit according to various aspects of the present invention;

[0041] Figure 3 This is a cross-sectional view depicting further details of a confined phase transition unit according to various aspects of the present invention;

[0042] Figure 4 This is a cross-sectional view depicting another configuration of the confined phase transition unit according to various aspects of the present invention;

[0043] Figure 5 This is a cross-sectional view depicting a mushroom-shaped configuration of phase change units according to various aspects of the present invention;

[0044] Figure 6 This illustrates the composition of the prior art. Figure 1A Lumped circuit models of various thermal resistances in thermal circuits;

[0045] Figure 7 It shows the composition Figure 2 Lumped circuit models of various thermal resistances of the thermal circuits of this invention as described herein; and

[0046] Figure 8 It shows the composition Figure 4 Lumped circuit models of various thermal resistances in thermal circuits.

[0047] It should be understood that the elements in the accompanying drawings are illustrated for simplicity and clarity. Common but well-known elements that may be useful or necessary in commercially viable embodiments may not be shown for easier viewing of the illustrated embodiments. Detailed Implementation

[0048] The principles of the invention described herein will be explained in the context of exemplary embodiments. Furthermore, those skilled in the art will recognize, based on the teachings herein, that many modifications can be made to the illustrated embodiments that fall within the scope of the claims. That is, no limitation is intended to be imposed on the embodiments shown and described herein, nor should any such limitation be inferred.

[0049] In one aspect, an exemplary device includes a top electrode 110, a bottom electrode 120, a node 130 between the top and bottom electrodes, wherein the node includes a phase change material, and a thermal confinement structure 155 in contact with the node, wherein the thermal confinement structure includes a dielectric layer 152 and a textured component 170. When the thermal confinement structure is not in place, heat loss to the surrounding medium (e.g., dielectric material 150) can be as high as 90%, and is a major mechanism limiting programming efficiency in phase change memory devices. By using the thermal confinement structure, heat is retained within the cell, thereby improving programming efficiency.

[0050] Optionally, the textured component 170 of the device includes a superlattice. The advantage of using a superlattice is that, compared to the dielectric material 150 (e.g., silicon dioxide or silicon nitride), the superlattice is a material with a lower thermal conductivity value and less temperature sensitivity. Therefore, materials such as superlattices (which can have fairly consistent low thermal conductivity values ​​over a certain temperature range) can contribute to thermal confinement.

[0051] Optionally, the van der Waals gap 175 of the superlattice is parallel to the current flow in the device. The main benefit of the van der Waals gap is its ability to thermally confine the heat generated by Joule heating within the device. Therefore, the effective thermal resistance of the device is increased.

[0052] Optionally, the top electrode 110, bottom electrode 120, and node 130 of the device have the same width. The advantage of the unit 100 components having a common width is that the additional thermal boundary resistance and the low thermal conductivity of the textured component 170 reduce heat flux between devices, which in turn reduces thermal crosstalk between adjacent devices. Optionally, the node width 130w of the device is smaller than the first electrode width 110w. The advantage of a narrower node width compared to the electrode width is that gaps or voids can be formed when attempting to fill adjacent spaces with textured material. These gaps or voids will further reduce thermal conductivity.

[0053] Optionally, the textured components of the device include alternating layers of a first layer and a second layer, wherein the first layer contacts the dielectric layer and comprises Sb₂Te₃, and the second layer contacts the first layer and comprises GeTe. The technical benefits of alternating layers are low thermal conductivity and manufacturability. The latter stems from the compatibility of the structure and materials with back-end processes.

[0054] Optionally, the device may further include: a second top electrode; a second bottom electrode; and a second node between the second top electrode and the second bottom electrode, wherein the thermal confinement structure 155 contacts the second node, and wherein the dielectric layer 152 is U-shaped. The technical advantage is that adjacent cells (e.g., the second set of electrodes and nodes) are shielded from heat generated by the programmed cells by the thermal confinement structure 155 interposed therebetween. Without the thermal confinement structure 155, heat loss would lead to write interference in adjacent cells. Specifically, when the first cell is programmed, amorphous markers in adjacent cells will be reduced due to thermal crosstalk-induced crystallization. Thermally induced crosstalk between cells adjacent to programmed cells is a major factor limiting the scalability of phase-change memory technology.

[0055] On the other hand, an exemplary device includes a top electrode 110, a bottom electrode 120, a node 130 between the top and bottom electrodes, and a thermal confinement structure 155 in contact with and above the node 130, wherein the node comprises a phase change material, and wherein the thermal confinement structure 155 comprises a first layer 171 and a second layer 172. The technical advantage of the mushroom-shaped unit having a double-layer thermal confinement structure 155 is that the textured component 170 can extend as the top electrode 110 of the node 130. Therefore, although conductive, the multilayer textured component 170 will provide thermal isolation from the metallic top electrode 110.

[0056] Optionally, the thermal confinement structure of the device includes a superlattice. The advantage of using a superlattice is that, compared to dielectric materials 150 (such as silicon dioxide or silicon nitride), a superlattice is a material with a lower thermal conductivity value and less temperature sensitivity. Therefore, materials such as superlattices (which can have fairly consistent low thermal conductivity values ​​over a certain temperature range) can contribute to thermal confinement.

[0057] Optionally, the van der Waals gap 175 of the superlattice is perpendicular to the current flow in the device. The benefit of a gap perpendicular to the current flow is enhanced thermal capacity.

[0058] Alternatively, the top electrode 100 and node 130 have the same width, which is greater than the width of the bottom electrode 120. The advantage of the narrow bottom electrode 120 is that it acts as a heater, thereby accelerating the programming of the cell.

[0059] In another aspect, an exemplary device includes a first phase-change unit, a second phase-change unit, and a thermal confinement structure 155 between the first and second phase-change units, wherein the thermal confinement structure 155 includes a dielectric layer 152 and a textured phase-change material. The technical advantage is that the second unit is shielded from heat generated by the programmed unit (first unit) by the thermal confinement structure 155. Without the thermal confinement structure 155, heat loss would lead to write interference in adjacent units. Specifically, when the first unit is programmed, amorphous markers in adjacent units would be reduced due to thermal crosstalk-induced crystallization. Thermally induced crosstalk between units adjacent to the programmed unit is a major factor limiting the scalability of phase-change memory technology.

[0060] Optionally, the dielectric layer 152 is conformal to the bottom surface, the sidewalls of the first phase change unit, and the sidewalls of the second phase change unit. The benefits of a conformal dielectric layer are manufacturability and increased thermal resistance.

[0061] Optionally, the entire sidewall of each of the first and second phase change units is straight and parallel to each other. The advantage of straight and parallel unit sidewalls is that the added thermal boundary resistance and the low thermal conductivity of the textured phase change material reduce the heat flux between devices.

[0062] Optionally, the first phase change unit and the second phase change unit include a top electrode, a bottom electrode, and a node between the top electrode and the bottom electrode, wherein the node width is smaller than the electrode width. This configuration can often advantageously form a slit or void, which will further reduce thermal conductivity.

[0063] In another aspect, an exemplary device includes a first electrode 110, a second electrode 120, a node 130 between the first and second electrodes, and a thermal confinement structure 155 adjacent to the node 130, wherein the thermal confinement structure 155 comprises a textured phase change material. Without a thermal confinement structure, heat loss to the surrounding medium (e.g., dielectric material 150) can be as high as 90%, and is a major mechanism limiting programming efficiency in phase change memory devices. By using a thermal confinement structure, heat is retained within the cell, thereby improving programming efficiency.

[0064] Optionally, the thermal confinement structure 155 of the device also includes a dielectric material 152 in contact with node 130, wherein a portion of the textured phase change material is configured parallel to the device current direction. Adding a dielectric layer 152 further enhances thermal resistance. The advantage of configuring the textured phase change material parallel to current flow is ease of fabrication. Optionally, a second portion of the textured phase change material is configured perpendicular to the device current direction. The advantage of configuring the textured phase change material perpendicular to current flow is enhanced thermal capacity.

[0065] Optionally, the first electrode and the node do not share a common width. The advantage of a narrower node width compared to the electrode width is that gaps or voids can be formed when attempting to fill adjacent spaces with a textured phase change material. These gaps or voids will further reduce thermal conductivity.

[0066] Optionally, a thermal confinement structure 155 of the device is located between node 130 and the first electrode 110, and the thermal confinement structure 155 also includes a seed layer in contact with node 130, and at least a portion of the textured phase change material is configured perpendicular to the device current direction. The technical advantage of this configuration is that the textured phase change material can extend as the top electrode 110 of node 130. Therefore, although conductive, the textured phase change material provides thermal isolation from the metallic top electrode 110.

[0067] In another aspect, an exemplary method of forming a device includes forming a first electrode 110, forming a second electrode 120, forming a node 130 between the first electrode 110 and the second electrode 120, and forming a thermal confinement structure 155 adjacent to the node 130, wherein the thermal confinement structure 155 comprises a textured phase change material. When the thermal confinement structure is absent, heat loss to the surrounding medium (e.g., dielectric material 150) can be as high as 90%, and is a major mechanism limiting programming efficiency in phase change memory devices. By using a thermal confinement structure, heat is retained within the cell, thereby improving programming efficiency.

[0068] Optionally, the thermal confinement structure 155 also includes a dielectric material 152 in contact with node 130, wherein a portion of the textured phase change material is configured parallel to the device current direction. The advantage of configuring the textured phase change material parallel to current flow is ease of fabrication.

[0069] Optionally, a portion of the textured phase change material is configured perpendicular to the current direction of the device. The benefit of configuring the textured phase change material perpendicular to the current flow is enhanced thermal capacity.

[0070] Optionally, the first electrode and the node do not share a common width. The advantage of a narrower node width compared to the electrode width is that gaps or voids can be formed when attempting to fill adjacent spaces with a textured material. These gaps or voids will further reduce thermal conductivity.

[0071] Optionally, a thermal confinement structure 155 is located between node 130 and the first electrode. The thermal confinement structure 155 further includes a seed layer in contact with node 130, and at least a portion of the textured phase change material is configured perpendicular to the programming current direction. The technical advantage of this configuration is that the thermal confinement structure 155 can extend as the first electrode of node 130. Therefore, although conductive, the thermal confinement structure 155 provides thermal isolation from the metallic first electrode.

[0072] Reference Figure 2 In the embodiment of the device depicted, three units 100 are separated by two thermal confinement structures 155. Each unit includes a bottom electrode 120, a node 130 of phase change material, and a top electrode 110. The node width 130w, the bottom electrode width 120w, and the top electrode width 110w can be equal within normal process tolerances. The electrodes can be TiN or any suitable conductor or combination of conductors. One or more electrodes may optionally also serve as heaters. Alternatively, an additional heater (not shown) may be present between one or two of the electrodes and the node 130. The heater can be TiN or any suitable material or combination. Current flows vertically in unit 100 (see [reference needed]). Figure 2 (thick arrow).

[0073] Continue to refer to Figure 2 The thermal confinement structure 155 may include a dielectric layer 152 and a textured component 170. Unlike the untextured component, the textured component 170 comprises a layered material with intervening van der Waals gaps. The untextured component is a component lacking van der Waals (referred to herein as “VDW”) gaps. In addition to lacking VWGs, the untextured component may also have a randomly oriented crystal structure. While the thermal confinement structure 155 always includes the textured component 170, the phase change material of node 130 may be textured or untextured. Advantageously, the additional thermal boundary resistance of the thermal confinement structure and the low thermal conductivity of the textured component 170 are expected to reduce the heat flux between adjacent units. For example, Figure 6 This illustrates the composition of the prior art. Figure 1A Lumped circuit models of various thermal resistances in thermal circuits.

[0074] Figure 7 It shows the composition Figure 2 The lumped circuit model of various thermal resistances of the thermal circuits of this invention is described in the figure.

[0075] Compared with existing technologies Figure 1A compared to, Figure 2 The model exhibits greater thermal resistance, not only because the presence of the textured material creates more interfaces, but also because the thermal resistance of the textured component 170 is greater than that of the dielectric material 150 in the prior art. Melting in the textured component 170 can be eliminated through thermal engineering of the dielectric layer 152. However, the textured component 170 can also be designed to amorphize during molten quenching, thus maintaining or even improving the thermal confinement effect.

[0076] Reference Figure 3This further describes one aspect of the textured component 170 of the thermal confinement structure 155. The textured component 170 may include at least two layers: a first layer 171 adjacent to the dielectric layer 152 and a second layer 172 adjacent to the first layer 171. Due to the textured material, a VDW gap 175 appears between the first and second layers. The first layer 171, the second layer 172, and the intervening VDW gap 175 may be repeated (in...). Figure 3 (In the example, repeated twice). The first and second layers can be the same material (homogeneous epitaxy) or different materials (heterogeneous epitaxy). The first layer 171 can be a seed layer. The textured component 170 can be a superlattice. The textured component 170 can include a chalcogenide material. In one embodiment, the first layer 171 is Sb₂Te₃, and the second layer 172 is GeTe. Other materials suitable as textured or non-textured materials will be described later.

[0077] Still refer to Figure 3 The dielectric layer 152, the first layer 171, and the second layer 172 can form a U-shape in the opening between the cells. Due to the aspect ratio of the thermal confinement structure 155 and the basic conformal characteristics of the deposited film, the VDW gap 175 can be mostly parallel to the current flow direction (see [reference]). Figure 3 (thick arrow).

[0078] Although Figure 3 A confined cell is depicted, wherein the layers of the thermally confined structure 155 fill the spacing between the cells, but these layers may also cover the top of the cell to provide top encapsulation. Furthermore, the layers of the thermally confined structure 155 may be deposited prior to cell film deposition and formation to further encapsulate the cell 100 at the bottom as well.

[0079] Reference Figure 4 One aspect of confined cells is that they have different electrode widths and node widths. Figure 4 In this aspect, the bottom electrode width 120w and the top electrode width 110w can be equal within normal process tolerances, while the node width 130w is smaller than the bottom electrode width 120w and the top electrode width 110w. Therefore, the thermal confinement structure 155 located between cells can have a wider width in the region adjacent to the node 130 and a narrower width in the region adjacent to the bottom electrode 120 and the top electrode 110. This width difference can be achieved through photolithographic patterning or by selectively utilizing the sidewall etching rate between the electrodes and nodes. Due to the unevenness of the sidewalls of the cell 100, gaps or voids 180 can be formed. These gaps or voids further increase the thermal boundary resistance. For example, Figure 8 It shows the composition Figure 4 Lumped circuit models of various thermal resistances in thermal circuits.

[0080] Here, the combined thermal resistance of the textured component 170 and the gap or void 180 is greater than the thermal resistance of the textured component 170, which in turn is greater than the thermal resistance of the dielectric layer 152, in contrast to the aforementioned prior art. Figure 1A Compared to the model, this results in a lower heat flux.

[0081] Although Figure 4 Although not shown, it should be understood that a VDW gap appears at the interface between the first layer 171 and the second layer 172. The VDW gap will be mostly parallel to the direction of current flow in cell 100 (thick arrow).

[0082] Reference Figure 5 This depicts one aspect of a mushroom-shaped unit 100, which has a bottom electrode 120, a node 130, a thermal confinement structure 155, and a top electrode 110. The materials of the bottom electrode 120, node 130, thermal confinement structure 155, and top electrode 110 can be as described previously, except that the thermal confinement structure 155, while having a first layer 171 and a second layer 172, may lack the dielectric layer 152 (e.g., Figure 5 (As shown). Since the thermal confinement structure 155 is formed on the horizontal surface of node 130, the VDW gap 175 is formed horizontally, or in other words, the VDW gap 175 is perpendicular to the surface formed by the thermal confinement structure 155. Figure 5 The thick vertical arrow indicates the direction of current flow in the unit.

[0083] The thermally confined structure 155 can be grown by depositing a seed layer (not shown) between node 130 and the first layer 171, or by indirect seeding, wherein a conductive layer, such as amorphous carbon, provides a template for a layer such as Sb₂Te₃, which then acts as a seed layer. In another extension, node 130 (e.g., an untextured phase change material) can be used as a seeding substrate to realize the thermally confined structure 155. In one embodiment, to construct the mushroom-shaped unit 100, node 130 (e.g., an untextured phase change material) can be deposited at room temperature to form an amorphous and high-resistivity state. The surface of the node is charged using an ion beam (e.g., Ar), and a seed layer is deposited at room temperature. The temperature is then increased to ~200°C to deposit the textured part 170.

[0084] Other materials suitable as textured or untextured materials are phase change materials, which can include Ge2Sb2Te5, Ge-rich GeSbTe (GST) chalcogenide alloys, carbon-doped GeSbTe (GST), N-doped GST, and impurity-doped phase change materials such as Ti-doped Sb2Te3 and Sc-doped Sb2Te3. SiSbTe (SST), GaSbTe, and GeBiTe phase change materials include chalcogenide compositions, such as alloys comprising at least two elements from the indium (In)-antimony (Sb)-tellurium (Te) (IST) alloy system, such as In2Sb2Te5, In1Sb2Te4, In1Sb4Te7, etc., and alloys comprising at least two elements from the germanium (Ge)-antimony (Sb)-tellurium (Te) (GST) alloy system, such as Ge8Sb5Te8, Ge2Sb2Te5, Ge1Sb2Te4, Ge1Sb4Te7, Ge4Sb4Te7, etc., and other chalcogenide alloy systems. As used herein, hyphenated chemical composition notation indicates the elements included in a particular mixture or compound, and is intended to represent all stoichiometry involving the elements shown. Other chalcogenide alloy systems that can be used in phase change memory nodes include, for example, Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, In-Ge-Te, Ge-Sb-Te, Te-Ge-As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, and Te-G. The following materials are used: e-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, and Ge-Te-Sn-Pt. Furthermore, alternating layers of chalcogenide materials with layers of secondary non-chalcogenide materials, such as doped / undoped metal nitrides or doped / undoped carbon, can form superlattice structures. Metal nitrides can include Ti. x Te y Ta x Te y composition.

[0085] Superlattices can include phase change materials arranged in superlattice (SL) stacks having alternating layers of one or more of the materials listed above.

[0086] Semiconductor device fabrication involves various steps in the device patterning process. For example, the fabrication of a semiconductor chip may begin, for instance, with the generation of multiple device patterns using CAD (Computer-Aided Design), followed by an effort to replicate these device patterns onto a substrate. The replication process can involve various exposure techniques and various subtractive (etching) and / or additive (deposition) material handling procedures. For example, in a photolithography process, a layer of photoresist material may first be applied to the top of a substrate, followed by selective exposure according to a predetermined device pattern or multiple patterns. The solubility of the photoresist exposed to light or other ionizing radiation (e.g., ultraviolet light, electron beams, X-rays, etc.) may vary depending on the solution. The photoresist can then be developed in a developer to remove unirradiated portions (in negative resists) or irradiated portions (in positive resists) of the resist layer to form a photoresist pattern or photomask. Subsequently, the photoresist pattern or photomask can be replicated or transferred to the substrate beneath the photoresist pattern.

[0087] Those skilled in the art use numerous techniques to remove material at various stages of semiconductor structure formation. As used herein, these processes are collectively referred to as "etching." Etching includes, for example, wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE) techniques, all of which are known techniques for removing selected material during semiconductor structure formation. Standard cleaning agent 1 (SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. SC2 contains a strong acid, such as hydrochloric acid, and hydrogen peroxide. Those skilled in the art fully understand the techniques and applications of etching; therefore, further detailed descriptions of these processes are not provided herein.

[0088] While the overall fabrication method and the resulting structure are novel, certain individual processing steps required to implement this method can be employed using conventional semiconductor fabrication techniques and tools. These techniques and tools are already familiar to those skilled in the art based on the teachings herein. For example, those skilled in the art will be familiar with epitaxial growth, self-aligned contact formation, high-k metal gate formation, etc. The term "high-k" has a clear meaning for those skilled in the art in the context of high-k metal gate (HKMG) stacks, and is not merely a relative term. Furthermore, one or more processing steps and tools for fabricating semiconductor devices are also described in numerous readily available publications, including, for example: *Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition*, James D. Plummer et al., Prentice Hall, 2001; and *Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices*, PH Holloway et al., Cambridge University Press, 2008, both of which are incorporated herein by reference. It should be emphasized that although certain individual processing steps are described herein, these steps are merely exemplary, and those skilled in the art may be familiar with several equally suitable and applicable alternatives.

[0089] It should be understood that the various layers and / or regions shown in the accompanying drawings may not be drawn to scale. Furthermore, for ease of illustration, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given drawing. This does not imply that un-explicitly shown semiconductor layers have been omitted in an actual integrated circuit device.

[0090] Those skilled in the art will understand that the exemplary structures discussed above can be distributed in their original form (i.e., a single wafer with multiple unpackaged chips), in bare die form, in package form, or incorporated as components of intermediate or final products.

[0091] The integrated circuits according to various aspects of the present invention can be used in virtually any application and / or electronic system. Based on the teachings of this disclosure, those skilled in the art will be able to conceive of other implementations and applications of the embodiments disclosed herein.

[0092] The illustrations of the embodiments described herein are intended to provide a general understanding of various embodiments and are not intended to be used as a complete description of all elements and features of devices and systems that may utilize the circuits and techniques described herein. Many other embodiments will become apparent to those skilled in the art based on the teachings herein; other embodiments may be used and derived therefrom, allowing for structural and logical substitutions and changes without departing from the scope of this disclosure. It should also be noted that in some alternative embodiments, some steps of the exemplary method may occur in a different order than indicated in the drawings. For example, two steps shown consecutively may actually be performed substantially simultaneously, or certain steps may sometimes be performed in reverse order depending on the functions involved. The drawings are also schematic only and are not drawn to scale. Therefore, the specification and drawings should be considered exemplary and not restrictive.

[0093] For convenience, the term "embodiment" is used individually and / or collectively to refer to an embodiment, and is not intended to limit the scope of this application to any single embodiment or inventive concept where more than one embodiment or inventive concept is actually shown. Therefore, although specific embodiments have been illustrated and described herein, it should be understood that arrangements achieving the same purpose may be substituted for the specific embodiments shown; that is, this disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, as well as other embodiments not specifically described herein, will become apparent to those skilled in the art based on the teachings herein.

[0094] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that when the term “comprising” is used in this specification, it specifies the presence of the stated feature, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. Terms such as “bottom,” “top,” “above,” “over,” “below,” and “below” are used to indicate the relative positioning of elements or structures relative to each other, not relative height. If a layer of a structure is described herein as being “above” another layer, it should be understood that intermediate elements or layers may or may not be present between the two layers. If a layer is described as being “directly situated” on another layer, it indicates that the two layers are in direct contact. As used herein and in the appended claims, “about” means within plus or minus ten percent.

[0095] Any means plus a functional element or steps plus a functional element in the following claims are intended to include any structure, material, action, and equivalent for performing the function in conjunction with other claimed elements of the specific claim. The description of various embodiments is given for illustrative and descriptive purposes and is not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from its scope and spirit. These embodiments were chosen and described to best explain the principles and practical application, and to enable others skilled in the art to understand the various embodiments with various modifications suitable for the particular intended use.

[0096] An abstract is provided to comply with 37 CFR § 1.76(b), which requires that the abstract enable the reader to quickly determine the nature of the technical disclosure. The abstract is submitted to be understood not to interpret or limit the scope or meaning of the claims. Furthermore, as can be seen in the foregoing detailed description, various features are combined in a single embodiment to simplify this disclosure. This method of disclosure should not be construed as reflecting an intention that the claimed embodiment requires more features than expressly recited in each claim. Rather, as reflected in the appended claims, the claimed subject matter may be less than all the features of a single embodiment. Therefore, the following claims are hereby incorporated into the detailed description, wherein each claim is independently claimed as a separate subject matter.

[0097] Based on the teachings provided herein, those skilled in the art will be able to conceive of other implementations and applications of the described techniques and the disclosed embodiments. Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the exemplary embodiments are not limited to those precise embodiments, and those skilled in the art can make various other changes and modifications thereto without departing from the scope of the appended claims.

Claims

1. A device comprising: Top electrode; Bottom electrode; A node located between a top electrode and a bottom electrode, wherein the node comprises a phase change material; Thermal confinement structure in contact with nodes; and The thermal confinement structure includes a dielectric layer and textured components.

2. The device according to claim 1, wherein, The textured component includes a superlattice.

3. The device according to claim 2, wherein, The van der Waals gaps of the superlattice are parallel to the current flow in the device.

4. The device according to claim 1, wherein, The top electrode, the bottom electrode, and the node have the same width.

5. The device according to claim 1, wherein, The node width is smaller than the width of the first electrode.

6. The device according to claim 1, wherein, The textured component comprises alternating layers of a first layer and a second layer; The first layer is in contact with the dielectric layer, and the first layer comprises Sb₂Te₃. The second layer is in contact with the first layer, and the second layer includes GeTe.

7. The device according to claim 1, further comprising: Second top electrode; Second bottom electrode; as well as The second node located between the second top electrode and the second bottom electrode; The thermal confinement structure is in contact with the second node, and the dielectric layer is U-shaped.

8. A device comprising: Top electrode; Bottom electrode; A node located between a top electrode and a bottom electrode, wherein the node comprises a phase change material; A thermal confinement structure that is in contact with and located on top of a node; and The thermal confinement structure includes a first layer and a second layer.

9. The device according to claim 8, wherein, The thermally confined structure includes a superlattice.

10. The device according to claim 9, wherein, The van der Waals gaps in the superlattice are perpendicular to the current flow in the device.

11. The device according to claim 8, wherein, The top electrode and the node have the same width, which is greater than the width of the bottom electrode.

12. A device comprising: First phase transition unit; Second phase change unit; as well as A thermal confinement structure located between the first phase change unit and the second phase change unit; The thermal confinement structure includes a dielectric layer and a textured phase change material.

13. The device according to claim 12, wherein, The dielectric layer is conformal with the bottom surface, the sidewall of the first phase change unit, and the sidewall of the second phase change unit.

14. The device according to claim 13, wherein, The entire sidewall of each of the first phase change unit and the second phase change unit is straight and parallel to each other.

15. The device according to claim 13, wherein, Each of the first phase change unit and the second phase change unit includes a top electrode, a bottom electrode, and a node between the top electrode and the bottom electrode; and The node width is smaller than the electrode width.

16. A device comprising: First electrode; Second electrode; The node located between the first electrode and the second electrode; as well as Thermal confinement structure of neighboring nodes; Among them, thermally confined structures include textured phase change materials.

17. The device according to claim 16, wherein, The thermal confinement structure also includes a dielectric material in contact with the node, wherein a portion of the textured phase change material is configured to be parallel to the device current direction.

18. The device according to claim 17, wherein, The second part of the textured phase change material is configured to be perpendicular to the current direction of the device.

19. The device according to claim 17, wherein, The first electrode and the node do not have a common width.

20. The device according to claim 16, wherein: The thermal confinement structure is located between the node and the first electrode; The thermal confinement structure further includes a seed layer that contacts the node; and At least a portion of the textured phase change material is configured to be perpendicular to the current direction of the device.

21. A method of manufacturing a device, comprising: Form the first electrode; Form a second electrode; A node is formed between the first electrode and the second electrode; as well as Forming a thermal confinement structure for neighboring nodes; Among them, thermally confined structures include textured phase change materials.

22. The method according to claim 21, wherein, The thermal confinement structure also includes a dielectric material in contact with the node, wherein a portion of the textured phase change material is configured to be parallel to the device current direction.

23. The method according to claim 21, wherein, A portion of the textured phase change material is configured perpendicular to the current direction of the device.

24. The method according to claim 22, wherein, The first electrode and the node do not have a common width.

25. The method according to claim 21, wherein: The thermal confinement structure is located between the node and the first electrode; The thermal confinement structure further includes a seed layer that contacts the node; and At least a portion of the textured phase change material is configured perpendicular to the direction of the programming current.

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