Fabricating semiconductor devices using selective dielectric over dielectric (DOD) deposition processes

Abstract

A method of manufacturing a semiconductor device includes providing a structure including a first insulating pattern and a metal pattern, the first insulating pattern and the metal pattern disposed on a substrate; performing a cleaning process on the structure; exposing the structure to a reducing agent; selectively forming a passivation layer on the metal pattern; selectively forming a second insulating pattern on the first insulating pattern; and performing a heat treatment on the structure.

Description

Technical Field

[0001] The inventive concept relates to a method for manufacturing semiconductor devices using a dielectric-on-dielectric (DoD) deposition process. Background Technology

[0002] As the geometry of the structures forming semiconductor devices becomes smaller and the types of these structures continue to evolve with improvements in integration and design, improved deposition methods are needed. Summary of the Invention

[0003] Technical issues The inventive concept provides a method for fabricating semiconductor devices using a dielectric-on-dielectric (DoD) deposition process with improved selectivity.

[0004] The inventive concept provides a method for manufacturing semiconductor devices using a DoD deposition process that selectively forms insulating patterns.

[0005] Furthermore, the technical ideas of the inventive concept are not limited to the problems mentioned above, and the scope of the technical ideas of the inventive concept can be clearly understood by those skilled in the art from the description herein.

[0006] Technical solution According to one aspect of the inventive concept, a method for manufacturing a semiconductor device is provided, the method comprising: providing a structure including a first insulating pattern and a metal pattern disposed on a substrate; performing a cleaning process on the structure; exposing the structure to a reducing agent; selectively forming a passivation layer on the metal pattern; selectively forming a second insulating pattern on the first insulating pattern; and performing a heat treatment on the structure.

[0007] According to another aspect of the inventive concept, a method for manufacturing a semiconductor device is provided, the method comprising: providing a structure including a first insulating pattern and a metal pattern disposed on a substrate; performing a cleaning process on the structure; exposing the structure to a reducing agent; selectively forming a passivation layer on the metal pattern; selectively forming a second insulating pattern on the first insulating pattern; and performing a heat treatment on the structure, wherein the step of forming the second insulating pattern includes a plurality of cycles, each of the plurality of cycles including supplying a catalyst to the structure, wherein a first portion of the catalyst is adsorbed by the first insulating pattern; performing a first purging operation to remove a second portion of the catalyst other than the first portion of the catalyst; supplying a precursor to the structure, a first portion of the precursor forming the second insulating pattern; and performing a second purging operation to remove a second portion of the precursor other than the first portion of the precursor.

[0008] According to another aspect of the inventive concept, a method for manufacturing a semiconductor device is provided, the method comprising: placing a structure including a first insulating pattern and a metal pattern in a cleaning solution, the first insulating pattern and the metal pattern being disposed on a substrate; performing a cleaning process on the structure; placing the structure within a deposition apparatus; exposing the structure to a reducing agent in a first process chamber included in the deposition apparatus; selectively forming a passivation layer on the metal pattern in a second process chamber included in the deposition apparatus, the second process chamber being different from the first process chamber; selectively forming a second insulating pattern on the first insulating pattern; and performing a heat treatment on the structure, wherein the steps of exposing the structure to the reducing agent and forming the passivation layer on the metal pattern include disconnecting the first process chamber and the second process chamber from each other.

[0009] Beneficial effects of the invention The inventive concept provides a method for fabricating semiconductor devices using a dielectric-on-dielectric (DoD) deposition process with improved selectivity.

[0010] The inventive concept provides a method for manufacturing semiconductor devices using a DoD deposition process that selectively forms insulating patterns. Attached Figure Description

[0011] Figure 1 This is a flowchart schematically illustrating a method for manufacturing a semiconductor device using a dielectric-on-dielectric (DoD) deposition process according to some embodiments; Figure 2 This is a schematic plan view of a deposition apparatus for performing a method of manufacturing a semiconductor device using a DoD deposition process according to some embodiments; Figures 3 to 7 Figure 8A, Figure 8B Figure 9 and Figure 10 This is a cross-sectional view shown in process sequence according to an embodiment for explaining a method of manufacturing a semiconductor device using a DoD deposition process; Figure 11A is a photograph of the surface of copper manufactured according to Comparative Example 1, taken using an atomic force microscope (AFM); Figure 11B is a photograph of the copper surface manufactured according to Experimental Example 1, taken using AFM; Figure 12A is a photograph of the copper pattern and SiO2 pattern manufactured according to Comparative Example 8, taken using a transmission electron microscope (TEM). Figure 12B is a photograph taken using a TEM of the copper pattern and the SiO2 pattern manufactured according to Comparative Example 9; and Figure 12C is a photograph taken using a TEM of the copper and SiO2 patterns fabricated according to Experimental Example 5. Detailed Implementation

[0012] In the following, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions may be omitted.

[0013] This disclosure allows for various modifications and numerous embodiments, specific embodiments of which will be shown in the accompanying drawings and described in detail in the written description. However, this is not intended to limit the embodiments to a particular mode of practice, and it will be understood that all modifications, equivalents, and substitutions are included in this disclosure without departing from the spirit and scope of the inventive concept. In this disclosure, certain detailed descriptions may be omitted where they serve to obscure the nature of the inventive concept.

[0014] According to an embodiment, the dielectric-on-dielectric (DoD) deposition process can be a selective DoD deposition process. For example, a DoD deposition process can refer to a technique that selectively deposits a subsequent insulating material on an existing insulating material.

[0015] Figure 1 This is a flowchart schematically illustrating a method for manufacturing a semiconductor device using a dielectric-on-dielectric (DoD) deposition process according to some embodiments. Figure 2 This is a schematic plan view of a deposition apparatus 1 for performing a method of manufacturing a semiconductor device using a DoD deposition process according to some embodiments. Figures 3 to 7 Figure 8A, Figure 8B Figure 9 and Figure 10 This is a cross-sectional view shown in process sequence according to an embodiment for explaining a method of manufacturing a semiconductor device using a DoD deposition process.

[0016] Reference Figures 1 to 5 The method for manufacturing a semiconductor device using a DoD deposition process according to an embodiment may include operation S105 of "providing a structure STR including a first insulating pattern 110 and a metal pattern 120" and operation S110 of "performing a cleaning process on the structure STR including the first insulating pattern 110 and the metal pattern 120". The structure STR including the first insulating pattern 110 and the metal pattern 120 can be provided by various methods, and the method of forming the structure STR is not limited. A DoD deposition process can refer to a process of selectively depositing a subsequent insulating material on an insulating pattern including an existing insulating material and a metal material. For example, the existing insulating material and the metal material may be patterned integrally with the semiconductor device, and the subsequent insulating material may be deposited on the existing insulating material and may not be deposited on the metal material. In an embodiment, the insulating material and the metal material of the insulating pattern may be disposed on the same layer. Prior to performing the cleaning process, the method for manufacturing a semiconductor device using a DoD deposition process may further include forming the first insulating pattern 110 and the metal pattern 120 on a substrate 100.

[0017] Reference Figure 3 A first insulating pattern 110 may be formed on the substrate 100. The substrate 100 may include a semiconductor material. For example, the substrate 100 may include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), and silicon carbide (SiC). Optionally, the substrate 100 may include at least one of a compound semiconductor (such as GaAs, InAs, InGaAs, or InP). Optionally, the substrate 100 may have structures such as dynamic random access memory (DRAM) cell transistors, 3D NAND flash memory, FinFETs, multi-bridge channel field-effect transistors (MBCFETs), capacitors, transistors, etc. When the substrate 100 includes structures such as DRAM, NAND flash memory, or MBCFETs, the substrate 100 may include various configurations made of a single material or multiple materials.

[0018] The steps of forming the first insulating pattern 110 may include: forming an insulating film (not shown) on a substrate 100; forming a photomask (not shown) on the insulating film (not shown); and performing an etching process on the insulating film (not shown) using the photomask (not shown) as an etching mask (not shown). Various methods may be used to form the first insulating pattern 110, and embodiments are not particularly limited to the examples described herein. The first insulating pattern 110 may include an insulating material. For example, the first insulating pattern 110 may include a low-dielectric material. For example, the first insulating pattern 110 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), carbon-doped silicon oxide (SiOC), carbon-doped silicon oxynitride (SiONC), aluminum oxide (Al2O3), or combinations thereof.

[0019] Reference Figure 4 A metal layer 120a covering the first insulating pattern 110 can be formed on the substrate 100. The metal layer 120a can cover the upper surface of the substrate 100. The metal layer 120a can be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or combinations thereof. In embodiments, the metal layer 120a may include a metallic material. For example, the metal layer 120a may include tungsten (W), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), palladium (Pd), nickel (Ni), ruthenium (Ru), iridium (Ir), rhodium (Rh), osmium (Os), scandium (Sc), niobium (Nb), copper (Cu), platinum (Pt), silver (Ag), gold (Au), or combinations thereof. In embodiments, the metal layer 120a may include a metal nitride. Metal nitrides may include, for example, tungsten nitride (WN), titanium nitride (TiN), aluminum nitride (AlN), molybdenum nitride (MoN), tantalum nitride (TaN), or combinations thereof.

[0020] In an embodiment, when the metal layer 120a comprises copper (Cu), the step of forming the metal layer 120a may include: forming a seed layer (not shown) covering the exposed surfaces of the substrate 100 and the first insulating pattern 110; and performing electroplating using the seed layer (not shown) as an electrode.

[0021] Reference Figure 5 , can be Figure 4 The metal layer 120a undergoes a planarization process 125. The planarization process 125 may be performed until the upper surface of the first insulating pattern 110 is exposed. The planarization process 125 may include, for example, a chemical mechanical polishing (CMP) method. Due to the planarization process 125, the metal pattern 120 may be... Figure 4 A metal layer 120a is formed. Due to the planarization process 125, the upper surface of the first insulating pattern 110 and the upper surface of the metal pattern 120 can be coplanar with each other. As a result, a structure STR including a substrate 100, a first insulating pattern 110 and a metal pattern 120 can be formed.

[0022] Reference Figure 1 , Figure 2 and Figure 6 Operation S110 can perform a cleaning process on the structure STR, which includes the first insulating pattern 110 and the metal pattern 120. Simultaneously, it can... Figure 2 A method for manufacturing a semiconductor device using a DoD deposition process is performed in deposition equipment 1.

[0023] The deposition apparatus 1 may include an inlet / outlet device 10, a vacuum transfer module 30, a first process chamber 40, a second process chamber 50, and a third process chamber 60. The inlet / outlet device 10 may include, for example, an equipment front-end module (EFEM). The inlet / outlet device 10 may include a loading port, an atmospheric environment robot, an aligner, a fan filter unit (FFU), etc. When the structural STR is located outside the deposition apparatus 1, the structural STR can be transferred to the vacuum transfer module 30 of the deposition apparatus 1 through the loading port of the inlet / outlet device 10. The vacuum transfer module 30 can maintain a low vacuum state and can prevent the structural STR from being affected by external substances and / or impacts. For example, the vacuum transfer module 30 can reduce or eliminate the structural STR's exposure to external substances and / or impacts. The first to third process chambers 40, 50, and 60 may each be connected to the vacuum transfer module 30. The first to third process chambers 40, 50, and 60 may be spaced apart from each other. The structure STR can be transferred from the vacuum transfer module 30 to a process chamber of the deposition apparatus 1 (e.g., one of the first to third process chambers 40, 50, and 60). The structure STR can be transferred to any one of the first to third process chambers 40, 50, and 60, and the process chamber to which the structure STR is transferred and the other process chambers to which the structure STR is not transferred can be disconnected from each other. For example, when the structure STR is transferred to the first process chamber 40 and the process is performed in the first process chamber 40, the second process chamber 50 and the third process chamber 60 may not be connected to the first process chamber 40. Disconnection can be, for example, a physical disconnection of the process chamber from the vacuum transfer module 30, or, for example, sealing one or more of the process chambers through a sealable process chamber door (not shown). After the process is performed on the structure STR in a process chamber, the structure STR can be transferred via the vacuum transfer module 30 to another process chamber where the process has not yet been performed. In this case, the structure STR is not exposed to the outside of the deposition apparatus 1 and is protected from external substances and / or impacts. Meanwhile, it should be noted that among the first to third process cavities 40, 50 and 60, the terms "first", "second" and "third" are arbitrarily numbered to distinguish multiple process cavities, and are not limited to positional relationships or manufacturing order.

[0024] In an embodiment, the operation S110 of performing a cleaning process on the structure STR including the first insulating pattern 110 and the metal pattern 120 may include exposing the structure STR to a cleaning solution 135. As an example, the step of exposing the structure STR to the cleaning solution 135 may include immersing the structure STR in a container 130 containing the cleaning solution 135. The operation S110 of performing a cleaning process on the structure STR including the first insulating pattern 110 and the metal pattern 120 may be performed in a process chamber of the deposition apparatus 1 (e.g., one of the first to third process chambers 40, 50, and 60). For example, the operation S110 of performing a cleaning process on the structure STR including the first insulating pattern 110 and the metal pattern 120 may be performed in the first process chamber 40. However, the inventive concept is not limited thereto, and the operation S110 of performing a cleaning process on the structure STR including the first insulating pattern 110 and the metal pattern 120 may be performed outside the deposition apparatus 1. This may vary depending on the implementation of the method of manufacturing a semiconductor device.

[0025] Cleaning solution 135 may include, for example, organic acids having a carboxyl group. Organic acids having a carboxyl group may include, for example, acetic acid, citric acid, formic acid, formic acid, acetic acid, propionic acid, butyric acid, valeric acid, hexanoic acid, heptanoic acid, octanoic acid, nonanoic acid, decanoic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, adipic acid, pimelic acid, octanoic acid, azelaic acid, sebacic acid, 2-hydroxypropane-1,2,3-tricarboxylic acid, 1-hydroxypropane-1,2,3-tricarboxylic acid, propane-1,2,3-tricarboxylic acid, 2-hydroxynonadecane-1,2,3-tricarboxylic acid, benzene-1,3,5-tricarboxylic acid, or combinations thereof. In embodiments, cleaning solution 135 may include diluted solutions of the examples described herein.

[0026] As an example, operation S110 of performing a cleaning process on a structure STR including a first insulating pattern 110 and a metal pattern 120 may include exposing the structure STR to a cleaning solution 135 containing 2 wt% (weight percentage) citric acid for about 2 minutes 30 seconds to about 3 minutes at room temperature, and washing the structure STR with distilled water.

[0027] When a cleaning process is performed on a structural STR comprising a first insulating pattern 110 and a metal pattern 120, metal oxides disposed on the upper surface of the metal pattern 120 can be removed. The metal oxides can be byproducts formed on the upper portion of the metal pattern 120 when the metal pattern 120 is exposed to outside air before the structural STR is placed into the deposition apparatus 1. For example, the metal oxides can be byproducts formed on the upper portion of the metal pattern 120 when the metal pattern 120 is exposed to outside air during the movement of the structural STR. As an example, when the metal pattern 120 comprises copper, the metal oxides can include Cu₂O and / or CuO. x(Where x is a natural number). The metal oxide can be disposed on the upper surface of the metal pattern 120 and also on the upper surface of the first insulating pattern 110. When the metal oxide separated from the upper surface of the metal pattern 120 is adsorbed on the upper surface of the first insulating pattern 110, the metal oxide can be disposed on both the upper surface of the metal pattern 120 and the upper surface of the first insulating pattern 110.

[0028] For example, the step of washing the structure STR with distilled water may include repeatedly immersing the structure STR in distilled water for about 1 minute each time. For example, the structure STR may be washed three times.

[0029] Reference Figure 1 , Figure 2 and Figure 7 The operation S120, which exposes the structure STR, which has already undergone cleaning, to a reducing agent, can be performed. Operation S120 can be performed in processes other than the first process chamber 40. For example, operation S120 can be performed in the second process chamber 50.

[0030] The reducing agent may include, for example, hydrogen-based plasma. Hydrogen-based plasma can refer to plasma generated by hydrogen or a group of gases containing hydrogen and another gas (e.g., an inert gas). Optionally, the reducing agent may include, for example, methanol, ethanol, n-propanol, isopropanol, or combinations thereof. Hydrogen-based plasma can be generated by supplying H2 and an inert gas in a direct plasma state or a remote plasma state.

[0031] For example, when the reducing agent comprises hydrogen-based plasma, the hydrogen-based plasma can be generated by a direct plasma generation device in an in-situ plasma generation device or a remote plasma generation device. For example, when the hydrogen-based plasma is generated by a direct plasma generation device, the operation S120 of exposing the structure STR to the reducing agent may include supplying about 70 SCCM (flow rate units) of H2 and about 100 SCCM of Ar to the structure STR for about 3 minutes and 30 seconds to about 4 minutes and 30 seconds in a temperature range of about 250°C to about 350°C. According to an embodiment, Ar may be a different type of inert gas. The pressure within the second process chamber 50 may be 1 Torr, and plasma power may be supplied to the H2 in the second process chamber 50. For example, the plasma power may be applied in a range greater than about 0 and less than about 2000 watts (W).

[0032] When the operation S120 of exposing the structure STR to the reducing agent is performed, metal oxides that may not have been removed in the operation S110 of performing the cleaning process on the structure STR, or metal oxides generated during the transfer between process chambers after the operation S110 of performing the cleaning process on the structure STR, can be removed.

[0033] During operation S120, which exposes the structure STR to a reducing agent, the height of the upper surface of the metal pattern 120 can be reduced. If a portion of the upper part of the metal pattern 120 is exposed to outside air and becomes metal oxide, the height of the upper part of the metal pattern 120 can be reduced, and the metal oxide is removed during operation S120, which exposes the structure STR to a reducing agent. The inventive concept is not limited thereto, and the height of the upper surface of the metal pattern 120 can be reduced during operation S110, which performs a cleaning process on the structure STR including the first insulating pattern 110 and the metal pattern 120, or during operation S120, which exposes the structure STR to a reducing agent, or both operation S110 and operation S120.

[0034] Reference Figure 1 , Figure 2 Figures 8A and 8B illustrate an operation S130 that selectively forms a passivation layer 150 on the metal pattern 120. Prior to forming the passivation layer 150, the operation of lowering the temperature of the structure STR and moving the structure STR to the third process chamber 60 may be further included. That is, the operation S120 of exposing the structure STR to a reducing agent and the operation S130 of selectively forming the passivation layer 150 on the metal pattern 120 may be performed continuously in the deposition apparatus 1. After performing the operation S120 of exposing the structure STR to the reducing agent, the structure STR may be directly transferred to the third process chamber 60 via the vacuum transfer module 30. In the case of directly transferring the structure STR to the third process chamber 60 via the vacuum transfer module 30, the structure STR can be protected from external substances and / or impacts. Therefore, oxidation of the upper portion of the metal pattern 120 can be reduced or prevented, and the selectivity of the passivation layer 150 formed on the metal pattern 120 can be increased. In an embodiment, the passivation layer 150 may be formed on the metal pattern 120 and may not be formed on the first insulating pattern 110. For example, the passivation layer 150 may be selectively formed on the metal pattern 120.

[0035] As an example, the passivation layer 150 may include a self-assembled monolayer (SAM) 151. Figure 8B is an enlarged view of the molecular structure of SAM 151. Referring to Figure 8B, SAM 151 may include reactive groups 153, chain groups 155, and functional groups 157. Reactive groups 153 and functional groups 157 may be disposed at the ends of chain groups 155. Reactive groups 153 and functional groups 157 may be spaced apart from each other, with chain groups 155 disposed between reactive groups 153 and functional groups 157. Reactive groups 153 may be portions adsorbed onto a solid surface. SAM 151 may be adsorbed onto a solid surface via reactive groups 153. Functional groups 157 may be portions that define the function of the molecular film of SAM 151. The materials that can bind to functional groups 157 can be controlled according to which molecules or atoms are included in functional groups 157. Chain groups 155 may be portions that form a regular molecular arrangement. In SAM 151, chain groups 155 and functional groups 157, other than reactive group 153, may not adsorb onto the solid surface. The solid surface may be, for example, a metal surface. Although chain groups 155 and functional groups 157 do not adsorb onto the solid surface, reactive group 153 may adsorb onto the solid surface; therefore, SAM 151 may be arranged in a direction perpendicular to the solid surface. With reactive group 153 adsorbed onto the solid surface and SAM 151 arranged in a direction perpendicular to the solid surface, SAM 151 may occupy a small area and be adsorbed onto the solid surface. When multiple SAMs 151 are adsorbed onto the solid surface, multiple SAMs 151 may form a three-dimensional (3D) structure. In an embodiment, SAM 151 may have selective adsorption for selectively forming passivation layer 150. For example, SAM 151 may be adsorbed only onto metal pattern 120 and may not be adsorbed onto first insulating pattern 110. In the embodiments, any type of SAM 151 with selective adsorption can be used as passivation layer 150.

[0036] As an example, the operation S130 of selectively forming a passivation layer 150 on the metal pattern 120 may include exposing the structure STR to a passivating gas at a temperature of about 125°C to about 150°C for about 10 minutes to about 20 minutes. The pressure of the passivating gas may be about 0.13 Torr to about 0.2 Torr. The passivating gas may be supplied to the structure STR and may be decomposed or recombinated with another material of the structure STR to form the passivation layer 150. Passivating gases may include, for example, methanethiol, ethanethiol, propanethiol, butanethiol, pentatylthiol, hexanethiol, heptanethiol, octylthiol, nonanethiol, decanethiol, undecanethiol, dodecanethiol, tridecanethiol, tetradecanethiol, pentadecanethiol, hexadecanethiol, heptadecanthiol, octadecanethiol, nonadecanthiol, tetrahydro-2H-pyran-4-thiol, 2-propen-1-thiol, tetrahydro-2H-pyran-4-thiol, thiophene, 4-methyl-1-benzenethiophenol, 3-methyl-1-benzenethiophenol, 2-methyl-1-benzenethiophenol, p-xylene-α-thiol, 1H, 1H,2H,2H-perfluorodecylthiol, 2,2,2-trifluoroethanethiol, 4-methyl-6-trifluoromethyl-pyrimidin-2-thiol, 4-trifluoromethylbenzylthiol, 4-(trifluoromethoxy)benzylthiol, 4-fluorobenzylthiol, 3,5-bis(trifluoromethyl)benzylthiophenol, 2-(trifluoromethyl)benzylthiophenol, 4-trifluoromethyl-2,3,5,6-tetrafluorobenzylthiol, 3,5-difluorobenzylthiol, 4-trifluoromethyl-2,3,5,6-tetrafluorobenzylthiol, p-trifluoromethylbenzylthiol, di-tert-butyl disulfide, diheptane disulfide, or combinations thereof. After exposing the structural STR to a passivating gas, a purging process can be performed on the structural STR. The purging process can include supplying an inert gas (such as Ar) for approximately 15 minutes. Due to the purging process, the remaining passivation gas, except for the passivation layer 150 formed on the structure STR, can be removed.

[0037] When only one of the operations S110 (cleaning the structure STR, which includes the first insulating pattern 110 and the metal pattern 120) and S120 (exposing the structure STR to a reducing agent) is performed, it may be impossible to remove the metal oxide from the upper surface of the first insulating pattern 110. In this case, the passivation gas may be adsorbed on the upper surface of the metal pattern 120 and also on the upper surface of the first insulating pattern 110, and the selectivity of the DoD deposition process may be degraded.

[0038] A method for manufacturing a semiconductor device according to the inventive concept may include an operation S110 of performing a cleaning process on a structure STR including a first insulating pattern 110 and a metal pattern 120, and an operation S120 of exposing the structure STR to a reducing agent. In the method including the operation S110 of performing a cleaning process on the structure STR including the first insulating pattern 110 and the metal pattern 120, and the operation S120 of exposing the structure STR to a reducing agent, metal oxides on the upper surface of the metal pattern 120 and metal oxides adsorbed on the upper surface of the first insulating pattern 110 can be removed. Therefore, a passivation layer 150 may be formed on the upper surface of the metal pattern 120, and may not be formed on the first insulating pattern 110, and the selectivity of the DoD deposition process can be improved. For example, the passivation layer 150 may be formed only on the upper surface of the metal pattern 120.

[0039] Reference Figure 1 , Figure 2 and Figure 9 The operation S140, selectively forming a second insulating pattern 160 on the first insulating pattern 110, can be performed. Before forming the second insulating pattern 160, the structure STR can be transferred from the third process cavity 60. For example, the structure STR can be transferred from the third process cavity 60 to the second process cavity 50. The operation S140, selectively forming the second insulating pattern 160 on the first insulating pattern 110, can be performed by supplying approximately 150 SCCM of Ar at an atmospheric pressure of approximately 0.7 Torr to approximately 0.8 Torr.

[0040] The operation S140 of selectively forming the second insulating pattern 160 on the first insulating pattern 110 may include a catalyst supply operation, a first purging operation, a precursor supply operation, and a second purging operation. The catalyst supply operation, the first purging operation, the precursor supply operation, and the second purging operation can be defined as a cycle.

[0041] The catalyst may include, for example, alkylaluminum, dialkylaminoaluminum, aluminum alkoxide, a mixture of alkyl-alkoxyaluminum, dialkylaluminum chloride, trimethylaluminum (TMA), aluminum dimethylisopropoxide (DMAI), or combinations thereof. The catalyst may be supplied in pulses for about 1 to about 2 seconds at room temperature. The catalyst may be supplied in a single pulse or multiple pulses. Due to the passivation layer 150, the catalyst may be adsorbed only onto the first insulating pattern 110. The catalyst may not be adsorbed onto the passivation layer 150. The catalyst may promote a reaction from which a second insulating pattern 160 can be formed from a precursor.

[0042] The first purging operation may include supplying approximately 150 SCCM of Ar at a pressure of approximately 0.7 Torr to approximately 0.8 Torr for approximately 25 to approximately 35 seconds. The first purging operation may be performed to remove excess catalyst. Excess catalyst may be a first portion of the catalyst that can be physically adsorbed, such that the excess catalyst does not participate in the reaction. That is, the first purging operation may be performed to remove excess catalyst other than the second portion used to generate the second insulating pattern 160.

[0043] The precursor may include a material capable of producing an insulating material. The precursor may include, for example, bis(tert-butoxy)(isopropoxy)silanol, bis(isopropoxy)(tert-butoxy)silanol, bis(tert-pentoxy)(isopropoxy)silanol, bis(isopropoxy)(tert-pentoxy)silanol, bis(tert-pentoxy)(tert-butoxy)silanol, bis(tert-butoxy)(tert-pentoxy)silanol, tris(tert-butoxy)silanol, tris(tert-pentoxy)silanol, or combinations thereof. The precursor may be pulsed for 30 seconds at about 105°C to about 115°C. The precursor may be supplied in a single pulse or multiple pulses. The precursor may be selectively adsorbed onto the first insulating pattern 110. For example, the precursor may be better adsorbed onto the first insulating pattern 110 than onto the passivation layer 150. After the precursor is adsorbed onto the first insulating pattern 110, a second insulating pattern 160 may be formed from the precursor.

[0044] The second purging operation may include supplying approximately 150 SCCM of Ar at a pressure of approximately 0.7 Torr to approximately 0.8 Torr for approximately 55 to approximately 65 seconds. The second purging operation may be performed to remove excess precursor. That is, the second purging operation may be performed to remove the first portion of the precursor, excluding the second portion used to generate the second insulating pattern 160, as excess precursor.

[0045] The operation S140 of selectively forming a second insulating pattern 160 on the first insulating pattern 110 can be repeated until a second insulating pattern 160 of a desired thickness can be formed. That is, the operation S140 of selectively forming a second insulating pattern 160 on the first insulating pattern 110 may include multiple cycles. For example, the operation S140 of selectively forming a second insulating pattern 160 on the first insulating pattern 110 may be performed two or more times. The second insulating pattern 160 may comprise the same material as the first insulating pattern 110.

[0046] Reference Figure 1 , Figure 2 and Figure 10The operation S150 of performing heat treatment on the structure STR can be performed. The operation S150 of performing heat treatment on the structure STR can be performed in the second process chamber 50 or the third process chamber 60, or the operation S150 of performing heat treatment on the structure STR can be performed outside the deposition equipment 1.

[0047] Operation S150 of performing heat treatment on the structural STR may include performing rapid heat treatment (RTP). RTP means heating the object to a high temperature within seconds or even milliseconds. For example, the heating rate of RTP may be from about 20°C / s to about 30°C / s (where s is seconds). Operation S150 of performing heat treatment on the structural STR may include performing heat treatment for about 25 minutes to about 35 minutes in an atmosphere of N2 pressure of 2.6 Torr and at a temperature of about 350°C to about 400°C. Operation S150 of performing heat treatment on the structural STR may include performing heat treatment for about 25 minutes to about 35 minutes at the highest temperature used in the STR. While performing heat treatment on the structural STR, the following may be removed: Figure 9 The passivation layer 150 is used. Therefore, the second insulating pattern 160 can be formed only on the first insulating pattern 110 and not on the metal pattern 120. Furthermore, by performing heat treatment, the dielectric constant of the second insulating pattern 160 can be reduced, the leakage current flowing into the second insulating pattern 160 can be reduced, and the electrical breakdown (EBD) voltage can be reduced. In other words, the electrical characteristics of the second insulating pattern 160 can be improved by performing heat treatment, and therefore the electrical characteristics of the entire semiconductor device can be improved.

[0048] The inventive concept will be described in more detail by way of comparative and experimental examples. However, the comparative and experimental examples described herein are intended to illustrate the inventive concept in more detail, and the scope of the technical idea of ​​the inventive concept is not limited to the examples described herein.

[0049] Figure 11A is a photograph of the surface of copper manufactured according to Comparative Example 1, taken using an atomic force microscope (AFM). Figure 11B is a photograph of the surface of copper manufactured according to Experimental Example 1, taken using an AFM.

[0050] In Comparative Example 1, the cleaning process can be performed only on the SiO2 patterns and copper patterns on the silicon wafer. Figure 1 (S110 in the text). Specifically, the silicon wafer can be immersed in a diluted solution of approximately 2 wt% citric acid for approximately 2 minutes and 45 seconds at room temperature, and then washed with distilled water. At this point, the silicon wafer can correspond to... Figure 5 The substrate 100, the SiO2 pattern can correspond to Figure 5 The first insulating pattern 110, and copper may correspond to Figure 5 Metal pattern 120.

[0051] In Experimental Example 1, operation S120, which exposes the silicon wafer of Comparative Example 1 to a reducing agent, can also be performed. Figure 1 Specifically, hydrogen-based plasma can be used as a reducing agent, and approximately 70 SCCM of H2 and approximately 100 SCCM of Ar are supplied to the silicon wafer at a temperature of approximately 300°C for approximately 4 minutes. At this time, the pressure can be approximately 1 Torr, and approximately 1500 W of direct plasma power is supplied to the H2 in the process chamber.

[0052] Reference Figure 1 Figures 11A and 11B show that the copper crystal size in Experimental Example 1 can be larger than that in Comparative Example 1. When the copper crystal size is larger, other substances can be better adsorbed onto the copper surface. For example, when the copper crystal size is larger, other substances can be better adsorbed onto the copper surface, and the passivation layer 150 (in Figures 8A and 8B) can be better adsorbed onto the copper surface. Figure 9 The passivation layer 150 can be better formed on the surface of copper. Because the passivation layer 150 is better formed on the surface of copper, the selectivity in the selective formation of subsequent insulating material on SiO2 in Experimental Example 1 can be further increased. Here, selectivity refers to the ratio of the thickness of the subsequent insulating material formed on the surface of SiO2 to the thickness of the subsequent insulating material formed on the surface of copper. The selectivity is increased because the thickness of the subsequent insulating material formed on the surface of copper decreases while the thickness of the subsequent insulating material formed on the surface of SiO2 increases.

[0053] Table 1 shows the measured thickness, dielectric constant, leakage current density, and EBD voltage of the SiO2 films formed on silicon wafers according to Experimental Example 2, Comparative Example 2, Comparative Example 3, Comparative Example 4, Comparative Example 5, and Comparative Example 6.

[0054] [Table 1]

[0055] In Table 1, n / a in Comparative Example 5 indicates that the dielectric constant value was not measured correctly. The leakage current density was measured when both electrodes (+ and -) were connected to SiO2 and a voltage of 1 MV / cm was applied to both electrodes.

[0056] Table 2 shows the experimental conditions for Experimental Example 2, Comparative Example 2, Comparative Example 3, Comparative Example 4, Comparative Example 5, and Comparative Example 6. The experimental conditions in Table 2 were applied to all Experimental Example 2, Comparative Example 2, Comparative Example 3, Comparative Example 4, Comparative Example 5, and Comparative Example 6, and only SiO2 was on the silicon wafer.

[0057] [Table 2]

[0058] In Table 2, "same as in Experimental Example 1" for the cleaning process indicates that the experimental conditions are the same as those used in Experimental Example 1. Similarly, "same as in Experimental Example 1" for exposure to the reducing agent indicates that the experimental conditions for exposing the silicon wafer to the reducing agent are the same as those used in Experimental Example 1. In subsequent heat treatment, in Experimental Example 2, RTP was rapidly performed on the silicon wafer with N2 gas at a temperature of approximately 400°C; in Comparative Example 3, heat treatment was performed on the silicon wafer with N2 gas at a temperature of 350°C for approximately 2.6 Torr; and in Comparative Example 6, RTP was performed on the silicon wafer with N2 gas at a temperature of approximately 400°C.

[0059] Referring to Experimental Example 2 and Comparative Example 2 in Tables 1 and 2, it can be confirmed that, compared with SiO2 in Comparative Example 2 and Comparative Example 4 without subsequent heat treatment, SiO2 in Experimental Example 2 with subsequent heat treatment exhibits a lower dielectric constant and leakage current density, as well as a higher EBD voltage. Therefore, it can be confirmed that subsequent heat treatment improves the electrical properties of SiO2.

[0060] Referring to Experimental Example 2 and Comparative Example 3 in Tables 1 and 2, it can be confirmed that, compared with SiO2 of Comparative Example 3, which can undergo subsequent heat treatment via conventional heat treatment, SiO2 of Experimental Example 2, which undergoes heat treatment via RTP, exhibits a lower dielectric constant and leakage current density, as well as a higher EBD voltage. Here, conventional heat treatment is the opposite of RTP and refers to the slow increase in temperature of the heat-treated object over tens of seconds or minutes. While the subsequent heat treatment temperature in Experimental Example 2 can be approximately 400°C, the subsequent heat treatment temperature in Comparative Example 3 is approximately 350°C. Therefore, it can be seen that RTP can improve the electrical properties of SiO2 more than conventional heat treatment, and that the electrical properties of SiO2 can be further improved when the temperature range is around 400°C. The range of around 400°C can include the range from approximately 350°C to approximately 400°C.

[0061] Referring to Experimental Example 2 and Comparative Example 6 in Tables 1 and 2, it can be confirmed that, compared with SiO2 in Comparative Example 6 which was not exposed to the reducing agent, SiO2 in Experimental Example 2 exposed to the H2 plasma reducing agent exhibits a lower dielectric constant and leakage current density, as well as a higher EBD voltage. Therefore, it can be confirmed that operations involving exposure to a reducing agent, in addition to performing a cleaning process, can improve the electrical properties of SiO2.

[0062] Table 3 shows the measured concentrations (at%) of carbon, copper, oxygen, and sulfur atoms in the samples according to Experimental Example 3, Comparative Example 7, and Comparative Example 8.

[0063] [Table 3]

[0064] The similarity between Experimental Example 3, Experimental Example 4, and Comparative Example 7 lies in the fact that a heat treatment is performed on a sample grafted with SAM 151 onto a copper layer deposited on a silicon wafer. 1-Dodecylthiol (1-DDT) can be used as the material for SAM 151, and 1-DDT is supplied in a process chamber at a temperature of approximately 125°C to approximately 150°C for approximately 15 minutes. However, as shown in Table 3, the difference between Experimental Example 3, Experimental Example 4, and Comparative Example 7 lies in the heat treatment conditions.

[0065] Referring to Experimental Examples 3, 4, and Comparative Example 7 in Table 3, it can be seen that the concentrations of carbon and sulfur atoms in the samples of Experimental Examples 3 and 4 are significantly lower than those in the sample of Comparative Example 7. The low concentrations of carbon and sulfur atoms in the samples indicate a low concentration of SAM 151. This means that while SAM 151 can be well removed in Experimental Examples 3 and 4, it may not be well removed in Comparative Example 7. In other words, it can be seen that SAM 151 can be well removed when the heat treatment temperature is in the range of approximately 350°C to approximately 400°C.

[0066] Figure 12A is a photograph taken using a transmission electron microscope (TEM) of the copper and SiO2 patterns manufactured according to Comparative Example 8. Figure 12B is a photograph taken using a TEM of the copper and SiO2 patterns manufactured according to Comparative Example 9. Figure 12C is a photograph taken using a TEM of the copper and SiO2 patterns manufactured according to Experimental Example 5.

[0067] In Comparative Example 8, SiO2 patterns and copper patterns are on a silicon wafer, and operations S110 for performing a cleaning process, S130 for selectively forming a passivation layer 150 on the copper pattern, and S140 for selectively forming subsequent SiO2 on the SiO2 pattern can be performed. In operation S110 for performing the cleaning process, the silicon wafer can be immersed in a diluted solution of about 2 wt% citric acid for about 2 minutes and 45 seconds at room temperature, and then washed with distilled water. Operation S130 for selectively forming a passivation layer 150 on the copper pattern may include exposing the silicon wafer to a passivation gas at a temperature of about 125°C to about 150°C for about 10 minutes to about 20 minutes. At this time, the pressure of the passivation gas may be about 0.13 Torr to about 0.2 Torr. The passivation gas includes 1-DDT. After exposing the silicon wafer to the passivation gas, a purging process is performed on the silicon wafer using an inert gas (such as Ar) for about 15 minutes. The selective formation of subsequent SiO2 on the SiO2 pattern, operation S140, may include placing the silicon wafer in a process chamber and supplying a catalyst, a first purging operation, a precursor supply operation, and a second purging operation. TMA can be used as the catalyst, and the TMA is supplied at room temperature for approximately 2 seconds. In the first purging operation, Ar at approximately 150 SCCM can be supplied for approximately 30 seconds at a pressure of approximately 0.7 Torr to approximately 0.8 Torr. Tris(tert-pentoxy)silanol can be used as the precursor, and the tris(tert-pentoxy)silanol is supplied in a pulse at approximately 110°C for approximately 30 seconds. In the second purging operation, Ar at approximately 150 SCCM can be supplied for approximately 60 seconds at a pressure of approximately 0.7 Torr to approximately 0.8 Torr.

[0068] Comparative Example 9 excludes the cleaning process operation S110 in Comparative Example 8 and includes the operation S120 of exposing the silicon wafer to a reducing agent. The operation S120 of exposing the silicon wafer to a reducing agent can be performed before the operation S130 of selectively forming the passivation layer 150 on the copper pattern. In the operation S120 of exposing the silicon wafer to a reducing agent, hydrogen-based plasma is used as the reducing agent, and approximately 70 SCCM of H2 and approximately 100 SCCM of Ar are supplied to the wafer at a temperature of approximately 300°C for approximately 4 minutes. At this time, the pressure can be approximately 1 Torr, and approximately 1500 W of direct plasma power is supplied to the H2 in the process chamber.

[0069] Experimental Example 5 may include all the operations of Comparative Example 8, and may include an operation S120 of exposing the silicon wafer to a reducing agent after the cleaning process operation S110 and before the operation S130 of selectively forming the passivation layer 150 on the copper pattern. The experimental conditions for the operation S120 of exposing the silicon wafer to a reducing agent in Experimental Example 5 may be the same as the experimental conditions for the operation S120 of exposing the silicon wafer to a reducing agent in Comparative Example 9.

[0070] In summary, as a pretreatment, only the cleaning process is performed in Comparative Example 8, only exposure to the reducing agent is performed in Comparative Example 9, and both the cleaning process and exposure to the reducing agent are performed in Experimental Example 5.

[0071] Referring to Figure 12A, in Comparative Example 8, when the pitch between the metal pattern and the SiO2 pattern is small, it can be seen that the subsequently deposited SiO2 can be formed on the existing SiO2 and also on the copper pattern (see the upper photograph of Figure 12A). Even when the pitch between the metal pattern and the SiO2 pattern is large, it can be seen that the selectivity of the subsequently deposited SiO2 can be limited (see the lower photograph of Figure 12A).

[0072] Referring to Figure 12B, it can be seen in Comparative Example 9 that the subsequently deposited SiO2 forms on the existing SiO2 and also on the copper pattern. That is to say, it can be seen in Comparative Example 9 that there is almost no selectivity.

[0073] Referring to Figure 12C, in Experimental Example 5, it can be confirmed that the selectivity of subsequently deposited SiO2 can be improved, whether the pitch between the metal pattern and the SiO2 pattern is small (see the upper photograph of Figure 12A) or large (see the lower photograph of Figure 12A).

[0074] Referring to Figures 12A, 12B, and 12C, it can be confirmed that the selectivity of subsequently deposited SiO2 can be improved when both the cleaning process and exposure to the reducing agent are performed simultaneously, as in Experimental Example 5, rather than when only the cleaning process is performed, as in Comparative Example 8, or when only exposure to the reducing agent is performed, as in Comparative Example 9.

[0075] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A structure including a first insulating pattern and a metal pattern is provided, wherein the first insulating pattern and the metal pattern are disposed on a substrate; Perform a cleaning process on the structure; Expose the structure to a reducing agent; A passivation layer is selectively formed on the metal pattern; A second insulating pattern is selectively formed on the first insulating pattern; as well as The structure is subjected to heat treatment.

2. The method according to claim 1, wherein, The steps involved in performing the cleaning process include: The structure is exposed to a cleaning solution comprising an organic acid having a carboxyl group; and The structure was washed with distilled water.

3. The method according to claim 2, wherein, Organic acids having a carboxyl group include at least one of acetic acid, citric acid, formic acid, formic acid, acetic acid, propionic acid, butyric acid, valeric acid, hexanoic acid, heptanoic acid, octanoic acid, nonanoic acid, decanoic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, adipic acid, pimelic acid, octanoic acid, azelaic acid, sebacic acid, 2-hydroxypropane-1,2,3-tricarboxylic acid, 1-hydroxypropane-1,2,3-tricarboxylic acid, prop-1-ene-1,2,3-tricarboxylic acid, propane-1,2,3-tricarboxylic acid, 2-hydroxynonadecane-1,2,3-tricarboxylic acid, and benzene-1,3,5-tricarboxylic acid.

4. The method according to claim 1, wherein, The reducing agent includes hydrogen-based plasma.

5. The method according to claim 4, wherein, The step of exposing the structure to a reducing agent includes supplying H2 and an inert gas to the structure in a temperature range of about 250°C to about 350°C and in a direct plasma state or a remote plasma state.

6. The method according to claim 1, wherein, The reducing agent includes at least one of methanol, ethanol, n-propanol, and isopropanol.

7. The method according to claim 1, wherein, The step of forming a passivation layer on a metal pattern includes: exposing the structure to a passivation gas, and Passivating gases include methanethiol, ethanethiol, propanethiol, butanethiol, pentatylthiol, hexanethiol, heptanethiol, octylthiol, nonanethiol, decanethiol, undecanethiol, dodecanethiol, tridecanethiol, tetradecanethiol, pentadecanethiol, hexadecanethiol, heptadecanthiol, octadecanethiol, nonadecanthiol, tetrahydro-2H-pyran-4-thiol, 2-propen-1-thiol, tetrahydro-2H-pyran-4-thiol, thiophene, 4-methyl-1-phenylthiophene, 3-methyl-1-phenylthiophene, 2-methyl-1-phenylthiophene, p-xylene-α-thiol, 1H, 1H At least one of the following: 2H,2H-perfluorodecylthiol, 2,2,2-trifluoroethanethiol, 4-methyl-6-trifluoromethyl-pyrimidin-2-thiol, 4-trifluoromethylbenzylthiol, 4-(trifluoromethoxy)benzylthiol, 4-fluorobenzylthiol, 3,5-bis(trifluoromethyl)benzylthiophenol, 2-(trifluoromethyl)benzylthiophenol, 4-trifluoromethyl-2,3,5,6-tetrafluorobenzylthiophenol, 3,5-difluorobenzylthiol, 4-trifluoromethyl-2,3,5,6-tetrafluorobenzylthiophenol, p-trifluoromethylbenzylthiophenol, di-tert-butyl disulfide, and diheptane disulfide.

8. The method according to claim 1, wherein, The passivation layer consists of a self-assembled monolayer (SAM).

9. The method according to claim 1, wherein, The steps of forming a second insulating pattern on a first insulating pattern include: A catalyst is supplied to the structure, wherein a first portion of the catalyst is adsorbed by a first insulating pattern; Perform a first purging operation to remove the second part of the catalyst, excluding the first part of the catalyst. A precursor is supplied to the structure, wherein a first portion of the precursor forms a second insulating pattern; and Perform a second purging operation to remove the second part of the precursor, excluding the first part of the precursor.

10. The method according to claim 9, wherein, The catalyst includes at least one of alkylaluminum, dialkylaminoaluminum, aluminum alkoxide, mixed alkyl-alkoxyaluminum, dialkylaluminum chloride, and aluminum dimethylisopropoxide (DMAI).

11. The method according to claim 9, wherein, The precursor includes at least one of bis(tert-butoxy)(isopropoxy)silanol, bis(isopropoxy)(tert-butoxy)silanol, bis(tert-pentoxy)(isopropoxy)silanol, bis(isopropoxy)(tert-pentoxy)silanol, bis(tert-pentoxy)(tert-butoxy)silanol, bis(tert-butoxy)(tert-pentoxy)silanol, tri(tert-butoxy)silanol, and tri(tert-pentoxy)silanol.

12. The method according to claim 1, wherein, The steps of performing heat treatment on the structure include: performing rapid heat treatment (RTP). The heating rate of RTP is approximately 20°C / s to approximately 30°C / s, and The RTP execution time is approximately 25 to 35 minutes.

13. The method according to claim 12, wherein, The heat treatment of the structure is performed in a temperature range of about 350°C to about 400°C, wherein the RTP is performed for about 25 minutes to about 35 minutes at the highest temperature used in the RTP.

14. The method according to claim 1, wherein, The steps of exposing the structure to a reducing agent and forming a passivation layer on the metal pattern are performed continuously in the same deposition apparatus.

15. A method of manufacturing a semiconductor device, the method comprising: A structure including a first insulating pattern and a metal pattern is provided, the first insulating pattern and the metal pattern being disposed on a substrate. Perform a cleaning process on the structure; Expose the structure to a reducing agent; A passivation layer is selectively formed on the metal pattern; A second insulating pattern is selectively formed on the first insulating pattern; as well as The structure is subjected to heat treatment. The step of forming the second insulating pattern includes multiple cycles, each of which includes: A catalyst is supplied to the structure, wherein a first portion of the catalyst is adsorbed by a first insulating pattern; Perform a first purging operation to remove the second part of the catalyst, excluding the first part of the catalyst. A precursor is supplied to the structure, and a first portion of the precursor forms a second insulating pattern; and Perform a second purging operation to remove the second part of the precursor, excluding the first part of the precursor.

16. The method according to claim 15, wherein, The steps of performing a cleaning process on the structure include: supplying a cleaning solution, which comprises an organic acid having a carboxyl group.

17. The method according to claim 15, wherein, The reducing agent includes hydrogen-based plasma.

18. The method according to claim 15, wherein, The step of forming a passivation layer on a metal pattern includes: exposing the structure to a passivation gas, and Passivating gases include methanethiol, ethanethiol, propanethiol, butanethiol, pentatylthiol, hexanethiol, heptanethiol, octylthiol, nonanethiol, decanethiol, undecanethiol, dodecanethiol, tridecanethiol, tetradecanethiol, pentadecanethiol, hexadecanethiol, heptadecanthiol, octadecanethiol, nonadecanthiol, tetrahydro-2H-pyran-4-thiol, 2-propen-1-thiol, tetrahydro-2H-pyran-4-thiol, thiophene, 4-methyl-1-phenylthiophene, 3-methyl-1-phenylthiophene, 2-methyl-1-phenylthiophene, p-xylene-α-thiol, 1H, 1H At least one of the following: 2H,2H-perfluorodecylthiol, 2,2,2-trifluoroethanethiol, 4-methyl-6-trifluoromethyl-pyrimidin-2-thiol, 4-trifluoromethylbenzylthiol, 4-(trifluoromethoxy)benzylthiol, 4-fluorobenzylthiol, 3,5-bis(trifluoromethyl)benzylthiophenol, 2-(trifluoromethyl)benzylthiophenol, 4-trifluoromethyl-2,3,5,6-tetrafluorobenzylthiophenol, 3,5-difluorobenzylthiol, 4-trifluoromethyl-2,3,5,6-tetrafluorobenzylthiophenol, p-trifluoromethylbenzylthiophenol, di-tert-butyl disulfide, and diheptane disulfide.

19. The method according to claim 15, wherein, The catalyst includes at least one of alkylaluminum, dialkylaminoaluminum, aluminum alkoxide, mixed alkyl-alkoxyaluminum, and dialkylaluminum chloride, and The precursor includes at least one of bis(tert-butoxy)(isopropoxy)silanol, bis(isopropoxy)(tert-butoxy)silanol, bis(tert-pentoxy)(isopropoxy)silanol, bis(isopropoxy)(tert-pentoxy)silanol, bis(tert-pentoxy)(tert-butoxy)silanol, bis(tert-butoxy)(tert-pentoxy)silanol, tri(tert-butoxy)silanol, and tri(tert-pentoxy)silanol.

20. A method of manufacturing a semiconductor device, the method comprising: The structure comprising a first insulating pattern and a metal pattern is placed in a cleaning solution, wherein the first insulating pattern and the metal pattern are set on a substrate; Perform a cleaning process on the structure; The structure is placed inside the deposition equipment; The structure is exposed to a reducing agent in a first process chamber included in a deposition apparatus; A passivation layer is selectively formed on a metal pattern in a second process chamber included in a deposition apparatus, the second process chamber being different from the first process chamber; A second insulating pattern is selectively formed on the first insulating pattern; as well as The structure is subjected to heat treatment. The steps of exposing the structure to a reducing agent and forming a passivation layer on the metal pattern include disconnecting the first process chamber and the second process chamber from each other.

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