Method for forming conformal silicon oxide thin films

Abstract

A method of depositing a high quality conformal silicon oxide (SiOx) film in the formation of a semiconductor device is described. The method includes exposing a semiconductor substrate to a first precursor, a first purge gas, a second precursor, a second purge gas, and a remote plasma source (RPS) microwave plasma to deposit a conformal silicon oxide (SiOx) film.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for depositing films in the fabrication of semiconductor devices. Specifically, embodiments of the present invention relate to depositing high-quality conformal silicon oxide (SiO2) in the formation of high aspect ratio semiconductor devices. x (Layer method) Background Technology

[0002] The semiconductor processing industry continuously strives to improve yield while increasing the uniformity of layers deposited on substrates with large surface areas. These same factors, combined with new materials, also provide greater circuit integration per unit area of ​​the substrate. As circuit integration increases, the demand for greater uniformity in layer thickness and processing control rises. Therefore, various technologies have been developed to deposit layers on substrates cost-effectively while maintaining control over layer characteristics.

[0003] The increasing complexity of advanced microelectronic devices places stringent demands on current deposition techniques. Unfortunately, the number of available chemical precursors is limited, and they must possess strong thermal stability, high reactivity, and suitable vapor pressures for film growth. Furthermore, precursors that meet these requirements often suffer from poor long-term stability and result in films containing high concentrations of impurities such as oxygen, nitrogen, and / or halides, which are generally detrimental to the target film application.

[0004] The performance of semiconductor devices with high aspect ratio apertures is related to the properties of the materials used and the thickness and area of ​​the structural layers. However, challenges arise as certain characteristics are tuned to accommodate device scaling. It is difficult to obtain high-quality (low wet etch rate (WER)) conformal silicon oxide (SiOx) films on high aspect ratio structures, especially in reentrant structures such as GAA and 3D DRAM, using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and plasma-enhanced atomic layer deposition (PEALD).

[0005] silicon dioxide (SiO) x Silicon oxide (SiOx) films possess attractive material and electrical properties for semiconductor devices. These films have been proposed and tested for applications in front-end to back-end components of semiconductors and microelectronics. Currently, most atomic layer deposition techniques for silicon oxide (SiOx) films are based on halogen-containing silane precursors. Halogen contamination can affect device performance and therefore requires additional removal steps. Furthermore, halogen removal sometimes requires higher thermal budgets. High-temperature processing is not desirable for temperature-sensitive substrates (e.g., logic and memory devices).

[0006] Therefore, there is a need in this field for high-quality silicon oxide (SiO2).x There is a need in the art for forming high-quality conformal silicon oxide (SiO2) films for logic or memory elements. Furthermore, there is a demand in the art for forming high-quality conformal silicon oxide (SiO2) films for logic or memory elements. x The need for membrane methods. Summary of the Invention

[0007] One or more embodiments of the present invention relate to a method for depositing a film on a semiconductor device. The method for depositing a film on a semiconductor device includes: exposing a semiconductor substrate in a semiconductor processing chamber to a first precursor; exposing the semiconductor substrate to a first purge gas; exposing the semiconductor substrate to a second precursor; exposing the semiconductor substrate to a second purge gas; and exposing the semiconductor substrate to a remote plasma source (RPS) microwave plasma to deposit a conformal silicon oxide (SiOx) film on the surface of the semiconductor substrate.

[0008] Another embodiment of the present invention relates to a method of manufacturing logic or memory elements. In one or more embodiments, the method of manufacturing logic or memory elements includes: in a deposition cycle, exposing a substrate having at least one feature, a top surface, a sidewall surface, and a bottom surface, contained in a semiconductor processing chamber, to a first precursor containing a silicon precursor, a first purge gas, a second precursor containing an oxidant, a second purge gas, and a remote plasma source (RPS) microwave plasma to conformally deposit a silicon oxide (SiOx) film on one or more of the top surface, sidewall surface, and bottom surface with at least one feature. Attached Figure Description

[0009] A more specific description of the invention, briefly summarized above, can be obtained by referring to the embodiments illustrated in the accompanying drawings, in which the foregoing features of the invention can be understood in detail. However, it will be noted that the drawings illustrate only typical embodiments of the invention and are therefore not intended to limit its scope, as other equivalent embodiments are permissible. The embodiments described herein are illustrative by way of example and are not limited to the drawings, in which the same reference numerals indicate similar elements.

[0010] Figure 1 A flowchart illustrating a method for depositing a film on a substrate according to one or more embodiments;

[0011] Figure 2A A cross-sectional view of a substrate according to one or more embodiments is shown;

[0012] Figure 2B A cross-sectional view of a substrate according to one or more embodiments is shown; and

[0013] Figure 3 A clustering tool according to one or more embodiments of the present invention is illustrated.

[0014] To facilitate understanding, the same reference numerals have been used wherever possible to refer to common elements in the figures. The figures are not drawn to scale and have been simplified for clarity. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further explanation. Detailed Implementation

[0015] Before describing several exemplary embodiments of the present invention, it will be understood that the invention is not limited to the details of the architecture or processing steps described in the following description. The invention can be implemented or performed in various ways and in other ways.

[0016] As used herein, the term “about” means approximately or nearly, and in the context of the stated value or range, it means a variation of ±15% or less of that value. For example, values ​​with differences of ±14%, ±10%, ±5%, ±2%, or ±1% would satisfy the definition of “about.”

[0017] Spatial relative terms such as “below,” “under,” “below,” “above,” “above,” and similar expressions are used herein to simplify descriptions of the relationship between one element and another element or feature, as illustrated in the figures. It will be understood that spatial relative terms are intended to cover different orientations of a semiconductor element in use or operation, other than those depicted in the figures. For example, if the semiconductor element in the figures is inverted, an element described as “below” or “under” other elements will be oriented “above” other elements. Therefore, the exemplary term “below” can encompass both above and below orientations. Semiconductor elements may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial relative descriptors used herein will be interpreted accordingly.

[0018] When used herein, the terms "substrate" or "wafer" refer to the surface or part thereof on which processing is performed. Unless the context clearly indicates otherwise, those skilled in the art will understand that "substrate" may also refer to only a part of a substrate. Furthermore, "deposition on a substrate" may mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0019] As used herein, “substrate” refers to any substrate on which layering processes are performed during manufacturing, or a material surface formed on a substrate. For example, substrate surfaces on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. In some embodiments, a semiconductor substrate comprises one or more of doped or undoped crystalline silicon (Si), doped or undoped crystalline silicon germanium (SiGe), doped or undoped amorphous silicon (Si), or doped or undoped amorphous silicon germanium (SiGe). The substrate may be exposed to pretreatment processes for polishing, etching, reduction, oxidation, hydroxylation, annealing, and / or baking of the substrate surface. In addition to layering processes performed directly on the surface of the substrate itself, any layering steps disclosed in this invention may also be performed over an underlying layer formed on the substrate, as described in more detail below, and the term “substrate surface” is intended to include this underlying layer as indicated by the context. Therefore, for example, where a layer or part of a layer has been deposited onto the substrate surface, the exposed surface of the newly deposited layer becomes the substrate surface.

[0020] For the avoidance of doubt, the identification methods of the materials disclosed herein do not imply stoichiometric ratios. For example, silicon oxide (SiO) contains silicon and oxygen, silicon nitride (SiN) contains silicon and nitrogen, and silicon oxynitride (SiON) contains silicon, oxygen, and nitrogen. Unless otherwise stated herein, these elements may be present in a 1:1 ratio or a 1:1:1 ratio, or not in a 1:1:1 ratio.

[0021] It will be appreciated that the methods described herein can be implemented on any substrate surface having one or more features formed therein, one or more layers formed thereon, or combinations thereof. The shape of the features can be any suitable shape, including but not limited to trenches, holes, and through-holes (circular or polygonal). When used in this manner, the term "feature" refers to any intentional surface irregularity. Suitable examples of features include, but are not limited to, trenches, through-holes, and slotted vias, with trenches having a top, sidewalls, and a bottom extending into the substrate, and through-holes having one or more sidewalls extending into the substrate to the bottom. The features described herein can have any suitable aspect ratio (the ratio of the depth of a feature to the width of a feature). In one or more embodiments, the aspect ratio of the features described herein is greater than or equal to about 1:1, 2:1, 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, or 40:1.

[0022] The phrase "above" indicates that there is direct contact between components. The phrase "directly above" indicates that there is direct contact between components without any components in between.

[0023] When used herein, the term "in-situ" refers to all processes being performed in the same processing chamber or in different processing chambers connected as part of an integrated processing system, such that each process is performed without vacuum disruption therebetween. When used herein, the term "non-in-situ" refers to processes being performed in at least two different processing chambers, such that one or more processes are performed with vacuum disruption therebetween. In some embodiments, processes are performed without vacuum disruption or exposure to ambient air.

[0024] When used in this specification and the appended claims, the terms “precursor,” “reactant,” “reactive gas,” and the like are used interchangeably to refer to any gaseous species that can react with the substrate surface.

[0025] When used herein, the term "chemical vapor deposition" refers to the exposure of at least one reactive species to deposit a material layer on a substrate surface. In some embodiments, a chemical vapor deposition (CVD) process includes mixing two or more reactive species in a process chamber to allow for gas-phase reaction and deposition of the reactive species. In some embodiments, a CVD process includes simultaneously exposing a substrate surface to two or more reactive species. In some embodiments, a CVD process includes continuously exposing a substrate surface to a first reactive species and intermittently exposing it to a second reactive species. In some embodiments, the substrate surface undergoes a CVD reaction to deposit a layer having a predetermined thickness. In a CVD process, this layer may be deposited in a single exposure of the mixed reactive species or in multiple exposures of the mixed reactive species, with cleanup between exposures. In some embodiments, the substrate surface is substantially simultaneously exposed to the first and second reactive species.

[0026] When used here, “substantially simultaneously” means that most of the period of exposure to the first responder species overlaps with the period of exposure to the second responder species.

[0027] As used herein, the term "decontamination" includes any suitable decontamination process that removes unreacted precursors, reaction products, and byproducts from a process area. Suitable decontamination processes include moving a substrate through a gas curtain to a portion or sector of the processing area that is free of or substantially free of reactants. In one or more embodiments, the decontamination chamber includes applying a vacuum. In some embodiments, the decontamination area includes flowing a decontamination gas over the substrate. In some embodiments, the decontamination process includes flowing an inert gas. In one or more embodiments, the decontamination gas is selected from one or more of nitrogen (N2), helium (He), neon (Ne), and argon (Ar). In some embodiments, the first reactive species is purified from the reaction chamber for a duration ranging from 0.1 seconds to 30 seconds, from 0.1 seconds to 10 seconds, from 0.1 seconds to 5 seconds, from 0.5 seconds to 30 seconds, from 0.5 seconds to 10 seconds, from 0.5 seconds to 5 seconds, from 1 second to 30 seconds, from 1 second to 10 seconds, from 1 second to 5 seconds, from 5 seconds to 30 seconds, from 5 seconds to 10 seconds, or from 10 seconds to 30 seconds before the substrate is exposed to the second reactive species.

[0028] "Cyclic deposition" or "atomic layer deposition (ALD)" refers to the sequential exposure of two or more reactive species to deposit a material layer on a substrate surface. The substrate or portions thereof are separately exposed to two or more reactive species in reaction regions introduced into a processing chamber. In time-domain ALD processes, exposure to each individual species is separated by a time delay to allow individual compounds to adhere to and / or react on the substrate surface, and then be decontaminated from the processing chamber. These reactive species are referred to as being sequentially exposed to the substrate. In spatial ALD processes, different portions of the substrate surface or material on the substrate surface are simultaneously exposed to these two or more reactive species, such that at any given point on the substrate, substantially no more than one reactive species is exposed simultaneously. As used in this specification and the appended claims, as will be understood by those skilled in the art to which this invention pertains, the term "substantially" as used in this regard means the possibility that a small portion of the substrate may be simultaneously exposed to multiple reactive gases due to diffusion, and that such simultaneous exposure is not intentional.

[0029] In one aspect of time-domain ALD processing, a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction region, followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction region, followed by a second delay. During each time delay, a purge gas, such as argon, is introduced into the processing chamber to purge the reaction region or remove any residual reactive species or reaction byproducts from the reaction region. Alternatively, the purge gas may flow continuously throughout the deposition process, such that only purge gas flows during the time delay between pulses of the reactive species. The reactive species are pulsed until a desired layer or layer thickness is formed on the substrate surface. In either scenario, the ALD processing of pulsed compound A, purge gas, compound B, and purge gas is a cycle. A cycle can be started with either compound A or compound B, and this cycle can continue in an individual sequence until a layer of predetermined thickness is achieved.

[0030] One or more layers deposited on or on a substrate are continuous. When used herein, the term "continuous" refers to a layer that covers the entire exposed surface without gaps or bare spots of material exposed beneath the deposited layer. A continuous layer may have gaps or bare spots with a surface area less than about 15% or less than about 10% of the total surface area of ​​the layer.

[0031] One or more layers deposited on a substrate or its surface are conformal. As used herein, "conformal" means that the layer conforms to the contour of a feature or layer. The conformality of a layer is typically quantified by the ratio of the average thickness of the layer deposited on the sidewalls of a feature to the average thickness of the same deposited layer on the field area or upper surface of the substrate. As used herein, a "conformally deposited" layer refers to a layer whose thickness is approximately uniform overall. The thickness variation of a conformally deposited layer is less than or equal to about 5%, 2%, 1%, or 0.5%. In one or more embodiments, the deposited film has a conformality greater than 90%, or greater than 91%, or greater than 92%, or greater than 93%, or greater than 94%, or greater than 95%, or greater than 96%, or greater than 97%, or greater than 98%, or greater than 99%.

[0032] Electronic components in devices such as personal computers, workstations, computer servers, mainframes, and other computer-related equipment such as printers, scanners, and hard drives utilize memory components with large data storage capabilities while maintaining low power consumption. There are two main types of random access memory (RAM): dynamic and static, which are well-suited for use in electronic components. Dynamic random access memory (DRAM) can be programmed to store a voltage, representing one of two binary values, but requires periodic reprogramming or "updating" to maintain this voltage for very short periods. Static random access memory (SRAM) is so named because it does not require periodic updates.

[0033] In this context, the term "Dynamic Random Access Memory" or "DRAM" refers to a memory cell that stores data bits by storing either a charge packet (i.e., a binary 1) or no charge (i.e., a binary 0) on a capacitor. The charge is conducted to the capacitor through the gate of an access transistor, and is sensed by turning on the same transistor, and the voltage disturbance generated by the charge packet being poured onto the interconnect at the transistor output is observed. Therefore, a single DRAM cell is made of one transistor and one capacitor. DRAM elements are formed from arrays of DRAM cells.

[0034] DRAM memory circuits are manufactured by replicating millions of identical circuit elements (known as DRAM cells) on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary bit) of data. In its most common form, a DRAM cell consists of two circuit components: a field-effect transistor (FET) and a capacitor.

[0035] The fabrication of a DRAM cell includes the fabrication of transistors, capacitors, and three contacts: one to a bit line, one to a word line, and one to a reference voltage. A transistor is a circuit component or element typically formed on a semiconductor device. Depending on the circuit design, transistors are formed on the semiconductor device after capacitors, inductors, resistors, diodes, wires, or other components. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of the substrate and exhibit a doping profile suitable for a particular application. The gate is positioned above the channel region and includes a gate dielectric interposed between the gate electrode and the channel region in the substrate.

[0036] In this context, the term "field-effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of a device. Enhancement-mode field-effect transistors typically exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by an electric field within the device, generated by the voltage difference between the body and the gate. The three terminals of an FET are the source (S), through which charge carriers enter the channel; the drain (D), through which charge carriers leave the channel; and the gate (G), which modulates the channel conductivity. Conventionally, the current entering the channel at the source (S) is denoted as I. S The current entering the channel at the drain (D) is denoted as I. D The drain-to-source voltage is indicated by V. DS By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., Id) can be controlled. D ).

[0037] A MOSFET (Metal-O-Silicon Field-Effect Transistor) is a type of field-effect transistor (FET). It features an insulated gate, the voltage of which determines the conductivity of the element. The ability to change conductivity by the amount of applied voltage is used to amplify or switch electronic signals. A MOSFET is based on the modulation of charge concentration through a metal-oxide-semiconductor (MOS) capacitor between the body electrode and the gate electrode, which is located above the body and insulated from all other element regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a separate, highly doped region separated by the body region. These regions can be p-type or n-type, but they are of the same type and opposite in type to the body region. The source and drain (different from the body) are highly doped and indicated by a "+" sign after the doping type.

[0038] If the MOSFET is an n-channel or nMOS FET, the source and drain are in the n+ region, while the bulk is in the p region. If the MOSFET is a p-channel or pMOS FET, the source and drain are in the p+ region, while the bulk is in the n region. The source is so named because it is the origin of charge carriers flowing through the channel (electrons for n-channels and holes for p-channels); similarly, the drain is where charge carriers leave the channel.

[0039] In this context, the term "FinFET" refers to a MOSFET transistor built on a substrate, where the gate is placed on two or three sides of the channel, forming a dual-gate or triple-gate structure. FinFET devices have been given the common name FinFET because the channel region forms "fins" on the substrate. FinFET devices feature fast switching times and high current densities.

[0040] When used herein, the term "gate all around (GAA)" is used to refer to an electronic device, such as a transistor, in which gate material surrounds a channel region on all sides. The channel region of a GAA transistor may include nanowires or nano-slabs, strip channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA element has a plurality of vertically spaced horizontal nanowires or horizontal strips, such that the GAA transistor is a stacked horizontal gate all around (hGAA) transistor.

[0041] In this context, the term "nanowire" refers to a nanostructure with a diameter of one nanometer (10⁻⁶). −9Nanowires are on the order of meters. A nanowire can also be defined as having a length-to-width ratio greater than 1000. Alternatively, a nanowire can be defined as a structure having a thickness or diameter limited to tens of nanometers or less and an unlimited length. Nanowires are used in transistors and some laser applications, and in one or more embodiments, nanowires are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and non-volatile (e.g., NAND) components. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure having a thickness ranging from about 0.1 nm to about 1000 nm.

[0042] The aforementioned methods involve forming a silicon oxide (SiOx) film on a substrate surface using atomic layer deposition (ALD) or plasma-enhanced atomic layer deposition (PEALD). The resulting silicon oxide film is of low quality (with high wet etching in diluted hydrofluoric acid (DHF), lacks good conformability suitable for high aspect ratio (HAR) structures, has high leakage current, and high breakdown electric field).

[0043] Embodiments of the present invention advantageously provide a plasma-enhanced atomic layer deposition (PEALD) method for depositing high-quality (low wet etch rate (WER)) conformal silicon oxide (SiOx) films without damaging the surrounding semiconductor structure. One or more embodiments of the method advantageously utilize RPS microwaves as the plasma source for PEALD. In one or more embodiments, RPS microwave treatment advantageously eliminates ion bombardment effects on the silicon oxide (SiOx) film.

[0044] In one or more embodiments, the methods described herein advantageously provide silicon oxide (SiOx) films with good conformability in high aspect ratio structures, high-quality films with low WER, and containing desired electrical properties.

[0045] One or more embodiments advantageously provide conformal silicon oxide (SiOx) films as dielectric materials for GAA structures. One or more embodiments advantageously provide conformal silicon oxide (SiOx) films as dielectric materials for 3D-DRAM structures. Some embodiments advantageously provide methods for directly depositing silicon oxide (SiOx) films on the surface of semiconductor substrates. In one or more embodiments, the deposited silicon oxide (SiOx) film has a low dielectric constant (k). In some embodiments, the dielectric constant is less than 4.5 (k < 4.5) or less than 4.0 (k < 4.0).

[0046] When used here, the term "high quality" means that the deposited silicon oxide (SiOx) film has a wet etch rate of less than 30 Å / min in a 100:1 dilution of hydrofluoric acid (DHF), or a wet etch rate of less than 5 Å / min in a 500:1 dilution of hydrofluoric acid (DHF).

[0047] When used here, the term "low leakage current" means that the deposited silicon oxide (SiOx) film has a leakage current of less than 1 x 10⁻⁶ at 2 MV / cm. -6 A / cm 2 When used here, the term "high collapse electric field" means that the deposited silicon oxide (SiOx) film has a collapse electric field greater than 6 MV / cm.

[0048] As is recognized by those skilled in the art, it is difficult to obtain conformal films with uniform composition in devices with high aspect ratios using plasma processing, especially, for example, on trenches / features of GAA and 3D-DRAM devices. Therefore, one or more embodiments advantageously provide RPS microwaves as a plasma source for conformal silicon oxide (SiOx) film PEALD. The PEALD method of one or more embodiments forms conformal films with uniform composition on high aspect ratio structures.

[0049] Embodiments of the present invention are illustrated by way of figures illustrating elements (e.g., GAA and 3D DRAM) and processes for forming semiconductor structures according to one or more embodiments of the present invention. The processes shown are merely illustrative possible uses for the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated applications.

[0050] Figure 1 A process flow diagram illustrating a deposition film method 10 according to one or more embodiments is shown. Figure 2A-2B A cross-sectional view of a semiconductor substrate processed according to one or more embodiments is shown. Figure 3 The plotting cluster tool 300 may contain, for example, any semiconductor element described herein, such as semiconductor element 100, in which it may be fabricated, and any method described herein, such as method 10, in which it may be performed.

[0051] Reference Figure 1 and Figure 2A-2B In one or more embodiments, during operation 12, a substrate is provided. As used in this specification and the appended claims, the term "provided" means that the substrate is made suitable for use in processing (e.g., positioned in a processing chamber).

[0052] Reference Figure 2AIn one or more embodiments, the substrate includes a first surface 102 and a second surface 104. In one or more embodiments, the first surface 102 comprises a first material, and the second surface 104 comprises a second material. In some embodiments, the first material and the second material are the same. In other embodiments, the first material and the second material are different.

[0053] In one or more embodiments, the first surface 102 comprises a metallic material. In one or more embodiments, the second surface 104 comprises a dielectric surface. In other embodiments, the second surface 104 comprises one or more of a dielectric surface, a semiconductor surface, a non-metallic surface, or a metallic surface, wherein the metal of the metallic surface is different from the metal of the first surface 102.

[0054] In one or more embodiments, the substrate on which the silicon oxide (SiOx) layer 107 is formed may include a material in which one or more features 107 may be formed. The substrate feature 107 may be characterized by any shape or construction according to the invention. In some embodiments, the feature 107 may be or include a trench structure, a via structure, or a hole formed within the substrate. While the substrate feature 107 may be characterized by any shape or size, in some embodiments, the substrate feature 107 may be characterized by a high aspect ratio or the ratio of the feature's depth to the width spanning the feature. For example, in some embodiments, the substrate feature 107 may be characterized by an aspect ratio greater than or equal to 5:1, and may be characterized by an aspect ratio greater than or equal to 10:1, greater than or equal to 15:1, greater than or equal to 20:1, greater than or equal to 25:1, greater than or equal to 30:1, greater than or equal to 40:1, greater than or equal to 50:1, or greater. Furthermore, feature 107 can be characterized as a narrow width or diameter spanning the feature between two sidewalls, such as a scale less than or equal to 20 nm, and can be characterized as a width spanning the feature less than or equal to 15 nm, less than or equal to 12 nm, less than or equal to 10 nm, less than or equal to 9 nm, less than or equal to 8 nm, less than or equal to 7 nm, less than or equal to 6 nm, less than or equal to 5 nm, or smaller. In some embodiments, feature 107 has a top surface 106, at least one sidewall surface 109, and a bottom surface 111.

[0055] As used herein, “metal” refers to metal, metallicity, metal alloy, metal oxide, metal nitride, or a combination thereof. As used herein, “metal surface” refers to any portion of a substrate formed of metal or a portion of the surface of a material. Metal surfaces may be exposed to pretreatment processes such as polishing, coating, doping, etching, reduction, oxidation, hydroxylation, annealing, UV curing, electron beam curing, and / or baking of the substrate. In addition to pretreatment directly on the metal surface itself, in this invention, any of the disclosed metal surface treatments may also be performed on the underlying metal surface, as described in more detail below, and the term “metal surface” is intended to include this underlying layer as indicated by the context. Thus, for example, where a film / layer or portion of a film / layer has already been deposited on a metal surface, the exposed surface of a newly deposited film / layer becomes the metal surface.

[0056] In one or more embodiments, the first surface 102 comprises a metal, a metal alloy, a metal oxide, a metal nitride, or a combination thereof. In one or more embodiments, the second surface 104 comprises a metal, a metal alloy, a metal oxide, a metal nitride, or a combination thereof. Non-limiting examples of metals include copper (Cu), cobalt (Co), nickel (Ni), tungsten (W), ruthenium (Ru), chromium (Cr), iron (Fe), platinum (Pt), gold (Au), silver (Ag), molybdenum (Mo), gallium (Ga), indium (In), tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), nickel (Ni), their oxides, or combinations thereof. In one or more specific embodiments, the first surface 102 comprises one or more of copper (Cu), cobalt (Co), ruthenium (Ru), tungsten (W), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), tantalum (Ta), aluminum (Al), nickel (Ni), or combinations thereof.

[0057] In one or more embodiments, the first surface 102 comprises a dielectric material. In one or more embodiments, the second surface 104 comprises a dielectric material. As used herein, "dielectric surface" refers to any portion of a substrate or a portion of a material surface formed of a dielectric material. Non-limiting examples of dielectric materials include silicon oxide (SiO2). x ), silicon nitride (Si x N y Silicon (Si), silicon oxynitride (SiON), carbides, oxycarbides, nitrides, oxynitrides, oxycarbonitrides, polymers, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicon glass (SiOCH), alumina (AlO) x ), hafnium oxide (HfO) x Zirconia (ZrO2) and titanium dioxide (TiO2) x Titanium nitride (TiN), tantalum oxide (Ta) xO5), Yttrium oxide (Y2O3), Lanthanum oxide (La2O3), Aluminum nitride (AlN), Magnesium oxide (MgO), Calcium fluoride (CaF2), Lithium fluoride (LiF), Strontium oxide (SrO), Silicon carbide (SiC), Barium oxide (BaO), Hafnium silicate (HfSiO4), Lanthanum aluminate (LaAlO3), Niobium pentoxide (Nb2O5), Barium titanate (BaTiO3), Strontium titanate (SrTiO3), Bismuth titanate (Bi4Ti3O5) 12 ), lead zirconate titanate (Pb(Zr, Ti)O3), calcium copper titanate (CaCu3Ti4O) 12 The second surface 104 comprises silicon oxide (SiO2), lithium niobate (LiNbO3), barium titanate (BaTiO3), and potassium niobate (KNbO3). In one or more embodiments, the second surface 104 comprises silicon oxide (SiO2). x Silicon carbide (SiOC), silicon carbonitride (SiOCN), silicon nitride (SiN), silicon oxynitride (SiON), silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), indium gallium zinc oxide (InGaZnO), aluminum oxide (AlO) x Aluminum nitride (AlN) and hafnium oxide (HfO) x One or more of them.

[0058] Reference Figure 1 One or more embodiments of the present invention relate to a method 10 for depositing a film. Figure 1 The diagram illustrates a representative plasma-enhanced atomic layer deposition (PEALD) process, in which a substrate or substrate surface is sequentially exposed to reactive gases in a manner that prevents or minimizes gas-phase reactions of the reactive gases. In some embodiments, the method may include a plasma-enhanced chemical vapor deposition (PECVD) process, in which reactive gases are mixed in a processing chamber to allow for gas-phase reactions of the reactive gases and deposition of a thin film.

[0059] Reference Figure 1 and Figure 2B In deposition 30 or deposition cycle 30, a process is performed to deposit a conformal silicon oxide (SiOx) film 108 on a substrate (or substrate surface). The deposition process may include one or more operations to form a film on the substrate. In operation 14, the substrate (or substrate surface) is exposed to a first precursor, such as a silicon-containing precursor, to deposit a film on the substrate (or substrate surface). The silicon-containing precursor may be any suitable compound that can react on the substrate surface (i.e., adsorb or chemisorb thereon) to leave silicon-containing species on the substrate surface.

[0060] In one or more embodiments, the first precursor may comprise any suitable silicon-containing precursor known to those skilled in the art. In one or more embodiments, the first precursor comprises a disilacyclobutane precursor or a trisilacyclohexane precursor. In one or more embodiments, the first precursor comprises disilacyclobutane having the chemical formula R 3 R 2 R 1 -Si-C x H 2x -Si-R 1 R 2 R 3 The precursor, or one or more of the trisilacyclohexane precursor, wherein R 1 R 2 R 3 The radical is independently selected from hydrogen (H), dimethylamino, diethylamino, alkyl, alkoxy, vinyl, silane, amine, or halide, and x is an integer in the range of 1 to 10 or in the range of 2 to 10.

[0061] In some embodiments, the first precursor is disilacyclobutane, having the general formula (I):

[0062] Where R 1 R 2 R 3 R 4 R 5 R 6 R 7 and R 8 Independently selected from hydrogen (H), alkyl, alkoxy, vinyl, silane, amine, dimethylamino, or halide. In a particular embodiment, R 1 R 2 R 5 、and R 6 It is hydrogen, and R 3 R 4 R 7 、and R 8 It is independently selected from hydrogen (H), alkyl, alkoxy, vinyl, silane, amine, dimethylamino, or halide.

[0063] In one or more embodiments, the first precursor comprises one or more of bis(tris(dimethylamido)silyl)methane, bis(trichlorosilyl)methane, and 1,1,3,3-tetrakis(dimethylamino)-1,3-disilacyclobutane.

[0064] In some embodiments, the first precursor is a trisilacyclohexane precursor having the general formula (II):

[0065] Where R 1 R 2 R 3 R 4 R 5 and R 6 It is independently selected from hydrogen (H), alkyl, alkoxy, vinyl, silane, amine, dimethylamino, or halide.

[0066] Unless otherwise specified, the terms “lower alkyl,” “alkyl,” or “alkane,” used alone or as part of another group, include both straight-chain and branched hydrocarbons containing 1 to 24 carbons in their regular chain, such as methyl, ethyl, propyl, isopropyl, butyl, tributyl, isobutyl, pentyl, hexyl, isohexyl, heptyl, 4,4-dimethylpentyl, octyl, 2,2,4-trimethylpentyl, nonyl, decyl, undecyl, dodecyl, their various branched isomers, and the like. These groups may optionally include up to 1 to 4 substituents.

[0067] When used here, the term "alkoxy" includes any of the aforementioned alkyl groups linked to an oxygen atom.

[0068] When used here, the term "vinyl" or "vinyl-containing" refers to a group containing a vinyl group (-CH=CH2).

[0069] When used here, the term "amine" refers to any organic compound containing at least one basic nitrogen atom, such as NR'2, where R' is independently selected from hydrogen (H) or alkyl.

[0070] When used here, the term "silane" refers to the compound SiR'3, where R' is independently selected from hydrogen (H) or alkyl.

[0071] When used herein, the term "halide" refers to a binary phase, one part of which is a halogen atom and the other part is an element or radical that is less electronegative than the halogen, to form fluoride, chloride, bromide, iodide, or arsenic compound. A halide ion is a negatively charged halogen atom. As known to those skilled in the art, halide anions include fluorides (F-), chlorides (Cl-), bromides (Br-), iodides (I-), and arsenic compounds (At-).

[0072] Deposition 30 can occur at any suitable temperature, pressure, and exposure period known to those skilled in the art. In some embodiments, the substrate (or substrate surface) is exposed to the first and second precursors at pressures ranging from 0.1 Torr to 100 Torr, or from 1 Torr to 50 Torr, and at temperatures ranging from 200 °C to 550 °C.

[0073] As used herein, "substrate surface" refers to any substrate surface on which layers may be formed. A substrate surface may have one or more features formed thereon, one or more layers formed thereon, or combinations thereof. Prior to the deposition of a silicon oxide (SiOx) film, the substrate (or substrate surface) may be pretreated, for example by polishing, etching, reduction, oxidation, halogenation, hydroxylation, annealing, baking, or similar treatments. In some embodiments, the substrate surface is part of a gate-all-around (GAA) element or a 3D-DRAM element.

[0074] In operation 16, the processing chamber or substrate surface is cleaned to remove unreacted first precursors, reaction products, and byproducts. When used in this manner, the term "processing chamber" also includes a portion of the processing chamber adjacent to the substrate surface without encompassing the entire internal volume of the processing chamber. For example, in spatially separated sections of processing chambers, the portion of the processing chamber adjacent to the substrate surface is cleaned of the first precursor by any suitable technique, including but not limited to moving the substrate through an air curtain to a portion or section of the processing chamber that does not contain or substantially does not contain the first precursor. In one or more embodiments, cleaning the processing chamber involves applying a vacuum. In some embodiments, cleaning the processing chamber involves flowing a clean gas over the substrate. In some embodiments, a portion of the processing chamber refers to a micro-volume or small-volume processing station within the processing chamber. The term "adjacent" to the substrate means the physical space next to the surface of the substrate, which provides sufficient space for surface reactions (e.g., precursor adsorption) to occur. In one or more embodiments, the clean gas is selected from, but is not limited to, one or more of nitrogen (N2), helium (He), neon (Ne), and argon (Ar). Purification process chambers, parts of the processing chambers, areas adjacent to the substrate surface, etc., remove unreacted reactants, reaction products, and byproducts from areas adjacent to the substrate surface.

[0075] In operation 18, the substrate (or substrate surface) is exposed to a second precursor to form a conformal silicon oxide (SiOx) film 108 on the substrate. The second precursor may comprise any suitable precursor known to those skilled in the art. In one or more embodiments, the second precursor comprises an oxidizing agent. The second precursor may react with silicon-containing species on the substrate surface to form the conformal silicon oxide (SiOx) film 108.

[0076] In one or more embodiments, the second precursor comprises one or more of a carboxylic acid, an alcohol (e.g., methanol, ethanol, propanol, isopropanol, and the like), acetic acid, ethylene glycol, oxygen (O2), ozone (O3), hydrogen peroxide (H2O2), and water (H2O).

[0077] During operation 18, exposure to the second precursor may occur at any suitable temperature, pressure, and exposure period known to those skilled in the art. In some embodiments, the substrate (or substrate surface) is exposed to the second precursor at pressures ranging from 0.1 Torr to 100 Torr, or from 1 Torr to 50 Torr, and at temperatures ranging from 200 °C to 550 °C.

[0078] As those skilled in the art will recognize, the order in which the substrate or substrate surface is exposed to the first precursor and the second precursor can be reversed. For example, in some embodiments, the substrate or substrate surface may be exposed to the second precursor in operation 14 and then to the first precursor in operation 18.

[0079] In operation 20, the processing chamber is cleaned after exposure to the second precursor. The cleanup process in operation 20 may be the same as or different from the cleanup in operation 16. The cleanup process, portions of the processing chamber, areas adjacent to the substrate surface, etc., remove unreacted silane reactants, reaction products, and byproducts from areas adjacent to the substrate surface.

[0080] Reference Figure 1 In operation 22, the substrate is exposed to a remote plasma source (RPS) microwave plasma. In one or more embodiments, method 10 in operation 22 uses a remote plasma source outside the plasma processing chamber and delivers remotely generated plasma to or excites plasma within the plasma processing chamber to introduce plasma into the processing area of ​​the chamber. In one or more embodiments, the RPS microwave plasma operates at a frequency greater than 300 MHz and less than 30 GHz, for example, 2.45 GHz, and has a very high charge and plasma density compared to a capacitive plasma source. In some embodiments, the plasma density ranges from 10 12 / cm 3 Up to 10 13 / cm3 And in some embodiments, the ion energy is less than 10 eV.

[0081] In one or more embodiments, the RPS microwave plasma comprises hydrogen (H2) or hydrogen (H2) mixed with an inert gas. The inert gas may comprise any suitable inert gas, including but not limited to argon (Ar), helium (He), neon (Ne), and nitrogen (N2). In one or more embodiments, a remote microwave plasma source generates microwave plasma with a high frequency. The microwave plasma may or may not have an ion blocker. In one or more embodiments, the plasma is configured to generate plasma with a high hydrogen radical (H*) density, with minimal or no ion bombardment.

[0082] Still refer to Figure 1 In operation 24, the processing chamber is cleaned after exposure to RPS microwave plasma. The cleanup of the processing chamber in operation 24 can be the same as or different from the cleanup in operations 16 and 20. The cleanup of the processing chamber, portions of the processing chamber, areas adjacent to the substrate surface, etc., removes unreacted silane reactants, reaction products, and byproducts from areas adjacent to the substrate surface.

[0083] Reference Figure 1 In step 26, the thickness of the deposited silicon oxide (SiOx) film 108 or the number of cycles between the first and second precursors is considered. If the deposited film has reached a predetermined thickness or a predetermined number of processing cycles have been performed, method 10 moves to post-processing operation 28. If the thickness of the deposited silicon oxide (SiOx) film 108 or the number of processing cycles has not reached a predetermined threshold, method 10 returns to deposition 30 to expose the substrate surface to the first precursor in operation 14 and continues.

[0084] In one or more embodiments, the silicon oxide (SiOx) film 108 formed by method 10 may have any suitable thickness. Those skilled in the art will recognize that the specific thickness of the silicon oxide (SiOx) film 108 may depend on the specific application. In some embodiments, the deposited silicon oxide (SiOx) film 108 has a thickness ranging from 1 Å to 200 Å, including the range from 5 Å to 100 Å and the range from 10 Å to 60 Å.

[0085] In one or more embodiments, the silicon oxide (SiOx) film 108 formed by method 10 resists etching by diluted hydrofluoric acid (DHF). Therefore, in one or more embodiments, the wet etch rate (WER) of the silicon oxide (SiOx) film 108 is low. In some embodiments, the WER in the diluted hydrofluoric acid (DHF) solution is less than 30 Å / min in 100:1 DHF. In other embodiments, the WER of the silicon oxide (SiOx) film 108 after deposition is less than 5 Å / min in 500:1 DHF.

[0086] In one or more embodiments, the silicon oxide (SiOx) film formed according to method 10 has a dielectric constant of less than 4.5, including less than 4 and less than 3.5.

[0087] In one or more embodiments, the silicon oxide (SiOx) film formed by method 10 has a low leakage current, having a leakage current of less than 1 x 10⁻⁶. -6 A / cm 2 At 2 MV / cm. In one or more embodiments, the silicon oxide (SiOx) film has a collapse electric field greater than 6 MV / cm.

[0088] Reference Figure 1 Optional post-processing operation 28 may be, for example, a process to modify film properties (e.g., annealing) or a further film deposition process (e.g., additional ALD or CVD processes) to grow an additional film. In one or more embodiments, optional post-processing operation 28 may be a process to modify the properties of the deposited film. In one or more embodiments, optional post-processing operation 28 includes one or more of hydrogen (H2), methane (CH4), or ammonia (NH3) plasma treatment. The hydrogen (H2), methane (CH4), or ammonia (NH3) plasma may be mixed with one or more inert gases, such as, but not limited to, argon (Ar), helium (He), nitrogen (N2), and neon (Ne). The plasma may be one or more of inductively coupled plasma (ICP), remote plasma source (RPS), microwave, RPS microwave, or capacitively coupled plasma (CCP).

[0089] Reference Figure 1 Method 10 or deposition 30 may be repeated once or multiple times to obtain a film with a desired thickness. In one or more embodiments, deposition 30 is repeated n times, where n is an integer ranging from 1 to 1000, including in the range of 1 to 500, or in the range of 1 to 350, or in the range of 1 to 100, or in the range of 1 to 50, or in the range of 1 to 10.

[0090] According to one or more embodiments, the semiconductor processing chamber in which the method, such as method 10, is performed can be maintained in processing conditions, and the processing conditions can be modified based on a specific application. In a particular embodiment, as those skilled in the art will appreciate, the processing conditions can be modified based on the type of semiconductor element being manufactured (e.g., a logic element or a memory element).

[0091] The semiconductor processing chamber performing, for example, method 10, can be maintained at any suitable temperature. In some embodiments, the semiconductor processing chamber is maintained at a temperature ranging from >200 °C to 600 °C.

[0092] Figure 3 A top-view diagram illustrating an example of a multi-chamber processing system 300 according to an embodiment of the present invention is provided. The processing system 300 generally includes a factory interface 302, load-locking chambers 304, 306, transfer chambers 308, 310 with individual transfer robots 312, 314, holding chambers 316, 318, and processing chambers 320, 322, 324, 326, 328, 330. As detailed herein, wafers in the processing system 300 can be processed in and transferred between various chambers without exposing the wafers to the external environment (e.g., the atmospheric environment that may exist in a semiconductor foundry). For example, wafers can be processed or transferred between various chambers in low-pressure (e.g., less than or equal to about 300 Torr) or vacuum environments without disrupting the low-pressure or vacuum environment between the various processes performed on the wafers in the processing system 300. Therefore, the processing system 300 can provide several integrated solutions for processing wafers.

[0093] exist Figure 3 In the illustrated example, the factory interface 302 includes a docking station 340 and factory interface robots 342 to facilitate wafer transfer. The docking station 340 is configured to receive one or more wafer transfer pods (FOUPs) 344. In some instances, each factory interface robot 342 generally includes blades 348 configured at one end of the individual factory interface robot 342 to transfer wafers from the factory interface 302 to load-locking chambers 304, 306.

[0094] Load-locking chambers 304 and 306 have individual ports 350 and 352 coupled to factory interface 302 and individual ports 354 and 356 coupled to transfer chamber 308. Transfer chamber 308 further has individual ports 358 and 360 coupled to holding chambers 316 and 318 and individual ports 362 and 364 coupled to processing chambers 320 and 322. Similarly, transfer chamber 310 has individual ports 366 and 368 coupled to holding chambers 316 and 318 and individual ports 370, 372, 374, and 376 coupled to processing chambers 324, 326, 328, and 330. Ports 354, 356, 358, 360, 362, 364, 366, 368, 370, 372, 374, and 376 can be, for example, slit valve openings, having slit valves for allowing wafers to pass through via transfer robots 312 and 314, and for providing a seal between individual chambers to prevent gas from passing between them. Generally, any port is open for transferring wafers. Otherwise, the ports are closed.

[0095] Load-locking chambers 304 and 306, transfer chambers 308 and 310, holding chambers 316 and 318, and processing chambers 320, 322, 324, 326, 328, and 330 are fluidly coupled to a gas and pressure control system (not explicitly shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryogenic pumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, a factory interface robot 342 transfers wafers from FOUP 344 through port 350 or 352 to load-locking chambers 304 or 306. The gas and pressure control system then evacuates load-locking chambers 304 or 306. The gas and pressure control system further maintains transfer chambers 308 and 310 and holding chambers 316 and 318 in an internal low-pressure or vacuum environment (which may include an inert gas). Therefore, evacuation of load-locked chambers 304 or 306 facilitates the passage of the wafer between the atmospheric environment of, for example, the fab interface 302 and the low-pressure or vacuum environment of the transfer chamber 308.

[0096] In the emptied load-locked chambers 304 or 306, the transfer robot 312 transfers the wafer from the load-locked chambers 304 or 306 through ports 354 or 356 into the transfer chamber 308. The transfer robot 312 is then able to transfer the wafer through individual ports 362, 364 to any of the processing chambers 320, 322 and / or between the processing chambers 320, 322 for processing, and to transfer the wafer through individual ports 358, 360 to the holding chambers 316, 318 for holding pending further transfer. Similarly, the transfer robot 314 can access wafers in holding chambers 316 or 318 through ports 366 or 368 and can transfer wafers through individual ports 370, 372, 374, 376 to any of the processing chambers 324, 326, 328, 330 and / or transfer wafers between the processing chambers 324, 326, 328, 330 for processing, and transfer wafers through individual ports 366, 368 to holding chambers 316, 318 for holding pending further transfer. The transfer and holding of wafers within the various chambers can be carried out in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0097] Processing chambers 320, 322, 324, 326, 328, and 330 can be any suitable chamber for processing a wafer. In some embodiments, processing chamber 320 can be used for annealing, processing chamber 322 can be used for cleaning, and processing chambers 324, 326, 328, and 330 can be used for epitaxial growth. In some instances, processing chamber 322 can be used for cleaning, processing chamber 320 can be used for etching, and processing chambers 324, 326, 328, and 330 can be used for individual epitaxial growth. Processing chamber 322 can be a pre-cleaning chamber. Processing chamber 320 can be an etching chamber.

[0098] System controller 390 is coupled to processing system 300 for controlling processing system 300 or its components. For example, processing controller 390 can control the operation of processing system 300 by directly controlling chambers 304, 306, 308, 316, 318, 310, 320, 322, 324, 326, 328, and 330 of processing system 300, or by controlling controllers associated with chambers 304, 306, 308, 316, 318, 310, 320, 322, 324, 326, 328, and 330. During operation, system controller 390 can collect data and feedback from individual chambers to coordinate the performance of processing system 300.

[0099] The system controller 390 generally includes a central processing unit (CPU) 392, memory 394, and support circuitry 396. The CPU 392 can be any type of general-purpose processor used in industrial settings. The memory 394, or non-transitory computer-readable medium, can be accessed by the CPU 392 and can be one or more of the following types of memory: random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any form of digital storage, local or remote. The support circuitry 396 is coupled to the CPU 392 and may include cache, clock circuitry, input / output subsystems, power supply, and the like. Various methods disclosed herein can generally be implemented under the control of the CPU 392, by which the CPU 392 executes computer code stored in memory 394 (or in the memory of a specific processing chamber), as, for example, software routines. When the computer code is executed by the CPU 392, the CPU 392 controls the chamber to perform processing according to various methods.

[0100] Other processing systems may have other configurations. For example, more or fewer processing chambers may be coupled to a transport device. In the illustrated example, the transport device includes transport chambers 308, 310 and holding chambers 316, 318. In other examples, more or fewer transport chambers (e.g., one transport chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as transport devices in a processing system.

[0101] The process can be stored as a software routine in the memory of the system controller 390, which, when executed by the processor, causes the processing chamber to perform the process of the present invention. The software routine can also be stored and / or executed by a second processor (not shown), located remotely to the hardware controlled by the processor. Some or all of the methods of the present invention can also be executed in hardware. Thus, the process can be implemented in software and in hardware using a computer system, as, for example, an application-specific integrated circuit or other type of hardware implementation, or a combination of software and hardware. When the software routine is executed by the processor, a general-purpose computer is transformed into a special-purpose computer (controller) that controls the chamber operation, thereby executing the process.

[0102] Embodiments of the present invention relate to non-transitory computer-readable media. In one or more embodiments, the non-transitory computer-readable medium includes instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform operations of any of the methods described herein (e.g., method 10). In one or more embodiments, the controller causes the processing chamber to perform operations of method 10.

[0103] The use of the terms “a” and “an” and “the” and similar indicative terms in the context of describing the materials and methods discussed herein (particularly in the context of the following claims) is intended to constructively cover both the singular and plural, unless otherwise specified herein or clearly contradicted by the context. Numerical ranges mentioned herein are intended only as shorthand for each separate numerical value falling within these ranges individually, and each separate numerical value is incorporated into this specification as if individually mentioned herein, unless otherwise specified herein. All methods described herein may be performed in any suitable order, unless otherwise specified herein or clearly contradicted by the context. The use of any and all example or exemplary language (e.g., “such as”) provided herein is intended only to better illustrate the materials and methods and does not impose any limitations on the scope, unless otherwise stated. No language in this specification should be construed as indicating that any non-declared element is necessary for the implementation of the disclosed materials and methods.

[0104] Throughout this specification, the references to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" indicate that a particular feature, structure, material, or characteristic described with respect to that embodiment is included in at least one embodiment of the invention. Therefore, the use of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" in various places throughout this specification does not necessarily refer to the same embodiment of the invention. Furthermore, in one or more embodiments, a particular feature, structure, material, or characteristic may be combined in any suitable manner.

[0105] While the invention has been described herein with reference to specific embodiments, those skilled in the art will understand that these embodiments are merely illustrative of the principles and applications of the invention. Various modifications and variations of the methods and apparatus of the invention can be made without departing from the spirit and scope of the invention, as will be apparent to those skilled in the art. Therefore, the invention may include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method for depositing a film on a semiconductor device, the method comprising: The semiconductor substrate in the semiconductor processing chamber will be exposed to the first precursor; The semiconductor substrate is exposed to a first purifying gas; Expose the semiconductor substrate to the second precursor; The semiconductor substrate is exposed to a second purification gas; and The semiconductor substrate is exposed to a remote plasma source (RPS) microwave plasma to deposit a conformal silicon oxide (SiOx) film on the surface of the semiconductor substrate.

2. The method of claim 1, wherein the remote plasma source (RPS) microwave plasma contains hydrogen (H2) or hydrogen (H2) mixed with an inert gas.

3. The method of claim 1, wherein the first precursor is a silicon-containing precursor.

4. The method of claim 2, wherein the first precursor comprises disilacyclobutane, trisilacyclohexane, or has the chemical formula R 3 R 2 R 1 -Si-C x H 2x -Si-R 1 R 2 R 3 One or more of the precursors, of which R 1 R 2 R 3 The radical is independently selected from hydrogen (H), dimethylamino, diethylamino, alkyl, alkoxy, vinyl, silane, amine, or halide, and x is an integer in the range of 1 to 10.

5. The method of claim 4, wherein the disilacyclobutane has the general formula (I): Where R 1 R 2 R 3 R 4 R 5 R 6 R 7 and R 8 It is independently selected from hydrogen (H), alkyl, alkoxy, vinyl, silane, amine, dimethylamino, or halide.

6. The method of claim 4, wherein the trisilacyclohexane has the general formula (II): Where R 1 R 2 R 3 R 4 R 5 and R 6 It is independently selected from hydrogen (H), alkyl, alkoxy, vinyl, silane, amine, dimethylamino, or halide.

7. The method of claim 5, wherein the first precursor is selected from the group consisting of bis(tris(dimethylamido)silyl)methane, bis(trichlorosilyl)methane, and 1,1,3,3-tetrakis(dimethylamino)-1,3-disilacyclobutane.

8. The method of claim 1, wherein the second precursor comprises one or more of a carboxylic acid, an alcohol, acetic acid, ethylene glycol, oxygen (O2), ozone (O3), hydrogen peroxide (H2O2), and water (H2O).

9. The method of claim 1, wherein the conformal silicon oxide (SiOx) film has a dielectric constant of less than 4.

5.

10. The method of claim 1, wherein the method is repeated n times, where n is an integer in the range of 1 to 1000.

11. The method of claim 1, wherein the method is performed at a temperature in the range of 200 °C to 550 °C.

12. The method of claim 1, wherein the first purified gas and the second purified gas are independently selected from argon (Ar), helium (He), neon (Ne), and nitrogen (N2).

13. A method of manufacturing a logic or memory element, the method comprising: In a deposition cycle, a substrate comprising at least one feature in a semiconductor processing chamber is exposed to a first precursor, a first purge gas, a second precursor, a second purge gas, and a remote plasma source (RPS) microwave plasma, wherein the at least one feature has a top surface, a sidewall surface, and a bottom surface, the first precursor comprising a silicon-containing precursor, and the second precursor comprising an oxidant, to conformally deposit a silicon oxide (SiOx) film on one or more of the top surface, the sidewall surface, and the bottom surface of the at least one feature.

14. The method of claim 13, wherein the remote plasma source (RPS) microwave plasma comprises hydrogen (H2) or hydrogen (H2) mixed with an inert gas, wherein the inert gas comprises one or more of argon (Ar), helium (He), neon (Ne), and nitrogen (N2).

15. The method of claim 13, wherein the first precursor comprises disilacyclobutane, trisilacyclohexane, or has the chemical formula R 3 R 2 R 1 -Si-C x H 2x -Si-R 1 R 2 R 3 One or more of the precursors, of which R 1 R 2 R 3 The radical is independently selected from hydrogen (H), dimethylamino, diethylamino, alkyl, alkoxy, vinyl, silane, amine, or halide, and x is an integer in the range of 2 to 10.

16. The method of claim 15, wherein the disilacyclobutane has general formula (I) and the trisilacyclohexane has general formula (II): Where R 1 R 2 R 3 R 4 R 5 R 6 R 7 、and R 8 It is independently selected from hydrogen (H), alkyl, alkoxy, vinyl, silane, amine, dimethylamino, or halide.

17. The method of claim 13, wherein the conformal silicon oxide (SiOx) film has a dielectric constant of less than 4.

5.

18. The method of claim 13, wherein the deposition cycle is repeated n times, where n is an integer in the range of 1 to 1000.

19. The method of claim 13, wherein the method is performed at a temperature in the range of 200 °C to 550 °C.

20. The method of claim 13, wherein the first purifying gas and the second purifying gas are independently selected from argon (Ar), helium (He), neon (Ne), and nitrogen (N2).

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