Using a pattern as an alignment mark

Abstract

Embodiments of the present disclosure provide a method including capturing images of features on a die formed on a semiconductor substrate, extracting a pattern from a portion of each captured image, and combining the patterns to form an alignment mark. The images are captured from four corners of the die. The pattern from the portion of each captured image is compared to other patterns on the die to determine uniqueness of the pattern. Embodiments of the present disclosure further provide a method including capturing an image on a semiconductor substrate, extracting a pattern from a previous material layer disposed on the semiconductor substrate from the captured image, and combining the patterns extracted from the previous material layer disposed on the semiconductor substrate to form an alignment mark. The alignment mark facilitates precise alignment of a lithographic printing mask.

Description

Technical Field

[0001] The embodiments described herein generally relate to semiconductor processing. More specifically, the embodiments described herein relate to using patterns on grains formed on a semiconductor substrate (e.g., a wafer), or using patterns from a previous material layer placed on the substrate as alignment marks. Background Technology

[0002] Many steps in semiconductor manufacturing processes require highly precise alignment, such as photolithography, substrate probing and testing, and substrate mounting and dicing. To meet industry demands, semiconductor manufacturers use high-speed automated production systems that require minimal intervention. Poorly performing vision alignment systems will stop more frequently for manual intervention and maintenance, disrupting production processes and increasing support costs. In addition to low production efficiency, poor alignment can also reduce substrate yield and the electrical functionality of die circuitry.

[0003] Therefore, there is a need in the art for improved methods for generating alignment marks. Summary of the Invention

[0004] Embodiments of this disclosure provide a method comprising: capturing feature images of a die formed on a semiconductor substrate; extracting a pattern from a portion of each captured image; and combining the patterns to form alignment marks. In one example, the images are captured from the four corners of the die. In another example, images are captured from side regions of the die. In yet another example, images are captured from multiple different central and non-central regions of the die. In one example, the patterns are combined in a tiled block format. In another example, the patterns are combined in a cross geometry. The pattern from that portion of each captured image is compared with other patterns on the die to determine the uniqueness of the pattern. The pattern is a circuit design. Alignment marks facilitate precise alignment of a lithographic mask. The alignment marks are stored in memory elements and are retrieved during lithographic mask alignment and positioning.

[0005] Embodiments of this disclosure provide a method comprising: capturing an image on a semiconductor substrate, extracting a pattern of a prior material layer disposed on the semiconductor substrate from the captured image, and combining the pattern extracted from the prior material layer disposed on the semiconductor substrate to form an alignment mark.

[0006] This disclosure provides an alignment mark generator, comprising: a camera for capturing a feature image on one of a plurality of dies formed on a semiconductor substrate or capturing an image directly from the semiconductor substrate; a pattern extractor for extracting a pattern from a portion of each captured image; and a pattern combiner for combining the extracted patterns to form alignment marks. In one example, the image is captured from the four corners of the die. In another example, the image is captured from a side region of the die. In yet another example, the image is captured from multiple different central and non-central regions of the die. In one example, the pattern is combined in a tiled block format. In another example, the pattern is combined in a cross geometry. The pattern from that portion of each captured image is compared with other patterns on the die to determine the uniqueness of the pattern. Alignment marks facilitate precise alignment of lithographic masks. Alignment marks are stored in memory elements and are retrieved during lithographic mask alignment and positioning. In another example embodiment, the pattern is extracted from the substrate itself, rather than from a die placed on the substrate. In other words, the pattern can be extracted from a previous material layer placed on the substrate before the die is placed. Attached Figure Description

[0007] To gain a more detailed understanding of the features described above, the present disclosure, which has been briefly outlined above, can be described in more detail with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only exemplary embodiments and should not be construed as limiting their scope, and other equivalent embodiments are permissible.

[0008] Figure 1A A snapshot of a portion of a die is shown to extract a pattern according to one or more embodiments described herein.

[0009] Figure 1B Alignment marks are formed by combining portions of a pattern of snapshots of such portions from a die, according to one or more embodiments described herein.

[0010] Figures 1C to 1E Alignment marks of different shapes and sizes are shown.

[0011] Figure 2 A circular semiconductor substrate according to one or more embodiments described herein is shown, wherein a plurality of grains are formed on the substrate, wherein a pattern from at least one grain is used to form alignment marks.

[0012] Figure 3 A rectangular panel according to one or more embodiments described herein is shown, wherein a plurality of grains are formed on the rectangular panel, wherein a pattern from at least one grain is used to form alignment marks.

[0013] Figure 4This is a flowchart of a method for implementing one or more embodiments described herein, which generates alignment marks from portions of a pattern extracted from one or more grains.

[0014] Figure 5 This is a flowchart of a method for implementing one or more embodiments described herein, which generates alignment marks from an extracted pattern.

[0015] Figure 6 An alignment mark generator according to one or more embodiments described herein is used to generate a single alignment mark from multiple patterns of a die formed on a semiconductor substrate.

[0016] Figure 7A A substrate according to one or more embodiments described herein is shown, the substrate including multiple patterns from a prior material layer, and a snapshot of a portion of the patterns on the substrate.

[0017] Figure 7B The illustration shows an alignment mark formed by combining portions of a pattern from a snapshot of a portion of a photographic substrate, according to one or more embodiments described herein.

[0018] Figure 7C The alignment mark shape following a pattern from a substrate is shown in combination of one or more embodiments described herein.

[0019] Figure 8 An alignment mark generator according to one or more embodiments described herein is shown, which is used to generate a single alignment mark from a plurality of patterns on a semiconductor substrate.

[0020] Figure 9 A flowchart is shown for implementing a method according to one or more embodiments described herein, which generates alignment marks from portions of a pattern extracted from a semiconductor substrate.

[0021] For ease of understanding, the same reference numerals are used as much as possible to identify the same elements in the figures. It is contemplated that elements and features of one embodiment may be advantageously incorporated into other embodiments without further description. Detailed Implementation

[0022] Embodiments of this disclosure generally relate to improving semiconductor manufacturing by implementing novel methods for aligning different layers, materials, or structures during the manufacturing process. The novel method involves implementing a novel approach to generating alignment marks. In typical systems, alignment marks are placed on scribe lines between dies on a semiconductor substrate. A common geometry for alignment marks is a cross shape. However, such scribe-lined alignment marks occupy too much space on the semiconductor substrate. Instead, exemplary embodiments use portions or subsets of patterns on one or more dies as alignment marks. In another exemplary embodiment, the pattern is extracted from the substrate itself, rather than from dies placed on the substrate. In other words, the pattern can be extracted from a previous material layer placed on the substrate before the dies are placed.

[0023] The fabrication of microelectronic components typically involves a complex sequence of processes, requiring hundreds of individual steps to be performed on semiconductors, dielectrics, and conductive substrates. Examples of these processes include oxidation, diffusion, ion implantation, thin film deposition, cleaning, etching, lithography, and other operations. Each operation is time-consuming and expensive.

[0024] As the critical dimensions of microelectronic components continue to shrink, the design and fabrication of these components on substrates have become, or have become, increasingly complex. Controlling critical dimensions and process uniformity has become increasingly important. The complex multilayer stacks used to fabricate microelectronic components involve precise process monitoring of critical dimensions related to thickness, roughness, stress, density, and potential defects. Process formulations for forming components often employ multiple incremental processes to ensure critical dimensions are maintained. Typically, each incremental process utilizes one or more processing chambers, which increases the additional time required to form the component and also increases the chance of forming defects. As the critical dimensions of these components shrink, past manufacturing techniques have encountered new obstacles. One manufacturing technique involves the use of alignment marks.

[0025] In semiconductor manufacturing, alignment marks are features used to precisely align different material layers or structures during the manufacturing process. These marks serve as reference points for aligning photolithography masks, which are used to pattern semiconductor substrates. Alignment marks are specially designed gratings that are generated on the semiconductor substrate along the pattern of each layer. Alignment marks consist of lines whose vertical sides are perpendicular to the substrate surface.

[0026] Alignment marks are typically small patterns or structures designed to be easily identifiable under a microscope or by an automated alignment system. Common types of alignment marks include crosses, squares, or other geometric shapes.

[0027] During semiconductor manufacturing, multiple layers of material are deposited or patterned on a silicon substrate to form an integrated circuit (IC). Each layer must be precisely aligned with the previously patterned layers to ensure the proper functionality of the final device. Alignment marks play a crucial role in achieving this alignment by providing reference points for aligning the photolithographic mask used when patterning each layer.

[0028] Advanced semiconductor manufacturing processes utilize various techniques to improve alignment accuracy, such as overlapping metrology systems that precisely measure multi-layer alignments based on alignment mark positions. Overall, alignment marks are crucial for achieving the high precision required in semiconductor manufacturing to ensure the reliability and performance of ICs.

[0029] Alignment marks in semiconductor manufacturing play a crucial role in ensuring precise alignment of different layers during the manufacturing process. However, several problems can arise with alignment marks, affecting the quality and yield of semiconductor devices. Some of these problems include:

[0030] Variations in the feature size and density of alignment marks. Alignment marks are typically manufactured using techniques similar to the lithography techniques used to pattern the semiconductor elements themselves. Variations in the feature size and density across the substrate can affect alignment accuracy, leading to misalignment problems.

[0031] Overlap error associated with alignment marks. Overlap error refers to the difference between the intended alignment of different layers and the actual alignment achieved during manufacturing. Various factors, such as equipment defects, thermal expansion, and mechanical stress, can cause overlap error, resulting in poor interlayer alignment.

[0032] Pattern recognition and detection errors associated with alignment marks. Automated alignment systems rely on pattern recognition algorithms to accurately detect alignment marks. However, problems such as pattern distortion, contamination, or low contrast can hinder the detection process, leading to alignment errors.

[0033] Process-induced distortion issues arise from the use of alignment marks. Semiconductor manufacturing processes such as deposition, etching, and annealing induce stress and deformation in the substrate. This can lead to misalignment of alignment marks between different layers, thereby affecting device performance and yield.

[0034] Mask alignment accuracy issues can also arise. Alignment marks on the photolithographic printing mask must be precisely positioned to ensure correct alignment during the patterning process. Any inaccuracies in mask alignment will propagate as alignment problems in the manufactured components.

[0035] Alignment across large areas is also challenging. In advanced semiconductor processes that simultaneously fabricate larger substrates or multiple dies, achieving consistent alignment across large areas can be challenging. Variations in the position of alignment marks across substrates or dies can lead to yield loss and degraded device performance.

[0036] Using alignment markers also presents process integration challenges. Semiconductor manufacturing involves multiple process steps, each of which affects alignment accuracy. Coordinating these processes to ensure consistent alignment throughout manufacturing presents integration challenges that impact overall yield and device performance.

[0037] Therefore, alignment marks are typically designed with strict shape and size definitions. Alignment marks can also occupy significant space on the substrate. Furthermore, alignment marks from different companies or customers are often incompatible.

[0038] Solving these alignment problems requires continuous improvement in manufacturing processes, equipment precision, and alignment techniques. Advanced metrology tools, process optimization strategies, and stricter control over manufacturing parameters are crucial for mitigating alignment-related issues and improving semiconductor manufacturing yields and device performance.

[0039] In exemplary embodiments, alignment marks do not need to be placed or etched onto scribe lines on the semiconductor substrate. Instead, in one example, the alignment marks are derived from a pattern formed on a die on the semiconductor substrate. A snapshot of the pattern is taken from the die on the substrate. The pattern is extracted from the snapshot and combined to form a single alignment mark. The snapshot may be taken from the four corners of the die. In other examples, the snapshot may be taken from other areas of the die. The combination of the extracted patterns forms a reference alignment mark, which can be compared with other patterns in various alignment processes. In another example, the alignment marks are derived from a pattern on the substrate itself. Specifically, the pattern is extracted from a previous material layer placed on the substrate. A snapshot is taken from the substrate. The pattern is extracted from a previous material layer placed on the substrate. These patterns are combined to form a single alignment mark. The snapshot may be taken from any part of the substrate.

[0040] This alignment mark generation strategy allows manufacturers to package more dies on a single substrate. Packing more dies on a substrate improves manufacturing efficiency and reduces the production cost per chip. Therefore, higher die density can be achieved on the substrate, and scribe line width can be significantly reduced. Optimizing scribe line width allows for closer die placement, thus increasing the number of dies that can be placed on a single semiconductor substrate.

[0041] Figure 1A A snapshot of a portion of a die is shown to extract a pattern according to one or more embodiments described herein.

[0042] In schematic diagram 100, die 110 among multiple dies includes multiple patterns. The patterns on die 110 of the substrate include transistor structures such as gates, sources, drains, and channels, which form the basic components of metal-oxide-semiconductor field-effect transistors (MOSFETs) or other types of transistors. Other patterns include interconnects, which are metal lines or wires used to connect various components within an integrated circuit (IC). These patterns include metal layers deposited on the substrate surface, with vias used to connect different layers. The patterns on the substrate may also include structures for creating capacitors and resistors. The patterns on the substrate may include PN junctions, which form the substrate for diodes and other semiconductor devices. The patterns on the substrate may also represent individual memory cells that store data as charge. Furthermore, logic gates and circuits can be formed by arranging transistors and interconnects on the substrate according to a specific design layout. Patterns can be produced using photolithography, etching, deposition, and other semiconductor manufacturing processes. The design and arrangement of these patterns are critical to the function, performance, and reliability of the semiconductor devices.

[0043] In conventional systems, alignment marks are used to ensure accurate alignment of different layers during the manufacturing process. These alignment marks are formed directly on a substrate comprising multiple grains. The alignment marks are placed on scribe lines formed between the grains of the substrate.

[0044] In contrast, the exemplary embodiment does not generate alignment marks on the scribing lines of the semiconductor substrate. Instead, the alignment marks are generated from existing patterns formed on the die of the semiconductor substrate. These patterns are generated by the customer.

[0045] Camera 160 can capture snapshots of portions of die 110. Die 110 can be any random die visible on the semiconductor substrate. Camera 160 can capture snapshots or images from the four corners of die 110. For example, a first image 120 is captured from the upper left corner, a second image 130 from the upper right corner, a third image 140 from the lower left corner, and a fourth image 150 from the lower right corner. Thus, in one case, images from the four corners of a die on the semiconductor substrate are selected to form alignment marks.

[0046] The first image 120 is magnified to show the pattern 122 formed on the first image. The user can select a portion 124 of the first image 120 as an alignment mark segment 125. The second image 130 is magnified to show the pattern 132 formed on the second image. The user can select a portion 134 of the second image 130 as an alignment mark segment 135. The third image 140 is magnified to show the pattern 142 formed on the third image. The user can select a portion 144 of the third image 140 as an alignment mark segment 145. Similarly, an alignment mark segment (not shown) can also be selected from the fourth image 150.

[0047] Part 124 includes unique or distinct segments, sections, or fragments of pattern 122 formed on die 110. Part 124 is a subset of the entire pattern 122. Pattern 122 is a portion of a customer-designed feature. Pattern 122 is unique to the customer. Features present on part 124 differ from other features in other areas of die 110. Thus, part 124 can be used as an alignment mark segment 125 because it is unique compared to other patterns visible on die 110.

[0048] Similarly, portion 134 includes unique or distinct segments, sections, or fragments of pattern 132 formed on die 110. Portion 134 is a subset of the entire pattern 132. Pattern 132 is a portion of a customer-designed feature. Pattern 132 is unique to the customer. Features present on portion 134 differ from other features in other areas of die 110. Thus, portion 134 can be used as an alignment mark segment 135 because it is unique compared to other patterns visible on die 110.

[0049] Similarly, portion 144 includes unique or distinct segments, sections, or fragments of pattern 142 formed on die 110. Portion 144 is a subset of the entire pattern 142. Pattern 142 is a portion of a customer-designed feature. Pattern 142 is unique to the customer. Features present on portion 144 differ from other features in other areas of die 110. Thus, portion 144 can be used as an alignment mark segment 145 because it is unique compared to other patterns visible on die 110.

[0050] Similarly, unique alignment mark segments can also be obtained from the fourth image 150 (in Figure 1C (As specified in the text, 155).

[0051] Alignment mark segments can be selectively obtained from the corresponding images captured by camera 160. For example, the user can select the leftmost region of the first image 120 to represent an alignment mark segment, and the user can select the rightmost region of the second image 130 to represent an alignment mark segment. Thus, the user can select a portion of the pattern within each captured image to represent an alignment mark segment. Once the alignment mark segments are selected, these segments are combined to form a single alignment mark, as described below. Figure 1B The discussion.

[0052] Figure 1B Alignment marks are formed by combining portions of a pattern of snapshots of such portions from a die, according to one or more embodiments described herein.

[0053] By combining alignment mark segment 125 in the first image 120, alignment mark segment 135 in the second image 130, alignment mark segment 145 in the third image 140, and another alignment mark segment 155 in the fourth image 150 ( Figure 1C Alignment marks 170 are formed. Therefore, four alignment mark segments from the four corners of the grain 110 are used to form alignment marks 170. Alignment marks 170 may be referred to as template marks or reference alignment marks.

[0054] In other example implementations, images can be captured from the side regions of the die 110. In other words, it is not necessary to capture images only from the four corners of the die 110, but rather any side region of the die 110 can be selected.

[0055] In other example implementations, images can be captured from the corners and side regions of the die 110. Alignment marks 170 can be formed from more than four images. Alignment marks 170 can be formed from five, seven, ten, twenty, or more images. The user can select any number of images from the die 110 to form alignment marks 170.

[0056] In other example implementations, images can be captured from multiple different central and non-central regions of the die 110. For example, images can be captured from two corners of the die 110 and several central regions of the die 110 to form alignment marks 170. The user may be able to select any number of images from the die 110 to form alignment marks 170.

[0057] In some embodiments, camera 160 may scan die 110 to detect a unique pattern suitable for forming alignment marks 170. Camera 160 may store the unique pattern in a storage device, such as a memory element. Figure 6 The storage device can be local to the camera 160 or associated with an external computing device.

[0058] Therefore, even if the alignment mark 170 is composed of a pattern derived or extracted from images of the four corners of the die 110, it is conceivable that the alignment mark 170 can be constructed from any number of images captured from any region or area of ​​the die 110.

[0059] Figures 1C to 1E Alignment marks of different shapes and sizes are shown.

[0060] Once alignment mark segments are selected, these segments are combined in a variety of different ways to construct alignment mark 170.

[0061] In one instance, in Figure 1C In this configuration, alignment mark segments 125, 135, 145, and 155 are combined in a tiled block format, such as a 2×2 tiled block, to form a single alignment mark.

[0062] In another instance, in Figure 1D If more than four alignment mark segments are selected, a larger tile configuration can be constructed. For example, 12 patterns can be selected from 12 images captured by camera 160. These 12 patterns can be combined into a 4×3 tile, which is designated as alignment mark 180A. Alignment mark 180A may include multiple tile blocks 182, each of which includes a different or unique pattern. Thus, 12 different patterns extracted from die 110 form alignment mark 180A and are assembled into a rectangle.

[0063] In another instance, in Figure 1E If more than four alignment mark segments are selected, a larger tile configuration can be constructed. For example, nine patterns can be selected from nine images captured by camera 160. These nine patterns can be combined into a cross shape, which is designated as alignment mark 180B. Alignment mark 180B may include multiple tiles 184, each of which includes a different or unique pattern. Thus, nine different patterns extracted from die 110 form alignment mark 180B and are assembled into a cross shape.

[0064] Therefore, alignment marks can be constructed in any shape or size. The shape or size can be selected by the customer. In other implementations, the shape or size can be selected by the user to meet certain customer design requirements. The shape or size can also be selected using machine learning techniques.

[0065] Figure 2 A circular substrate according to one or more embodiments described herein is shown, wherein a plurality of grains are formed on the substrate, wherein a pattern from at least one grain is used to form alignment marks.

[0066] The substrate 200 includes a plurality of dies 210. Alignment marks can be extracted from one die 210. In one example, a camera takes snapshots of the four corners of a die 210. A first image 212 is taken at the first corner of the die 210, a second image 214 is taken at the second corner of the die 210, a third image 216 is taken at the third corner of the die 210, and a fourth image 218 is taken at the fourth corner of the die 210. A first pattern is extracted from the first image 212, a second pattern is extracted from the second image 214, a third pattern is extracted from the third image 216, and a fourth pattern is extracted from the fourth image 218. The first pattern is a part or subset of the entire pattern captured in the first image 212. The second pattern is a part or subset of the entire pattern captured in the second image 214. The third pattern is a part or subset of the entire pattern captured in the third image 216. The fourth pattern is a part or subset of the entire pattern captured in the fourth image 218.

[0067] The first, second, and third patterns combine to form a single alignment mark or reference mark. The pattern from this portion of each captured image is compared to other patterns on die 210 to determine the uniqueness of the pattern. These patterns constitute a circuit design. A single alignment mark facilitates precise alignment of the lithographic printing mask.

[0068] Figure 3 A rectangular panel according to one or more embodiments described herein is shown, wherein a plurality of grains are formed on the rectangular panel, wherein a pattern from at least one grain is used to form alignment marks.

[0069] The rectangular panel 300 includes a plurality of dies 310. Alignment marks can be extracted from one die 310. In one example, a camera takes snapshots of the four corners of a die 310. A first image 312 is taken at the first corner of the die 310, a second image 314 is taken at the second corner of the die 310, a third image 316 is taken at the third corner of the die 310, and a fourth image 318 is taken at the fourth corner of the die 310. A first pattern is extracted from the first image 312, a second pattern is extracted from the second image 314, a third pattern is extracted from the third image 316, and a fourth pattern is extracted from the fourth image 318. The first pattern is a part or subset of the entire pattern captured in the first image 312. The second pattern is a part or subset of the entire pattern captured in the second image 314. The third pattern is a part or subset of the entire pattern captured in the third image 316. The fourth pattern is a part or subset of the entire pattern captured in the fourth image 318.

[0070] The first, second, and third patterns combine to form a single alignment mark or reference mark. The pattern from this portion of each captured image is compared to other patterns on die 310 to determine the uniqueness of the pattern. These patterns constitute a circuit design. A single alignment mark facilitates precise alignment of the lithographic printing mask.

[0071] The rectangular panel 300 illustrates scribe lines 320 separating the dies 310. In a conventional configuration, alignment marks are placed on the scribe lines 320. The scribe lines 320 extend horizontally and vertically along the surface of the semiconductor substrate. The width of the scribe lines 320 can vary depending on the specific manufacturing process and the requirements of the semiconductor manufacturer. However, the width of the scribe lines 320 is typically in the range of tens to hundreds of micrometers (µm). The width of the scribe lines is carefully controlled to accommodate conventional alignment marks.

[0072] However, according to the example implementation, the width of the scribe line can be significantly reduced because such scribe lines do not need to adapt to conventional alignment marks. Instead, alignment marks can be generated from a portion or subset of a pattern formed on the die. Alignment marks generated from a portion or subset of a pattern on the die do not need to be placed or etched on the scribe line. Instead, alignment marks generated from a pattern on the die can be stored in a memory element and retrieved when performing lithographic mask alignment.

[0073] Therefore, process complexity can be reduced by not directly providing alignment marks on the scribing lines of the semiconductor substrate. Developing and implementing scribing patterns for each customer requires careful consideration of the manufacturing process. The complexity of scribing design and execution increases manufacturing costs and cycle time. According to an example implementation, by removing alignment marks from the scribing lines of the semiconductor substrate, manufacturing costs and cycle time can be significantly reduced. Furthermore, scribing can weaken the structural integrity of the semiconductor substrate, making it more susceptible to breakage during transport or handling. According to an example implementation, by removing alignment marks from the scribing lines of the semiconductor substrate, the scribing lines can be finer, thus strengthening the structural integrity of the substrate itself.

[0074] Therefore, the width of the scribing can be significantly reduced, and the scribing width can be designed only for substrate cutting and chip separation purposes, thereby minimizing any negative impact of such scribing on semiconductor manufacturing processes and device performance.

[0075] Figure 4 This is a flowchart of a method for implementing one or more embodiments described herein, which generates alignment marks from portions of a pattern extracted from one or more grains.

[0076] In frame 410, snapshots or images are taken of the four corners of a die formed on a semiconductor substrate. These snapshots are taken using a camera. The snapshots are then provided to the user. The snapshots or images can be stored in a memory element ( Figure 6 ).

[0077] In box 420, a pattern is extracted from each of the four snapshots. Thus, a first pattern is extracted from the first snapshot of the first corner, a second pattern is extracted from the second snapshot of the second corner, a third pattern is extracted from the third snapshot of the third corner, and a fourth pattern is extracted from the fourth snapshot of the fourth corner.

[0078] In box 430, determine whether the four extracted patterns are unique.

[0079] If not, the process proceeds to frame 432.

[0080] In box 432, other patterns including unique features are extracted from the snapshot.

[0081] If so, the process proceeds to frame 440.

[0082] In box 440, four patterns are combined to form a single alignment mark. These four patterns can be combined in a tile format to form a 2×2 tile. The first, second, third, and fourth patterns are different from each other. Each of the first, second, third, and fourth patterns includes different or unique features or circuit designs.

[0083] In frame 450, a single alignment mark serves as a reference alignment mark for comparison with other patterns during alignment steps, such as in lithography processes.

[0084] Figure 5 This is a flowchart of a method for implementing one or more embodiments described herein, which generates alignment marks from an extracted pattern.

[0085] In frame 510, a feature image of a die formed on a semiconductor substrate is captured.

[0086] In box 520, a subset of patterns is extracted from a portion of each captured image.

[0087] In frame 530, patterns are combined to form alignment marks. These patterns can be combined into several different configurations.

[0088] Figure 6 An alignment mark generator according to one or more embodiments described herein is used to generate a single alignment mark from multiple patterns of a die formed on a semiconductor substrate.

[0089] Alignment mark generator 600 includes: a camera 610 for capturing feature images of die 612 among a plurality of dies formed on a semiconductor substrate 614; a pattern extractor 620 for extracting a pattern 622 from a portion of each captured image; and a pattern combiner 630 for combining the extracted patterns to form an alignment mark 640. The alignment mark 640 may be stored in a storage device, such as a memory element 650. The alignment mark 640 may be retrieved from the memory element 650. The memory element 650 may store the final alignment mark for each customer. The memory element 650 may also store patterns extracted from each customer's die. For example, customer A may have 100 extracted patterns, customer B may have 500 extracted patterns, and customer C may have 1000 extracted patterns. A mechanism may also be provided to determine whether any newly extracted pattern is substantially similar to a previously requested and stored pattern associated with the customer.

[0090] Figure 7A A substrate according to one or more embodiments described herein is shown, the substrate including multiple patterns from a prior material layer, and a snapshot of a portion of the patterns on the substrate.

[0091] In another embodiment, alignment marks can be generated from a pattern of a previous layer on the substrate of a semiconductor substrate. For example, the semiconductor substrate or substrate 705 includes a plurality of patterns 710. The plurality of patterns 710 are not formed on any die. Instead, the plurality of patterns 710 are formed on the substrate 705 using previous layers before any die is placed on the substrate 705. In one example, camera 160 (FIG. 1) can take a snapshot of a portion of the plurality of patterns 710. The user can select, for example, a first pattern portion 715 and a second pattern portion 717. The first pattern portion 715 and the second pattern portion 717 each include a unique design.

[0092] In one embodiment, a pattern extracted from a semiconductor substrate or substrate 705 is compared with other patterns on the semiconductor substrate or substrate 705 to determine the uniqueness of the pattern.

[0093] Figure 7B The illustration shows an alignment mark formed by combining portions of a pattern from a snapshot of a portion of a photographic substrate, according to one or more embodiments described herein.

[0094] The first pattern portion 715 and the second pattern portion 717 are combined to form the alignment mark 720. The first pattern portion 715 and the second pattern portion 717 can be selected from any part or segment of the substrate 705. Selecting two pattern portions is only one example. The user can select any number of pattern portions from the substrate 705 to form the alignment mark 720. In one example, 5, 7, 10, 12 or more pattern portions can be selected from the substrate 705 to form the alignment mark 720. The pattern portions can be combined into any number of configurations to form the alignment mark 720.

[0095] Figure 7C The alignment mark shape following a pattern from a substrate is shown in combination of one or more embodiments described herein.

[0096] In one example, the alignment mark 720 can form a rectangular shape 722. Therefore, the first pattern portion 715 and the second pattern portion 717 can be combined to form the rectangular shape 722. In other example embodiments that select more than two pattern portions, the final shape of the alignment mark 720 can be a square or a cross, or any other shape that can be conceived by those skilled in the art.

[0097] Therefore, alignment marks can be constructed in any shape or size. The shape or size can be selected by the customer. In other implementations, the shape or size can be selected by the user to meet certain customer design requirements. The shape or size can also be selected using machine learning techniques.

[0098] Figure 8 An alignment mark generator according to one or more embodiments described herein is shown, which is used to generate a single alignment mark from a plurality of patterns on a semiconductor substrate.

[0099] Alignment mark generator 800 includes: a camera 610 for capturing patterns formed on a semiconductor substrate or substrate 705; a pattern extractor 620 for extracting a first pattern portion 715 and a second pattern portion 717 from a portion of each captured image; and a pattern combiner 630 for combining the extracted patterns to form alignment marks 720. Alignment marks 720 may be stored in a storage device, such as a memory element 650. Alignment marks 720 may be retrieved from the memory element 650. The memory element 650 may store the final alignment marks for each customer. The memory element 650 may also store patterns extracted from the substrate 705.

[0100] Figure 9 A flowchart is shown for implementing a method according to one or more embodiments described herein, which generates alignment marks from portions of a pattern extracted from a semiconductor substrate.

[0101] In frame 910, a camera captures an image of a pattern on the semiconductor substrate of the substrate.

[0102] In frame 920, the target pattern is extracted from a semiconductor substrate or multiple portions of the substrate.

[0103] In frame 930, target patterns are combined to form alignment marks directly from patterns extracted from previous layers positioned on a semiconductor substrate or substrate.

[0104] In an alternative implementation, annotated data can be used to train a machine learning model to extract patterns from the die of a substrate or directly from the substrate. The machine learning model can be constructed using data collection, data annotation, data preprocessing, feature extraction, model selection, and model training. The data collection step may include collecting a dataset of video or imagery of previous patterns used by the customer or visible on the substrate. Thus, the machine learning model can be trained to extract specific, unique patterns from the die on the substrate or directly from the substrate. The machine learning model can use patterns previously extracted from the same customer to determine unique patterns for subsequent applications by the same customer. Thus, the machine learning model can, for example, learn to discard any patterns on the die or on the substrate that may have been previously used to build alignment marks for this customer.

[0105] In summary, a lithographic printing system prints patterns onto a substrate. Manufacturing a microchip requires up to 100 such patterns, all of which must be precisely aligned with each other for the chip to function. The ability of a lithographic printing system to align one pattern with a previous pattern is measured by the system's coverage performance. To achieve this coverage, the lithographic printing system needs to know the substrate's position before exposing it, with accuracy down to the decimal part of the nanometer. Alignment masks are used for system calibration and to align the pattern with previously fabricated layers. According to an example implementation, alignment marks do not need to be etched onto scribe lines on the substrate. Instead, in one instance, the alignment marks are derived from a pattern formed on a die on the substrate. A pattern snapshot is taken from the die on the substrate. The pattern is extracted from the snapshot and combined to form a single alignment mark. The snapshot may be taken from the four corners of the die. In other instances, the snapshot may be taken from other areas of the die. The combination of extracted patterns forms a reference alignment mark, which can be compared with other patterns in various alignment steps. In another instance, the alignment mark is derived from a pattern on the substrate itself. Specifically, the pattern is extracted from a previous material layer placed on the substrate. A snapshot is taken from a substrate. A pattern is extracted from a previous layer of material placed on the substrate. These patterns are combined to form a single alignment mark. The snapshot can be taken from any part of the substrate.

[0106] This alignment mark generation strategy allows manufacturers to package more dies on a single substrate. Packing more dies on a substrate is a key strategy for improving manufacturing efficiency and reducing the production cost per chip. Therefore, higher die density can be achieved on the substrate, and scribe line width can be significantly reduced. Optimizing scribe line width allows for closer die placement, thus increasing the number of dies that can be placed on a single semiconductor substrate.

[0107] Although this specification contains numerous specific implementation details, such details should not be considered as limiting the scope of the claims, but rather as descriptions of specific features of particular embodiments. Certain features described in the context of standalone embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although previously described features may be described as functioning in certain combinations, and even initially so requested, in some cases one or more features from the requested combination may be removed from that combination, and the requested combination may be for a sub-combination or a variation thereof.

[0108] Specific embodiments of the objective have been described. It will be apparent to those skilled in the art that other embodiments, modifications, and substitutions of the described embodiments are within the scope of the following claims. Although operations are illustrated in a specific order in the drawings or claims, this should not be construed as requiring the operations to be performed in the specific order or sequence shown, or requiring the performance of all illustrated operations (some operations may be considered optional) to obtain the desired result. In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous, and its implementation is considered appropriate. Although the individual steps in the embodiments of the method or process are presented and described sequentially, those skilled in the art will understand that some or all steps may be performed in a different order, may be combined or omitted, and some or all steps may be performed in parallel. These steps may be performed actively or passively. The method or process may be repeated or extended to support multiple components or multiple users in a field environment. Therefore, this scope should not be considered limited to the specific arrangement of the steps shown in the flowcharts or diagrams.

[0109] Furthermore, any requested implementation is considered to be at least applicable to computer-implemented methods; non-transitory computer-readable media storing computer-readable instructions to perform computer-implemented methods; and computer systems including computer memory interoperability coupled to a hardware processor configured to perform computer-implemented methods or instructions stored on non-transitory computer-readable media.

[0110] As used herein, “CPU,” “controller,” “processor,” “at least one processor,” or “one or more processors” generally refers to a single processor configured to perform one or more operations, or multiple processors configured to collectively perform one or more operations. In the case of a multiprocessor system, the performance of one or more operations may be partitioned among different processors, although one processor may perform multiple operations and multiple processors may collectively perform a single operation. Similarly, “a memory,” “at least one memory,” or “one or more memory” generally refers to a single memory configured to store data and / or instructions, or multiple memories configured to collectively store data and / or instructions.

[0111] As used herein, “gas” and “fluid” are used interchangeably, and either term generally refers to an element, compound, material, etc., that has the properties of a gas, a fluid, or both.

[0112] Unless otherwise defined, all technical and scientific terms used shall have the same meaning as commonly understood by one of ordinary skill in the art to which such systems, devices, methods, processes and compositions pertain.

[0113] In this disclosure, the terms "top," "bottom," "side," "above," "below," "up," "down," "upward," "downward," "horizontal," "vertical," etc., do not indicate absolute direction. Rather, these terms indicate direction relative to a non-specific reference plane. This non-specific reference plane may be vertical, horizontal, or other angular directions.

[0114] The singular forms “a,” “an,” and “the” include multiple indicators unless the context clearly specifies otherwise. In the claims, unless specifically stated otherwise, an element referred to in the singular form does not mean “one and only one,” but rather “one or more.” Unless specifically stated otherwise, the term “some” indicates one or more.

[0115] Embodiments of this disclosure may suitably "include the disclosed limiting features," "consist of the disclosed limiting features," or "consist substantially of the disclosed limiting features," and may be implemented without any undisclosed limiting features. As used herein and in the appended claims, the words "comprising," "having," and "including," and all their grammatical variations, are intended to have an open, non-limiting meaning that does not exclude additional elements or steps.

[0116] "Optional" and "depending on the circumstances" mean that the material, event, or situation described below may or may not exist or occur. The description includes both the possibility that the material, event, or situation has occurred and the possibility that it has not occurred.

[0117] "Coupled" and "coupling" indicate that the material described below is connected to the material described above. The connection may be direct or indirect and may or may not include intermediate components such as piping, wiring, fasteners, mechanical power transmission, electrical communication, wired and / or wireless transmission, which may be suitable for the operation of the components.

[0118] As used herein, the term "determine" encompasses a variety of actions. For example, "determine" can include calculation, operation, processing, deduction, investigation, searching (e.g., searching in a table, database, or other data structure), and confirming. Furthermore, "determine" can include receiving (e.g., receiving information) and accessing (e.g., accessing data in memory). Additionally, "determine" can include parsing, selecting, picking, and building.

[0119] When the terms “approximately” or “about” are used, the term can indicate a value variation of up to ±10%, up to 5%, up to 2%, up to 1%, up to 0.5%, up to 0.1%, or up to 0.01%.

[0120] A range can be expressed as from about one specific value to about another specific value, including such specific values. When expressing such a range, it should be understood that another implementation is from one specific value to another specific value, and all specific values ​​within that range and combinations thereof.

[0121] As used herein, terms such as “first” and “second” are arbitrarily designated and are used only to distinguish two or more components of a system, device, or combination. It should be understood that the terms “first” and “second” serve no other purpose and are not part of the component names or descriptions, nor do they necessarily define the relative positions or locations of the components. Furthermore, it should be understood that the mere use of the terms “first” and “second” does not require the existence of any “third” component, although such a possibility is anticipated within the scope of the various embodiments described.

[0122] Although only a few exemplary embodiments have been described in detail, those skilled in the art will readily understand that various modifications can be made to the exemplary embodiments without substantially departing from the scope of the disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the foregoing claims. In the claims, the term "means plus function" is intended to cover structures described as performing the enumerated functions, including not only structural equivalents but also equivalent structures. With respect to any limitation in any claim, the applicant expressly intends not to invoke patent law, except where the claims expressly use the term "means" and the related function.

[0123] Although the foregoing describes an implementation of this disclosure, other implementations of this disclosure may be designed without departing from the basic scope of this disclosure, the scope of which is defined by the appended claims.

Claims

1. A method, the method comprising: Capture images of features on a die formed on a semiconductor substrate; Extract patterns from each captured image portion; and The patterns are combined to form alignment marks.

2. The method of claim 1, wherein the image is captured from the four corners of the grain.

3. The method of claim 1, wherein the image is captured from a side region of the grain.

4. The method of claim 1, wherein the image is captured from a plurality of different central and non-central regions of the grain.

5. The method of claim 1, wherein the patterns are combined in a tiled block format.

6. The method of claim 1, wherein the patterns are combined into a cross geometry.

7. The method of claim 1, wherein the pattern from the portion of each captured image is compared with other patterns on the grain to determine the uniqueness of the pattern.

8. The method of claim 1, wherein the pattern is a circuit design.

9. The method of claim 1, wherein the alignment mark facilitates precise alignment of the lithographic printing mask.

10. The method of claim 1, wherein the alignment mark is stored in a memory element and is retrieved during lithographic mask alignment.

11. A method, the method comprising: Capture images on a semiconductor substrate; Extract patterns from previous material layers placed on the semiconductor substrate from the captured image; and The pattern extracted from the previous material layer placed on the semiconductor substrate is combined to form alignment marks.

12. The method of claim 11, wherein the patterns are combined in a tiled block format.

13. The method of claim 11, wherein the patterns are combined in a cross-shaped geometric pattern.

14. The method of claim 11, wherein the pattern extracted from the semiconductor substrate is compared with other patterns on the semiconductor substrate to determine the uniqueness of the pattern.

15. An alignment mark generator, the alignment mark generator comprising: A camera for capturing an image of a feature on one of a plurality of grains formed on a semiconductor substrate or for capturing an image of a feature directly from the semiconductor substrate. A pattern extractor, used to extract patterns from each portion of a captured image; and A pattern combiner for combining the extracted patterns to form alignment marks.

16. The alignment mark generator of claim 15, wherein the pattern is combined in a tiled block format.

17. The alignment mark generator of claim 15, wherein the pattern is combined in a cross geometry.

18. The alignment mark generator of claim 15, wherein the pattern from the portion of each captured image is compared with other patterns on the die or the semiconductor substrate to determine the uniqueness of the pattern.

19. The alignment mark generator of claim 15, wherein the alignment marks facilitate precise alignment of the lithographic printing mask.

20. The alignment mark generator of claim 15, wherein the alignment marks are stored in a memory element and retrieved during lithographic mask alignment.

Images