Package substrate having stacked electronic component structure disposed in cavity of core

Abstract

In one aspect, a substrate includes: a core having a cavity; a first set of one or more metallization layers disposed at an upper portion of the core; and a stacked electronic component structure disposed in the cavity, wherein the stacked electronic component structure includes: a first electronic component including an upper surface having a second set of one or more metallization layers and a first set of via structures electrically coupling the first electronic component with the first set of one or more metallization layers; and a second electronic component positioned above the first electronic, the second electronic component including an upper surface having a third set of one or more metallization layers electrically coupling the second electronic component with the first set of one or more first metallization layers.

Description

Technical Field

[0001] This disclosure relates generally to a packaging substrate, and more specifically to a packaging substrate having stacked electronic components disposed in a cavity of a core substrate of the packaging substrate. Background Technology

[0002] Integrated circuit (IC) technology has made significant strides in improving computing power through the miniaturization of electronic components. An IC can be implemented as an IC chip on which a set of circuits is integrated. In some implementations, one or more IC chips can be physically carried and protected by an IC package, where the various power and signal nodes of the one or more IC chips can be electrically coupled to corresponding conductive terminals of the IC package via electrical paths formed in the package substrate. Various packaging technologies are found in many electronic devices, including processors, servers, radio frequency (RF) integrated circuits, etc. Advanced packaging and processing technologies can be used to realize complex devices, such as multi-component devices and system-on-a-chip (SoC) devices, which can include multiple functional blocks, each designed to perform a specific function, such as microprocessor functions, graphics processing unit (GPU) functions, communication functions (e.g., WiFi, Bluetooth, and other communications), etc.

[0003] In some implementations, embedded electronic components (such as deep trench capacitors) have been incorporated into IC packages to improve performance and reduce package size. One factor driving the use of such embedded electronic components is the desire for products with small form factor offering the same or better electrical performance as comparable larger electronic components. Summary of the Invention

[0004] The following is a simplified summary of the invention relating to one or more aspects disclosed herein. Therefore, this summary should not be considered an exhaustive overview relating to all conceived aspects, nor should it be considered to identify key or decisive elements relating to all conceived aspects or to depict the scope associated with any particular aspect. Thus, the sole purpose of this summary is to present, in a simplified form, certain concepts relating to one or more aspects involving the mechanisms disclosed herein, prior to the detailed description presented below.

[0005] In one aspect, a substrate includes: a core having a cavity; a first group of one or more metallization layers disposed at an upper portion of the core; and a stacked electronic component structure disposed in the cavity, wherein the stacked electronic component structure includes: a first electronic component including an upper surface having a second group of one or more metallization layers and a first group of via structures electrically coupling the first electronic component to the first group of one or more metallization layers; and a second electronic component located above the first electronic component, the second electronic component including an upper surface having a third group of one or more metallization layers electrically coupling the second electronic component to the first group of one or more first metallization layers.

[0006] In one aspect, an electronic device includes a substrate comprising: a core substrate including a core having a cavity; a first group of one or more metallization layers disposed at an upper portion of the cavity; and a stacked electronic component structure disposed within the cavity, wherein the stacked electronic component structure includes: a first electronic component including an upper surface having a second group of one or more metallization layers and a first group of vias electrically coupling the first electronic component to the first group of one or more metallization layers; and a second electronic component located above the first electronic component, the second electronic component including an upper surface having a third group of one or more metallization layers electrically coupling the second electronic component to the first group of one or more metallization layers.

[0007] In one aspect, a method of forming a substrate includes: forming a stacked electronic component structure, the stacked electronic component structure including: a first electronic component including an upper surface having a first set of one or more metallization layers and a first set of vias electrically coupling the first electronic component to a first set of one or more pads disposed on the upper surface of the stacked electronic component structure; a second electronic component located above the first electronic component, the second electronic component including an upper surface having a second set of one or more metallization layers electrically coupling the second electronic component to a second set of one or more pads disposed on the upper surface of the stacked electronic component structure; and positioning the stacked electronic component structure in a cavity of a core substrate.

[0008] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. Attached Figure Description

[0009] When considered in conjunction with the accompanying drawings, a more complete understanding of the various aspects of this disclosure and its many advantages therefrom will become better understood by referring to the following detailed description, which is presented for illustrative purposes only and does not constitute any limitation on this disclosure.

[0010] Figure 1 This is a cross-sectional view of a first example substrate having embedded electronic components according to various aspects of this disclosure.

[0011] Figure 2 This is a cross-sectional view of an example substrate having stacked electronic components disposed in a cavity at the core, according to various aspects of this disclosure.

[0012] Figure 3 This is a cross-sectional view of an example substrate having stacked electronic components disposed in a cavity at the core, according to various aspects of this disclosure.

[0013] Figures 4 to 7 Various stacked electronic component structures according to aspects of this disclosure are illustrated.

[0014] Figures 8A to 8D Exemplary operations that can be used to manufacture stacked electronic components according to various aspects of this disclosure are described.

[0015] Figures 9A to 9D Exemplary operations that can be used to manufacture stacked electronic components according to various aspects of this disclosure are described.

[0016] Figure 10 This is a flowchart illustrating an example method for manufacturing a substrate according to various aspects of this disclosure.

[0017] Figure 11 An outline view of a package according to various aspects of the present disclosure is illustrated, the package including a surface mount substrate, integrated devices, and a substrate structure having a stacked electronic component structure disposed in a cavity at the core.

[0018] Figure 12 Example methods for providing or manufacturing a package according to various aspects of this disclosure are illustrated, the package including an integrated device comprising a substrate having electronic components on a core.

[0019] Figure 13 Various electronic devices that can be integrated with any of the aforementioned devices according to various aspects of this disclosure are illustrated.

[0020] By convention, features depicted in the accompanying drawings may not be drawn to scale. Accordingly, for clarity, the dimensions of the depicted features may be arbitrarily enlarged or reduced. By convention, some figures in the drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular device or method. Furthermore, similar reference numerals are used throughout the specification and drawings to represent similar features. Detailed Implementation

[0021] Various aspects of this disclosure are illustrated in the following description and related figures with respect to specific embodiments. Alternative aspects or embodiments may be designed without departing from the scope of this teaching. Furthermore, well-known elements of the illustrative embodiments herein will not be described in detail or will be omitted to avoid obscuring the relevant details of the teachings in this disclosure.

[0022] In some of the described example implementations, instances are identified where various parts of the component structures and operations are available from known conventional techniques and are subsequently arranged according to one or more exemplary embodiments. In such instances, internal details of the parts of known conventional component structures and / or operations may be omitted to help avoid potential confusion with the concepts illustrated in the exemplary embodiments disclosed herein.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that the term “comprising,” as used herein, specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0024] Figure 1This is a cross-sectional view of a first example substrate 100 having embedded electronic components according to various aspects of the present disclosure. In this example, substrate 100 includes a core 102 having a cavity 104 extending entirely through the core 102. Electronic component 106 is disposed within the cavity 104. In this example, electronic component 106 includes a plurality of deep trench capacitors (DTCs) 108. Electronic component 106 has one or more metallization layers 110 disposed on an upper surface of electronic component 106, wherein the uppermost portion has a metal terminal 112 providing electrical connection between electronic component 106 and one or more metallization layers 114. Since the thickness T1 of electronic component 106 is less than the depth T2 of cavity 104, the lower portion of cavity 104 contains a material (e.g., dielectric resin) forming a support structure 116. Support structure 116 elevates electronic component 106 into a position within cavity 104 in which the metal terminal 112 can be connected to a metallized portion of metallization layer 114. In this example, the metallization layer is a patterned metallization layer, but a specific arrangement of pads and via structures is not shown because the structure of such components has design flaws and, according to various aspects of this disclosure, electronic component 106 may alternatively be one or more of active electronic components, passive electronic components (e.g., deep trench capacitors (DTC)), dies, etc.

[0025] According to various aspects of this disclosure, the substrate (e.g., substrate 100) described herein, comprising core and embedded electronic components, relates to a package substrate. A package substrate is part of an integrated circuit package, providing mechanical strength to the board and allowing it to connect to external devices. Such package substrates will be distinguished from other substrates, such as substrates that may be included within the embedded electronic component itself, dies comprising substrates (e.g., silicon substrates or other similar electronic devices), etc. Figure 1 In this embodiment, an external device is illustrated as an integrated circuit package 118 located on the upper portion of substrate 100. Substrate 100 is also configured for electrical connection to another device or substrate via one or more patterned metallization layers 120 and corresponding solder joints 122.

[0026] Although Figure 1The structure of the illustrated substrate 100 is suitable for many high-performance applications (e.g., computing and automotive applications), but current trends involve applications requiring substrates with higher electronic component densities. Some aspects of this disclosure are realized in recognition that the space within cavity 104 is not being used optimally in current packaging substrate architectures. For example, some aspects of this disclosure are realized in recognition that the area occupied by support structure 116 can be reused. Furthermore, some aspects of this disclosure are realized in recognition that, in certain scenarios, it may be feasible to reduce the space occupied by electronic components (e.g., DTCs) generally disposed in cavity 104 to make room for additional electronic component architectures. For example, in the context of DTCs, the current depth T1 of an existing DTC structure (e.g., typically less than about 780 micrometers in a cavity with a depth greater than 780 micrometers) can be reduced to depth T3 while still maintaining the functionality and integrity of capacitor 108, thereby leaving the volume of cavity 104 associated with depth T4 available for additional electronic components. Some aspects of this disclosure are further realized with the understanding that in certain scenarios, the support structure 116 does not need to exist within the cavity 104, thereby providing more space for additional electronic components.

[0027] Figure 2 This is a cross-sectional view of an example substrate 200 having stacked electronic components disposed in a core cavity, according to various aspects of this disclosure. For simplicity, Figure 1 Some of the figure marks used are also used to specify Figure 2 Similar components in [the text].

[0028] According to various aspects of this disclosure, similar to substrate 100, Figure 2 The example substrate 200 shown includes a core 102 having a cavity 104. Similarly, the example substrate 200 includes one or more patterned metallization layers 114 disposed on the upper portion of the core 102. Figure 1 The example shown differs from the one depicted; the example substrate 200 includes a stacked electronic component structure 202 disposed within a cavity 104. In this example, the stacked electronic component structure 202 includes a first electronic component 204 and a second electronic component 206 at least partially covering the first electronic component. The first electronic component 204 and the second electronic component 206 may be at least partially surrounded by a dielectric material 208. In one aspect, the dielectric material 208 embeds the first electronic component 204 and the second electronic component 206 within the cavity 104 and secures them to each other.

[0029] In one aspect, the first electronic component 204 may include one or more patterned metallization layers 210 located on the upper surface 212. A set of via structures 215 electrically connects the first electronic component 204 to a set of patterned metallization layers 114 located on the upper portion of the core 102. In one aspect, the electrical connection provided by the via structures 215 may include through-substrate vias (TSVs) 214, conductive portions of the patterned metallization layers 210, conductive portions of the patterned metallization layers 110, and metal terminals 112. In one aspect, some of the TSVs 214 may extend through the dielectric material 208, while other TSVs 214 may extend through the second electronic component 206.

[0030] The second electronic component 206 of the example substrate 200 may include an upper surface 216 having a patterned metallization layer 210. In one aspect, the patterned metallization layer 210 electrically connects the second electronic component 206 to the metallization layer 114 via metal terminals 112.

[0031] Figure 3 This is a cross-sectional view of an example substrate 300 having stacked electronic components disposed in a core cavity, according to various aspects of this disclosure. For simplicity, Figure 1 and Figure 2 Some of the figure marks used have also been used to specify Figure 3 Similar components in [the text].

[0032] According to various aspects of this disclosure, similar to substrate 200, Figure 3 The example substrate 300 shown includes a core 102 having a cavity 104. Similarly, the example substrate 300 includes one or more patterned metallization layers 114 disposed on the upper portion of the core 102. Figure 2 The example shown is the same; the example substrate 300 includes a stacked electronic component structure 302 disposed in the cavity 104. However, in this example, the stacked electronic component structure 302 is... Figure 2 The stacked electronic component structure 202 differs from this one. Here, the second electronic component 206 covers a pair of side-by-side electronic components 306 and 308. In one aspect, the side-by-side electronic components 306 and 308 are at least partially surrounded by a common support material 309 (e.g., a molding material). In another aspect, the common support material 309 secures the side-by-side electronic components 306 and 308 in a fixed relationship. Here, electronic components 204, 306, and 308 may be at least partially surrounded by a dielectric material 208. In one aspect, the dielectric material 208 embeds and secures the electronic components 204, 306, and 308 within the cavity 104.

[0033] In one aspect, electronic component 306 may include one or more patterned metallization layers 310 located on its upper surface. A set of via structures 312 electrically connects electronic component 306 to a set of patterned metallization layers 114 located on the upper portion of core 102. In one aspect, the electrical connection provided by the via structures 312 may include through-substrate vias (TSVs) 314, conductive portions of patterned metallization layers 310, conductive portions of patterned metallization layers 110, and metal terminals 112. In one aspect, some of the TSVs 314 extend through dielectric material 208, while other TSVs 314 extend through electronic component 206.

[0034] In one aspect, electronic component 308 may include one or more patterned metallization layers 316 located on its upper surface. A set of via structures 318 electrically connects electronic component 306 to a set of patterned metallization layers 114 located on the upper portion of core 102. In one aspect, the electrical connection provided by the via structures 318 may include through-substrate vias (TSVs) 320, conductive portions of patterned metallization layers 316, conductive portions of patterned metallization layers 110, and metal terminals 112. In one aspect, some of the TSVs 320 extend through dielectric material 208, while other TSVs 320 extend through electronic component 206.

[0035] Figures 4 to 7 Various stacked electronic component structures according to aspects of this disclosure are illustrated. In one aspect, each of the various stacked electronic component structures includes a DTC component overlaid on one or more different electronic components in different convergence solution scenarios (e.g., stacking of different types of electronic components). However, in consideration of the teachings of this disclosure, it should be understood that the overlaid electronic component can be an electronic component other than a DTC component.

[0036] Figure 4 An example stacked electronics structure 400 according to various aspects of this disclosure is illustrated, the stacked electronics structure having a DTC 402 located above an electronics component 404 other than a DTC component. In one aspect, the electronics component 404 has a width that coexists with the width of the DTC 402 and therefore all TSVs 406 extend through the DTC 402.

[0037] In the example scenario, electronic component 404 may be an input / output hub (I / O hub). In one aspect, an I / O hub may be a central component or subsystem managing input and output operations between various components of the system. In another aspect, an I / O hub may act as an interface between processing units (such as CPUs, GPUs, memory modules, etc.) and external peripheral devices or equipment. An I / O hub may be operable to facilitate communication of data, control signals, and / or power distribution between such internal components and external components.

[0038] In the example scenario, electronic component 404 could be a skew matching block. A skew matching block is a component used to manage or mitigate timing skew in electronic signal paths. For example, in high-speed electronic systems (such as those found in computers, telecommunications equipment, and other digital devices), signal timing can be critical for proper operation. Due to variations in path length, material properties, and other factors, signals traveling along different paths may arrive at their destination at slightly different times. This difference in arrival time is called skew. Skew matching blocks are designed to address such timing problems by adjusting the signal paths so that all signals arrive at their destination simultaneously or within an allowable timing window. This can be achieved through various means, such as adding delay lines, using phase-locked loops (PLLs), or employing other circuit techniques to equalize path lengths or dynamically adjust signal timing.

[0039] In one aspect, electronic component 404 may be a serializer / deserializer (SerDes). In another aspect, such a SerDes may include one or both portions of a pair of functional blocks for high-speed communication, compensating for limited input / output (I / O) bandwidth by efficiently converting data between serial and parallel interfaces in each direction.

[0040] In one aspect, electronic component 404 can be an I / O unwrapping block. In another aspect, an I / O unwrapping block can facilitate more efficient management, routing, or organization of I / O connections. This may involve hardware or software solutions that optimize the connection layout to minimize crosstalk, electromagnetic interference, or physical constraints within the substrate / package.

[0041] Figure 5 Another example of a stacked electronics structure 500 according to various aspects of this disclosure is illustrated, having a DTC 502 located above an electronics component 504 other than the DTC component. In one aspect, the electronics component 504 may be a passive circuit element, such as a bulk inductor. In another aspect, such a bulk inductor may be located within an inductor capable of managing high-power levels for applications such as DC-DC converters, power management modules, or electromagnetic interference (EMI) filtering. Figure 5In this configuration, the DTC has a width smaller than that of the electronic component 504. Therefore, at least some of the TSVs in TSV 506 can be routed through the dielectric material 208.

[0042] Figure 6 Another example of a stacked electronics structure 600 according to various aspects of this disclosure is illustrated, the stacked electronics structure having a DTC 602 located above an electronics component 604 other than the DTC component. In one aspect, the electronics component 604 may be an I / O hub, a SerDes component, a skew matching block and an unwrap block, or a combination thereof. In one aspect, a signal 606 associated with the electronics component may be routed through the DTC 602, the dielectric material 208, or a combination thereof.

[0043] Figure 7 Another example of a stacked electronics structure 700 according to various aspects of this disclosure is illustrated, the stacked electronics structure having a DTC 702 located above side-by-side electronics 704, 706 other than the DTC component. In one aspect, the side-by-side electronics 704, 706 may include I / O hubs, SerDes components, skew matching blocks and unwinding blocks, or combinations thereof. In one aspect, a signal 708 associated with electronics 704 may be routed through the DTC 702, dielectric material 208, or a combination thereof. In one aspect, a signal 710 associated with electronics 706 may be routed through the DTC 702, dielectric material 208, or a combination thereof.

[0044] Figures 8A to 8D Exemplary operations that can be used to manufacture stacked electronic components according to various aspects of this disclosure are described. Figure 8A In this configuration, stacked electronic components are shown in an intermediate state 800, where electronic component 802 (e.g., DTC) is connected to electronic component 804. In one aspect, in a prior manufacturing operation, electronic component 802 may be fabricated with a patterned metallization layer 806. Similarly, in a prior manufacturing operation, electronic component 804 may be fabricated with a patterned metallization layer 808. Likewise, in a prior manufacturing operation, electronic component 802 may be fabricated with a via structure 810. Figure 8A In this configuration, one or more TSVs 812 are electrically connected to corresponding portions of the patterned metallization layer 808. In one aspect, the TSVs 812 can be attached to corresponding portions of the patterned metallization layer 808 during a TSV bonding operation.

[0045] exist Figure 8BIn the diagram, the stacked electronic components are shown in an intermediate state 814, wherein dielectric material 816 (e.g., molding material) has been deposited over the electronic components 802, the exposed portions of the patterned metallization layers 806 and 808, and the TSV 812. In one aspect, the dielectric material 816 may be deposited during a molding manufacturing operation.

[0046] exist Figure 8C In the diagram, the stacked electronic components are shown in an intermediate state 818, where the upper portion of the dielectric material 816 has been removed to expose the conductive portions of the patterned metallization layers 806 and 808, as well as the TSV 812. In one aspect, the upper portion of the dielectric material 816 can be removed during a chemical mechanical polishing (CMP) operation.

[0047] exist Figure 8D In this embodiment, the stacked electronic assembly is shown in a final state 820, wherein metal contacts 822 have been formed for electrical connection with conductive portions of patterned metallization layers 806 and 808 and TSV 812. In one aspect, the metal contacts 822 may be formed in a standard metal bump manufacturing operation (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, etc.). In another aspect, the final state 820 of the stacked electronic assembly may be inserted into and secured within a cavity of a core for connection with patterned metallization layers disposed above the upper and lower surfaces of the core.

[0048] Figures 9A to 9D Exemplary operations that can be used to manufacture stacked electronic components according to various aspects of this disclosure are described. Figure 9A In this configuration, stacked electronic components are shown in an intermediate state 900, where electronic component 902 (e.g., DTC) is connected to a pair of side-by-side electronic components 904 and 906. In one aspect, in a prior manufacturing operation, electronic component 902 may be fabricated with a patterned metallization layer 908. Similarly, in a prior manufacturing operation, side-by-side electronic components 904 and 906 may be fabricated with patterned metallization layers 910 and 912. Likewise, in a prior manufacturing operation, electronic component 902 may be fabricated with a corresponding via structure 914. For… Figure 9A For the purpose of the manufacturing operation shown in Figure 9, in the previous manufacturing operation, side-by-side electronic components 904 and 906 can be embedded in a common support material 916 and fixed to a carrier 918. Figure 9A In this configuration, one or more TSVs 920 and 922 are electrically connected to corresponding portions of patterned metallization layers 910 and 912. In one aspect, TSVs 920 and 922 may be attached to corresponding portions of patterned metallization layers 910 and 912 during a TSV bonding operation.

[0049] exist Figure 9BIn the diagram, the stacked electronic components are shown in an intermediate state 924, where dielectric material 926 (e.g., molding material) has been deposited over electronic components 902, side-by-side electronic components 904 and 906, exposed portions of patterned metallization layers 908, 910 and 912, and TSVs 920 and 922. In one aspect, dielectric material 96 may be deposited during a molding manufacturing operation.

[0050] exist Figure 9C In the diagram, the stacked electronic components are shown in an intermediate state 928, where the upper portion of the dielectric material 926 has been removed to expose the conductive portions of the patterned metallization layers 908, 910, and 912, as well as TSVs 920 and 922. In one aspect, the upper portion of the dielectric material 926 may be removed during a chemical mechanical polishing (CMP) operation.

[0051] exist Figure 9D In this embodiment, the stacked electronic assembly is shown in its final state 930, wherein metal contacts 932 have been formed for electrical connection with conductive portions of the patterned metallization layer 908 and TSVs 920 and 922. In one aspect, the metal contacts 932 can be formed in standard metal bump manufacturing operations (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, etc.). In another aspect, the final state 930 of the stacked electronic assembly can be inserted and secured within a cavity of a core for connection with patterned metallization layers disposed on the upper and lower surfaces of the core.

[0052] Figure 10 This is a flowchart illustrating an example method 1000 for manufacturing a substrate according to various aspects of the present disclosure. In operation 1002, a stacked electronic component structure is formed, comprising: a first electronic component including an upper surface having one or more metallization layers of a first group and a first group of vias electrically coupling the first electronic component to one or more pads disposed on the upper surface of the stacked electronic component structure; and a second electronic component located above the first electronic component, the second electronic component including an upper surface having one or more metallization layers of a second group, the second group of metallization layers electrically coupling the second electronic component to one or more pads disposed on the upper surface of the stacked electronic component structure. In operation 1004, the stacked electronic component structure is positioned within a cavity of a core substrate.

[0053] The technical advantage of method 1000 is that it can be used to form a substrate in a manner that facilitates the optimization of the use of the cavity in the core. In one aspect, the resulting method can provide a substrate fabricated having a stacked electronic component structure, which is stacked to meet the increasing demand for electronic packaging density.

[0054] Figure 11 A contour view of a package 1100 according to various aspects of the present disclosure is illustrated. The package includes a surface mount substrate 1102, an integrated device 1103, and an integrated device 1105 (e.g., a substrate having embedded stacked electronic components and a core). The package 1100 can be coupled to a printed circuit board (PCB) 1106 via a plurality of solder interconnects 1110. The PCB 1106 may include at least one board dielectric layer 1160 and a plurality of board interconnects 1162.

[0055] Surface mount substrate 1102 includes at least one dielectric layer 1120 (e.g., a substrate dielectric layer), a plurality of interconnects 1122 (e.g., substrate interconnects), a solder mask layer 1140, and a solder mask layer 1142. Integrated device 1103 can be coupled to surface mount substrate 1102 via a plurality of solder interconnects 1130. Integrated device 1103 can be coupled to surface mount substrate 1102 via a plurality of solder interconnects 1150. Integrated device 1105 can be coupled to surface mount substrate 1102 via a plurality of solder interconnects 1152 and a plurality of solder interconnects 1150.

[0056] The package (e.g., 1100) may be implemented in a radio frequency (RF) package. This RF package may be a radio frequency front-end (RFFE) package. The package (e.g., 1100) may be configured to provide wireless fidelity (WiFi) communication and / or cellular communication (e.g., 2G, 3G, 4G, 5G). The package (e.g., 1100) may be configured to support Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), and / or Long Term Evolution (LTE). The package (e.g., 1100) may be configured to transmit and receive signals with different frequencies and / or communication protocols.

[0057] Figure 12 An example method 1200 for providing or manufacturing a package according to various aspects of this disclosure is illustrated, the package including an integrated device comprising a substrate having electronic components on a core. In some specific embodiments, Figure 12 Method 1200 can be used to provide or manufacture the invention described in this disclosure. Figure 11 Package 1100. However, method 1200 can be used to provide or manufacture any package described in this disclosure.

[0058] It should be pointed out that, Figure 12The method may combine one or more processes to simplify and / or clarify the methods for providing or manufacturing packages that include integrated devices (including magnetic layers) and / or integrated passive devices (including magnetic layers). In some specific implementations, the order of the processes may be changed or modified.

[0059] The method (at 1205) provides a surface mount substrate (e.g., 1102). The surface mount substrate 1102 may be supplied by a vendor or manufactured. The surface mount substrate 1102 includes at least one dielectric layer 1120 and a plurality of interconnects 1122. The surface mount substrate 1102 may include an embedded trace substrate (ETS). In some embodiments, at least one dielectric layer 1120 may include a prepreg layer.

[0060] The method (at 1210) couples at least one integrated device (e.g., 1103) to a first surface of a substrate (e.g., 1102). For example, the integrated device 1103 may be coupled to the surface mount substrate 1102 via a plurality of pillar interconnects 1132 and a plurality of solder interconnects 1130. The plurality of pillar interconnects 1132 may be optional. The plurality of solder interconnects 1130 are coupled to a plurality of interconnects 1122. A solder reflow process may be used to couple the integrated device 1103 to the plurality of interconnects via the plurality of solder interconnects 1130.

[0061] The method (at 1210) also couples at least one integrated passive device (e.g., 1105) to a first surface of a substrate (e.g., 1102). For example, the integrated device 1105 can be coupled to the surface mount substrate 1102 via a plurality of pillar interconnects 1152 and a plurality of solder interconnects 1150. The plurality of pillar interconnects 1152 may be optional. The plurality of solder interconnects 1150 are coupled to a plurality of interconnects 1122. A solder reflow process can be used to couple the integrated device 1105 to the plurality of interconnects via the plurality of solder interconnects 1150.

[0062] The method (at 1215) couples a plurality of solder interconnects (e.g., 1110) to a second surface of a substrate (e.g., 1102). A solder reflow process can be used to couple the plurality of solder interconnects 1110 to the substrate.

[0063] Figure 13Examples of various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated stacked packages (PoP), system-in-package (SiP), or system-on-a-chip (SoC) are illustrated. For example, mobile phone device 1302, laptop computer device 1304, fixed-location terminal device 1306, wearable device 1308, or motor vehicle 1310 may include device 1300 as described herein. For example, device 1300 may be any of the devices and / or integrated circuit (IC) packages described herein. Figure 13 The illustrated devices 1302, 1304, 1306, and 1308, as well as vehicle 1310, are merely exemplary. Other electronic devices may also feature device 1300, including but not limited to devices (e.g., electronic devices) comprising the following group: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (such as watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (such as autonomous vehicles), or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0064] Specific implementation examples are described in the following numbering section: Aspect 1. A substrate, the substrate comprising: a core having a cavity; a first group of one or more metallization layers disposed at an upper portion of the core; and a stacked electronic component structure disposed in the cavity, wherein the stacked electronic component structure comprises: a first electronic component including an upper surface having a second group of one or more metallization layers and a first group of via structures electrically coupling the first electronic component to the first group of one or more metallization layers; and a second electronic component located above the first electronic component, the second electronic component including an upper surface having a third group of one or more metallization layers electrically coupling the second electronic component to the first group of one or more metallization layers.

[0065] Aspect 2. The substrate according to aspect 1, wherein: the second electronic component includes a deep trench capacitor (DTC).

[0066] Aspect 3. The substrate according to any one of Aspects 1 to 2, wherein: the first electronic component includes an input / output (I / O) hub.

[0067] Aspect 4. The substrate according to any one of Aspects 1 to 3, wherein: the first electronic component includes a skew matching block.

[0068] Aspect 5. The substrate according to any one of Aspects 1 to 4, wherein: the first electronic component includes a bulk inductor.

[0069] Aspect 6. The substrate according to any one of Aspects 1 to 5, wherein: the first electronic component includes an input / output (I / O) unwinding block.

[0070] Aspect 7. The substrate according to any one of Aspects 1 to 6, wherein the stacked electronic component structure further comprises: a third electronic component disposed next to the first electronic component, the third electronic component having an upper surface and a second set of via structures, the upper surface having a third set of one or more metallization layers, the second set of via structures electrically coupling the third electronic component to the first set of one or more metallization layers.

[0071] Aspect 8. The substrate according to aspect 7, wherein: the first electronic component and the third electronic component are disposed side by side in a common support material.

[0072] Aspect 9. The substrate according to any one of Aspects 1 to 8, wherein: the core has a thickness greater than about 780 micrometers.

[0073] Aspect 10. An electronic device comprising a substrate, the substrate comprising: a core substrate including a core having a cavity; a first group of one or more metallization layers disposed at an upper portion of the cavity; and a stacked electronic component structure disposed in the cavity, wherein the stacked electronic component structure comprises: a first electronic component including an upper surface having a second group of one or more metallization layers and a first group of vias electrically coupling the first electronic component to the first group of one or more metallization layers; and a second electronic component located above the first electronic component, the second electronic component including an upper surface having a third group of one or more metallization layers electrically coupling the second electronic component to the first group of one or more metallization layers.

[0074] Aspect 11. The substrate according to aspect 10, wherein: the second electronic component includes a deep trench capacitor (DTC).

[0075] Aspect 12. The substrate according to any one of Aspects 10 to 11, wherein: the first electronic component includes an input / output (I / O) hub.

[0076] Aspect 13. The substrate according to any one of Aspects 10 to 12, wherein: the first electronic component includes a skew matching block.

[0077] Aspect 14. The substrate according to any one of Aspects 10 to 13, wherein: the first electronic component includes a bulk inductor.

[0078] Aspect 15. The substrate according to any one of Aspects 10 to 14, wherein: the first electronic component includes an input / output (I / O) unwinding block.

[0079] Aspect 16. The substrate according to any one of Aspects 10 to 15, wherein the stacked electronic component structure further comprises: a third electronic component disposed adjacent to the first electronic component, the third electronic component having an upper surface and a second set of vias, the upper surface having a third set of one or more metallization layers, the second set of vias electrically coupling the third electronic component to the first set of one or more metallization layers.

[0080] Aspect 17. The substrate according to aspect 16, wherein: the first electronic component and the third electronic component are disposed side by side in a common support material.

[0081] Aspect 18. The substrate according to any one of Aspects 10 to 17, wherein: the core has a thickness greater than about 780 micrometers.

[0082] Aspect 19. An electronic device according to any one of Aspects 10 to 18, wherein the electronic device includes at least one of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, or a device in a motor vehicle.

[0083] Aspect 20. A method of forming a substrate, the method comprising: forming a stacked electronic component structure, the stacked electronic component structure comprising: a first electronic component, the first electronic component including an upper surface having a first set of one or more metallization layers and a first set of vias, the first set of vias electrically coupling the first electronic component to a first set of one or more pads disposed on the upper surface of the stacked electronic component structure; and a second electronic component, the second electronic component being located above the first electronic component, the second electronic component including an upper surface having a second set of one or more metallization layers, the second set of one or more metallization layers electrically coupling the second electronic component to a second set of one or more pads disposed on the upper surface of the stacked electronic component structure; and positioning the stacked electronic component structure in a cavity of a core substrate.

[0084] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and arts. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0085] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0086] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. The term “electrical coupling” can mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can travel between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term “encapsulation” means that an object may partially or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component located at the top may be above a component located at the bottom. A top component may be considered a bottom component, and vice versa. As described in this disclosure, a first component located “above” a second component may mean that the first component is above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term “above” as used in this application in the context of one component being above another component may be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Therefore, for example, "the first component is on top of the second component" can mean: (1) the first component is on top of the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located in the second component. The terms "about 'value X'" or "approximately value X" as used in this disclosure mean within 10% of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0087] In some embodiments, an interconnect is an element or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metallization layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0088] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structure diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. A process terminates when its operations are completed.

[0089] As can be seen in the detailed description above, different features are grouped together in the examples. This manner of disclosure should not be construed as an intention to have more features in the example aspects than are explicitly mentioned in each aspect. Rather, the various aspects of this disclosure may include fewer features than those in the individual example aspects disclosed. Therefore, the following aspects should be regarded accordingly as incorporated into the description, where each aspect can be considered as a separate example on its own. While each dependent aspect may refer to an aspect of a particular combination with one of the other aspects, the aspect of that dependent aspect is not limited to that particular combination. It should be understood that other example aspects may also include combinations of the subject matter of a dependent aspect with any other dependent or independent aspect, or any feature combined with other dependent and independent aspects. The various aspects disclosed herein explicitly include these combinations unless explicitly stated or readily inferred that a particular combination is not intended for use (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor). Furthermore, it is contemplated that aspects of an aspect may be included in any other independent aspect, even if that aspect does not directly depend on the independent aspect.

[0090] While the foregoing disclosure illustrates exemplary aspects of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined by the appended claims. The functions, steps, and / or actions of the method claims according to the aspects of this disclosure described herein need not be performed in any particular order. Furthermore, although elements of this disclosure may be described or claimed in the singular, the plural form may also be considered unless expressly stated as limited to the singular.

Claims

1. A substrate, the substrate comprising: The core has a cavity; A first group of one or more metallization layers is disposed on the upper portion of the core; and A stacked electronic component structure disposed within the cavity, wherein the stacked electronic component structure comprises: A first electronic component, comprising an upper surface having one or more second metallization layers and a first set of via structures, the first set of via structures electrically coupling the first electronic component to the first set of one or more metallization layers. A second electronic component is located above the first electronic component. The second electronic component includes an upper surface having a third set of one or more metallization layers that electrically couple the second electronic component to the first set of one or more metallization layers.

2. The substrate according to claim 1, wherein: The second electronic component includes a deep trench capacitor (DTC).

3. The substrate according to claim 1, wherein: The first electronic component includes an input / output (I / O) hub.

4. The substrate according to claim 1, wherein: The first electronic component includes a skew matching block.

5. The substrate according to claim 1, wherein: The first electronic component includes a bulk inductor.

6. The substrate according to claim 1, wherein: The first electronic component includes an input / output (I / O) unwrapping block.

7. The substrate according to claim 1, wherein the stacked electronic component structure further comprises: A third electronic component is disposed next to the first electronic component. The third electronic component has an upper surface and a second set of via structures. The upper surface has a third set of one or more metallization layers. The second set of via structures electrically couples the third electronic component to the first set of one or more metallization layers.

8. The substrate according to claim 7, wherein: The first electronic component and the third electronic component are arranged side by side in a common support material.

9. The substrate according to claim 1, wherein: The core has a thickness greater than approximately 780 micrometers.

10. An electronic device, the electronic device comprising: A substrate, the substrate comprising: A core substrate, the core substrate comprising a core having a cavity; A first group of one or more metallization layers is disposed on the upper portion of the cavity; and A stacked electronic component structure disposed within the cavity, wherein the stacked electronic component structure comprises: A first electronic component, the first electronic component including an upper surface having one or more second metallization layers and a first set of vias, the first set of vias electrically coupling the first electronic component to the first set of one or more metallization layers, and A second electronic component is located above the first electronic component. The second electronic component includes an upper surface having a third set of one or more metallization layers that electrically couple the second electronic component to the first set of one or more metallization layers.

11. The substrate according to claim 10, wherein: The second electronic component includes a deep trench capacitor (DTC).

12. The substrate according to claim 10, wherein: The first electronic component includes an input / output (I / O) hub.

13. The substrate according to claim 10, wherein: The first electronic component includes a skew matching block.

14. The substrate according to claim 10, wherein: The first electronic component includes a bulk inductor.

15. The substrate according to claim 10, wherein: The first electronic component includes an input / output (I / O) unwrapping block.

16. The substrate of claim 10, wherein the stacked electronic component structure further comprises: A third electronic component is disposed next to the first electronic component. The third electronic component has an upper surface and a second set of vias. The upper surface has a third set of one or more metallization layers. The second set of vias electrically couples the third electronic component to the first set of one or more metallization layers.

17. The substrate according to claim 16, wherein: The first electronic component and the third electronic component are arranged side by side in a common support material.

18. The substrate according to claim 10, wherein: The core has a thickness greater than approximately 780 micrometers.

19. The electronic device of claim 10, wherein the electronic device comprises at least one of the following: Music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, or devices in motor vehicles.

20. A method of forming a substrate, the method comprising: Forming a stacked electronic component structure, the stacked electronic component structure includes: A first electronic component, comprising an upper surface having one or more metallization layers and a first set of vias, the first set of vias electrically coupling the first electronic component to one or more pads disposed on the upper surface of the stacked electronic component structure. A second electronic component, located above the first electronic component, includes an upper surface having one or more second sets of metallization layers, the second set of one or more metallization layers electrically coupling the second electronic component to one or more pads disposed on the upper surface of the stacked electronic component structure; and The stacked electronic component structure is positioned within the cavity of the core substrate. 。

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