Integrated device with conductive pillar structures for die interconnection

Abstract

A device includes a substrate including a set of metal layers separated from each other by a set of dielectric layers. The set of metal layers defines a first set of metal lines and a second set of metal lines. The substrate includes a first set of conductive pillars configured to be electrically connected to a first die and a second set of conductive pillars interconnecting the first set of metal lines to the first set of conductive pillars. The substrate also includes a first set of pads configured to be electrically connected to the first die and a first set of conductive vias interconnecting the second set of metal lines to the first set of pads. The first set of conductive pillars extends from a surface of the substrate.

Description

Cross-references to related applications

[0001] This application claims the benefit of priority to jointly owned U.S. non-provisional patent application No. 18 / 609,991, filed March 19, 2024, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0002] Various features are involved in integrated devices. Background Technology

[0003] Electrical connections exist at every level of a system hierarchy. This hierarchy includes interconnections of active devices at the lowest system level, all the way up to system-level interconnections at the highest level. For example, interconnect layers connect different devices on an integrated circuit. As integrated circuits become more complex, more interconnect layers are used to provide electrical connections between devices. Recently, due to the sheer number of interconnected devices in modern electronic devices, the number of interconnect layers in a circuit has substantially increased. The increasing number of interconnect layers to support the growing number of devices involves more complex processes.

[0004] Existing mobile application devices require small form factor, low cost, tight power budgets, and high electrical performance. Mobile packaging designs have evolved to meet these diverse goals to enable multimedia-enhanced mobile applications. However, when multiple dies are arranged within a small form factor, these mobile applications are susceptible to power and signal routing challenges. The design and fabrication of devices for mobile applications are challenging due to the conflicting design goals. For example, smaller form factor devices are generally more expensive to design and manufacture, and the small size can exacerbate other problems such as thermal management. As another example, performance can be improved by providing more signal paths between dies; however, providing more signal paths typically increases cost and size. Summary of the Invention

[0005] Various features are involved in integrated devices.

[0006] One example provides a device including a substrate. The substrate includes a set of metal layers spaced apart from each other by a set of dielectric layers, the set of metal layers defining a first set of metal lines and a second set of metal lines. The substrate includes a first set of conductive pillars configured to be electrically connected to a first die. The substrate includes a second set of conductive pillars interconnecting the first set of metal lines to the first set of conductive pillars. The substrate includes a first set of pads configured to be electrically connected to the first die. The substrate also includes a first set of conductive vias interconnecting the second set of metal lines to the first set of pads. The first set of conductive pillars extends from a surface of the substrate.

[0007] Another example provides a device comprising: a first die including a first circuit and a second die including a second circuit. The device further includes a substrate configured to electrically connect the first circuit to the second circuit and to electrically connect the first circuit, the second circuit, or both, to one or more off-package devices. The substrate includes a set of metal layers spaced apart from each other by a set of dielectric layers. The set of metal layers defines a first set of metal lines and a second set of metal lines. The substrate includes a first set of conductive pillars electrically connected to the first die. The substrate includes a first set of pads electrically connected to the first die. The substrate includes a second set of conductive pillars interconnecting the first set of metal lines to the first set of conductive pillars. The substrate includes a first set of conductive vias interconnecting the second set of metal lines to the first set of pads. The substrate includes a third set of conductive pillars electrically connected to the second die. The substrate includes a second set of pads electrically connected to the second die. The substrate includes a fourth set of conductive pillars interconnecting the first set of metal lines to the third set of conductive pillars to interconnect the first die to the second die. The substrate also includes a second set of conductive vias interconnecting the second set of metal lines to the second set of pads. The first set of conductive pillars and the third set of conductive pillars extend from the surface of the substrate.

[0008] Another example provides a method of manufacturing a device. The method includes forming a first metal line from a first set of metal lines and a second metal line from a second set of metal lines in a metal layer of a substrate. The method includes forming a second conductive post connected to the first metal line in a dielectric layer above the metal layer. The method includes forming a conductive via connected to the second metal line in the dielectric layer. The method includes forming a pad connected to the conductive via and configured to be electrically connected to a first die. The method further includes forming a first conductive post connected to the second conductive post and configured to be electrically connected to the first die. The first conductive post extends from the surface of the substrate. Attached Figure Description

[0009] The various features, essence, and advantages will become apparent when the detailed description set forth below is understood in conjunction with the accompanying drawings, in which similar reference characters are used for corresponding identification throughout.

[0010] Figure 1 A cross-sectional profile view of a device including conductive pillar structures for die interconnection is illustrated.

[0011] Figure 2 Examples are shown that can be included in Figure 1 A cross-sectional profile view of pillars, pads, vias, and lines in the device.

[0012] Figure 3A , Figure 3B , Figure 3C and Figure 3D An exemplary process for manufacturing a device including conductive post structures for die interconnection is illustrated.

[0013] Figure 4A, Figure 4B and Figure 4C This also illustrates another exemplary stage of a process for manufacturing a device that includes conductive pillar structures for die interconnection.

[0014] Figure 5 This is a flowchart illustrating an exemplary method for manufacturing a device including conductive pillar structures for die interconnection.

[0015] Figure 6 Examples are provided of various electronic devices that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages and / or device packages described herein. Detailed Implementation

[0016] In the following description, specific details are set forth to provide a thorough understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid complicating these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid complicating these aspects of this disclosure. As another example, various devices and structures disclosed herein are illustrated schematically. Such illustrative representations are not to scale and are generally intentionally simplified. For illustration purposes, integrated devices may have dozens or hundreds of contacts and corresponding interconnects; however, a very small number of such contacts and interconnects are illustrated herein to highlight key features of this disclosure without unduly complicating the figures.

[0017] Specific aspects of this disclosure are described below with reference to the accompanying drawings. In this description, common features are designated by common reference numerals. As used herein, various terms are used only for the purpose of describing particular embodiments and are not intended to limit the scope of the embodiments. For example, the singular forms “a” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. Furthermore, some features described herein are singular in some embodiments and plural in others. For ease of reference herein, such features are generally introduced as “one or more” features and are subsequently referred to in the singular or optional plural form (as indicated by “(multiple)”), unless the aspect relating to multiples of features is being described.

[0018] In some accompanying figures, multiple instances of a particular type of feature are shown. In some cases, only a portion of such features may be identified using reference numerals. For example, a single reference numeral may be shown and associated with a representative instance of the feature so as not to obscure other aspects of the figure. Where physical and / or logical distinctions between similar features are important, the same reference numeral may be used for each such feature, and different instances may be distinguished by adding letters to the reference numeral. When features are referred to herein as a group or a type (e.g., when a specific feature among these features is not referenced), reference numerals are used without distinguishing letters. However, when a specific feature of multiple features of the same type is referred to herein, reference numerals are used with distinguishing letters. For example, referencing... Figure 1 Multiple dies are illustrated and associated with reference numerals 102A and 102B. When referring to a specific die among these dies (such as die 102A), the distinguishing letter "A" is used. However, when referring to any one of these dies or to these dies as a group, reference numeral 102 is used without the distinguishing letter.

[0019] As used herein, the term "comprising" may be used interchangeably with "including". As used herein, "exemplary" indicates an example, specific implementation, and / or aspect, and should not be construed as limiting or indicating a preference or preferred specific implementation. As used herein, ordinal numbers (e.g., "first", "second", "third", etc.) used to modify elements such as structures, components, operations, etc., do not themselves indicate any priority or order of that element relative to another element, but merely distinguish that element from another element with the same name (but using an ordinal number). As used herein, the term "group" refers to one or more elements in a particular set, and the term "multiple" refers to multiple (e.g., two or more) elements in a particular set.

[0020] Improvements in manufacturing technology and the demand for lower-cost and more capable electronic devices have led to increased complexity in integrated circuits (ICs). Typically, more complex ICs have more complex interconnect schemes to enable interaction between ICs within a device. Due to the sheer number of interconnected devices in today's state-of-the-art mobile applications, the number of interconnect layers in the circuitry has also increased substantially.

[0021] These interconnects include back-end process (BEOL) interconnect layers, which can refer to conductive interconnect layers used for electrical coupling to front-end process (FEOL) active devices of the IC. Various BEOL interconnect layers are formed at corresponding BEOL interconnect levels, where lower BEOL interconnect levels typically use a thinner metal layer than upper BEOL interconnect levels. BEOL interconnect layers can be electrically coupled to middle-end process (MOL) interconnect layers, which interconnect to the IC's FEOL active devices.

[0022] Existing mobile application devices require small form factor, low cost, tight power budgets, and high electrical performance. Mobile packaging designs have evolved to meet these diverse goals to enable multimedia-enhanced mobile applications. One approach to reducing package size is to integrate multiple dies within a single package. An example of a multi-die package is a two-dimensional (2D) package architecture where two or more dies are coupled side-by-side to a package substrate. Dies in this configuration can interact with each other (e.g., via die-to-die connections) and with external devices (e.g., via external interconnects). The challenge with such a configuration is that die-to-die and external interconnects have different design criteria. For example, external interconnects are typically larger than the dimensions required for die-to-die connections (e.g., line width, line spacing, etc.). Various workarounds have been used to address this size difference. For instance, additional devices (e.g., interposer devices or bridging dies) can be added to the package to allow for wiring of die-to-die connections using smaller lines. As another example, additional layers or separate stacked substrates can be added to the package substrate to provide die-to-die connections and redistribute wiring to external interconnects.

[0023] Another approach to reducing package size is the 2.5D architecture, in which two or more devices are positioned side-by-side on a package substrate, and one or more additional devices are stacked on top of at least one of the side-by-side devices. For illustration, a stacked die arrangement can be coupled side-by-side to the package substrate with another die, a passive device, another die stack, etc. Stacked die solutions and chiplet architectures are becoming increasingly prevalent as stacked die and chiplet architecture product lines achieve significantly improved power performance area (PPA) yields.

[0024] Various challenges are associated with reducing package size in multi-die packages using 2D packaging architectures. For example, conventional layer-to-layer connections are formed in the substrate using laser drilling processes during via formation. The capabilities and registration accuracy of laser drilling mechanisms result in relatively large via and pad diameters. For multi-die connections, a relatively large number of connections are required to interconnect the dies, but using conventional package design rules, the routing required for such a large number of connections may be infeasible. Providing this routing requires fine line-to-space (L / S) characteristics and a relatively large number of layers for routing, where vias provide layer-to-layer connections for the routing.

[0025] Various aspects of this disclosure provide a device including a conductive pillar structure for die interconnects that addresses many challenges of multi-die packages. For example, the conductive pillar structure is configured to provide signal paths between two or more dies coupled to a package substrate using conductive pillar (e.g., copper pillar) processing techniques to form layer-to-layer connections with a reduced size compared to conventional vias. The reduced size allows for routing a larger number of traces between the pillars in each layer, thereby reducing the number of layers required to carry die-to-die wiring. A technical benefit achieved by using this arrangement is that a large number of die-to-die signal paths can be set in a small area of ​​the substrate, resulting in improved performance due to the increased interconnects between dies without a corresponding increase in package size. The reduced size also allows for the use of relatively large line and space characteristics to form die-to-die connections, thereby providing improved power and thermal performance compared to alternative methods such as redistribution layers.

[0026] As used herein, the term "layer" includes films and is not construed as indicating vertical or horizontal thickness unless otherwise stated. As used herein, the term "chiplet" can refer to a block of integrated circuits, a block of functional circuitry, or other similar circuitry specifically designed to work with one or more other chiplets to form a larger, more complex chiplet architecture.

[0027] Exemplary devices including conductive pillar structures for die interconnects Figure 1 An example of a device 100 comprising a plurality of dies 102 coupled to a substrate 106 is illustrated. Figure 1In this embodiment, die 102 includes die 102A and die 102B. Each die 102 may include circuitry 104, such as multiple transistors and / or other circuit elements arranged and interconnected to form a power distribution network (PDN), logic cell, memory cell, etc. Components of circuitry 104 may be formed in and / or on the semiconductor substrate of die 102. Different embodiments may use different types of transistors, such as field-effect transistors (FETs), planar FETs, finFETs, gate-all-around FETs, or a mixture of transistor types. In some embodiments, front-end process (FEOL) processes may be used to fabricate integrated circuit 104 in and / or on the semiconductor substrate to form each die in die 102.

[0028] The circuit 104 of each die 102 is electrically connected to a set of contacts of the die 102. Figure 1 The contacts of die 102A include contacts 162A (e.g., conductive pillars with microbumps) configured to be electrically connected to contacts 162B of die 102B, and also include contacts configured to pass through substrate 106 via substrate 106 (e.g., Figure 1 The ball grid array (BGA) 160 in the package is coupled to contacts 164A (e.g., conductive pads) of an external device. Similarly, the contacts of die 102B include contacts 162B configured to be electrically connected to contacts 162A of die 102A, and also include contacts 164B configured to be coupled to external devices via contacts of BGA 160 through substrate 106. In a particular aspect, as further described below, die-to-die connections, such as signal paths between contacts 162A and 162B, are routed through embedded interconnect structures within die-to-die interconnect regions 130 of substrate 106.

[0029] The substrate 106 includes a set of stacked layers, comprising metal layers and dielectric layers. Adjacent metal layers are separated from each other by one or more dielectric layers and are patterned to define metal lines. The metal lines are interconnected via conductive vias and conductive pillars to define conductive paths through the substrate 106. Figure 1 In the illustrative and non-limiting specific example illustrated, substrate 106 includes a set of metal layers including metal layer 110 (e.g., M1 layer), metal layer 112 (e.g., M2 layer), metal layer 114 (e.g., M3 layer), metal layer 116 (e.g., M4 layer), metal layer 118 (e.g., M5 layer), metal layer 120 (e.g., M6 layer), metal layer 122 (e.g., M7 layer), metal layer 124 (e.g., M8 layer), metal layer 126 (e.g., M9 layer), metal layer 128 (e.g., M10 layer), and core 140. Figure 1In this configuration, adjacent metal layers are separated from each other by dielectric layers (such as dielectric layer 132 between metal layers 110 and 112, dielectric layer 134 between metal layers 112 and 114, dielectric layer 136 between metal layers 114 and 116, and dielectric layer 138 between metal layers 116 and 118) and are electrically connected by one or more conductive vias (such as conductive via 142) and / or by one or more conductive posts (such as conductive post 168).

[0030] Figure 1 An example is also shown on the first side of the substrate 106 (e.g., Figure 1 A solder mask 108 is exemplified on the top side of the substrate 106 (in the orientation shown), defining an opening through which contacts 150 (e.g., contacts 150A and 150B) and conductive posts 152 (e.g., conductive posts 152A and 152B) extend. Similarly, on the second side of the substrate 106 (e.g., the top side of the substrate 106), a solder mask layer 108 is exemplified, defining an opening through which contacts 150 (e.g., contacts 150A and 150B) and conductive posts 152 (e.g., conductive posts 152A and 152B) extend. Figure 1 The solder mask layer on the bottom side of the oriented section (illustrated in the diagram) defines an opening in the metal layer 128 through which the solder balls of the BGA 160 are coupled to the substrate 106.

[0031] The first set of conductors forms a conductive path between contacts 162. The first set of conductors includes a first set of metal wires and conductive posts within the die-to-die interconnect region 130. For example, in... Figure 1 In the first set of conductors, within the die-to-die interconnect region 130, there are metal lines defined within metal layer 110, metal lines defined within metal layer 112, metal lines defined within metal layer 114, and conductive posts 168 between them. A second set of conductors, distinct from the first set and including a second set of metal lines in metal layers 110 through 128 and conductive vias (e.g., conductive via 142) between them, forms a conductive path between the BGA 160 and the contact 164 of the die 102.

[0032] A first set of metal wires and conductive posts 168 in the die-to-die interconnect region 130 are electrically connected to conductive posts 152, exemplified as a set of conductive posts 152A configured to be electrically connected to die 102A and a set of conductive posts 152B configured to be electrically connected to die 102B. The sets of conductive posts 152A and 152B extend from the surface of the substrate 106 and are respectively connected to contacts 162A and 162B of die 102A and die 102B. A set of conductive posts 168A interconnects the first set of metal wires to conductive posts 152A, and a set of conductive posts 168B interconnects the first set of metal wires to conductive posts 152B to interconnect die 102A to die 102B.

[0033] Figure 190 illustrates a first non-limiting example of a portion of a first set of conductors in a die-to-die interconnect region 130. Conductive post 168A includes a conductive material 178 extending from a lower line 174 formed at a lower metal layer (metal layer 114) through a dielectric layer 134 to an upper line 176 formed at an upper metal layer (metal layer 112). Similarly, conductive material extends from line 176 through a dielectric layer 132 to a line 182 formed at a metal layer 110. Conductive post 152A is formed on line 182 and extends through a solder mask layer 108 to protrude from the upper surface of the substrate 106.

[0034] As illustrated in Figure 190, the interface 180A between line 176 and conductive material 178 is located below the upper surface 184 of dielectric layer 134. For example, during the formation of substrate 106, processes including soft etching cause the top of conductive material 178 to be recessed below the upper surface 184 of dielectric layer 134. When line 176 is formed, metal applied to the upper surface 184 extends into the recess to contact the conductive material and form interface 180A. A similar process is performed during the formation of line 182, and reference is made to… Figures 3A to 3D The manufacturing process is described in further detail.

[0035] Figure 192 depicts an alternative example in which a portion of the conductive material 178 extends over the upper surface 184 of the dielectric layer 134 to form an interface 180B with the upper line 176. In this example, the dielectric layer 134 may be the lower layer of a double dielectric laminate applied over the conductive material 178. The upper layer of the double dielectric laminate is removed, thereby exposing the upper surface 184 and the upper end of the conductive material 178 protruding from the upper surface 184. When the upper line 176 is formed, metal applied to the upper surface 184 forms around the protruding portion of the conductive material 178 and forms the interface 180B. A similar process is performed during the formation of the line 182, and reference is made to... Figures 4A to 4C The manufacturing process is described in further detail.

[0036] In Figures 190 and 192, metal line processing techniques such as photolithography and etching are used to achieve higher accuracy in smaller size and spacing dimensions compared to conventional substrate pad and via processing (such as conventional laser drilling to form via openings through the dielectric layer), forming lines 182, 176 and 174 in metal layers 110, 112 and 114, respectively.

[0037] although Figure 1Not illustrated, but one or more of lines 182, 176 or 174 pass through one or more of the first set of metal wires and, in some cases, are connected to the set of conductive posts 168B via one or more conductive posts to provide a signal propagation path between the contacts 162A of die 102A and the contacts 162B of die 102B.

[0038] In addition to conductive posts 152 and 168 connected to the first metal line in the die-to-die interconnect region 130, the substrate 106 also includes a set of pads 154A configured to be electrically connected to the die 102 and a set of pads 154B configured to be electrically coupled to the die 102B. As illustrated, electrical contacts 150A (such as solder balls) electrically connect pads 154A and corresponding contacts 164A of the die 102A. Similarly, electrical contacts 150B electrically connect pads 154B and corresponding contacts 164B of the die 102B.

[0039] A second set of conductors, including a second set of metal lines and conductive vias 142, forms a conductive path between the contacts 164 of die 102 and BGA 160. For example, the conductive vias 142A interconnect the second set of metal lines to the pads 154A, and the conductive vias 142B interconnect the second set of metal lines to the pads 154B.

[0040] The size and arrangement of the second set of conductors are designed to provide external package connectivity, such as conductive paths for power, ground, and external input / output (I / O), while the size and arrangement of the first set of conductors in the die-to-die interconnect region 130 are designed to provide die-to-die connections. For example, using metal pillars (e.g., copper pillars) for conductive pillars 152 and 168 allows for a reduction in bump pitch (e.g., the minimum spacing between conductive pillars 152) in the die-to-die interconnect region 130 compared to using conventional layer-to-layer via connections; for example, the bump pitch of conductive pillar 152 is smaller than the bump pitch of pad 154. Therefore, the substrate 106 provides a higher contact density in the die-to-die interconnect region 130.

[0041] Additionally, the first set of metal lines and posts 168 in the die-to-die interconnect region 130 has first characteristic dimensions (e.g., line width and line spacing, post width and post spacing), which are selected to provide a large number of signal paths, particularly in small regions, and the second set of metal lines and vias 142 has second characteristic dimensions (e.g., line width and line spacing, via width and via spacing, via pad width and via pad spacing), which are selected to provide target current carrying capacity and enable the use of standard manufacturing techniques. In certain aspects, one or more of the first characteristic dimensions are smaller than their corresponding second characteristic dimensions in the second characteristic dimensions. For example, a line having a vertical connection to a post within the die-to-die interconnect region 130 has a smaller horizontal dimension than the via pad for the via 142, which results in a larger number of metal lines (“escape lines”) routed between adjacent conductive posts 152 and adjacent posts 168 for a similar pitch compared to metal lines that can be routed between adjacent pads 154 and adjacent vias 142, as referenced. Figure 2 Further description.

[0042] One technical advantage of using conductive pillars 152 and 168 is that the smaller horizontal dimensions allow for a greater number of signal paths to be laid between dies 102, with little or no increase in the size of the substrate 106. The higher space density of the conductive pillars 152 reduces the surface area occupied by die-to-die contacts on the substrate 106 and also allows for shorter signal paths between contacts 162A and 162B compared to conventional pad and via structures. Increasing the number of signal paths between dies 102 and shortening their length generally improves the performance of device 100. Furthermore, the smaller dimensions of the conductive pillars 152, 168, and associated lines enable a larger number of escape lines in the die-to-die interconnect region 130, allowing interconnection of dies 102 using a smaller number of layers and thus reducing the overall size of device 100 relative to conventional devices.

[0043] although Figure 1 A single die-to-die interconnect region 130 is illustrated, but in other examples, device 100 includes more than one die-to-die interconnect region 130. For illustration, a third die (or another device) may be coupled to substrate 106 and interconnected with any or both of the dies 102 via another die-to-die interconnect region having a conductive pillar structure similar to that described for the die-to-die interconnect region 130.

[0044] Although region 130 is referred to herein as die-to-die interconnect region 130, in other examples, the conductive posts 152, 168 of region 130 are used to interconnect other types of devices, such as connecting a die to a passive device or connecting two passive devices. Furthermore, although die-to-die interconnect region 130 is... Figure 1 The example is illustrated as including two dielectric layers 132, 134 between three metal layers 110, 112, and 114; however, in other examples, the die-to-die interconnect region 130 includes more than three or fewer metal layers. Similarly, although the substrate 106 is... Figure 1 The substrate 106 is illustrated as having ten metal layers 110, 112, 114, 116, 118, 120, 122, 124, 126 and 128, but in other examples, the substrate 106 includes more than ten or fewer metal layers.

[0045] In some implementations, device 100 may be integrated with one or more other devices to form an integrated package device. For example, substrate 106 may correspond to an upper or lower substrate of a stacked package device. For illustration, when substrate 106 corresponds to the lower substrate of a stacked package device, another substrate may be positioned above die 102 and electrically connected to metal layer 110 via an interposer conductor.

[0046] In some implementations, die 102 may correspond to a chiplet interconnected via die-to-die interconnect region 130. Alternatively, one of the dies in die 102 may be the bottom chiplet in a stacked chiplet arrangement. In such a stacked chiplet arrangement, another die (i.e., another chiplet) is stacked on top of and electrically connected to one of the dies. Using chiplets arranged and interconnected as a 3D stack can offer various benefits compared to providing the same functional circuitry in a single monolithic chip. For example, each chiplet is smaller than a monolithic die that includes all the same functional circuitry blocks. Since yield losses in IC manufacturing tend to increase with die size, using smaller dies can reduce yield losses in the IC manufacturing process (i.e., increase yield). Another benefit is that the chiplets can be manufactured in different locations and / or by different manufacturers, and in some cases, using different manufacturing technologies (e.g., different manufacturing technology nodes). As an example, one die 102 of a chiplet-based integrated device may include components (e.g., interconnects, transistors, etc.) having a first minimum size, and another die of the chiplet-based integrated device may include components (e.g., interconnects, transistors, etc.) having a second minimum size, wherein the second minimum size is larger than the first minimum size. In contrast, all circuitry on a monolithic die is manufactured using the same manufacturing technology and equipment. Therefore, when manufacturing a monolithic die, the entire die may be subject to the most stringent manufacturing constraints of the most complex components of the die. In contrast, when using chiplets, different chiplets can be manufactured using different manufacturing technologies (e.g., different manufacturing technology nodes), and only one or more chiplets including the most complex components are subject to the most stringent manufacturing constraints. In this arrangement, chiplets manufactured using cheaper and / or higher yield manufacturing technologies can be integrated with chiplets manufactured using more expensive and / or lower yield manufacturing technologies to form an integrated device, resulting in overall savings. Furthermore, in some cases, as technology improves, the design of one or two chiplets can be changed, allowing the new chiplet design to be integrated with the older chiplet design. This increases manufacturing flexibility and reduces design costs.

[0047] In various embodiments, device 100 may include components such as power management integrated circuits (PMICs), application processors (including one or more processor cores), modems, radio frequency (RF) devices, passive devices, filters, capacitors, inductors, transmitters, receivers, gallium arsenide (GaAs) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memory (including multiple memory cells), power management processors, and / or combinations thereof. In such embodiments, die 102 may operate as any one of these components (or a combination of these components) that include active circuitry.

[0048] Figure 2 A cross-sectional profile view of contacts and vias that may be included in device 100 is illustrated.

[0049] Figure 202 illustrates pad 154X and adjacent pad 154Y of the group of contact pads 154. Each pad in pads 154X and 154Y has a horizontal dimension (pad width) D1, which can be designed to receive solder material within a corresponding opening in the solder mask layer 108. An escape line 216A is located between pads 154X and 154Y. Escape line 216A has a horizontal dimension (line width) D2 and is separated from each pad in pads 154X and 154Y by a horizontal dimension (pitch) D3. The resulting pad-to-pad pitch (e.g., bump pitch) D4 is determined by the following expression: D1 + D3 + D2 + D3.

[0050] In this exemplary, non-limiting example, the minimum pad width (D1) is 80 micrometers (µm), the minimum line width (D2) is 8 µm, and the minimum pitch dimension (D3) is 11 µm. In this example, the minimum bump pitch D4 is 110 µm. This minimum bump pitch may be too large to accommodate a sufficient number of die-to-die interconnects within a given die area, or multiple additional layers may be required to route signal paths between dies 102, due to the presence of only a single escape line 216A between pads 154X and 154Y.

[0051] Figure 204 illustrates conductive post 152X and adjacent conductive post 152Y in the group of conductive posts 152. Line 210X electrically connects conductive post 152X to post 168X in the group of posts 168, and line 210Y electrically connects conductive post 152Y to post 168Y in the group of posts 168. Each line in lines 210X and 210Y has a horizontal dimension (width) D5, and each of conductive posts 152X, 152Y, 168X, and 168Y has a horizontal dimension (D6). Multiple metal wires, illustrated as three escape lines 216B, 216C, and 216D, are positioned between conductive posts 152X and 152Y. Each escape line 216B, 216C, and 216D has a horizontal dimension (line width) D8 and is separated from adjacent structures by a horizontal dimension (spacing) D7. The resulting pitch D9 is determined to be: D5 + 3. D8+4 D7.

[0052] In the illustrative, non-limiting example, the minimum line width (D5) at the post connection is 20 μm, the minimum line width (D8) is 6 μm, and the minimum pitch dimension (D7) is 8 μm. In this example, the minimum pitch D9 is 70 μm. Therefore, compared to the first figure 202, the conductive posts illustrated in the second figure 204 provide a larger number of escape lines between adjacent posts with a smaller pitch. Compared to the conventional pad structure illustrated in the first figure 202, the larger number of escape lines 216 enables die-to-die interconnects using fewer layers (and therefore a smaller substrate 106).

[0053] Figure 206 illustrates a conductive via 142X extending from the upper via pad 220A through the dielectric layer 134 to the lower via pad 220B. The via 142X has a tapered profile created by laser drilling an opening in the dielectric layer 134 to the lower via pad 220B. The via 142X has a horizontal dimension (maximum width) D10, and each of the via pads 220A and 220B has a horizontal dimension (width) D11. The trace 222 has a horizontal dimension (line width) D12 and is separated from the lower via pad 220B by a horizontal dimension (spacing) D13.

[0054] In this exemplary, non-limiting example, the minimum maximum via width (D10) is 60µm, the minimum pad width (D10) is 90µm, the minimum line width (D12) is 8µm, and the minimum pitch dimension (D13) is 16µm. Therefore, in this example, the minimum via-to-via pitch is 130µm.

[0055] The minimum maximum via width D10 (e.g., 60µm) and the minimum pad width D11 (e.g., 90µm) may be limited by laser capability and registration criteria. In contrast, the pillar structure of the second figure 204 can be formed with much higher accuracy, such as 5µm accuracy, which allows lines with a width of 20µm to be used for pillars with a width of 10µm.

[0056] Figure 208 in the fourth illustration illustrates another example of an uninterrupted escape line from adjacent conductive posts 152X, 152Y, lines 210X, 210Y, and posts 168X, 168Y in Figure 204. Lines 210X and 210Y are separated by a horizontal dimension (spacing) D14. The resulting pitch D15 is determined to be: D5 + D14.

[0057] In the illustrative, non-limiting example, the minimum line width (D5) is 20 μm, and the minimum pitch dimension (D14) is 20 μm. In this example, the minimum pitch D14 is 40 μm, which achieves a higher interconnect density compared to the conventional laser-drilled via structure illustrated in Figure 206. Therefore, in the example described with reference to Figures 202 to 208, the minimum spacing between the posts in the conductive posts 152 is smaller than the minimum spacing between the pads in the group of pads 154, and the minimum spacing between the posts in the group of posts 168 is smaller than the minimum spacing between the vias in the group of vias 142.

[0058] Furthermore, in the examples described with reference to Figures 202 to 208, pad 154 has a first characteristic dimension (e.g., width, pitch) and conductive post 152 has a second characteristic dimension (e.g., width, pitch), wherein the first characteristic dimension of pad 154 is larger than the second characteristic dimension of conductive post 152. In a particular example, the pitch of pad 154 is greater than 90 μm (e.g., 110 μm in the first figure 202 with one escape line, or 101 μm without an escape line), and the pitch of conductive post 152 is less than 80 μm (e.g., 70 μm with three escape lines, or 40 μm without an escape line). Similarly, the set of conductive posts 168 has a first characteristic horizontal dimension (e.g., width, pitch), and the set of conductive vias 142 has a second characteristic horizontal dimension (e.g., maximum width, pitch), wherein the first characteristic horizontal dimension of the set of conductive posts 168 is smaller than the second characteristic horizontal dimension of the set of conductive vias 142.

[0059] Exemplary steps for manufacturing a device including conductive pillar structures for die interconnection In some specific implementations, manufacturing devices that include conductive pillar structures involves several processes. Figure 3A , Figure 3B , Figure 3C and Figure 3D Examples are provided or manufactured as per the reference. Figure 1 or Figure 2 The description includes exemplary processes for devices comprising conductive pillar structures for die interconnects. In some specific embodiments, Figures 3A to 3D The process can be used to provide Figure 1 Device 100 (e.g., during the manufacture of the device).

[0060] It should be noted that Figures 3A to 3D The processes can be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture integrated devices. In some embodiments, the order of processes may be changed or modified. In some embodiments, one or more processes may be substituted or replaced without departing from the scope of this disclosure. In the following description, reference is made to various exemplary stages of the processes, which are... Figures 3A to 3D Numbering (using circled numbers).

[0061] Figure 3A Stage 1 illustrates the state after a set of metal layers 300 on the substrate has been formed. Figures 3A to 3D (relative to) Figure 1 A simplified set of metal layers 300 is illustrated, including metal layer 302, metal layer 304, and metal layer 306. A dielectric layer 308 is located between metal layers 302 and 304, and a dielectric layer 310 is located between metal layers 304 and 306. Metal layers 302, 304, and 306 are patterned to form conductive lines, such as metal line 312 in metal layer 302 and metal line 314 in metal layer 306. Additionally, metal layer 302 is patterned to form lines 320, such as patterns for copper pillar connections for copper pillar placement, such as... Figure 1 Line 174. Conductive vias interconnect the various metal lines in the metal lines. For example, a conductive via 316 passing through dielectric layer 310 electrically connects the metal lines of metal layer 306 to the metal lines of metal layer 304. Conductive via 316 may correspond to Figure 1 Conductive via 142.

[0062] The group of metal layers 300 can be formed using a lamination process. For example, one or more of metal layers 302, 304, and 306 can be formed concurrently using a symmetrical lamination process. Alternatively, the group of metal layers 300 can be constructed on a carrier substrate (not shown) or a core of the substrate (e.g., Figure 1 On the core 140). For illustration, metal layers 302, 304, and 306 may respectively correspond to or include Figure 1 Metal layers 114, 116 and 118.

[0063] Metal layers 302, 304, and 306 can be patterned to define metal lines (e.g., metal lines 312, 314, and 320) using one or more subtractive processes (such as etching, engraving, or ablation of the material of the metal layers), one or more additive processes (such as printing or deposition), or a combination of additive and subtractive processes. Additive or subtractive processes can use patterned mask layers (such as patterned dry films) to guide the patterning of metal layers 302, 304, and 306 to define metal lines. Each dielectric layer 308, 310 can correspond to a polymer layer or prepreg layer that is cured to form the respective dielectric layer 308, 310. Conductive vias can be formed using drilling operations (e.g., laser drilling) to form openings, which are then filled or coated with a conductive material (e.g., using plating or deposition processes) to form conductive vias. In some embodiments, plating or deposition guided by a mask layer can be used to concurrently form metal layers and fill openings to form conductive vias.

[0064] Figure 3A The set of specific metal layers 300 illustrated is merely an example. In other specific embodiments, stage 1 ends with a package substrate of any type or configuration that includes conductors (e.g., two or more metal layers and conductive vias therebetween) forming conductive paths between the two sides of the set of metal layers 300.

[0065] Phase 2 illustrates the state after the mask layer 322 is formed on the metal layer 302 and the dielectric layer 308. The mask layer 322 includes a dry film resist layer or another mask layer (e.g., a photoresist layer).

[0066] Stage 3 illustrates the state after the mask layer 322 has been patterned using a photolithography process to include an opening 324 comprising exposure lines 320 (e.g., a pattern for placing copper pillars). For example, exposure and development processes can be applied to the mask layer 322 to form the opening 324.

[0067] Stage 4 illustrates the state after the conductive post 326 has been formed in the opening 324. The conductive post 326 can be formed using a plating and / or deposition operation guided by the mask layer 322 to apply a conductive material (e.g., copper) within the opening 324 to contact the line 320. The conductive post 326 can correspond to Figure 1 Conductive post 168 of die-to-die interconnection region 130.

[0068] Figure 3BStage 5A illustrates the state after mask layer 322 has been removed and dielectric layer 328 encapsulating conductive pillars 326 has been formed on metal layer 302 and dielectric layer 308. Mask layer 322 removal can be performed using one or more peel, delamination, or ashing operations, or other operations suitable for separating mask layer 322 from adjacent structures such as conductive pillars 326, metal layer 302, and / or dielectric layer 308. Dielectric layer 328 can be formed using one or more lamination processes and can correspond to… Figure 1 The dielectric layer 134.

[0069] Phase 6A illustrates the state after the upper surface of the conductive via 326 has been exposed. The dielectric layer 308 can be mechanically thinned using a grinding operation to reach the upper surface of the conductive pillar 326, and a soft etching operation (e.g., a relatively slow, finely controlled etching process) can be performed to remove residues on the surface of the dielectric layer 308 and etch the conductive material of the conductive pillar 326 to expose the upper surface of the conductive material of the conductive pillar 326 in the recess 330 of the surface of the dielectric layer 328.

[0070] Phase 7A illustrates the state after the dielectric layer 328 is patterned to include openings 332 of via pads 334 in the exposed metal layer 302. The openings 332 can be formed using a drilling process such as laser drilling.

[0071] Stage 8A illustrates the state after a conductive via 340 has been formed in the opening 332 and a metal layer 336 has been patterned to form a metal line including a line 338 (e.g., a copper pillar connection) on the pillar 326 and a via pad 342 has been formed on the via 340. The via 340, metal layer 336, or both can be formed using a semi-additive process or other processes and may include performing a mask-guided plating operation and / or deposition operation to apply a conductive material (e.g., copper), followed by one or more stripping, delamination, or ashing operations to remove the mask layer. The conductive material of the line 338 extends within the recess 330 to electrically connect with the conductive material of the pillar 326, such that the interface between the line 338 and the conductive material of the pillar 326 is below the upper surface of the dielectric layer 328, as shown in the reference. Figure 1 As depicted in Figure 190. According to one aspect, metal layer 336 corresponds to... Figure 1 The metal layer 112, line 338 corresponds to the upper line 176 illustrated in Figure 190, and via 340 corresponds to via 142.

[0072] Stages 2 through 8A can be repeated to add one or more additional layers.

[0073] Figure 3CPhase 9A illustrates the state after repeating phases 2 to 8A to add dielectric layer 344 and metal layer 346 and after forming mask layer 348. Although phase 9A illustrates the state after a single cycle of repeating phases 2 to 8A, in other embodiments, multiple cycles of repeating phases 2 to 8A may be performed to add additional layers.

[0074] A dielectric layer 344 is formed on the dielectric layer 328 and the metal layer 336. The dielectric layer 344 includes a conductive via 350 electrically connected to a via pad 342 and a conductive post 354 electrically connected to a line 338. The metal layer 346 is formed on the dielectric layer 344 and is patterned to form pads 352 on the via 350 and lines 356 (e.g., copper post connections) on the posts 354. According to one aspect, the pads 352 correspond to pads 154, and the lines 356 correspond to... Figure 1 Line 182 is illustrated in diagram 190.

[0075] A mask layer 348 may be formed on a metal layer 346 and a dielectric layer 344. The mask layer 348 includes a dry film resist layer or another mask layer (e.g., a photoresist layer). The mask layer 348 is patterned to include openings 358 for exposure lines 356. For example, exposure and development processes may be applied to the mask layer 348 to form the openings 358.

[0076] Stage 10A illustrates the state after the conductive post 360 has been formed in the opening 358. The conductive post 360 can be formed using a plating operation and / or deposition operation guided by the mask layer 348 to apply a conductive material (e.g., copper) within the opening 358 to contact the line 356. According to one aspect, the conductive post 360 corresponds to Figure 1 Conductive post 152.

[0077] Phase 11A illustrates the state after the removal of mask layer 348. The removal of mask layer 348 can be performed using one or more peeling, delamination or ashing operations, or other operations suitable for separating mask layer 348 from adjacent structures such as conductive pillars 360, metal layer 346 and / or dielectric layer 344.

[0078] Figure 3D Stage 12A illustrates the state after the formation of solder resist layer 370, which at least partially covers the conductive pillar 360 and covers the metal layer 346 and the dielectric layer 344. Solder resist layer 370 can be formed using one or more lamination processes or one or more liquid or gel application processes (e.g., spraying, roller coating, dip coating or other coating operations).

[0079] Stage 13A illustrates the state after the solder mask 370 has been thinned to expose the top portion of the conductive pillar 360 and after the opening 376 has been formed to expose the pad 352. The solder mask 370 can be thinned using a chemical down etching process that retains the top portion of the conductive pillar 360. The opening 376 can be formed using a drilling process such as laser drilling.

[0080] Phase 14A illustrates the state after die 380 (including die 380A and die 380B) has been attached to electrical contacts 378 and conductive posts 360 to form device 390. In a particular embodiment, die 380 includes contact pads coupled to electrical contacts 378, and electrical contacts 378 include solder bumps in openings 376 that are heated to reflow solder to electrically connect the contact pads of die 380 to pads 352. In a particular embodiment, die 380 includes conductive posts 374 and solder bumps 372, such as microbumps, at the ends of conductive posts 374. The solder bumps are heated to reflow solder to electrically connect conductive posts 374 to conductive posts 360.

[0081] Electrically connecting die 380 to pad 352 provides a conductive path between die 380 and the outer package contact. For example, electrically connecting die 380A to contact 378A provides a conductive path 388A from die 380A to the outer package contact, and electrically connecting die 380B to contact 378B provides a conductive path 388B from die 380B to the outer package contact. Electrically connecting die 380 to conductive post 360 provides a conductive path between dies 380. For example, electrically connecting die 380A and die 380B to conductive post 360 via die-to-die interconnect structures (such as...) Figure 1 The conductive pillar structure of the die-to-die interconnect region 130 provides a conductive path 386 between dies 380.

[0082] Figure 4A , Figure 4B and Figure 4C Examples are provided or manufactured as per the reference. Figure 1 Another exemplary process stage of the device including the conductive pillar structure is described. Figures 4A to 4C The process includes stages 5B to 14B, as Figures 3B to 3D An alternative to phases 5A to 14A, and can be used to provide Figure 1 Device 100 (e.g., during its manufacture).

[0083] Process from Figure 4A Phase 5B (in its Figure 3B(After stage 4) Stage 5A illustrates the state after mask layer 322 has been removed and the double dielectric layer encapsulating conductive pillar 326 has been formed on metal layer 302 and dielectric layer 308. Mask layer 322 removal can be performed using one or more stripping, delamination, or ashing operations, or other operations suitable for separating mask layer 322 from adjacent structures such as conductive pillar 326, metal layer 302, and / or dielectric layer 308.

[0084] The double-layer dielectric includes a dielectric layer 428 and a "buttercoat" layer 429 on the dielectric layer 428 (e.g., a resin layer, such as an epoxy resin layer). The double-layer dielectric can be formed using one or more lamination processes, and the dielectric layer 428 can correspond to... Figure 1 The dielectric layer 134.

[0085] Phase 6B illustrates the state after the thin coating 429 has been removed to expose the upper surface of the conductive pillar 326. The upper portion of the conductive material of the thin coating 429, which extends above the upper surface of the dielectric layer 428, can be removed by performing a desmearing process to expose the conductive pillar 326.

[0086] Phase 7B illustrates the state after the dielectric layer 428 is patterned to include openings 332 of via pads 334 in the exposed metal layer 302. The openings 332 can be formed using a drilling process such as laser drilling.

[0087] Phase 8B illustrates the state after conductive via 340 has been formed in opening 332 and metal layer 336 has been patterned to form metal lines including lines 438 (e.g., copper pillar connections) on pillar 326 and via pad 342 has been formed on via 340. Via 340, metal layer 336, or both can be formed using a semi-additive process or other processes, and may include performing a mask-guided plating operation and / or deposition operation to apply a conductive material (e.g., copper), followed by one or more stripping, delamination, or ashing operations to remove the mask layer.

[0088] The conductive material of line 438 encapsulates the exposed upper portion of the conductive material of pillar 326 protruding above the upper surface of dielectric layer 428, such that the interface between the conductive material of line 438 and pillar 326 is located above the upper surface of dielectric layer 328, as shown in the reference. Figure 1 As depicted in Figure 192. According to one aspect, metal layer 336 corresponds to... Figure 1 The metal layer 112, line 438 corresponds to the upper line 176 illustrated in Figure 192, and via 340 corresponds to via 142.

[0089] The steps of stages 2, 3, 4, 5B, 6B, 7B and 8B (e.g., stages 2 to 8B) can be repeated to add one or more additional layers.

[0090] Figure 4B Phase 9B illustrates the state after repeating phases 2 to 8B to add dielectric layer 444 and metal layer 346 and after forming mask layer 348. Although phase 9B illustrates the state after a single cycle of repeating phases 2 to 8B, in other embodiments, multiple cycles of repeating phases 2 to 8B may be performed to add additional layers.

[0091] A dielectric layer 444 is formed on the dielectric layer 428 and the metal layer 336. The dielectric layer 444 includes a conductive via 350 electrically connected to a via pad 342 and a conductive post 354 electrically connected to a line 438. The metal layer 346 is formed on the dielectric layer 444 and patterned to form pads 352 on the via 350 and lines 456 (e.g., copper post connections) on the posts 354. According to one aspect, the pads 352 correspond to pad 154, and the lines 456 correspond to... Figure 1 Line 182 is illustrated in diagram 192.

[0092] Mask layer 348 may be formed on metal layer 346 and dielectric layer 444. Mask layer 348 includes a dry film resist layer or another mask layer (e.g., a photoresist layer). Mask layer 348 is patterned to include openings 358 of exposure lines 456. For example, exposure and development processes may be applied to mask layer 448 to form openings 358.

[0093] Phase 10B illustrates the state after the conductive post 360 has been formed in the opening 358. The conductive post 360 can be formed using a plating and / or deposition operation guided by the mask layer 348 to apply a conductive material (e.g., copper) within the opening 358 to contact the line 456. According to one aspect, the conductive post 360 corresponds to Figure 1 Conductive post 152.

[0094] Phase 11B illustrates the state after the removal of mask layer 348. The removal of mask layer 348 can be performed using one or more stripping, delamination, or ashing operations, or other operations suitable for separating mask layer 348 from adjacent structures such as conductive pillars 360, metal layer 346, and / or dielectric layer 444.

[0095] Figure 4C Phase 12B illustrates the state after the formation of solder resist layer 370, which at least partially covers the conductive pillar 360 and the metal layer 346 and dielectric layer 444. Solder resist layer 370 can be formed using one or more lamination processes or one or more liquid or gel application processes (e.g., spraying, roller coating, dip coating or other coating operations).

[0096] Phase 13B illustrates the state after the solder mask 370 has been thinned to expose the top portion of the conductive pillar 360 and after the opening 376 has been formed to expose the pad 352. The solder mask 370 can be thinned using a chemical down etching process that retains the top portion of the conductive pillar 360. The opening 376 can be formed using a drilling process such as laser drilling.

[0097] Phase 14B illustrates the state after die 380 (including die 380A and die 380B) is attached to electrical contact 378 and conductive post 360 to form device 390. In a particular embodiment, die 380 includes contact pads coupled to electrical contact 378, and electrical contact 378 includes solder bumps in opening 376 that are heated to reflow solder to electrically connect the contact pads of die 380 to pad 352. In a particular embodiment, die 380 includes conductive post 374 and solder bumps 372, such as microbumps, at the lower end of conductive post 374. The solder bumps are heated to reflow solder bump 372 to electrically connect conductive post 374 to conductive post 360.

[0098] Electrically connecting die 380 to pad 352 provides a conductive path between die 380 and the outer package contact. For example, electrically connecting die 380A to contact 378A provides a conductive path 388A from die 380A to the outer package contact, and electrically connecting die 380B to contact 378B provides a conductive path 388B from die 380B to the outer package contact. Electrically connecting die 380 to conductive post 360 provides a conductive path between dies 380. For example, electrically connecting die 380A and die 380B to conductive post 360 via die-to-die interconnect structures (such as...) Figure 1 The conductive pillar structure of the die-to-die interconnect region 130 provides a conductive path 386 between dies 380.

[0099] An exemplary flowchart of a method for manufacturing a device including conductive pillar structures for die interconnects. In some specific implementations, manufacturing devices that include conductive pillars and via structures for die interconnection involves several processes. Figure 5 An exemplary flowchart illustrating a method 500 for providing or manufacturing a device including a conductive pillar structure is shown. In some specific embodiments, method 500 may be used to provide or manufacture Figure 1 Device 100 or Figure 3D or Figure 4C Any of the devices 390. It should be noted that... Figure 5 Method 500 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture integrated devices. In some specific implementations, the order of the processes may be changed or modified.

[0100] Method 500 includes forming, at block 502, a first metal line from a first group of metal lines and a second metal line from a second group of metal lines in a metal layer of a substrate. For example, the metal layer may correspond to... Figure 1 Metal layer 112. The first set of metal lines may correspond to the metal lines in the die-to-die interconnect region 130, and the second set of metal lines may correspond to the metal lines coupled to the via 142 providing a signal path to the BGA 160. Reference Figure 3A Phase 1 describes an example of the operations that can be used to form the first metal wire and the second metal wire.

[0101] Method 500 includes forming, at block 504, a second conductive pillar connected to a first metal line in a dielectric layer above a metal layer. For example, the second conductive pillar may correspond to a conductive pillar 168 formed in dielectric layer 132. Forming the second conductive pillar may include performing a photoresist process to form a first via (such as a reference via) in a photoresist layer above the metal layer. Figure 3A (as described in stage 3 of forming opening 324), and depositing the conductive material of the second conductive pillar into the first hole (as referenced). Figure 3A The formation of the conductive pillar 326 in stage 4 is described. Forming the second conductive pillar may further include removing the photoresist layer to expose the conductive material, and layering a piezoelectric layer (such as a reference layer) on top of the exposed conductive material. Figure 3B The formation of the dielectric layer 328 in stage 5A (as described), or the formation of a dielectric layer including Figure 4A The stage 5B has a double-layer dielectric layer 428 and a thin coating layer 429.

[0102] In some embodiments, forming the second conductive pillar includes performing soft etching to expose the upper surface of the conductive material in a recess on the upper surface of the dielectric layer, such as a reference. Figure 3B The formation of the recess 330 in stage 6A is described. In such embodiments, method 500 further includes forming a line on the upper surface of the conductive material, wherein the interface between the line and the conductive material is located below the upper surface of the dielectric layer. For example, the line may correspond to Figure 1 The upper line 176 is illustrated in Figure 190, and can be referenced as follows. Figure 3B It is formed as described in stage 8A.

[0103] In some embodiments, forming the second conductive pillar includes performing a desizing process to expose the upper portion of the conductive material by removing the epoxy resin layer from the dielectric layer, such as referenced... Figure 4AThe removal of the thin coating layer 429 in stage 5B is described. In such embodiments, method 500 further includes forming a line with an exposed upper portion encapsulating the conductive material, wherein the upper portion of the conductive material extends above the upper surface of the dielectric layer to form an interface with the line. For example, the line may correspond to Figure 1 The upper line 176 is illustrated in Figure 192, and can be referenced as follows. Figure 4A It is formed as described in stage 8B.

[0104] Method 500 includes forming a conductive via connected to a second metal line in a dielectric layer at block 506. For example, the conductive via may include or correspond to... Figure 1 The conductive via 142. According to one aspect, the second conductive post has a smaller horizontal dimension than the conductive via. Forming the conductive via may include forming the second hole in the dielectric layer using a laser drilling process, and depositing the conductive material of the conductive via into the second hole. (Reference) Figure 3B Phase 7A to 8A or Figure 4A Phases 7B to 8B describe examples of operations that can be used to form conductive vias.

[0105] Method 500 includes forming, at block 508, a pad connected to a conductive via and configured to be electrically connected to a first die. For example, the pad may include or correspond to... Figure 1 Pad 154. (Reference) Figure 3B Stage 8A or Figure 4A Phase 8B describes examples of operations that can be used to form pads.

[0106] Method 500 includes forming, at block 510, a first conductive post connected to a second conductive post and configured to be electrically connected to a first die, wherein the first conductive post extends from the surface of a substrate. For example, the first conductive post may correspond to Figure 1 Conductive post 152. Reference. Figure 4A Phases 9A to 11A or Figure 4B Phases 9B to 11B describe examples of operations that can be used to form the first conductive pillar.

[0107] In some implementations, the method further includes forming a solder mask layer on the dielectric layer and using a laser drilling process to form openings in the solder mask layer to expose the upper surface of the pads. A first conductive post protrudes above the upper surface of the solder mask layer. For example, the solder mask layer may correspond to... Figure 1 Solder mask layer 108. (Reference) Figure 3D Phases 12A and 13A or Figure 4C Phases 12B and 13B describe examples of operations that can be used to form solder mask layers and openings.

[0108] Exemplary electronic devices Figure 6 Examples include Figure 1 Device 100 or Figure 3D or Figure 4C Device 390 or various electronic devices integrated therewith. For example, mobile phone device 602, laptop computer device 604, fixed-location terminal device 606, wearable device 608, or vehicle 610 (e.g., automotive or aerospace equipment) may include device 600. Device 600 may include, for example... Figure 1 Device 100 Figure 3D or Figure 4C Device 390 or other devices described herein. Figure 6 The devices 602, 604, 606, and 608 illustrated herein, as well as vehicle 610, are merely exemplary. Other electronic devices may also feature device 600, including, but not limited to, the group comprising devices (e.g., electronic devices) such as: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0109] Figures 1 to 6 One or more of the components, processes, features, and / or functions illustrated herein may be rearranged and / or combined into a single component, process, feature, or function, or implemented in multiple components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that in this disclosure… Figures 1 to 6 The corresponding descriptions are not limited to dies and / or ICs. In some specific implementations, Figures 1 to 6 The corresponding descriptions can be used to manufacture, create, supply, and / or produce devices and / or integrated devices. In some specific implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0110] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0111] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. Object A coupled to object B may be coupled to at least a portion of object B. The term “electrical coupling” may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can flow between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The terms “enclosing,” “enclosing,” and / or any derivative meaning that an object can partially or completely enclose another object. The terms “top” and “bottom” are arbitrary. A component located at the top may be above a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component located “above” a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term “above” as used in this application in the context of one component being above another component can be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Therefore, for example, "the first component is on top of the second component" can mean: (1) the first component is on top of the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located in the second component. Values ​​from about X to XX can refer to values ​​between X and XX, including both X and XX. Values ​​between X and XX can be discrete or continuous. As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean within 10% of "value X".For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1. "Multiple" components can include all possible components or only some of all possible components. For example, if a device comprises ten components, the term "multiple components" can refer to all ten components or only some of the ten components.

[0112] In some embodiments, an interconnect is a component or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0113] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structure diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. A process terminates when its operations are completed.

[0114] Further examples are described below to facilitate understanding of this disclosure.

[0115] According to Embodiment 1, a device includes a substrate comprising: a set of metal layers separated from each other by a set of dielectric layers, the set of metal layers defining a first set of metal lines and a second set of metal lines; a first set of conductive pillars configured to be electrically connected to a first die; a second set of conductive pillars interconnecting the first set of metal lines to the first set of conductive pillars; a first set of pads configured to be electrically connected to the first die; and a first set of conductive vias interconnecting the second set of metal lines to the first set of pads; wherein the first set of conductive pillars extends from a surface of the substrate.

[0116] Example 2 includes the device according to Example 1, wherein the minimum distance between the pillars in the first group of conductive pillars is less than the minimum distance between the pads in the first group of pads.

[0117] Example 3 includes the device according to Example 1 or Example 2, and the device further includes: a second set of pads configured to be electrically coupled to a second die; a third set of conductive posts configured to be electrically connected to the second die; and a fourth set of conductive posts interconnecting the first set of metal lines to the third set of conductive posts to interconnect the first die to the second die.

[0118] Example 4 includes a device according to any one of Examples 1 to 3, wherein the first group of conductive pillars includes a first pillar and a second pillar adjacent to the first pillar, and wherein a plurality of metal wires in the first group of metal wires are located between the first pillar and the second pillar.

[0119] Example 5 includes a device according to any one of Examples 1 to 4, wherein the first pitch of the first set of pads is greater than 90 micrometers, and the second pitch of the first set of conductive pillars is less than 80 micrometers.

[0120] Example 6 includes a device according to any one of Examples 1 to 5, wherein the first set of pads has a first feature size and the first set of conductive pillars has a second feature size, and wherein the first feature size is larger than the second feature size.

[0121] Example 7 includes a device according to any one of Examples 1 to 6, wherein the second set of conductive pillars has a first characteristic horizontal dimension, and the first set of conductive vias has a second characteristic horizontal dimension, wherein the first characteristic horizontal dimension is smaller than the second characteristic horizontal dimension.

[0122] Example 8 includes a device according to any one of Examples 1 to 7, wherein the conductive pillar in the second set of conductive pillars includes a conductive material extending from a lower line formed on a lower metal layer to an upper line formed on an upper metal layer, wherein a dielectric layer is located between the lower metal layer and the upper metal layer, and wherein the interface between the upper line and the conductive material is located below the upper surface of the dielectric layer.

[0123] Example 9 includes a device according to any one of Examples 1 to 7, wherein the conductive pillar in the second set of conductive pillars includes conductive material extending from a lower line formed at a lower metal layer to an upper line formed at an upper metal layer, wherein a dielectric layer is located between the lower metal layer and the upper metal layer, and wherein a portion of the conductive material extends above the upper surface of the dielectric layer to form an interface with the upper line.

[0124] According to Embodiment 10, a device includes: a first die including a first circuit; a second die including a second circuit; and a substrate configured to electrically connect the first circuit to the second circuit and electrically connect the first circuit, the second circuit, or both to one or more off-package devices, the substrate including a set of metal layers separated from each other by a set of dielectric layers, the set of metal layers defining a first set of metal lines and a second set of metal lines; a first set of conductive pillars electrically connected to the first die; a first set of pads electrically connected to the first die; and a second set of conductive pillars that... The first set of metal lines interconnects to the first set of conductive pillars; the first set of conductive vias interconnects the second set of metal lines to the first set of pads; the third set of conductive pillars electrically connected to the second die; the second set of pads electrically connected to the second die; the fourth set of conductive pillars interconnects the first set of metal lines to the third set of conductive pillars to interconnect the first die to the second die; and the second set of conductive vias interconnects the second set of metal lines to the second set of pads; wherein the first set of conductive pillars and the third set of conductive pillars extend from the surface of the substrate.

[0125] Example 11 includes the device according to Example 10, wherein the first group of conductive pillars includes a first pillar and a second pillar adjacent to the first pillar, and wherein a plurality of metal wires in the first group of metal wires are located between the first pillar and the second pillar.

[0126] Example 12 includes the device according to Example 10 or Example 11, wherein the first set of pads has a first feature size and the first set of conductive pillars has a second feature size, and wherein the first feature size is larger than the second feature size.

[0127] Example 13 includes a device according to any one of Examples 10 to 12, wherein the second set of conductive pillars has a first characteristic horizontal dimension, and the first set of conductive vias has a second characteristic horizontal dimension, wherein the first characteristic horizontal dimension is smaller than the second characteristic horizontal dimension.

[0128] According to Embodiment 14, a method of manufacturing includes: forming a first metal line in a first group of metal lines and a second metal line in a second group of metal lines in a metal layer of a substrate; forming a second conductive post connected to the first metal line in a dielectric layer above the metal layer; forming a conductive via connected to the second metal line in the dielectric layer; forming a pad connected to the conductive via and configured to be electrically connected to a first die; and forming a first conductive post connected to the second conductive post and configured to be electrically connected to the first die, wherein the first conductive post extends from the surface of the substrate.

[0129] Example 15 includes the method according to Example 14, wherein forming the second conductive pillar includes: performing a photoresist process to form a first hole in a photoresist layer above the metal layer; depositing a conductive material of the second conductive pillar into the first hole; removing the photoresist layer to expose the conductive material; and laminating the dielectric layer on the exposed conductive material.

[0130] Example 16 includes the method according to Example 14 or Example 15, and the method further includes: mechanically thinning the dielectric layer and performing soft etching to expose the upper surface of the conductive material in a recess of the upper surface of the dielectric layer; and forming a line contacting the upper surface of the conductive material, wherein the interface between the line and the conductive material is located below the upper surface of the dielectric layer.

[0131] Example 17 includes the method according to Example 14 or Example 15, and the method further includes: performing a descaling process by removing an epoxy resin layer from the dielectric layer to expose an upper portion of the conductive material; and forming a line encapsulating the exposed upper portion of the conductive material, wherein the upper portion of the conductive material extends above the upper surface of the dielectric layer to form an interface with the line.

[0132] Example 18 includes the method according to any one of Examples 14 to 17, wherein forming the second conductive via includes: forming a second hole in the dielectric layer using a laser drilling process; and depositing a conductive material of the conductive via into the second hole.

[0133] Example 19 includes the method according to any one of Examples 14 to 18, wherein the second conductive post has a smaller horizontal dimension than the conductive via.

[0134] Example 20 includes the method according to any one of Examples 14 to 19, and the method further includes: forming a solder resist layer on the dielectric layer; and forming an opening in the solder resist layer using a laser drilling process to expose the upper surface of the pad, wherein the first conductive post protrudes above the upper surface of the solder resist layer.

[0135] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be illustrative and not to limit the scope of the appended claims. Therefore, the teachings herein are readily applicable to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A device, the device comprising: A substrate, the substrate comprising: A set of metal layers, the set of metal layers being separated from each other by a set of dielectric layers, the set of metal layers defining a first set of metal lines and a second set of metal lines; The first set of conductive posts is configured to be electrically connected to the first die; The second set of conductive posts interconnects the first set of metal wires to the first set of conductive posts; The first set of pads is configured to be electrically connected to the first die; and The first set of conductive vias interconnects the second set of metal lines to the first set of pads; The first set of conductive pillars extends from the surface of the substrate.

2. The device according to claim 1, wherein the minimum distance between the pillars in the first group of conductive pillars is less than the minimum distance between the pads in the first group of pads.

3. The device according to claim 1, further comprising: The second set of pads is configured to be electrically coupled to the second die; The third set of conductive posts is configured to be electrically connected to the second die; and A fourth set of conductive posts interconnects the first set of metal wires to the third set of conductive posts, thereby interconnecting the first die to the second die.

4. The device according to claim 1, wherein the first group of conductive posts includes a first post and a second post adjacent to the first post, and wherein a plurality of metal wires in the first group of metal wires are located between the first post and the second post.

5. The device according to claim 1, wherein the first pitch of the first set of pads is greater than 90 micrometers, and wherein the second pitch of the first set of conductive posts is less than 80 micrometers.

6. The device of claim 1, wherein the first set of pads has a first feature size, and the first set of conductive posts has a second feature size, and wherein the first feature size is larger than the second feature size.

7. The device according to claim 1, wherein the second group of conductive pillars has a first characteristic horizontal dimension, and the first group of conductive vias has a second characteristic horizontal dimension, wherein the first characteristic horizontal dimension is smaller than the second characteristic horizontal dimension.

8. The device of claim 1, wherein the conductive pillars in the second set of conductive pillars comprise conductive material extending from a lower line formed on the lower metal layer to an upper line formed on the upper metal layer, wherein a dielectric layer is located between the lower metal layer and the upper metal layer, and wherein the interface between the upper line and the conductive material is located below the upper surface of the dielectric layer.

9. The device of claim 1, wherein the conductive pillars in the second set of conductive pillars comprise conductive material extending from a lower line formed on a lower metal layer to an upper line formed on an upper metal layer, wherein a dielectric layer is located between the lower metal layer and the upper metal layer, and wherein a portion of the conductive material extends above the upper surface of the dielectric layer to form an interface with the upper line.

10. A device, the device comprising: The first die includes a first circuit. The second die includes a second circuit. and A substrate configured to electrically connect the first circuit to the second circuit and to electrically connect the first circuit, the second circuit, or both, to one or more external devices, the substrate comprising: A set of metal layers, the set of metal layers being separated from each other by a set of dielectric layers, the set of metal layers defining a first set of metal lines and a second set of metal lines; The first set of conductive pillars is electrically connected to the first die. The first set of pads is electrically connected to the first die; The second set of conductive posts interconnects the first set of metal wires to the first set of conductive posts; The first set of conductive vias interconnects the second set of metal lines to the first set of pads; The third set of conductive posts is electrically connected to the second die. The second set of pads is electrically connected to the second die. A fourth set of conductive posts interconnects the first set of metal wires to the third set of conductive posts, thereby interconnecting the first die to the second die; and The second set of conductive vias interconnects the second set of metal lines to the second set of pads; The first group of conductive pillars and the third group of conductive pillars extend from the surface of the substrate.

11. The device of claim 10, wherein the first group of conductive posts comprises a first post and a second post adjacent to the first post, and wherein a plurality of metal wires in the first group of metal wires are located between the first post and the second post.

12. The device of claim 10, wherein the first set of pads has a first feature size, and the first set of conductive posts has a second feature size, and wherein the first feature size is larger than the second feature size.

13. The device of claim 10, wherein the second set of conductive pillars has a first characteristic horizontal dimension, and the first set of conductive vias has a second characteristic horizontal dimension, and wherein the first characteristic horizontal dimension is smaller than the second characteristic horizontal dimension.

14. A method of manufacturing, the method comprising: A first metal line from a first group of metal lines and a second metal line from a second group of metal lines are formed in the metal layer of the substrate. A second conductive post connected to the first metal line is formed in a dielectric layer above the metal layer; A conductive via is formed in the dielectric layer to connect to the second metal line; A pad is formed that is connected to the conductive via and configured to be electrically connected to the first die; as well as A first conductive post is formed that is connected to the second conductive post and configured to be electrically connected to the first die. The first conductive post extends from the surface of the substrate.

15. The method of claim 14, wherein forming the second conductive pillar comprises: Perform a photoresist process to form a first hole in a photoresist layer above the metal layer; The conductive material of the second conductive post is deposited into the first hole; Remove the photoresist layer to expose the conductive material; as well as The dielectric layer is laminated on top of the exposed conductive material.

16. The method of claim 15, further comprising: The dielectric layer is mechanically thinned and soft etching is performed to expose the upper surface of the conductive material in the recesses of the upper surface of the dielectric layer; as well as A line is formed that contacts the upper surface of the conductive material. The interface between the line and the conductive material is located below the upper surface of the dielectric layer.

17. The method of claim 15, further comprising: A descaling process is performed by removing the epoxy resin layer from the dielectric layer to expose the upper portion of the conductive material. as well as Form lines that encapsulate the exposed upper portion of the conductive material. The upper portion of the conductive material extends above the upper surface of the dielectric layer to form an interface with the line.

18. The method of claim 15, wherein forming the conductive via comprises: A second hole is formed in the dielectric layer using a laser drilling process; as well as The conductive material of the conductive via is deposited into the second hole.

19. The method of claim 14, wherein the second conductive post has a horizontal dimension smaller than that of the conductive via.

20. The method of claim 14, further comprising: A solder resist layer is formed on the dielectric layer; as well as An opening is formed in the solder mask layer using a laser drilling process to expose the upper surface of the pads. The first conductive post protrudes above the upper surface of the solder resist layer.

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