Semiconductor wafer level packaging method and packaging structure

Abstract

The application discloses a semiconductor wafer-level packaging method and a packaging structure. In the semiconductor wafer-level packaging method, the ring-shaped protrusion is arranged, and the glue coating mode is used, so that the packaging bonding strength is maintained, the air tightness and reliability of the packaging structure are improved, and the bonding glue can prevent the functional area from being affected.

Description

Semiconductor wafer level packaging method and packaging structure

[0001] This application claims priority to the application with the filing date of August 21, 2024, in the China Patent Office, the application number of 202411151003.5, and the invention title of "Semiconductor wafer level packaging method and packaging structure", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the chip bonding packaging technical field, in particular to a semiconductor wafer level packaging method and packaging structure. BACKGROUND

[0003] For chip packaging with functional areas, a substrate is usually bonded with a chip to protect the functional areas of the chip. In the prior art, the chip and the substrate are bonded with polymer-glue, which is the most cost-effective.

[0004] There are several ways to apply glue:

[0005] The first is screen printing. Place the side of the substrate that needs to be glued face up, set a windowed screen on this side, the window (i.e. the glueing place) is set on the part of the substrate that needs to be bonded, use a scraper to scrape the glue on the screen onto the substrate, the glue is squeezed onto the bonding part of the substrate through the windowed part of the screen during this process, and the gluing is completed.

[0006] The second is roll gluing. Place the side of the substrate that needs to be glued face up, roll the glue-covered roller on the surface of the substrate, and the surface of the part of the substrate that needs to be bonded will be covered with glue.

[0007] However, whether it is screen printing or roll gluing, when the two sides of the substrate are flat or the height difference between the groove area used to form the cavity and the bonding part is small, and the substrate part of the cavity area (the area where the chip functional area is located) has certain functions (such as glass substrate, which needs to be transparent) or is provided with some functional structures (such as micro-mechanical structures), if screen printing is used, the screen will be deformed when it is pressed during the gluing process, and some glue will flow along the back of the screen when it flows down the window. In the case of no relative height or low relative height, the screen will come into contact with the cavity area and be covered with glue. If roll gluing is used, because the thickness of the glue on the roller is relatively thick (about 10 μm), and the roller brush surface is circular, there is a slight arc when it comes into contact with the substrate. In the case of no relative height or low relative height, the movement of the roller will make the cavity area easily covered with glue.

[0008] Therefore, neither of the above two gluing methods is suitable, and there is a high probability that the glue will be applied to the functional area, affecting the performance of the packaged device.

[0009] The information disclosed in this Background section is only for the purpose of increasing an understanding of the general context of the present application and does not therefore constitute SUMMARY

[0010] The present application aims to provide a semiconductor wafer level packaging method and packaging structure which can solve the problems in the prior art.

[0011] To achieve the above object, a specific embodiment of the present application provides a technical solution as follows:

[0012] A semiconductor wafer level packaging method, comprising:

[0013] providing a first wafer with a plurality of chip units, each of the chip units having a functional area and a first bonding area arranged around the functional area;

[0014] providing a second wafer or substrate with a second bonding area corresponding to the first bonding area;

[0015] forming a first annular protrusion on the first bonding area of the chip units, the first annular protrusions between adjacent chip units having a first spacing area, and / or forming at least one first annular protrusion on the second bonding area of the second wafer or substrate, the first annular protrusions between adjacent second bonding areas having a second spacing area;

[0016] filling glue in the first spacing area and / or the second spacing area, the glue protruding from the top surface of the first annular protrusion;

[0017] aligning and pressing the second wafer or substrate and the first wafer.

[0018] In one or more embodiments of the present application, the amount of glue is controlled so that, after alignment and pressing, the glue protruding from the top surface of the first annular protrusion is partially or entirely extruded to the side of the first annular protrusion away from the first spacing area and / or the second spacing area.

[0019] In one or more embodiments of the present application, the glue extruded to the side of the first annular protrusion away from the first spacing area and / or the second spacing area is in contact with at least one of the first wafer and the second wafer or substrate.

[0020] In one or more embodiments of the present application, the glue extruded to the side of the first annular protrusion away from the first spacing area and / or the second spacing area is in contact with both the first wafer and the second wafer or substrate.

[0021] In one or more embodiments of the present application, before aligning and pressing the second wafer or substrate with the first wafer, further comprising:

[0022] forming a second ring-shaped bump on the first bonding region of the chip unit and / or on the second bonding region of the second wafer or substrate.

[0023] In one or more embodiments of the present application, the inner diameter of the second ring-shaped bump is smaller than the inner diameter of any of the first ring-shaped bumps on the first bonding region or the second bonding region to which the second ring-shaped bump belongs.

[0024] A third spacing region is formed between the second ring-shaped bump and the first ring-shaped bump adjacent to the second ring-shaped bump.

[0025] In one or more embodiments of the present application, the amount of glue is controlled so that, after aligning and pressing, the glue protruding from the top surface of the first ring-shaped bump is only partially or completely extruded into the third spacing region.

[0026] In one or more embodiments of the present application, a first cutting region is formed between adjacent chip units, and the first cutting region is located in the first spacing region.

[0027] The second wafer or substrate has a second cutting region corresponding to the first cutting region, and the second cutting region is located in the second spacing region.

[0028] In one or more embodiments of the present application, the polymer includes glue.

[0029] In one or more embodiments of the present application, a connection portion is provided between two adjacent rings of the first ring-shaped bump, and the connection portion is located inside the first bonding region or the second bonding region to which the first ring-shaped bump belongs, and is electrically connected to the two adjacent rings of the first ring-shaped bump.

[0030] In one or more embodiments of the present application, the inner diameter of the first ring-shaped bump formed on the first bonding region is different from the inner diameter of the first ring-shaped bump formed on the second bonding region.

[0031] A semiconductor wafer-level packaging method, comprising:

[0032] providing a first wafer having one or more chip units, each of the chip units having a functional region and a first bonding region arranged around the functional region;

[0033] providing a second wafer or substrate having a second bonding region corresponding to the first bonding region;

[0034] forming at least two circles of first annular protrusions on the first bonding region of the chip unit, and / or forming at least two circles of first annular protrusions on the second bonding region of the second wafer or substrate, and forming fourth spacing regions between adjacent first annular protrusions;

[0035] filling glue in the fourth spacing regions, the glue protruding the top surface of the first annular protrusions;

[0036] aligning and pressing the second wafer or substrate with the first wafer.

[0037] In one or more embodiments of the present application, the amount of glue filled is controlled so that after aligning and pressing, the glue protruding the top surface of the first annular protrusions is partially or completely squeezed to the side of the first annular protrusions away from the fourth spacing regions.

[0038] In one or more embodiments of the present application, the amount of glue filled is controlled so that after aligning and pressing, the glue protruding the top surface of the first annular protrusions is partially squeezed to the space between the top surface of the first annular protrusions and the first bonding region or the second bonding region aligned therewith.

[0039] In one or more embodiments of the present application, when more than two circles of first annular protrusions are formed, the amount of glue filled in the fourth spacing region close to the functional region is less than or equal to the amount of glue filled in other fourth spacing regions.

[0040] In one or more embodiments of the present application, before aligning and pressing the second wafer or substrate with the first wafer, further comprising:

[0041] a step of arranging an annular cofferdam on the second bonding region of the second wafer or substrate and / or on the first bonding region of the first wafer;

[0042] In one or more embodiments of the present application, the inner diameter of the annular cofferdam is smaller than the inner diameter of any first annular protrusion on the first bonding region or the second bonding region to which the annular cofferdam belongs.

[0043] The annular cofferdam is arranged on the first bonding region or the second bonding region aligned with the top surface of the innermost circle of first annular protrusions.

[0044] In one or more embodiments of the present application, the polymer includes glue.

[0045] In one or more embodiments of the present application, there is a connecting portion between two adjacent circles of first annular protrusions, the connecting portion being arranged inside the first bonding region or the second bonding region to which the first annular protrusions belong and electrically connected with the two adjacent circles of first annular protrusions.

[0046] In one or more embodiments of the present application, the first annular protrusion formed on the first bonding region has a different inner diameter from the first annular protrusion formed on the second bonding region.

[0047] A semiconductor wafer level packaging method, comprising

[0048] providing a wafer having a plurality of chip units, each of the chip units comprising a functional region, at least one pad disposed within or around the functional region, and a first bonding region surrounding the functional region, the pad comprising an opening region;

[0049] providing a substrate comprising a cavity region, a second bonding region corresponding to the first bonding region, and a third bonding region corresponding to the pad, the cavity region corresponding to the functional region and capable of encompassing the functional region;

[0050] forming a first pad corresponding annular protrusion on the pad, the first pad corresponding annular protrusion surrounding the opening region, and / or forming a second pad corresponding annular protrusion on the third bonding region opposite to the pad, the second pad corresponding annular protrusion corresponding to the opening region;

[0051] filling a polymer capable of bonding within the first pad corresponding annular protrusion, the top surface of the polymer being higher than the top surface of the first pad corresponding annular protrusion, and / or filling a polymer capable of bonding within the second pad corresponding annular protrusion, the top surface of the polymer being higher than the top surface of the second pad corresponding annular protrusion;

[0052] aligning and pressing the substrate and the wafer together; and

[0053] providing a via hole corresponding to the opening region on at least one of the wafer and the substrate, so that the opening region is exposed to an environment outside the chip unit.

[0054] In one or more embodiments of the present application, the third bonding region forms an island structure outside the second bonding region.

[0055] In one or more embodiments of the present application, the third bonding region forms an island structure outside the second bonding region.

[0056] In one or more embodiments of the present application, the island structure is connected to the second bonding region by a bridge structure.

[0057] In one or more embodiments of the present application, a predetermined width of glue overflow region is left around the second bonding region and the third bonding region in the cavity region, and after aligning and pressing, the polymer can be squeezed into the glue overflow region.

[0058] In one or more embodiments of the present application, an excess glue area is provided between the adjacent chip units, and the polymer can be squeezed into the excess glue area after alignment and pressing.

[0059] In one or more embodiments of the present application, before the substrate and the wafer are aligned and pressed, the method further comprises:

[0060] The step of providing a substrate corresponding annular cofferdam on the substrate and / or on the third bonding area of the wafer, the inner diameter of the substrate corresponding annular cofferdam is greater than the outer diameter of the first pad corresponding annular protrusion and the outer diameter of the second pad corresponding annular protrusion.

[0061] A semiconductor wafer level packaging method, comprising

[0062] Providing a wafer with a plurality of chip units, each of the chip units comprising a functional area, at least one pad provided in or around the functional area, and a first bonding area surrounding the functional area, wherein the pad comprises an opening area;

[0063] Providing a substrate comprising a cavity area, a second bonding area and a third bonding area, wherein the second bonding area corresponds to the first bonding area, the third bonding area corresponds to the pad, and the cavity area corresponds to and can encompass the functional area;

[0064] Forming at least one circle of first annular protrusions on the first bonding area, with a first spacing area between the first annular protrusions of adjacent chip units, and / or forming at least one circle of first annular protrusions on the second bonding area, with a second spacing area between the first annular protrusions of adjacent second bonding areas;

[0065] Forming a first pad corresponding annular protrusion on the pad, which surrounds the opening area, and / or forming a second pad corresponding annular protrusion on the opposite third bonding area of the pad, which corresponds to the opening area;

[0066] Filling a polymer that plays a key role in the first spacing area and / or in the second spacing area, the top surface of the polymer being higher than the top surface of the first annular protrusion;

[0067] Filling a polymer that plays a key role in the first pad corresponding annular protrusion, the top surface of the polymer being higher than the top surface of the first pad corresponding annular protrusion, and / or filling a polymer that plays a key role in the second pad corresponding annular protrusion, the top surface of the polymer being higher than the top surface of the second pad corresponding annular protrusion;

[0068] Aligning and pressing the substrate and the wafer; and

[0069] forming a via hole on at least one of the wafer and the substrate corresponding to the opening region, so that the opening region is exposed to an environment outside the chip unit.

[0070] In one or more embodiments of the present application, at least one of the pads is electrically connected to the first annular bump on the first bonding region.

[0071] In one or more embodiments of the present application, at least one of the first pad corresponding annular bumps is connected to the first annular bump on the first bonding region.

[0072] In one or more embodiments of the present application, at least one of the second pad corresponding annular bumps is connected to the first annular bump on the second bonding region.

[0073] In one or more embodiments of the present application, the pad comprises a pad body and a protrusion surrounding the pad body, the opening region is disposed on the pad body, and the first pad corresponding annular bump is disposed on the protrusion and has the same height as the first annular bump on the first bonding region.

[0074] A semiconductor wafer level packaging method, comprising

[0075] providing a wafer having a plurality of chip units, each of the chip units comprising a functional region, at least one pad disposed within or around the functional region, and a first bonding region surrounding the functional region, wherein the pad comprises an opening region;

[0076] providing a substrate comprising a cavity region, a second bonding region, and a third bonding region, wherein the second bonding region corresponds to the first bonding region, the third bonding region corresponds to the pad, and the cavity region corresponds to and can encompass the functional region;

[0077] forming at least two circles of first annular bumps on the first bonding region of the chip unit, and / or forming at least two circles of first annular bumps on the second bonding region of the substrate, and forming a fourth spacing region between adjacent first annular bumps;

[0078] forming a first pad corresponding annular bump on the pad surrounding the opening region, and / or forming a second pad corresponding annular bump on the opposite third bonding region of the pad corresponding to the opening region;

[0079] filling a polymer having a keying function in the fourth spacing region, and the top surface of the polymer is higher than the top surface of the first annular bump;

[0080] filling a polymer in the first pad corresponding annular protrusion, a top surface of the polymer being higher than a top surface of the first pad corresponding annular protrusion, and / or filling a polymer in the second pad corresponding annular protrusion, a top surface of the polymer being higher than a top surface of the second pad corresponding annular protrusion;

[0081] aligning and pressing the substrate with the wafer; and

[0082] forming a through hole on at least one of the wafer and the substrate corresponding to the opening region, so that the opening region is exposed to an environment outside the chip unit.

[0083] In one or more embodiments of the present application, at least one of the pads is electrically connected with the first annular protrusion on the first bonding region.

[0084] In one or more embodiments of the present application, at least one of the first pad corresponding annular protrusions is connected with the first annular protrusion on the first bonding region.

[0085] In one or more embodiments of the present application, at least one of the second pad corresponding annular protrusions is connected with the first annular protrusion on the second bonding region.

[0086] In one or more embodiments of the present application, the pad comprises a pad body and a protruding portion surrounding the pad body, the opening region is disposed on the pad body, and the first pad corresponding annular protrusion is disposed on the protruding portion and has the same height as the first annular protrusion on the first bonding region.

[0087] In one or more embodiments of the present application, the method for forming the first annular protrusion comprises:

[0088] forming a layer structure;

[0089] forming a photoresist layer on the layer structure and patterning to form an annular protrusion pattern;

[0090] transferring the annular protrusion pattern to the layer structure to form the annular protrusion; or,

[0091] The method for forming the annular protrusion comprises:

[0092] forming a photoresist layer and patterning to form an annular recess pattern;

[0093] forming a layer structure covering the annular recess pattern;

[0094] removing the annular recess pattern while removing the layer structure on the surface of the annular recess pattern to form the annular protrusion.

[0095] In one or more embodiments of the present application, the glue is filled by dispensing or printing.

[0096] In one or more embodiments of the present application, the method of forming the first annular protrusion, the first pad corresponding annular protrusion and the second pad corresponding annular protrusion comprises:

[0097] forming a layer structure;

[0098] forming a photoresist layer on the layer structure and patterning to form an annular protrusion pattern;

[0099] transferring the annular protrusion pattern to the layer structure to form the annular protrusion; or,

[0100] the method of forming the annular protrusion comprises:

[0101] forming a photoresist layer and patterning to form an annular recess pattern;

[0102] forming a layer structure covering the annular recess pattern;

[0103] removing the annular recess pattern while removing the layer structure on the surface of the annular recess pattern to form the annular protrusion.

[0104] In one or more embodiments of the present application, the glue is filled by dispensing or printing.

[0105] A semiconductor package structure, comprising:

[0106] a first chip having a first surface, the first surface having a functional area and a first bonding area, the first bonding area being disposed around the functional area;

[0107] a second chip or substrate disposed on the first surface of the first chip, the second chip or substrate having a second bonding area bonded to the first bonding area;

[0108] a glue bonding layer disposed between the first bonding area and the second bonding area; and

[0109] a first annular protrusion disposed on the first bonding area and / or the second bonding area and partially or entirely located in the glue bonding layer.

[0110] In one or more embodiments of the present application, a second annular protrusion is further included, which is disposed on the first bonding region of the first chip and / or the second bonding region of the second chip or substrate, an inner diameter of the second annular protrusion is smaller than an inner diameter of any of the first annular protrusions on the first bonding region or the second bonding region to which the second annular protrusion belongs, a third spacing region is formed between the second annular protrusion and the first annular protrusion adjacent to the second annular protrusion, and the third spacing region is partially or entirely provided with the glue bonding layer.

[0111] In one or more embodiments of the present application, a height of the second annular protrusion is greater than or equal to a height of the first annular protrusion.

[0112] A semiconductor packaging structure includes:

[0113] A first chip has a first surface, the first surface has a functional region and a first bonding region, and the first bonding region is disposed around the functional region;

[0114] A second chip or a substrate is disposed on the first surface of the first chip, and the second chip or the substrate has a second bonding region bonded with the first bonding region;

[0115] At least two circles of first annular protrusions are disposed on the first bonding region of the first chip and / or on the second bonding region of the second chip or the substrate, a fourth spacing region is formed between adjacent first annular protrusions, and the fourth spacing region is provided with glue, the glue extends from the fourth spacing region to at least part of a space between a top surface of the first annular protrusion and the first bonding region or the second bonding region opposite to the top surface.

[0116] In one or more embodiments of the present application, an annular cofferdam is further included, which is disposed on the first bonding region or the second bonding region opposite to a top surface of the first annular protrusion closest to the functional region.

[0117] A semiconductor packaging structure includes

[0118] A wafer has a first surface and a second surface, the first surface of the wafer includes a functional region, at least one pad disposed in or around the functional region, and a first bonding region around the functional region, and the pad includes an opening region;

[0119] A substrate has a first surface and a second surface, the first surface of the substrate is disposed opposite to the first surface of the wafer, includes a cavity region, a second bonding region, and a third bonding region, the second bonding region corresponds to the first bonding region, the third bonding region corresponds to the pad, and the cavity region corresponds to the functional region and can encapsulate the functional region;

[0120] at least one of the first pad corresponding annular protrusion and the second pad corresponding annular protrusion, wherein the first pad corresponding annular protrusion is located on the pad and surrounds the opening region, the second pad corresponding annular protrusion is located on the third bonding region and corresponds to the opening region, and a polymer for bonding is arranged in the first pad corresponding annular protrusion and the second pad corresponding annular protrusion; and

[0121] a through hole arranged on the second surface of the wafer and / or the second surface of the substrate and corresponding to the opening region.

[0122] In one or more embodiments of the present application, the third bonding region forms a peninsula structure on the second bonding region.

[0123] In one or more embodiments of the present application, the third bonding region forms an island structure outside the second bonding region.

[0124] In one or more embodiments of the present application, the island structure is connected to the second bonding region through a bridge structure.

[0125] A semiconductor packaging structure, comprising

[0126] A wafer comprising a plurality of chip units, having a first surface and a second surface, the first surface of the wafer comprising a functional region, at least one pad arranged in or around the functional region, and a first bonding region surrounding the functional region, the pad comprising an opening region;

[0127] A substrate having a first surface and a second surface, the first surface of the substrate being oppositely arranged with the first surface of the wafer, comprising a cavity region, a second bonding region and a third bonding region, wherein the second bonding region corresponds to the first bonding region, the third bonding region corresponds to the pad, and the cavity region corresponds to and can encompass the functional region;

[0128] at least one first annular protrusion arranged on the first bonding region of the wafer and / or on the second bonding region of the substrate, a first spacing region being formed between the first annular protrusions on the first bonding regions of adjacent chip units, a second spacing region being formed between the first annular protrusions on the second bonding regions of adjacent chip units, and a polymer for bonding being arranged in at least one of the first spacing region and the second spacing region;

[0129] at least one of the first pad corresponding annular protrusion and the second pad corresponding annular protrusion, wherein the first pad corresponding annular protrusion is located on the pad and surrounds the opening area, the second pad corresponding annular protrusion is located on the third bonding area and corresponds to the opening area, and a polymer for bonding is arranged in the first pad corresponding annular protrusion and the second pad corresponding annular protrusion; and

[0130] a through hole arranged on the second surface of the wafer and / or the second surface of the substrate and corresponding to the opening area.

[0131] In one or more embodiments of the present application, at least one of the pads is electrically connected to the first annular protrusion on the first bonding area.

[0132] In one or more embodiments of the present application, at least one of the first pad corresponding annular protrusions is connected to the first annular protrusion on the first bonding area.

[0133] In one or more embodiments of the present application, at least one of the second pad corresponding annular protrusions is connected to the first annular protrusion on the second bonding area.

[0134] In one or more embodiments of the present application, the pad comprises a pad body and a protruding portion surrounding the pad body, the opening area is arranged on the pad body, and the pad corresponding annular protrusion is arranged on the protruding portion and has the same height as the first annular protrusion on the first bonding area.

[0135] A semiconductor packaging structure, comprising

[0136] A wafer comprising a plurality of chip units, having a first surface and a second surface, the first surface of the wafer comprising a functional area, at least one pad arranged in or around the functional area, and a first bonding area surrounding the functional area, the pad comprising an opening area;

[0137] A substrate having a first surface and a second surface, the first surface of the substrate being oppositely arranged with the first surface of the wafer, comprising a cavity area, a second bonding area and a third bonding area, wherein the second bonding area corresponds to the first bonding area, the third bonding area corresponds to the pad, and the cavity area corresponds to and can encompass the functional area;

[0138] At least two annular protrusions are arranged on the first bonding area of the wafer and / or on the second bonding area of the substrate, and a fourth spacing area is formed between adjacent first annular protrusions, and a polymer for bonding is arranged in the fourth spacing area.

[0139] At least one of the first pad corresponding annular protrusion and the second pad corresponding annular protrusion, wherein the first pad corresponding annular protrusion is located on the pad and surrounds the opening area, the second pad corresponding annular protrusion is located on the third bonding area and corresponds to the opening area, and a polymer for bonding is arranged in the first pad corresponding annular protrusion and the second pad corresponding annular protrusion; and

[0140] A through hole is arranged on the second surface of the wafer and / or the second surface of the substrate and corresponds to the opening area.

[0141] In one or more embodiments of the present application, at least one of the pads is electrically connected to the first annular protrusion on the first bonding area.

[0142] In one or more embodiments of the present application, at least one of the first pad corresponding annular protrusions is connected to the first annular protrusion on the first bonding area.

[0143] In one or more embodiments of the present application, at least one of the second pad corresponding annular protrusions is connected to the first annular protrusion on the second bonding area.

[0144] In one or more embodiments of the present application, the pad comprises a pad body and a protruding portion surrounding the pad body, the opening area is arranged on the pad body, and the pad corresponding annular protrusion is arranged on the protruding portion and has the same height as the first annular protrusion on the first bonding area.

[0145] Compared with the prior art, the semiconductor wafer level packaging method and packaging structure of the present application can prevent the glue applied during bonding from polluting the functional area, and at the same time, by controlling the amount of glue, the applied glue can be prevented from overflowing and affecting the functional area.

[0146] The semiconductor wafer level packaging method and packaging structure of the present application can maintain the bonding strength of the packaging structure while improving the air tightness and reliability of the packaging structure by arranging the annular protrusion and cooperating with the glue application mode, and can also prevent the bonding glue from affecting the functional area. BRIEF DESCRIPTION OF DRAWINGS

[0147] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0148] FIG. 1 is a process flow diagram of a semiconductor wafer level packaging method in a first embodiment of the present application;

[0149] Figures 2a-2d are schematic views of process steps of a semiconductor wafer level packaging method according to an embodiment of the present application;

[0150] Figure 3 is a schematic view of a portion of Figure 2d;

[0151] Figure 4 is a schematic view of a portion of a step corresponding to Figure 2d according to an embodiment of the present application;

[0152] Figure 5 is a schematic view of a portion of a step corresponding to Figure 2d according to an embodiment of the present application;

[0153] Figures 6a-6d are schematic views of process steps of a semiconductor wafer level packaging method according to an embodiment of the present application;

[0154] Figure 7 is a schematic view of a portion of Figure 6d;

[0155] Figure 8 is a schematic view of a portion of a step corresponding to Figure 2d according to an embodiment of the present application;

[0156] Figure 9 is a process flow diagram of a semiconductor wafer level packaging method according to a second embodiment of the present application;

[0157] Figures 10a-10d are schematic views of process steps of a semiconductor wafer level packaging method according to an embodiment of the present application;

[0158] Figure 11 is a schematic view of a portion of Figure 10d;

[0159] Figure 12 is a schematic view of a portion of a step corresponding to Figure 10d according to an embodiment of the present application;

[0160] Figure 13 is a schematic view of a portion of a step corresponding to Figure 10d according to an embodiment of the present application;

[0161] Figure 14 is a schematic view of a portion of a step corresponding to Figure 10d according to an embodiment of the present application;

[0162] Figures 15a-15d are schematic views of process steps of a semiconductor wafer level packaging method according to an embodiment of the present application;

[0163] Figure 16 is a schematic view of a portion of Figure 15d;

[0164] Figure 17 is a schematic view of a structure of a pad and a via in a chip structure according to an embodiment of the present application;

[0165] Figure 18 is a process flow diagram of a semiconductor wafer level packaging method according to an embodiment of the present application;

[0166] Figures 19a and 19b are schematic views of a wafer and a substrate structure according to a step corresponding to Figure 18;

[0167] FIG. 20a and FIG. 20b show a schematic diagram of a structure of setting a first-pad corresponding annular bump and a second-pad corresponding annular bump between the pad and the substrate;

[0168] FIG. 21 shows a connection relationship between the second bonding area and the third bonding area in the embodiment of the present application;

[0169] FIG. 22 shows a structure of the glue overflow area in the embodiment of the present application;

[0170] FIG. 23 shows an optional structure of the pad in the embodiment of the present application;

[0171] FIG. 24 shows a connection relationship between the annular bump and the pad in the embodiment of the present application. DETAILED DESCRIPTION

[0172] In order to make the person skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the protection scope of the present application.

[0173] As described in the background, for the packaging of the substrate with functional properties or for the chip whose functional area cannot be affected, the silk screen printing glue coating method or the glue rolling method in the prior art can easily coat the bonding glue to the position of the substrate corresponding to the chip functional area or to the chip functional area, and thus is not suitable for the bonding of the above-mentioned substrate and chip.

[0174] Based on this, the present application provides a semiconductor wafer level packaging method, by setting the annular bump, cooperating with the glue coating method, maintaining the packaging bonding strength, improving the air tightness and reliability of the packaging structure, and preventing the bonding glue from affecting the functional area.

[0175] As shown in FIG. 1, the semiconductor wafer level packaging method in the first embodiment of the present application includes the following specific steps:

[0176] S1, providing a first wafer with a plurality of chip units, each chip unit having a functional area and a first bonding area, the first bonding area being arranged around the functional area;

[0177] S2, providing a second wafer or a substrate, the second wafer or the substrate having a second bonding area corresponding to the first bonding area;

[0178] S3, forming a first annular protrusion on the first bonding area of the chip unit, the first annular protrusions between adjacent chip units have a first interval area, and / or forming at least one first annular protrusion on the second bonding area of the second wafer or substrate, the first annular protrusions between adjacent second bonding areas have a second interval area;

[0179] S4, filling glue in the first interval area and / or the second interval area, the glue protruding the top surface of the first annular protrusion;

[0180] S5, aligning and pressing the second wafer or substrate with the first wafer.

[0181] After aligning and pressing, the first bonding area and the second bonding area oppositely arranged on the first wafer and the second wafer or substrate are bonded to each other.

[0182] In the above technical solution, by controlling the filling amount of the glue, after aligning and pressing, the glue protruding the top surface of the first annular protrusion is partially or completely extruded to the side of the first annular protrusion away from the first interval area and / or the second interval area. The glue extruded to the side of the first annular protrusion away from the first interval area and / or the second interval area at least contacts one of the first wafer and the second wafer or substrate. Or, the glue extruded to the side of the first annular protrusion away from the first interval area and / or the second interval area contacts both the first wafer and the second wafer or substrate.

[0183] Preferably, the glue can be filled in the first interval area and / or the second interval area by dispensing or printing.

[0184] Preferably, the number of the first annular protrusions can be set to multiple circles to further increase the air tightness.

[0185] When the number of the first annular protrusions is multiple circles, the glue can not only be filled in the first interval area between the first annular protrusions of adjacent chip units and / or the second interval area between the first annular protrusions of adjacent second bonding areas, but also can be further filled in the area between adjacent first annular protrusions to further increase the bonding strength.

[0186] It can be understood that, with the increase of the number of the first annular protrusions, the first annular protrusions will be closer and closer to the functional area, at this time, the glue protruding the top surface of the first annular protrusion is easy to flow to the functional area after bonding, thereby affecting the functional area. In order to make the glue after bonding not affect the functional area located in the surrounding circle of the first annular protrusion, the amount of glue filled in the first interval area and / or the second interval area close to the functional area can be controlled to be less than or equal to the amount of glue filled in other first interval areas and / or second interval areas, so that the glue filled in the first interval area and / or the second interval area close to the functional area will not be squeezed out of the bonding area after aligning and pressing, thereby affecting the functional area.

[0187] In another embodiment, the adhesive flowing to the functional area after bonding can also be blocked by setting a ring of protrusions on the second bonding area and / or the first bonding area.

[0188] Specifically, the height of the second ring-shaped protrusion is greater than or equal to the height of the first ring-shaped protrusion. The inner diameter of the second ring-shaped protrusion is smaller than the inner diameter of any first ring-shaped protrusion on the first bonding area and / or the second bonding area. A third spacing area is formed between the second ring-shaped protrusion and the first ring-shaped protrusion adjacent to it.

[0189] After bonding of the first wafer and the second wafer or substrate, the adhesive protruding from the top surface of the first ring-shaped protrusion is only partially or completely extruded into the third spacing area, i.e. the second ring-shaped protrusion can block the adhesive flowing to the functional area after bonding. At the same time, since the top surface of the second ring-shaped protrusion can be in complete contact with the first bonding area or the second bonding area for alignment and sealing, it can block the volatile gas generated by the curing of the adhesive in the first spacing area and / or the second spacing area and / or the third spacing area from entering the functional area, thereby avoiding adverse effects on the functional area.

[0190] It can be understood that between adjacent chip units on the first wafer, a first cutting area for cutting will be formed. The second wafer or substrate has a second cutting area corresponding to the first cutting area. In order to improve the bonding strength, the width of the first spacing area is preferably greater than or equal to the width of the first cutting area, i.e. the first cutting area is located in the first spacing area. The width of the second spacing area is preferably greater than or equal to the width of the second cutting area, i.e. the second cutting area is located in the second spacing area.

[0191] In an optional embodiment, the inner diameter of the first ring-shaped protrusion formed on the first bonding area is different from the inner diameter of the first ring-shaped protrusion formed on the second bonding area, so that the upper and lower first ring-shaped protrusions are misaligned with each other when pressed together. This is beneficial to increase the permeation path of the gas, thereby improving the effective time of sealing.

[0192] Preferably, the width of the ring-shaped protrusion is less than half of the total width of the sealing area, specifically, the total width of the multiple rings of first ring-shaped protrusions provided on the first bonding area is less than half of the width of the first bonding area, and the total width of the multiple rings of first ring-shaped protrusions provided on the second bonding area is less than half of the width of the second bonding area, thereby providing sufficient bonding space for the corresponding first bonding area and second bonding area.

[0193] The ring-shaped protrusion can be of inorganic material, including metal, silicon, silicon oxide, aluminum nitride, lithium tantalate, etc.

[0194] Preferably, the first ring-shaped protrusion and the second ring-shaped protrusion can both be metal protrusions, which can be made by the following method:

[0195] First, a metal layer structure is formed by sputtering or evaporation; a photoresist layer is formed on the metal layer structure and patterned (the area for forming the first annular protrusion and / or the second annular protrusion is reserved), forming a first annular protrusion pattern and / or a second annular protrusion pattern; the first annular protrusion pattern and / or the second annular protrusion pattern is transferred to the metal layer structure, forming the first annular protrusion and / or the second annular protrusion; and the remaining photoresist layer is removed.

[0196] Second, a photoresist layer is formed and patterned (the area for forming the first annular protrusion and / or the second annular protrusion is removed), forming an annular recess pattern; a metal layer structure covering the annular recess pattern is formed by sputtering or evaporation;

[0197] The annular recess pattern is removed, and the metal layer structure on the surface of the annular recess pattern is removed at the same time, forming the first annular protrusion and / or the second annular protrusion.

[0198] The semiconductor wafer level packaging method of the present application is described below through several specific embodiments.

[0199] Embodiment 1

[0200] Referring to FIG. 2a, a substrate 10 is provided, and a plurality of grooves 11 are formed on the substrate 10. The substrate 10 has a second bonding area S2, and each groove 11 is surrounded by a second bonding area S2. A second cutting area S4 is formed between adjacent second bonding areas S2.

[0201] It can be understood that in other embodiments, the grooves 11 can not be provided on the substrate 10. At this time, each annular second bonding area S2 on the substrate 10 has a certain area in the middle to correspond to the functional area of the chip unit of the wafer to be bonded. In other embodiments, the substrate 10 can be another functional wafer.

[0202] Referring to FIG. 2b, a first annular protrusion 121 is provided on each second bonding area S2 of the substrate 10. The first annular protrusions 121 of adjacent second bonding areas S2 form a second spacing area A with a certain width.

[0203] The first annular protrusion 121 on each second bonding area S2 is arranged as close as possible to the outer edge of the second bonding area S2 but does not exceed the outer edge, so that the width of the second spacing area A is greater than or equal to the width of the second cutting area S4, improving the bonding area of the subsequent glue and improving the bonding strength. A certain buffer space is reserved between the first annular protrusion 121 and the inner edge of the second bonding area S2.

[0204] Specifically, the first annular protrusion 121 is preferably a metal protrusion, and the first annular protrusion 121 can be made in the following two ways.

[0205] First, the entire surface of the second bonding region S2 is sputtered or evaporated with metal to form a metal layer structure. A photoresist layer is coated on the metal layer structure. The photoresist layer is patterned (the area for forming the first annular protrusion is reserved) to form a first annular protrusion pattern. The metal layer structure is etched with the patterned photoresist layer as a mask to transfer the first annular protrusion pattern to the metal layer structure to form the first annular protrusion. The remaining photoresist layer is removed.

[0206] Second, the entire surface of the second bonding region S2 is coated with a photoresist layer (lift off photoresist). The photoresist layer is patterned (the area for forming the first annular protrusion is removed) to form an annular recess pattern. The metal is sputtered or evaporated to form a metal layer structure covering the annular recess pattern. The patterned photoresist layer is peeled off and the metal layer evaporated on the photoresist layer is also peeled off to form the first annular protrusion.

[0207] Referring to FIG. 2c, the space between the adjacent first annular protrusions 121 is filled with glue by dispensing or printing. The glue is filled to the top surface of the first annular protrusion 121. The amount of glue filled is controlled so that, after subsequent alignment and pressing, the glue on the top surface of the first annular protrusion 121 is completely squeezed to the side of the first annular protrusion 121 away from the second spacing region A.

[0208] Referring to FIG. 2d, a first wafer 20 is provided, which has a plurality of chip units 21, and a first cutting region S3 corresponding to a second cutting region S4 is formed between adjacent chip units 21. Each chip unit 21 has a functional region S0 and a first bonding region S1 arranged around the functional region S0. The second bonding region S2 of the substrate 10 is aligned and pressed with the first bonding region S1 of the first wafer 20. During alignment and pressing, the substrate 10 is arranged at the bottom and the first wafer 20 is arranged at the top. By adjusting the process parameters such as temperature and pressure, the glue on the top surface of the first annular protrusion 121 is squeezed to flow around.

[0209] Referring to FIG. 3, which is a partial schematic view of FIG. 2d, in FIG. 3, the glue on the top surface of the first annular protrusion 121 is completely squeezed to the space on the side of the first annular protrusion 121 away from the second spacing region A, but does not flow to the region where the functional region is located. The glue squeezed to the side of the first annular protrusion 121 away from the second spacing region A is in contact with the surfaces of the first wafer 20 and the substrate 10.

[0210] Finally, subsequent packaging is completed as needed, and the first cutting region and the second cutting region are cut into single package structures.

[0211] It can be understood that the first annular protrusion 121 can also be formed on the first bonding region S1 of the first wafer 10.

[0212] Embodiment 2

[0213] The difference between Embodiment 2 and Embodiment 1 is that the pressure of the pressing process parameter is different when the alignment pressing is performed.

[0214] In Embodiment 2, in order to improve the uniformity of the packaging and the bonding strength between the first wafer 20 and the substrate 10, the contact area of the glue with the substrate 10 (including the first annular protrusion 121) and the first wafer 20 is increased as much as possible without affecting the functional region S0. Referring to FIG. 4, the pressure during pressing is reduced, and the amount of glue protruding from the top surface of the first annular protrusion 121 is controlled, so that after the alignment pressing, the glue protruding from the top surface of the first annular protrusion 121 is partially extruded into the space on the side of the first annular protrusion 121 away from the second spacing region A, but does not flow to the region where the functional region is located. The top surface of the first annular protrusion 121 of the first wafer 20 and the substrate 10 is not completely in contact, and the space is filled with glue.

[0215] Embodiment 3

[0216] The difference between Embodiment 3 and Embodiment 1 is only that the amount of glue protruding from the top surface of the first annular protrusion 121 is different in the step shown in FIG. 2c.

[0217] In Embodiment 3, referring to FIG. 5, the glue protruding from the top surface of the first annular protrusion 121 is completely extruded into the space on the side of the first annular protrusion 121 away from the second spacing region A, but does not flow to the region where the functional region is located. The glue extruded to the side of the first annular protrusion 121 away from the second spacing region A is in contact with the surface of the first wafer 20 but not in contact with the surface of the substrate 10.

[0218] Embodiment 4

[0219] Referring to FIG. 6a, a substrate 10 is provided, and a plurality of grooves 11 are formed on the substrate 10. The substrate 10 has a second bonding region S2, and each groove 11 is surrounded by a second bonding region S2. A second cutting region S4 is formed between adjacent second bonding regions S2.

[0220] It can be understood that in other embodiments, the grooves 11 can also not be provided on the substrate 10. At this time, each annular second bonding region S2 on the substrate 10 has a certain region in the middle to correspond to the functional region of the chip unit of the wafer to be bonded. In other embodiments, the substrate 10 can also be another functional wafer.

[0221] Referring to FIG. 6b, a first annular bump 121 is arranged on each second bonding area S2 of the substrate 10. A second spacing area A with a certain width is formed between the first annular bumps 121 of adjacent second bonding areas S2. Meanwhile, a second annular bump 122 is arranged on each second bonding area S2 of the substrate 10. The inner diameter of the second annular bump 122 is smaller than that of the first annular bump 121, and the height of the second annular bump 122 is greater than or equal to that of the first annular bump 121. A third spacing area C is formed between the second annular bump 122 and the adjacent first annular bump 121.

[0222] Specifically, the first annular bump 121 and the second annular bump 122 are preferably metal bumps, which can be manufactured in the following two ways.

[0223] First, sputtering or evaporation of metal is performed on the entire surface of the second bonding area S2 to form a metal layer structure. A photoresist layer is coated on the metal layer structure to form a photoresist layer. The photoresist layer is patterned to retain the area for forming the annular bump (including the first annular bump and the second annular bump), and an annular bump pattern is formed. The metal layer structure is etched with the patterned photoresist layer as a mask to transfer the annular bump pattern to the metal layer structure, and the annular bump is formed. The remaining photoresist layer is removed.

[0224] Second, a photoresist layer is coated (lift off photoresist) on the entire surface of the second bonding area S2 to form a photoresist layer. The photoresist layer is patterned to remove the area for forming the annular bump (including the first annular bump and the second annular bump), and an annular recess pattern is formed. Sputtering or evaporation of metal is performed to form a metal layer structure covering the annular recess pattern. The patterned photoresist layer is peeled off, and the metal layer evaporated on the photoresist layer is also peeled off, forming the annular bump.

[0225] Referring to FIG. 6c, the second spacing area A between adjacent first annular bumps 121 is filled with glue by dispensing or printing. The glue is filled to the top surface of the first annular bump 121. The amount of glue filled is controlled so that, after subsequent alignment and pressure bonding, the glue on the top surface of the first annular bump 121 is only partially or completely extruded into the third spacing area C. The third spacing area C can also accommodate the volatile gas generated by the curing of the glue, so that it does not enter the functional area and adversely affect the functional area.

[0226] Referring to FIG. 6d, a first wafer 20 is provided, the first wafer 20 has a plurality of chip units 21, each chip unit 21 has a functional area S0 and a first bonding area S1, the first bonding area S1 is arranged around the functional area S0. The substrate 10 is aligned and pressed with the first wafer 20. When aligned and pressed, the substrate 10 is arranged below, the first wafer 20 is arranged above, by adjusting the pressing process parameters such as temperature, pressure and the like, so that the glue on the top surface of the convex first annular protrusion 121 is extruded to flow around.

[0227] Referring to FIG. 7, FIG. 7 is a partial schematic view of FIG. 6d, in FIG. 7, the glue on the top surface of the convex first annular protrusion 121 is extruded into the third spacing area C and does not flow into the area where the functional area is located. The glue extruded into the third spacing area C is in contact with the surfaces of the first wafer 20 and the substrate 10. The third spacing area C can also accommodate the volatile gas generated by the curing of the glue, so that it does not enter the functional area and adversely affect the functional area.

[0228] Finally, subsequent packaging is completed according to needs, and the first cutting area and the second cutting area are cut into single package structures.

[0229] Embodiment 5

[0230] Embodiment 5 is different from embodiment 1 only in that in embodiment 5, the first annular protrusions 121 are arranged on the first bonding areas S1 of the first wafer 20 and the second spacing areas S2 of the substrate 10 or the second wafer, respectively. Referring to FIG. 8, the first annular protrusions 121 between adjacent first bonding areas S1 have a first spacing area B, and the first annular protrusions 121 between adjacent second bonding areas S2 have a second spacing area A.

[0231] One or all of the first spacing area B and the second spacing area A are filled with glue.

[0232] After alignment and pressing, the first annular protrusions 121 of the first bonding area S1 are arranged in a staggered manner with the first annular protrusions 121 of the second bonding area S2.

[0233] The application also provides a package structure packaged by using the above packaging method.

[0234] Referring to FIGS. 2d and 3-5, the package structure of the application includes a first wafer 20, a substrate 10, a glue bonding layer and first annular protrusions 121.

[0235] The first wafer 20 has a first surface, the first surface has a functional area S0 and a first bonding area S1, the first bonding area S1 is arranged around the functional area S0.

[0236] The substrate 10 has a second surface with a second bonding area S2, and a groove 11 is formed on the second surface and surrounded by the second bonding area S2. The second surface of the substrate 10 is attached to the first surface of the first wafer 20, and the groove 11 corresponds to and covers the functional area S0, and the second bonding area S2 is bonded to the first bonding area S1.

[0237] It can be understood that the groove 11 can not be provided in other embodiments.

[0238] The glue bonding layer is provided between the first bonding area S1 and the second bonding area S2.

[0239] The first annular protrusion 121 is provided on the first bonding area S1 and / or the second bonding area S2 and partially or entirely located in the glue bonding layer.

[0240] In a preferred embodiment, the first annular protrusion 121 is selected from a metal bump to further improve the air tightness.

[0241] In another embodiment, referring to FIG. 7, a second annular protrusion 122 is further provided on the first bonding area S1 and / or the second bonding area S2 and located within the range surrounded by the first annular protrusion 121. The height of the second annular protrusion 122 is higher than or equal to the height of the first annular protrusion 121, and a third spacing area C is formed between the second annular protrusion 122 and the first annular protrusion 121 adjacent thereto. The third spacing area C is not in communication with the area where the functional area is located, and the glue bonding layer is partially or entirely provided in the third spacing area C.

[0242] As shown in FIG. 9, the semiconductor wafer level packaging method in the second embodiment of the present application includes the following specific steps:

[0243] S10, providing a first wafer with one or more chip units, each chip unit having a functional area and a first bonding area surrounding the functional area.

[0244] S20, providing a second wafer or substrate having a second bonding area corresponding to the first bonding area.

[0245] S30, forming at least two circles of first annular protrusions on the first bonding area of the chip unit, and / or forming at least two circles of first annular protrusions on the second bonding area of the second wafer or substrate, and a fourth spacing area is formed between adjacent first annular protrusions.

[0246] S40, filling glue in the fourth spacing area, and the glue protrudes above the top surface of the first annular protrusion.

[0247] S50, aligning and pressing the second wafer or substrate with the first wafer.

[0248] In the above technical solution, the filling amount of glue is controlled so that after alignment and compression, the glue protruding from the top surface of the first annular protrusion is extruded to partially or completely fill the space between the top surface of the first annular protrusion and the first bonding area or the second bonding area aligned with the top surface. Alternatively, the filling amount of glue is controlled so that after alignment and compression, the glue protruding from the top surface of the first annular protrusion is extruded to completely fill all the space between the top surface of the first annular protrusion and the first bonding area or the second bonding area aligned with the top surface, and extend to the side surface of the first annular protrusion away from the fourth spacing area.

[0249] Preferably, the glue can be filled in the fourth spacing area by dispensing or printing.

[0250] Preferably, the number of turns of the first annular protrusion can be set to more than two to further increase the air tightness.

[0251] When the number of turns of the first annular protrusion is greater than two, as the number of turns of the first annular protrusion increases, the first annular protrusion is closer and closer to the functional area. At this time, the glue on the top surface of the first annular protrusion is prone to flow to the location of the functional area after bonding, thereby affecting the functional area. In order to prevent the glue after bonding from affecting the functional area located within the surrounding turns of the first annular protrusion, the amount of glue filled in the fourth spacing area close to the functional area can be controlled so that the amount of glue protruding from the top surface of the first annular protrusion in the fourth spacing area is partially or completely filled after alignment and compression. Preferably, the glue partially fills the space between the top surface of the first annular protrusion and the first bonding area or the second bonding area aligned with the top surface, so that the glue is not extruded out of the bonding area.

[0252] Further, in order to ensure the bonding strength between the first wafer and the substrate or the second wafer, the amount of glue filled in the remaining fourth spacing areas away from the functional area can be controlled to be slightly more than the amount of glue filled in the fourth spacing area close to the functional area, so that the amount of glue protruding from the top surface of the first annular protrusion in the remaining fourth spacing areas is extruded to completely fill all the space between the top surface of the first annular protrusion and the first bonding area or the second bonding area aligned with the top surface, and extend to the side surface of the first annular protrusion after alignment and compression.

[0253] In another embodiment, a ring-shaped dike can also be provided on the second bonding area of the second wafer or the substrate and / or the first bonding area of the first wafer to block the glue from flowing to the functional area after bonding. The inner diameter of the ring-shaped dike is smaller than the inner diameter of any first annular protrusion. The ring-shaped dike is arranged on the first bonding area or the second bonding area aligned with the top surface of the innermost turn of the first annular protrusion, and the height of the ring-shaped dike is less than the height between the second bonding area and the first bonding area and greater than or equal to the height between the top surface of the first annular protrusion and the first bonding area or the second bonding area aligned with the top surface.

[0254] Exemplarily, when the first ring-shaped protrusions are arranged on the first bonding region of the first wafer, the ring-shaped dam is arranged on the second bonding region of the substrate or the second wafer, and is arranged at a position such that, after the substrate or the second wafer and the first wafer are bonded, the ring-shaped dam is located between the innermost first ring-shaped protrusion and the functional region. The height of the ring-shaped dam is arranged to partially overlap the first ring-shaped protrusion in a direction parallel to the first surface of the first wafer.

[0255] Exemplarily, when the first ring-shaped protrusions are arranged on the second bonding region of the substrate or the second wafer, the ring-shaped dam is arranged on the first bonding region of the first wafer, and is arranged at a position such that, after the substrate or the second wafer and the first wafer are bonded, the ring-shaped dam is located between the innermost first ring-shaped protrusion and the functional region. The height of the ring-shaped dam is arranged to partially overlap the first ring-shaped protrusion in a direction parallel to the first surface of the first wafer.

[0256] In other embodiments, the flow of the adhesive to the functional region after bonding can also be blocked by a combination of the ring-shaped dam and the amount of adhesive.

[0257] Preferably, the first ring-shaped protrusion can be a metal protrusion, which can be manufactured in the following ways:

[0258] First, a metal layer structure is sputtered or evaporated; a photoresist layer is formed on the metal layer structure and is patterned (the region used to form the first ring-shaped protrusion is retained), forming a ring-shaped protrusion pattern; the ring-shaped protrusion pattern is transferred to the metal layer structure, forming the first ring-shaped protrusion; and the remaining photoresist layer is removed.

[0259] Second, a photoresist layer is formed and patterned (the region used to form the first ring-shaped protrusion is removed), forming a ring-shaped recess pattern; a metal layer structure covering the ring-shaped recess pattern is sputtered or evaporated;

[0260] The ring-shaped recess pattern and the metal layer structure on the surface of the ring-shaped recess pattern are removed simultaneously, forming the first ring-shaped protrusion.

[0261] The semiconductor wafer-level packaging method of the present application is described below through several specific embodiments.

[0262] Embodiment 6 (two circles of first ring-shaped protrusions arranged on the substrate)

[0263] Referring to FIG. 10a, a substrate 10 is provided, and a plurality of grooves 11 are formed on the substrate 10. The substrate 10 has a second bonding region S2, and each groove 11 is surrounded by a second bonding region S2.

[0264] It can be understood that in other embodiments, the grooves 11 can also not be provided on the substrate 10. At this time, each annular second bonding area S2 on the substrate 10 has a certain area in the middle to correspond to the functional area of the chip to be bonded. In other embodiments, the substrate 10 can also be another functional wafer.

[0265] Referring to FIG. 10b, two circles of first annular protrusions 121 are provided on the second bonding area S2 of the substrate 10. The two circles of first annular protrusions 121 are coaxial or spaced apart at different axes, and a fourth spacing area D with a certain width is formed between the two circles of first annular protrusions 121. A certain buffer space is reserved between the inner circle of the first annular protrusions 121 and the inner edge of the second bonding area S2.

[0266] Specifically, the first annular protrusions 121 are preferably metal protrusions.

[0267] Referring to FIG. 10c, the fourth spacing area D between the two circles of first annular protrusions 121 is filled with glue by dispensing or printing. The glue is filled to slightly protrude the top surface of the first annular protrusions 121.

[0268] Referring to FIG. 10d, a first wafer 20 is provided, and the first wafer 20 has a plurality of chip units 21, each of which has a functional area S0 and a first bonding area S1 provided around the functional area S0. The substrate 10 is aligned and pressed with the first wafer 20. When aligning and pressing, the substrate 10 is arranged below, and the first wafer 20 is arranged above. By adjusting the process parameters such as temperature and pressure, the glue on the top surface of the first protruding annular protrusions 121 is extruded to flow to the surrounding.

[0269] Referring to FIG. 11, which is a partial schematic view of FIG. 10d, in FIG. 11, the glue on the top surface of the protruding first annular protrusions 121 is extruded to fill the entire space between the top surface of the first annular protrusions 121 and the first bonding area S1 aligned with the top surface. Among them, the area between the two sides of the two circles of first annular protrusions 121 away from each other is defined as the space area or the entire space area between the top surface of the first annular protrusions 121 and the first bonding area S1 aligned with the top surface. The above definition is used in the remaining embodiments below.

[0270] Finally, subsequent packaging is completed as needed.

[0271] Embodiment 7

[0272] The difference between Embodiment 7 and Embodiment 6 is only that the amount of glue on the top surface of the protruding first annular protrusions 121 is different in the step shown in FIG. 10c.

[0273] In Embodiment 7, in order to improve the uniformity of the package and to improve the bonding strength between the first wafer 20 and the substrate 10, the contact area of the glue with the substrate 10 (including the first annular protrusion 121) and the first wafer 20 is increased as much as possible without affecting the functional area S0. Referring to FIG. 12, the amount of glue protruding from the top surface of the first annular protrusion 121 is controlled so that, after alignment and pressing, the glue protruding from the top surface of the first annular protrusion 121 is squeezed to fill all the space between the top surface of the first annular protrusion 121 and the first bonding area S1 aligned with the top surface, and extends to the side surface of the first annular protrusion 121 away from the fourth spacing area D.

[0274] Embodiment 8 (three circles of first annular protrusions are arranged on the substrate)

[0275] The difference between Embodiment 8 and Embodiment 7 is that, in Embodiment 8, three circles of first annular protrusions 121 are arranged. The fourth spacing area D between adjacent first annular protrusions 121 is filled with glue. The arrangement of three circles of first annular protrusions 121 further improves the air tightness of the package. When there is a non-uniformity in the first bonding area S1 around the functional area S0 of the first wafer 20 (due to different fluctuations caused by design), the arrangement of multiple circles of first annular protrusions 121 can provide multiple air tightness insurance effects.

[0276] Referring to FIG. 13, in Embodiment 8, the amount of glue in each fourth spacing area D is controlled to be the same, so that the glue protruding from the top surface of the first annular protrusion 121 in each fourth spacing area D is squeezed to fill all the space between the top surface of the first annular protrusion 121 and the first bonding area S1 aligned with the top surface after alignment and pressing, and extends to the side surface of the first annular protrusion 121.

[0277] Embodiment 9

[0278] The difference between Embodiment 9 and Embodiment 8 is only that, in the step shown in FIG. 10c, the amount of glue protruding from the top surface of the first annular protrusion 121 is different.

[0279] It can be understood that the more circles of first annular protrusions 121 are arranged, the closer the first annular protrusions will be to the functional area S0. Therefore, when the first annular protrusions 121 are arranged in three circles, the buffer area corresponding to the functional area S0 in the innermost circle of the first annular protrusions 121 will be too narrow, so that when alignment and pressing are performed, the glue protruding from the top surface of the first annular protrusion 121 will easily flow to the functional area S0, thereby affecting the functional area S0.

[0280] Thus, referring to FIG. 14, in order to make the glue after bonding not to affect the functional area S0 located within the surrounding of the first annular protrusion 121, the amount of glue filled into the fourth interval area close to the functional area S0, defined as the fourth interval area D1, is slightly less than the amount of glue filled into the fourth interval area far from the functional area S0, defined as the fourth interval area D2, so that the amount of glue protruding from the top surface of the first annular protrusion 121 in the fourth interval area D1 after alignment and pressing fills part of the space between the top surface of the first annular protrusion 121 and the first bonding area S1 aligned with the top surface, so that the glue cannot be squeezed out of the bonding area. While the amount of glue protruding from the top surface of the first annular protrusion 121 in the fourth interval area D2 after alignment and pressing is squeezed to completely fill the space between the top surface of the first annular protrusion 121 and the first bonding area S1 aligned with the top surface, and extends to the side surface of the first annular protrusion 121.

[0281] Embodiment 10

[0282] The difference between Embodiment 10 and Embodiment 6 is that in Embodiment 10, the first annular protrusion 121 is arranged on the first bonding area S1 of the first wafer 20.

[0283] Embodiment 11

[0284] Referring to FIG. 15a, a substrate 10 is provided, and the substrate 10 is formed with a plurality of grooves 11, and the substrate 10 has a second bonding area S2, and each groove 11 is surrounded by a second bonding area S2.

[0285] It can be understood that in other embodiments, the substrate 10 can also not be provided with the grooves 11. At this time, each annular second bonding area S2 on the substrate 10 has a certain area in the middle to correspond to the functional area of the chip to be bonded. In other embodiments, the substrate 10 can also be another functional wafer.

[0286] Referring to FIG. 15b, three circles of first annular protrusions 121 are arranged on the second bonding area S2 of the substrate 10. The three circles of first annular protrusions 121 are coaxial or arranged at intervals with different shafts, and a fourth interval area D with a certain width is formed between the adjacent two circles of first annular protrusions 121. In this embodiment, the fourth interval area close to the functional area is defined as the fourth interval area D1, and the fourth interval area far from the functional area is defined as the fourth interval area D2.

[0287] Specifically, the first annular protrusion 121 is preferably a metal protrusion.

[0288] Referring to FIG. 15c, the glue is filled in the fourth interval area D1 and the fourth interval area D2 by dispensing or printing. The glue is filled to slightly protrude from the top surface of the first annular protrusion 121.

[0289] Referring to FIG. 15d, a first wafer 20 is provided, the first wafer 20 has a plurality of chip units 21, each chip unit 21 has a functional area S0 and a first bonding area S1, the first bonding area S1 is arranged around the functional area S0. An annular cofferdam 21 is arranged on the first bonding area S1. The inner diameter of the annular cofferdam 21 is smaller than the inner diameter of any first annular protrusion 121 on the substrate 10, so that after subsequent alignment and pressing, the annular cofferdam 21 is located in the innermost circle, blocking the adhesive from flowing to the functional area S0 after bonding.

[0290] The substrate 10 is aligned and pressed with the first wafer 20. During alignment and pressing, the substrate 10 is arranged below, and the first wafer 20 is arranged above. By adjusting the process parameters such as temperature and pressure, the adhesive on the top surface of the protruding first annular protrusion 121 is extruded to flow around.

[0291] Referring to FIG. 16, which is a partial schematic view of FIG. 15d, in FIG. 16, by controlling the amount of adhesive filled into the fourth interval area D1 close to the functional area S0, the amount of adhesive is slightly less than the amount of adhesive filled into the fourth interval area D2 away from the functional area S0, so that the amount of adhesive on the top surface of the protruding first annular protrusion in the fourth interval area D1 is partially filled into the space between the top surface of the first annular protrusion 121 and the first bonding area S1 aligned with the top surface after alignment and pressing, so that the adhesive cannot be extruded out of the bonding area. While the amount of adhesive on the top surface of the protruding first annular protrusion 121 in the fourth interval area D2 is extruded to completely fill the entire space between the top surface of the first annular protrusion 121 and the first bonding area S1 aligned with the top surface after alignment and pressing, and extends to the side surface of the second annular protrusion 121.

[0292] Finally, subsequent packaging is completed as needed.

[0293] The technical effects of the above packaging method will be described below in combination with Test 1 and Test 2. In Scheme 1 and Scheme 2, a radio frequency chip (FBAR) is bonded respectively. In Scheme 1, the technical scheme adopted is to not arrange an annular protrusion structure between the bonding areas, only fill polymer adhesive between the two bonding areas, and bond the opposite two bonding areas. In Scheme 2, the technical scheme provided by the present application is adopted, that is, an annular protrusion is arranged between the bonding areas, and polymer adhesive is filled in the interval area formed by the annular protrusion, and the opposite two bonding areas are bonded.

[0294] Test 1

[0295] Test 1: Leak detection of the RF chips in Scheme 1 and Scheme 2, which includes at least one of the following two steps: fine leak detection using a test method selected from tracer gas helium, radioactive isotope or optical method; and coarse leak detection using a test method selected from fluorocarbon, dye impregnation, weight gain or optical method. Alternatively, the RF chips in Scheme 1 and Scheme 2 are leak detected based on GJB548B-2005. The test results are shown in Table 1:

[0296] Table 1. Leak rate of Scheme 1 and Scheme 2

[0297] As can be seen from Table 1, Scheme 1 and Scheme 2 differ by an order of magnitude in terms of leak rate value. Obviously, Scheme 2 greatly delays the penetration of gas molecules into the region where the functional area is located, significantly improving the air tightness of the chip packaging structure.

[0298] Test 2

[0299] Frequency offset (difference in frequency before and after reliability) is a core performance indicator of RF chips. The air tightness of the cavity determines the amount of water vapor entering it. Water vapor will adhere to the working area membrane, causing its thickness to increase, resulting in frequency offset. The greater the offset, the worse the air tightness of the cavity.

[0300] Therefore, the RF chips packaged using Scheme 1 and Scheme 2 are further subjected to uHast test (unbiased high acceleration stress test, environmental conditions 130°C temperature, 85% humidity), and the frequency offset values of the bonding structures using Scheme 1, Scheme 2 and only metal bonding packaging method are compared after 96 hours. The standard offset value of this chip is 0.6 MHz, and the test results are shown in Table 2:

[0301] Table 2. Comparison of frequency offset values of Scheme 1 and Scheme 2

[0302] As can be seen from Table 2, Scheme 2 can achieve the chip standard and has the same effect as metal bonding, while Scheme 1 has a large offset value.

[0303] As can be seen from Test 1 and Test 2, the packaging method using Scheme 2 (i.e. the scheme of setting a ring-shaped protruding structure in the bonding area and bonding with polymer) not only improves the air tightness of the packaging structure, but also achieves the same effect as metal bonding in terms of reliability.

[0304] In summary, the technical scheme according to the embodiment of the present application improves the cavity air tightness to the reliability effect equivalent to the metal medium bonding by the cooperation of the metal bump in contact with the two bonding regions arranged oppositely and the glue. The technical scheme not only retains the high air tightness advantages of the medium-free bonding and the metal medium bonding, but also has the advantages of low cost and low requirement on wafer surface flatness of the polymer bonding.

[0305] Further, the above embodiment is also beneficial to solve the problems of high cost caused by the strict dependence of the medium-free bonding and the metal medium bonding on the nanoscale surface roughness and the multi-step process, and the small molecule diffusion problem caused by the high polymer component penetration of the polymer bonding.

[0306] In the embodiment of the present application, as shown in FIG. 17, in order to connect the chip with the outside world, a pad 150 can be arranged on the functional region of the chip, and a through hole 160 connected with the pad 150 is opened on the surface of the chip, wherein the pad is provided with an opening region 151 connected with the outside world, one side of the opening region 151 is arranged on the surface adjacent to the substrate of the pad, and the other side is arranged on the surface adjacent to the wafer of the pad. When the pad is connected with the outside world, the through hole 160 is arranged on the surface of the corresponding wafer or substrate, one end of the through hole 160 is connected with the pad, so that the opening region 151 is exposed outside the environment of the chip. In use, the pad 150 is connected with the outside world through the through hole 160. As shown in FIG. 17, the through hole can be opened on the first wafer, or on the second wafer or substrate. In the case of arranging the opening region 151, the second wafer or substrate needs to be bonded with the pad 150, that is, a third bonding region S3 is arranged to provide support for the pad 150. As shown on the right side of FIG. 17, if the third bonding region S3 is not arranged, when the pad 155 is connected with the outside world through the through hole 160, it will be in a suspended state, which has the risk of causing reliability failure.

[0307] Therefore, as shown in FIG. 18, the semiconductor wafer level packaging method for the pad in the embodiment of the present application includes the following specific steps:

[0308] providing a wafer with a plurality of chip units, each chip unit including a functional region, at least one pad arranged in or around the functional region, and a first bonding region surrounding the functional region, the pad including an opening region;

[0309] providing a substrate including a cavity region, a second bonding region and a third bonding region, wherein the second bonding region corresponds to the first bonding region, the third bonding region corresponds to the pad, and the cavity region corresponds to and can encompass the functional region;

[0310] forming a first pad corresponding annular protrusion on the pad, which surrounds the opening region, and / or forming a second pad corresponding annular protrusion on the third bonding region opposite to the pad, which corresponds to the opening region;

[0311] filling a polymer in the first pad corresponding annular protrusion, the top surface of the polymer being higher than the top surface of the first pad corresponding annular protrusion, and / or filling a polymer in the second pad corresponding annular protrusion, the top surface of the polymer being higher than the top surface of the second pad corresponding annular protrusion;

[0312] aligning and pressing the substrate and the wafer; and

[0313] forming a via corresponding to the opening region on at least one of the wafer and the substrate, so that the opening region is exposed to the environment outside the chip unit.

[0314] After aligning and pressing, the first bonding region and the second bonding region on the wafer and the substrate are bonded to each other, and the pad and the third bonding region are bonded to each other.

[0315] The packaging method between the chip unit and the substrate is further described below based on the combination of the packaging method for the pad and the embodiments 1 to 11.

[0316] The structure of the chip unit 21 and the substrate 22 is shown in FIGS. 19a and 19b. The working components of the chip (such as MEMS mechanical structure, movable components, etc.) are arranged in the functional region S0, and the pad 150 is arranged in the interior or periphery of the functional region S0. The opening region 151 is arranged on the pad 150, and the opening region 151 corresponds to the opening of the chip structure or the substrate, and the size of the opening region 151 is smaller than the size of the pad 150. Preferably, the opening region 151 is located in the center of the pad 150. The substrate 22 includes a cavity region 220, a second bonding region S2 and a third bonding region S3. The second bonding region S2 corresponds to the first bonding region S1, the third bonding region S3 corresponds to the pad 150, the cavity region 220 corresponds to the functional region S0 and can encapsulate the functional region S0. When the chip is working, the environment of the cavity region 220 is vacuum or gas with a certain pressure.

[0317] Similarly to the above embodiments 1 to 11, by arranging the annular protrusion between the pad 150 and the third bonding region S3, the air tightness and reliability of the packaging structure are improved. As shown in FIGS. 20a and 20b, the first pad corresponding annular protrusion 251 can be formed around the opening region 151 on the pad 150, or the second pad corresponding annular protrusion 252 corresponding to the opening region can be formed on the third bonding region S3 opposite to the pad 151.

[0318] The first-pad corresponding annular protrusion 251 and the second-pad corresponding annular protrusion 252 can be inorganic materials, including metal, silicon, silicon oxide, aluminum nitride, lithium tantalate, etc., and are preferably metal materials. The protrusion structure is formed on the surface material of the sealing area of the chip and / or the substrate, and the material thereof can be the same as or different from the surface material. For example, the first-pad corresponding annular protrusion 251 is formed on the silicon material substrate 22 by etching the silicon substrate multiple times, or the first-pad corresponding annular protrusion 251 is formed on the silicon oxide material substrate 22 by deposition, photolithography, etching, etc., or the second-pad corresponding annular protrusion 252 is formed on the metal material pad 150 by deposition, photolithography, etching, etc.

[0319] In an optional embodiment, the protrusion width is less than half of the total width of the sealing area, i.e., the width of the first-pad corresponding annular protrusion 251 is less than half of the width of the pad 150, and the width of the second-pad corresponding annular protrusion 252 is less than half of the width of the third bonding area S3, thereby providing sufficient bonding space for the opposite pad 150 and the third bonding area S3.

[0320] In an optional embodiment, as shown in FIG. 20a, the first-pad corresponding annular protrusion 251 is connected with the first annular protrusion on the first bonding area S1. Or in an optional embodiment, as shown in FIG. 20b, the second-pad corresponding annular protrusion is connected with the first annular protrusion on the second bonding area. By connecting the annular protrusions arranged on the pad and the third bonding area with the annular protrusions arranged on the first bonding area and the second bonding area, it is beneficial to further increase the sealing performance of the package and to simplify the process flow of forming the pad corresponding annular protrusion. At the same time, it is also beneficial to improve the electromagnetic shielding performance of the chip.

[0321] In an optional embodiment, as shown in FIG. 21, a predetermined width of glue overflow area 260 is left around the second bonding area S2 and the third bonding area S3 in the cavity area 220, so that after alignment and pressing, the glue can be extruded into the glue overflow area 260. In addition, as not shown in the drawings of the present application, the glue overflow area 260 can also be arranged between the third bonding area S3 and the functional area S0. By arranging the glue overflow area 260, the glue coated in the area bonded by the glue (such as between the first bonding area S1 and the second bonding area S2, and such as between the third bonding area S3 and the pad 150) can overflow to the glue overflow area 260 during pressing, thereby avoiding affecting the devices in the functional area S0.

[0322] In an embodiment of the present application, the glue flowing to the four corners of the chip unit during the pressing process comes from three directions, i.e. two adjacent sides and the intersection thereof. Therefore, in an optional embodiment, the glue overflow area can be further arranged between the adjacent chip units, and the glue overflow area 260 is arranged at the intersection between the chip units, so that the glue can be squeezed into the glue overflow area 260 after the alignment and pressing.

[0323] As shown in FIG. 22, the third bonding area S3 in the cavity area 220 and the second bonding area S2 surrounding the cavity area 220 have different shapes and connection relationships. The cavity area 220 is a recessed part, and the second bonding area S2 and the third bonding area S3 are protruding parts in the cavity area 220. In an optional embodiment, the second bonding area S2 and the third bonding area S3 have the same height. At this time, if the recessed cavity area 220 is regarded as the sea and the second bonding area S2 is regarded as the continent, the third bonding area S3 at this time can be regarded as an island or a peninsula. When the third bonding area S3 is connected with the second bonding area S2, the two form a “peninsula” structure. When the third bonding area S3 is separated from the second bonding area S2, the third bonding area S3 forms an “island” structure relative to the second bonding area S2.

[0324] The “island” structure of the third bonding area S3 can be connected with the second bonding area S2 through one or more connecting parts. As shown in FIG. 22, the “island” structure of the third bonding area S3 is connected with the second bonding area S2 through one or more “bridge” structures. In an optional embodiment, the third bonding area S3 is connected with the second bonding area S2 through one “bridge” structure, and the glue overflow area 260 capable of accommodating glue is formed on both sides of the “bridge”. In another optional embodiment, the third bonding area S3 is connected with the second bonding area S2 through two “bridge” structures, and the glue overflow area 260 capable of accommodating glue is formed between the two “bridges”.

[0325] The relationship between the second bonding area S2 and the third bonding area S3 can be selected according to different use cases. For example, when the opening area 151 of the pad 150 is close to the first bonding area S1, the third bonding area S3 is close to the second bonding area S2 in space at this time, and the “peninsula” or “island”+“bridge” connection mode can be selected. When the opening area 151 of the pad 150 is far away from the first bonding area S1, the third bonding area S3 is far away from the second bonding area S2 in space at this time, and the “island” structure can be selected. For another example, when the amount of glue overflow in the bonding area is large, the “island”+“bridge” or “island” form can be selected to enable the cavity area 220 to accommodate more glue and avoid affecting the functional area S0.

[0326] In an optional embodiment, as shown in FIG. 23, the pad 150 comprises a pad body and a protrusion 152 surrounding the pad body, and the opening region 151 is arranged on the pad body. Further, the protrusion 152 can be directly used as the first pad corresponding annular protrusion 251, or the first pad corresponding annular protrusion 251 can be arranged on the protrusion 152 surrounding the opening region. This pad structure is beneficial for the formation of the pad 150 on the wafer by sputtering or evaporation. In another optional embodiment, as shown in FIG. 23, the protrusion 152 is located at the center of the pad.

[0327] In an optional embodiment, as shown in FIG. 24, the pad 150 and the first annular protrusion 121 are arranged to have the same material and structure, so that the pad 150 and the protrusion 152 thereof can be formed in the same step and on the same layer as the first annular protrusion 121. Further, in an optional embodiment, the protrusion 152 on both sides of the pad 150 has the same height as the first annular protrusion 121 on the first bonding region S1, which is beneficial for improving the sealing performance when the wafer is pressed against the substrate.

[0328] In an optional embodiment, when the first annular protrusion 121 is metal, the pad 150 is short-circuited with the ground, as shown in FIG. 24, and the pad 150 is connected with the first annular protrusion 121 on the first bonding region S1 through the metal inside the wafer, which is beneficial for improving the electromagnetic shielding performance of the chip.

[0329] In the above technical solution, after alignment and pressing, the glue of the protruding first pad corresponding annular protrusion and / or the second pad corresponding annular protrusion is extruded to the outside of the first pad corresponding annular protrusion and / or the second pad corresponding annular protrusion. The extruded glue is in contact with at least one of the pad and the third bonding region.

[0330] Preferably, the glue can be filled in the first pad corresponding annular protrusion and / or the second pad corresponding annular protrusion by dispensing or printing.

[0331] Preferably, the number of turns of the first pad corresponding annular protrusion and / or the second pad corresponding annular protrusion can be set to multiple turns to further increase the air tightness. When the number of turns of the first pad corresponding annular protrusion and / or the second pad corresponding annular protrusion is set to multiple turns, in an optional embodiment, the glue can be further filled in the region between adjacent first pad corresponding annular protrusions or second pad corresponding annular protrusions to further increase the bonding strength.

[0332] In an optional embodiment, the adhesive flow to the functional area after bonding can be blocked by setting a substrate corresponding annular cofferdam on the substrate and / or the third bonding area of the wafer. The inner diameter of the substrate corresponding annular cofferdam is greater than the outer diameter of the first pad corresponding annular protrusion and the outer diameter of the second pad corresponding annular protrusion, so that after alignment and pressing, the annular cofferdam is located outside the first pad corresponding annular protrusion and the second pad corresponding annular protrusion, and plays a role in blocking the adhesive flow.

[0333] In an optional embodiment, the packaging method provided by the application comprises the following steps:

[0334] The substrate and the wafer are respectively placed in the bonding fixture, preferably, one with adhesive is placed on the lower side, and a separation layer is arranged between the two for separation;

[0335] The positions of the substrate and the chip are adjusted by the alignment machine, so that the wafer and the corresponding bonding area on the substrate one by one, wherein the first bonding area S1 corresponds to the second bonding area S2, and the third bonding area S3 corresponds to the pad 150, and the positions of the two are fixed by using the fixture lock;

[0336] The two are placed in the bonding machine, and vacuum is extracted between the two to achieve the required environment of the cavity. Optionally, after vacuum extraction, a characteristic gas is filled, such as inert gas (for example, N2 or Ar), heat-sensitive gas (for example, SF6), and macromolecular gas, etc.;

[0337] The wafer and the substrate are heated, so that the temperature reaches the temperature at which the adhesive has the best flowability; at the same time, the separation layer therebetween is extracted and pressure is applied, so that the adhesive of the protruding part is extruded and flows to the bonding area, and the two do not have a gap at the annular protrusion structure;

[0338] The temperature is heated to the curing temperature of the adhesive. During the curing process, the adhesive undergoes polycondensation reaction, resulting in a certain degree of shrinkage, generating a force that makes the wafer and the substrate relatively close, so that the annular protrusion structure can tightly adhere to the bonding object;

[0339] After the curing is completed, cooling is performed.

[0340] The application also provides a packaging structure packaged by using the above packaging method.

[0341] Referring to FIGS. 10d and 11-14, the chip packaging structure of the application comprises a first wafer 20, a substrate 10, an adhesive bonding layer, and at least two annular protrusions 121.

[0342] The first wafer 20 has a first surface, and the first surface has a functional area S0 and a first bonding area S1, and the first bonding area S1 is arranged around the functional area S0.

[0343] The substrate 10 has a second surface with a second bonding region S2, and a groove 11 is formed on the second surface and surrounded by the second bonding region S2. The second surface of the substrate 10 is arranged to abut the first surface of the first wafer 20, and the groove 11 corresponds to and covers the functional region S0, and the second bonding region S2 is bonded to the first bonding region S1.

[0344] It can be understood that the groove 11 can also not be provided in other embodiments.

[0345] The glue bonding layer is arranged between the first bonding region S1 and the second bonding region S2.

[0346] The plurality of first annular protrusions 121 are arranged on the second bonding region S2 and / or the first bonding region S1, and the plurality of first annular protrusions 121 are arranged in concentric rings, and part or all of the plurality of first annular protrusions 121 are located in the glue bonding layer.

[0347] In a preferred embodiment, the first annular protrusions 121 are selected from metal bumps to further improve the air tightness.

[0348] In another embodiment, as shown in FIG. 16, a ring-shaped cofferdam 21 is further included on the first bonding region S1 or the second bonding region S2 which is arranged to abut the top surface of the first annular protrusion 121 closest to the functional region S0. The ring-shaped cofferdam 21 is located between the innermost first annular protrusion 121 and the functional region S0. The height of the ring-shaped cofferdam 21 is arranged to partially overlap the first annular protrusion 121 in a direction parallel to the first surface of the first wafer 20, so as to block the glue from the fourth spacing region D in the innermost circle.

[0349] In an optional embodiment, the packaging structure includes a wafer, a substrate, and a via arranged thereon.

[0350] The wafer has a first surface and a second surface, and the first surface of the wafer includes a functional region, at least one pad arranged in or around the functional region, and a first bonding region surrounding the functional region, and the pad includes an opening region. The substrate has a first surface and a second surface, and the first surface of the substrate is arranged opposite to the first surface of the wafer, and includes a cavity region, a second bonding region, and a third bonding region, wherein the second bonding region corresponds to the first bonding region, the third bonding region corresponds to the pad, and the cavity region corresponds to and can encapsulate the functional region.

[0351] The first pad corresponds to a ring-shaped protrusion arranged on the pad and surrounding the opening region, and the second pad corresponds to a ring-shaped protrusion arranged on the third bonding region and corresponding to the opening region, and a polymer for bonding is arranged in the first pad corresponding ring-shaped protrusion and the second pad corresponding ring-shaped protrusion. The via is arranged on at least one of the second surface of the wafer and the second surface of the substrate, and corresponds to the opening region.

[0352] The application also provides a packaging structure, comprising a wafer, a substrate and a via disposed thereon.

[0353] The wafer comprises a plurality of chip units and has a first surface and a second surface, the first surface of the wafer comprises a functional region, at least one pad disposed in or around the functional region, and a first bonding region surrounding the functional region, the pad comprises an opening region. The substrate has a first surface and a second surface, the first surface of the substrate is disposed opposite to the first surface of the wafer, and comprises a cavity region, a second bonding region and a third bonding region, wherein the second bonding region corresponds to the first bonding region, the third bonding region corresponds to the pad, and the cavity region corresponds to the functional region and can encompass the functional region.

[0354] At least one first annular protrusion is located on the first bonding region of the wafer and / or disposed on the second bonding region of the substrate, a first spacing region is formed between the first annular protrusions on the first bonding regions of adjacent chip units, a second spacing region is formed between the first annular protrusions on the second bonding regions of adjacent chip units, and a polymer for bonding is disposed in at least one of the first spacing region and the second spacing region. The first pad corresponding annular protrusion is located on the pad and surrounds the opening region, the second pad corresponding annular protrusion is located on the third bonding region and corresponds to the opening region, and a polymer for bonding is disposed in the first pad corresponding annular protrusion and the second pad corresponding annular protrusion. The via is disposed on at least one of the second surface of the wafer and the second surface of the substrate and corresponds to the opening region.

[0355] The application also provides a packaging structure, comprising a wafer, a substrate and a via disposed thereon.

[0356] The wafer comprises a plurality of chip units and has a first surface and a second surface, the first surface of the wafer comprises a functional region, at least one pad disposed in or around the functional region, and a first bonding region surrounding the functional region, the pad comprises an opening region. The substrate has a first surface and a second surface, the first surface of the substrate is disposed opposite to the first surface of the wafer, and comprises a cavity region, a second bonding region and a third bonding region, wherein the second bonding region corresponds to the first bonding region, the third bonding region corresponds to the pad, and the cavity region corresponds to the functional region and can encompass the functional region.

[0357] At least two first annular protrusions are located on the first bonding region of the wafer and / or disposed on the second bonding region of the substrate, a fourth spacing region is formed between adjacent first annular protrusions, and a polymer for bonding is disposed in the fourth spacing region. The first pad corresponding annular protrusion is located on the pad and surrounds the opening region, the second pad corresponding annular protrusion is located on the third bonding region and corresponds to the opening region, and a polymer for bonding is disposed in the first pad corresponding annular protrusion and the second pad corresponding annular protrusion. The via is disposed on at least one of the second surface of the wafer and / or the second surface of the substrate and corresponds to the opening region.

[0358] In the above embodiments, glue is used for bonding between the first wafer and the second wafer or substrate, which can be a polymer bonding material with certain condensation reaction, such as thermosetting glue, for example, Epoxy-353nd of Epoxy Technology. It is also understood by those skilled in the art that any other material capable of achieving the bonding effect between the wafer and the substrate, such as a polymer, can also be used. Preferably, a polymer with less gas and moisture outgassing when solidified is selected as the bonding material to reduce the pollution of the cavity area.

[0359] Compared with the prior art, the semiconductor wafer-level packaging method and packaging structure of the present application can prevent the glue applied during bonding from polluting the functional area, and at the same time, prevent the applied glue from overflowing and affecting the functional area by controlling the amount of glue.

[0360] The semiconductor wafer-level packaging method and packaging structure of the present application can improve the air tightness and reliability of the chip packaging structure while maintaining the packaging bonding strength by the arrangement of the annular protrusion and the glue application mode, and can also prevent the bonding glue from affecting the functional area.

[0361] It is apparent to those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, but can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all respects as illustrative and not restrictive, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended to encompass all changes falling within the meaning and range of equivalents of the elements of the claims. Any reference signs in the claims should not be considered as limiting the claims involved.

[0362] In addition, it should be understood that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that those skilled in the art can understand.

[0363] The present application also includes the following technical solutions:

[0364] 1. A semiconductor wafer-level packaging method, comprising:

[0365] providing a first wafer having a plurality of chip units, each chip unit having a functional area and a first bonding area arranged around the functional area;

[0366] providing a second wafer or substrate having second bonding regions corresponding to the first bonding regions;

[0367] forming a first ring-shaped bump on the first bonding region of the chip unit, the first ring-shaped bump having a first spacing region between adjacent first ring-shaped bumps of the chip units, and / or forming at least one first ring-shaped bump on the second bonding region of the second wafer or substrate, the first ring-shaped bump having a second spacing region between adjacent first ring-shaped bumps of the second bonding regions;

[0368] filling the first spacing region and / or the second spacing region with glue, the glue protruding from a top surface of the first ring-shaped bump;

[0369] aligning and pressing the second wafer or substrate to the first wafer.

[0370] 2. The semiconductor wafer level packaging method of claim 1, wherein the amount of glue is controlled such that, after aligning and pressing the second wafer or substrate to the first wafer, the glue protruding from the top surface of the first ring-shaped bump is partially or entirely squeezed to a side of the first ring-shaped bump away from the first spacing region and / or the second spacing region.

[0371] 3. The semiconductor wafer level packaging method of claim 1, wherein the glue squeezed to the side of the first ring-shaped bump away from the first spacing region and / or the second spacing region at least contacts one of the first wafer and the second wafer or substrate; or

[0372] the glue squeezed to the side of the first ring-shaped bump away from the first spacing region and / or the second spacing region contacts both the first wafer and the second wafer or substrate.

[0373] 4. The semiconductor wafer level packaging method of claim 1, further comprising, before aligning and pressing the second wafer or substrate to the first wafer:

[0374] forming a second ring-shaped bump on the first bonding region of the chip unit and / or on the second bonding region of the second wafer or substrate.

[0375] 5. The semiconductor wafer level packaging method of claim 1, wherein:

[0376] an inner diameter of the second ring-shaped bump is smaller than an inner diameter of any first ring-shaped bump on the first bonding region or the second bonding region to which the second ring-shaped bump belongs;

[0377] the second ring-shaped bump and an adjacent first ring-shaped bump form a third spacing region therebetween.

[0378] 6. The semiconductor wafer level packaging method of claim 1, wherein the amount of glue is controlled such that, after aligning and pressing the second wafer or substrate to the first wafer, the glue protruding from the top surface of the first ring-shaped bump is only partially or entirely squeezed to the third spacing region.

[0379] 7. The semiconductor wafer level packaging method, wherein a first cutting region is formed between adjacent chip units, and the first cutting region is located in the first spacing region.

[0380] The second wafer or substrate has a second cutting region corresponding to the first cutting region, and the second cutting region is located in the second spacing region.

[0381] 8. A semiconductor wafer level packaging method, comprising:

[0382] providing a first wafer having one or more chip units, each chip unit having a functional region and a first bonding region arranged around the functional region;

[0383] providing a second wafer or substrate having a second bonding region corresponding to the first bonding region; forming at least two rings of first annular bumps on the first bonding region of the chip units, and / or forming at least two rings of first annular bumps on the second bonding region of the second wafer or substrate, and a fourth spacing region is formed between adjacent first annular bumps;

[0384] filling glue in the fourth spacing region, and the glue protrudes from the top surface of the first annular bumps;

[0385] aligning and pressing the second wafer or substrate with the first wafer.

[0386] 9. The semiconductor wafer level packaging method, wherein the amount of glue is controlled so that after aligning and pressing, the glue protruding from the top surface of the first annular bumps is squeezed to the side of the first annular bumps away from the fourth spacing region.

[0387] 10. The semiconductor wafer level packaging method, wherein the amount of glue is controlled so that after aligning and pressing, the glue protruding from the top surface of the first annular bumps is partially squeezed into the space between the top surface of the first annular bumps and the first bonding region or the second bonding region aligned therewith.

[0388] 11. The semiconductor wafer level packaging method, wherein when more than two rings of first annular bumps are formed, the amount of glue in the fourth spacing region close to the functional region is controlled to be less than or equal to the amount of glue in other fourth spacing regions.

[0389] 12. The semiconductor wafer level packaging method, wherein before aligning and pressing the second wafer or substrate with the first wafer, further comprising:

[0390] a step of arranging an annular cofferdam on the second bonding region of the second wafer or substrate and / or on the first bonding region of the first wafer.

[0391] 13. The semiconductor wafer level packaging method, wherein the inner diameter of the annular dam is smaller than the inner diameter of any first annular bump on the first bonding region or the second bonding region.

[0392] The annular dam is disposed on the first bonding region or the second bonding region which is aligned with the top surface of the innermost first annular bump.

[0393] 14. The semiconductor wafer level packaging method, wherein the method of forming the first annular bump comprises:

[0394] forming a layer structure;

[0395] forming a photoresist layer on the layer structure and patterning the photoresist layer to form an annular bump pattern;

[0396] transferring the annular bump pattern to the layer structure to form the annular bump; or,

[0397] the method of forming the first annular bump comprises:

[0398] forming a photoresist layer and patterning the photoresist layer to form an annular recess pattern;

[0399] forming a layer structure covering the annular recess pattern;

[0400] removing the annular recess pattern and the layer structure on the surface of the annular recess pattern to form the annular bump.

[0401] 15. The semiconductor wafer level packaging method, wherein the adhesive is filled by dispensing or printing.

[0402] 16. A semiconductor package structure, comprising:

[0403] a first chip having a first surface, the first surface having a functional region and a first bonding region disposed around the functional region;

[0404] a second chip or a substrate disposed on the first surface of the first chip, the second chip or the substrate having a second bonding region bonded to the first bonding region;

[0405] an adhesive bonding layer disposed between the first bonding region and the second bonding region; and

[0406] a first annular bump disposed on the first bonding region and / or the second bonding region and partially or entirely located in the adhesive bonding layer.

[0407] 17. The semiconductor package structure of claim 16, further comprising a second ring-shaped bump disposed on the first bonding region of the first chip and / or the second bonding region of the second chip or substrate, the second ring-shaped bump having an inner diameter smaller than that of any first ring-shaped bump disposed on the first bonding region or the second bonding region, and a third spacing region being formed between the second ring-shaped bump and a first ring-shaped bump adjacent to the second ring-shaped bump, and the third spacing region being partially or entirely filled with the glue bonding layer.

[0408] 18. The semiconductor package structure of claim 17, wherein the second ring-shaped bump has a height greater than or equal to that of the first ring-shaped bump.

[0409] 19. A semiconductor package structure, comprising:

[0410] a first chip having a first surface, the first surface having a functional region and a first bonding region disposed around the functional region;

[0411] a second chip or substrate disposed on the first surface of the first chip, the second chip or substrate having a second bonding region bonded to the first bonding region;

[0412] at least two turns of first ring-shaped bumps disposed on the first bonding region of the first chip and / or the second bonding region of the second chip or substrate, and a fourth spacing region being formed between adjacent first ring-shaped bumps, and the fourth spacing region being filled with glue, and the glue extending from the fourth spacing region into at least part of a space between a top surface of the first ring-shaped bump and the first bonding region or the second bonding region positioned opposite to the top surface.

[0413] 20. The semiconductor package structure of claim 19, further comprising a ring-shaped coffer disposed on the first bonding region or the second bonding region positioned opposite to a top surface of the first ring-shaped bump disposed closest to the functional region.

[0414] It should be noted that the embodiments herein are described in a progressive manner in the specification, and each embodiment focuses on the differences from other embodiments, and the same or similar parts of each embodiment can be mutually referred to. For the method disclosed in the embodiments, since it corresponds to the system disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the system.

Claims

A semiconductor wafer level packaging method characterized by, The method comprises: providing a first wafer having a plurality of chip units, each of the chip units having a functional region and a first bonding region arranged around the functional region; providing a second wafer or substrate having a second bonding region corresponding to the first bonding region; forming at least one ring of first protrusions on the first bonding region of the chip units, the first protrusions of adjacent chip units having a first spacing region therebetween, and / or forming at least one ring of first protrusions on the second bonding region of the second wafer or substrate, the first protrusions of adjacent second bonding regions having a second spacing region therebetween; filling a polymer that functions as a bonding agent in the first spacing region and / or in the second spacing region, the polymer protruding from a top surface of the first protrusions; aligning and pressing the second wafer or substrate to the first wafer. The semiconductor wafer-level packaging method according to claim 1, wherein the amount of the polymer is controlled such that, after aligning and pressing, the polymer protruding from the top surface of the first protrusions is partially or entirely extruded to a side of the first protrusions away from the first spacing region and / or the second spacing region. The semiconductor wafer-level packaging method according to claim 2, wherein the polymer extruded to the side of the first protrusions away from the first spacing region and / or the second spacing region is in contact with at least one of the first wafer and the second wafer or substrate; or the polymer extruded to the side of the first protrusions away from the first spacing region and / or the second spacing region is in contact with both the first wafer and the second wafer or substrate. Before aligning and pressing the second wafer or substrate to the first wafer, the method further comprises: forming a second ring of protrusions on the first bonding region of the chip units and / or on the second bonding region of the second wafer or substrate. The semiconductor wafer level packaging method according to claim 1, wherein The semiconductor wafer-level packaging method according to claim 4, wherein an inner diameter of the second ring of protrusions is smaller than an inner diameter of any of the first protrusions on the first bonding region or the second bonding region to which the second ring of protrusions belongs; a third spacing region is formed between the second ring of protrusions and the first protrusions adjacent to the second ring of protrusions. The semiconductor wafer-level packaging method according to claim 5, wherein the amount of the polymer is controlled such that, after aligning and pressing, the polymer protruding from the top surface of the first protrusions is partially or entirely extruded into the third spacing region. The semiconductor wafer-level packaging method according to claim 1, wherein a first dicing region is formed between adjacent chip units, the first dicing region being located in the first spacing region; the second wafer or substrate has a second dicing region corresponding to the first dicing region, the second dicing region being located in the second spacing region. The semiconductor wafer-level packaging method according to claim 1, wherein the polymer comprises glue. The semiconductor wafer-level packaging method according to claim 1, wherein ​ ​ The connecting part is arranged inside the first bonding area or the second bonding area to which the first annular protrusion belongs and is electrically connected with the two adjacent first annular protrusions. The semiconductor wafer packaging method according to claim 1, wherein, The inner diameter of the first annular protrusion formed on the first bonding area is different from the inner diameter of the first annular protrusion formed on the second bonding area. A semiconductor wafer level packaging method characterized by, The semiconductor wafer packaging method according to claim 1, wherein, A first wafer having one or more chip units is provided, each of the chip units having a functional area and a first bonding area arranged around the functional area; A second wafer or substrate having a second bonding area corresponding to the first bonding area is provided; At least two annular protrusions are formed on the first bonding area of the chip units and / or at least two annular protrusions are formed on the second bonding area of the second wafer or substrate, and a fourth spacing area is formed between the adjacent first annular protrusions; A polymer for bonding is filled in the fourth spacing area, and the polymer protrudes from the top surface of the first annular protrusion; and The second wafer or substrate is aligned and pressed against the first wafer. The semiconductor wafer packaging method according to claim 11, wherein, The amount of the polymer is controlled so that, after the alignment and pressing, the polymer protruding from the top surface of the first annular protrusion is extruded to the side of the first annular protrusion away from the fourth spacing area. The semiconductor wafer packaging method according to claim 11, wherein, The amount of the polymer is controlled so that, after the alignment and pressing, the polymer protruding from the top surface of the first annular protrusion is partially extruded into the space between the top surface of the first annular protrusion and the first bonding area or the second bonding area aligned with the top surface. The semiconductor wafer packaging method according to claim 11, wherein, When more than two annular protrusions are formed, the amount of the polymer in the fourth spacing area close to the functional area is controlled to be less than or equal to the amount of the polymer in the other fourth spacing areas. The semiconductor wafer packaging method according to claim 11, wherein, Before the second wafer or substrate is aligned and pressed against the first wafer, the method further comprises: A step of arranging a first annular cofferdam on the second bonding area of the second wafer or substrate and / or on the first bonding area of the first wafer. The semiconductor wafer packaging method according to claim 15, wherein, The inner diameter of the first annular cofferdam is smaller than the inner diameter of any of the first annular protrusions on the first bonding area or the second bonding area to which the first annular cofferdam belongs; The first annular cofferdam is arranged on the first bonding area or the second bonding area aligned with the top surface of the innermost annular protrusion. The semiconductor wafer packaging method according to claim 11, wherein, The polymer comprises glue. The semiconductor wafer packaging method according to claim 11, wherein, The connecting part is arranged inside the first bonding area or the second bonding area to which the first annular protrusion belongs and is electrically connected with the two adjacent first annular protrusions. The semiconductor wafer packaging method according to claim 11, wherein The inner diameter of the first annular protrusion formed on the first bonding area is different from the inner diameter of the first annular protrusion formed on the second bonding area. A semiconductor wafer level packaging method characterized by, The semiconductor wafer packaging method according to claim 20, wherein A wafer with a plurality of chip units is provided, each of the chip units comprising a functional area, at least one pad arranged in or around the functional area, and a first bonding area surrounding the functional area, the pad comprising an opening area; A substrate is provided, the substrate comprising a cavity area, a second bonding area and a third bonding area, wherein the second bonding area corresponds to the first bonding area, the third bonding area corresponds to the pad, and the cavity area corresponds to the functional area and can encompass the functional area; A first pad corresponding annular protrusion is formed on the pad, surrounding the opening area, and / or a second pad corresponding annular protrusion is formed on the pad opposite the third bonding area, corresponding to the opening area; A polymer for bonding is filled in the first pad corresponding annular protrusion, the top surface of the polymer being higher than the top surface of the first pad corresponding annular protrusion, and / or a polymer for bonding is filled in the second pad corresponding annular protrusion, the top surface of the polymer being higher than the top surface of the second pad corresponding annular protrusion; The substrate and the wafer are aligned and pressed together; And A via hole corresponding to the opening area is arranged on at least one of the wafer and the substrate, so that the opening area is exposed to the environment outside the chip unit. The semiconductor wafer packaging method according to claim 20, wherein The third bonding area forms an island structure on the second bonding area. The semiconductor wafer packaging method according to claim 20, wherein The third bonding area forms an island structure outside the second bonding area. The semiconductor wafer packaging method according to claim 22, wherein The island structure is connected to the second bonding area through a bridge structure. The semiconductor wafer packaging method according to claim 20, wherein A predetermined width of overflow area is left around the second bonding area and the third bonding area in the cavity area, and after the alignment and pressing, the polymer can be squeezed into the overflow area. The semiconductor wafer packaging method according to claim 20, wherein An overflow area is arranged between the adjacent chip units, and after the alignment and pressing, the polymer can be squeezed into the overflow area. The semiconductor wafer packaging method according to claim 21, wherein Before the substrate and the wafer are aligned and pressed together, the method further comprises: A substrate corresponding annular weir is arranged on the substrate and / or the third bonding area of the wafer, the inner diameter of the substrate corresponding annular weir being greater than the outer diameter of the first pad corresponding annular protrusion and the outer diameter of the second pad corresponding annular protrusion. A semiconductor wafer level packaging method characterized by, comprising providing a wafer having a plurality of chip units, each of the chip units comprising a functional region, at least one pad disposed within or around the functional region, and a first bonding region surrounding the functional region, wherein the pad comprises an opening region; providing a substrate comprising a cavity region, a second bonding region, and a third bonding region, wherein the second bonding region corresponds to the first bonding region, the third bonding region corresponds to the pad, and the cavity region corresponds to and is capable of encompassing the functional region; forming at least one ring of first annular bumps on the first bonding region, the first annular bumps of adjacent chip units having a first spacing region therebetween, and / or forming at least one ring of first annular bumps on the second bonding region, the first annular bumps of adjacent second bonding regions having a second spacing region therebetween; forming a first pad corresponding annular bump on the pad, the first pad corresponding annular bump surrounding the opening region, and / or forming a second pad corresponding annular bump on the pad opposite the third bonding region, the second pad corresponding annular bump corresponding to the opening region; filling a polymer that is keying in the first spacing region and / or in the second spacing region, the polymer having a top surface that is higher than a top surface of the first annular bumps; filling a polymer that is keying in the first pad corresponding annular bump, the polymer having a top surface that is higher than a top surface of the first pad corresponding annular bump, and / or filling a polymer that is keying in the second pad corresponding annular bump, the polymer having a top surface that is higher than a top surface of the second pad corresponding annular bump; aligning and pressing the substrate and the wafer together; and providing a via on at least one of the wafer and the substrate that corresponds to the opening region, the opening region being exposed to an environment outside of the chip units. The semiconductor wafer level packaging method of claim 27, wherein at least one of the pads is electrically connected to the first annular bumps on the first bonding region. The semiconductor wafer level packaging method of claim 27, wherein at least one of the first pad corresponding annular bumps is connected to the first annular bumps on the first bonding region. The semiconductor wafer level packaging method of claim 27, wherein at least one of the second pad corresponding annular bumps is connected to the first annular bumps on the second bonding region. The semiconductor wafer level packaging method of claim 27, wherein the pad comprises a pad body and a protrusion surrounding the pad body, the opening region is disposed on the pad body, and the first pad corresponding annular bump is disposed on the protrusion, the first pad corresponding annular bump having the same height as the first annular bumps on the first bonding region. comprising A semiconductor wafer level packaging method characterized by, providing a wafer having a plurality of chip units, each of the chip units comprising a functional region, at least one pad disposed within or around the functional region, and a first bonding region surrounding the functional region, wherein the pad comprises an opening region; ​ A substrate is provided, which includes a cavity region, a second bonding region and a third bonding region, wherein the second bonding region corresponds to the first bonding region, the third bonding region corresponds to the pad, and the cavity region corresponds to and can encompass the functional region; At least two circles of first annular protrusions are formed on the first bonding region of the chip unit, and / or at least two circles of first annular protrusions are formed on the second bonding region of the substrate, and a fourth spacing region is formed between adjacent first annular protrusions; A first pad corresponding annular protrusion is formed on the pad, which surrounds the opening region, and / or a second pad corresponding annular protrusion is formed on the opposite third bonding region of the pad, which corresponds to the opening region; A polymer for bonding is filled in the fourth spacing region, and the top surface of the polymer is higher than the top surface of the first annular protrusion; A polymer for bonding is filled in the first pad corresponding annular protrusion, and the top surface of the polymer is higher than the top surface of the first pad corresponding annular protrusion, and / or a polymer for bonding is filled in the second pad corresponding annular protrusion, and the top surface of the polymer is higher than the top surface of the second pad corresponding annular protrusion; The substrate is aligned and pressed with the wafer; And A via hole corresponding to the opening region is arranged on at least one of the wafer and the substrate, so that the opening region is exposed to the environment outside the chip unit. The semiconductor wafer level packaging method according to claim 32, wherein At least one of the pads is electrically connected with the first annular protrusion on the first bonding region. The semiconductor wafer level packaging method according to claim 32, wherein At least one of the first pad corresponding annular protrusions is connected with the first annular protrusion on the first bonding region. The semiconductor wafer level packaging method according to claim 32, wherein At least one of the second pad corresponding annular protrusions is connected with the first annular protrusion on the second bonding region. The semiconductor wafer level packaging method according to claim 32, wherein The pad includes a pad body and a protruding part surrounding the pad body, the opening region is arranged on the pad body, and the first pad corresponding annular protrusion is arranged on the protruding part and has the same height as the first annular protrusion on the first bonding region. The semiconductor wafer level packaging method according to claim 1 or 11, characterized in that, The method for forming the first annular protrusion includes: forming a layer structure; forming a photoresist layer on the layer structure and patterning to form an annular protrusion pattern; transferring the annular protrusion pattern to the layer structure to form the annular protrusion; or The method for forming the first annular protrusion includes: forming a photoresist layer and patterning to form an annular recess pattern; forming a layer structure covering the annular recess pattern; removing the annular recess pattern while removing the layer structure on the surface of the annular recess pattern to form the annular protrusion. The semiconductor wafer level packaging method according to claim 37, wherein The polymer is filled by dispensing or printing. The semiconductor wafer level packaging method according to any one of claims 20, 27 and 32, wherein The method for forming the first annular protrusion, the first pad corresponding annular protrusion and the second pad corresponding annular protrusion includes: forming a layer structure; forming a photoresist layer on the layer structure and patterning the photoresist layer to form a ring-shaped protrusion pattern; transferring the ring-shaped protrusion pattern to the layer structure to form the ring-shaped protrusion; or the method for forming the ring-shaped protrusion comprises: forming a photoresist layer and patterning the photoresist layer to form a ring-shaped recess pattern; forming a layer structure covering the ring-shaped recess pattern; removing the ring-shaped recess pattern while removing the layer structure on the surface of the ring-shaped recess pattern to form the ring-shaped protrusion. The semiconductor wafer level packaging method according to claim 39, wherein filling the polymer by dispensing or printing. A semiconductor package structure characterized by comprises: a first chip having a first surface, the first surface having a functional area and a first bonding area arranged around the functional area; a second chip or substrate arranged on the first surface of the first chip, the second chip or substrate having a second bonding area bonded with the first bonding area; a glue bonding layer arranged between the first bonding area and the second bonding area; and a first ring-shaped protrusion arranged on the first bonding area and / or the second bonding area and partially or entirely located in the glue bonding layer. The semiconductor package structure of claim 41, wherein further comprising a second ring-shaped protrusion arranged on the first bonding area of the first chip and / or the second bonding area of the second chip or substrate, an inner diameter of the second ring-shaped protrusion being smaller than an inner diameter of any of the first ring-shaped protrusions on the first bonding area or the second bonding area to which the second ring-shaped protrusion belongs, a third spacing area being formed between the second ring-shaped protrusion and a first ring-shaped protrusion adjacent to the second ring-shaped protrusion, the third spacing area being partially or entirely provided with the glue bonding layer. The semiconductor package structure of claim 41, wherein a height of the second ring-shaped protrusion is greater than or equal to a height of the first ring-shaped protrusion. A semiconductor package structure characterized by comprises: a first chip having a first surface, the first surface having a functional area and a first bonding area arranged around the functional area; a second chip or substrate arranged on the first surface of the first chip, the second chip or substrate having a second bonding area bonded with the first bonding area; at least two turns of first ring-shaped protrusions arranged on the first bonding area of the first chip and / or arranged on the second bonding area of the second chip or substrate, a fourth spacing area being formed between adjacent first ring-shaped protrusions, the fourth spacing area being provided with a polymer, the polymer extending from the fourth spacing area to at least part of a space between a top surface of the first ring-shaped protrusion and the first bonding area or the second bonding area opposite to the top surface. The semiconductor package structure of claim 44, wherein further comprising a ring-shaped cofferdam arranged on the first bonding area or the second bonding area opposite to a top surface of the first ring-shaped protrusion arranged closest to the functional area. A semiconductor package structure characterized by comprises a wafer having a first surface and a second surface, the first surface of the wafer comprising a functional area, at least one pad arranged in or around the functional area, and a first bonding area arranged around the functional area, the pad comprising an opening area; a substrate having a first surface and a second surface, the first surface of the substrate being oppositely arranged to the first surface of the wafer, comprising a cavity region, a second bonding region and a third bonding region, wherein the second bonding region corresponds to the first bonding region, the third bonding region corresponds to the pad, and the cavity region corresponds to the functional region and is capable of encompassing the functional region; at least one of a first pad corresponding annular protrusion and a second pad corresponding annular protrusion, wherein the first pad corresponding annular protrusion is located on the pad and surrounds the opening region, the second pad corresponding annular protrusion is located on the third bonding region and corresponds to the opening region, and a polymer for bonding is arranged in the first pad corresponding annular protrusion and the second pad corresponding annular protrusion; and a via hole arranged on the second surface of the wafer and / or the second surface of the substrate and corresponding to the opening region. The semiconductor package structure according to claim 46, wherein the third bonding region forms an island structure outside the second bonding region. The semiconductor package structure according to claim 46, wherein the third bonding region forms an island structure outside the second bonding region. The semiconductor package structure according to claim 48, wherein the island structure is connected to the second bonding region through a bridge structure. A semiconductor package structure characterized by The semiconductor package structure according to claim 49, wherein the first pad corresponding annular protrusion and the second pad corresponding annular protrusion are arranged on the pad and the third bonding region, respectively, and a polymer for bonding is arranged in the first pad corresponding annular protrusion and the second pad corresponding annular protrusion. The semiconductor package structure according to claim 49, wherein at least one of the first pad corresponding annular protrusion and the second pad corresponding annular protrusion is arranged on the pad and the third bonding region, respectively, and a polymer for bonding is arranged in the first pad corresponding annular protrusion and the second pad corresponding annular protrusion. The semiconductor package structure according to claim 49, wherein the first pad corresponding annular protrusion and the second pad corresponding annular protrusion are arranged on the pad and the third bonding region, respectively, and a polymer for bonding is arranged in the first pad corresponding annular protrusion and the second pad corresponding annular protrusion. The semiconductor package structure according to claim 49, wherein at least one of the first pad corresponding annular protrusion and the second pad corresponding annular protrusion is arranged on the pad and the third bonding region, respectively, and a polymer for bonding is arranged in the first pad corresponding annular protrusion and the second pad corresponding annular protrusion. The semiconductor package structure according to claim 50, wherein at least one of the first pad corresponding annular protrusion and the second pad corresponding annular protrusion is arranged on the pad and the third bonding region, respectively, and a polymer for bonding is arranged in the first pad corresponding annular protrusion and the second pad corresponding annular protrusion. The semiconductor package structure of claim 50, wherein At least one of the first pad corresponding annular protrusions is connected to the first annular protrusions on the first bonding region. The semiconductor package structure of claim 50, wherein At least one of the second pad corresponding annular protrusions is connected to the first annular protrusions on the second bonding region. The semiconductor package structure of claim 50, wherein The pad comprises a pad body and a protruding portion surrounding the pad body, the opening region is disposed on the pad body, and the pad corresponding annular protrusion is disposed on the protruding portion and has the same height as the first annular protrusions on the first bonding region. A semiconductor package structure characterized by The semiconductor package structure of claim 55, wherein The semiconductor package structure of claim 55, wherein At least one of the first pad corresponding annular protrusions is connected to the first annular protrusions on the first bonding region. The semiconductor package structure of claim 55, wherein At least one of the second pad corresponding annular protrusions is connected to the first annular protrusions on the second bonding region. The semiconductor package structure of claim 55, wherein The pad comprises a pad body and a protruding portion surrounding the pad body, the opening region is disposed on the pad body, and the pad corresponding annular protrusion is disposed on the protruding portion and has the same height as the first annular protrusions on the first bonding region. ​ ​ ​ ​ ​ ​ ​

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