A method for stabilizing double-loop operating point and an electrocardiosignal acquisition front end
Patent Information
- Application Number
- CN202611213595.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-11
- Publication Date
- 2026-10-30
AI Technical Summary
[0005]本发明的目的在于提供一种心电信号采集前端及双环工作点稳定方法,以解决OECT心电采集前端中后级放大链路基线漂移和OECT器件工作点偏移相互叠加、容易导致信号饱和和长期采集不稳定的问题
[0012]本发明的机制性技术效果在于:相比仅采用后级高通或积分反馈,本方案能够在不直接改变心电有效波形窗口内OECT偏置的情况下,使OECT器件工作点回到目标区间;相比仅采用数字偏置调节,本方案通过模拟环路先防止仪表放大器饱和,降低数字环路误跟踪心电低频成分的概率。由此,模拟环路先稳后级,数字环路慢速回调OECT工作点,且数字更新避开心电有效事件和模拟环路暂态。
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Figure CN122997701A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of cross-disciplinary technology of bioelectrical signal acquisition and organic electrochemical transistor interface circuits, and particularly to a front-end for electrocardiogram signal acquisition and a method for stabilizing the dual-loop operating point. Background Technology
[0002] Organic electrochemical transistors (OECTs) possess advantages such as low operating voltage, high transconductance, ion-electron hybrid conduction, and suitability for biological interface coupling, and have been used for acquiring physiological electrical signals such as electrocardiograms (ECGs), electroencephalograms (EEGs), and electromyograms (EMGs). However, simply using OECTs for ECG signal recording is not the only innovative point emphasized in this invention.
[0003] In actual ECG acquisition, the OECT front end usually faces two different levels of drift problems at the same time: First, the slow DC drift introduced by the OECT device and the biological interface will enter the subsequent amplification link, causing the output baseline of the instrumentation amplifier to shift or even saturate; Second, the operating point of the OECT device itself will deviate from the high transconductance or linear operating region with changes in electrochemical reactions, ion migration, hydrogel water content, human contact state and bias conditions.
[0004] If only high-pass filtering or integral feedback is used in the later stage, although the output baseline of the amplification link can be pulled back to the ADC input range, the transconductance and linear operating point of the OECT device itself cannot be restored. If only digital bias adjustment is used, the adjustment action will directly change the bias of the OECT device, which may easily misinterpret the effective low-frequency components of the ECG or the QRS complex as operating point drift and cause waveform disturbances. Therefore, a dual-loop cooperative stabilization scheme with time-scale separation and interlocking constraints is needed. Summary of the Invention
[0005] The purpose of this invention is to provide a front-end for ECG signal acquisition and a method for stabilizing the dual-loop operating point, so as to solve the problem that the baseline drift of the post-amplification link and the offset of the OECT device operating point in the OECT ECG acquisition front-end can be superimposed, which can easily lead to signal saturation and long-term acquisition instability.
[0006] To achieve the above objectives, the present invention provides an electrocardiogram (ECG) signal acquisition front end, including an OECT front end sensor, a signal processing circuit, an operating point acquisition circuit, an adjustable bias generation circuit, and a control unit; the OECT front end sensor includes at least two input OECT devices and at least one bias / tail end OECT device.
[0007] The operating point voltage of the operating point acquisition circuit includes at least one of the following: OECT output common-mode voltage, source-drain operating voltage, common source node voltage, and tail bias node voltage; the OECT bias terminal of the OECT front-end sensor includes at least one of the following: VDD, VSS, Vbias, and Vref.
[0008] The signal processing circuit includes an input coupling and filtering unit, an instrumentation amplification unit, an integral feedback unit, a second-order low-pass filter unit, and a voltage follower and output buffer unit. The output of the integral feedback unit is connected to the reference terminal, compensation terminal, or equivalent bias terminal of the instrumentation amplification unit to form an analog low-frequency drift suppression loop. The operating point acquisition circuit, the control unit, and the adjustable bias generation circuit form a digital operating point adjustment loop that acts on the OECT bias terminal.
[0009] The core of this invention is not simply to place two feedback loops in parallel, but to give the two loops a clear division of labor in terms of frequency band and time scale, and to ensure that the digital bias update is constrained by the stable state of the analog loop and the effective waveform window of the electrocardiogram; the time constant of the analog low-frequency drift suppression loop can be 0.5s to 60s, preferably 1s to 20s; the update cycle of the digital operating point adjustment loop can be 5s to 300s, preferably 10s to 60s.
[0010] The conditions for digital bias updates include: the output change rate of the integral feedback unit is lower than a preset threshold, the sampled values of N consecutive operating points deviate from the target operating range, and no QRS complex is detected in the current sampling window, where N is an integer greater than or equal to 2; if the above conditions are not met, the control unit prohibits, delays, or limits the updating of the adjustable bias voltage.
[0011] Both input OECT devices and the bias / tail OECT device can employ a stacked structure of OECT devices. This OECT device uses a combination of a gDPP-g2T channel layer, an Ag / AgCl gate, and a hydrogel / electrolyte layer. The gDPP-g2T channel forms a P-type organic electrochemical transistor channel, the Ag / AgCl gate provides a relatively stable electrochemical gate interface, and the hydrogel / electrolyte layer forms an ion conduction path between the physiological potential, the gate, and the channel.
[0012] The key technical advantages of this invention are as follows: Compared to using only high-pass or integral feedback in the later stage, this solution can bring the OECT device's operating point back to the target range without directly changing the OECT bias within the effective ECG waveform window; compared to using only digital bias adjustment, this solution prevents instrumentation amplifier saturation through the analog loop, reducing the probability of the digital loop mistracking low-frequency ECG components. Thus, the analog loop stabilizes the later stage first, the digital loop slowly reverts to the OECT operating point, and the digital update avoids effective ECG events and analog loop transients. Attached Figure Description
[0013] Figure 1 This is a system overall structure block diagram provided in the embodiments of the present invention; Figure 2 This is a schematic diagram of the cross-sectional structure of a single OECT device provided in an embodiment of the present invention; Figure 3 A schematic diagram of the structure of the OECT device, the three-tube OECT sensor, and the external PCB / FPC flexible connection board provided in the embodiments of the present invention; Figure 4 This is a schematic diagram of the signal processing circuit structure provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the dynamic power supply and operating point acquisition circuit structure provided in an embodiment of the present invention; Explanation of reference numerals in the attached figures: 100. OECT device; 101. Flexible substrate; 102. Au source; 103. Au drain; 104. gDPP-g2T channel layer; 105. Au gate bottom or Au gate connection layer; 106. Ag / AgCl gate; 107. Hydrogel / electrolyte layer; 108. Overall encapsulation layer; 200. Three-tube OECT sensor; 201. First OECT device / M1 input OECT; 202. Second OECT device / M2 input OECT; 203. Third OECT device / M5 tail current OECT; 204. Common source node; 205. OUT+ output terminal; 206. OUT- output terminal; 207. ECG+ input terminal; 208. ECG- input terminal; 209. 210. Vbias input terminal; 211. VSS / tail bias terminal; 212. Au external connection pad; 213. Conductive silver paste; 214. UV fixing adhesive; 215. Copper wire; 300. External PCB / FPC flexible connection board; 301. PCB / FPC substrate; 302. R3 resistor load interface; 303. R4 resistor load interface; 304. Copper wire solder joint on PCB; 400. Signal processing circuit; 401. Input coupling and filtering; 402. Instrumentation amplification unit; 403. Integral feedback unit; 404. Second-order low-pass filter unit; 405. Voltage follower and output buffer unit; 406. OECT operating point voltage acquisition; 501. Multi-channel digital-to-analog converter circuit; 502. Polarity mapping circuit. Detailed Implementation
[0014] The technical solution of the present invention will be described below with reference to the accompanying drawings. It should be understood that the described embodiments are only for explaining the present invention and are not intended to limit the scope of protection of the present invention. Where there is no conflict, the technical features of the various embodiments can be combined with each other.
[0015] An electrocardiogram (ECG) signal acquisition front-end includes an OECT front-end sensor, a signal processing circuit 400, an operating point acquisition circuit, an adjustable bias generation circuit, and a control unit. The OECT front-end sensor includes at least two input OECT devices and at least one bias / tail-end OECT device for acquiring and initially amplifying ECG signals. The signal processing circuit 400 includes an input coupling and filtering unit 401, an instrumentation amplification unit 402, an integral feedback unit 403, a second-order low-pass filter unit 404, and a voltage follower and output buffer unit 405. The output of the integral feedback unit 403 is connected to the reference terminal, compensation terminal, or equivalent terminal of the instrumentation amplification unit 402. The control unit, the operating point acquisition circuit, and the adjustable bias generation circuit form a digital operating point adjustment loop. The control unit is configured to acquire the operating point voltage of the OECT front-end sensor, and to provide at least one adjustable bias voltage to the OECT bias terminal of the OECT front-end sensor. Furthermore, the control unit is only allowed to update the adjustable bias voltage when the output change rate of the integral feedback unit 403 is lower than a preset threshold, N consecutive operating point sample values deviate from the target operating range, and no QRS complex is detected in the current sampling window. Here, N is an integer greater than or equal to 2.
[0016] like Figure 1 As shown, the system in this embodiment includes host computer software and a hardware acquisition terminal. The host computer software is developed based on the Qt 6 framework and runs on the Android 14 operating system. It is used to implement device scanning and connection, ADC data reception and buffering, ECG waveform display, operating point parameter display, and DAC bias voltage transmission. The hardware acquisition terminal uses an nRF54L15 microcontroller to complete ECG signal acquisition, operating point voltage acquisition, digital filtering, QRS group detection, and Bluetooth Low Energy communication. It also uses an MCP4728 multi-channel digital-to-analog converter to generate an adjustable OECT bias voltage. The host computer software interacts with the hardware acquisition terminal via Bluetooth Low Energy for data and control commands. The above software platform and hardware model are only used to illustrate one possible implementation and do not constitute a limitation on the scope of protection of this invention.
[0017] like Figure 2 As shown, the OECT device 100 includes a flexible substrate 101, an Au source 102, an Au drain 103, a gDPP-g2T channel layer 104, an Au gate bottom or Au gate connection layer 105, an Ag / AgCl gate 106, a hydrogel / electrolyte layer 107, and an overall encapsulation layer 108.
[0018] A typical fabrication process includes: ultrasonically cleaning the flexible substrate 101 sequentially with deionized water, acetone, isopropanol, or ethanol, followed by rinsing with deionized water, drying with nitrogen, and drying at 60°C to 100°C, preferably at 80°C; then activating the substrate surface with UV ozone or oxygen plasma treatment; depositing a Cr / Au metal layer under a vacuum of no more than 1.5 × 10^-3 Pa, wherein the Cr adhesion layer has a thickness of 2 nm to 10 nm and the Au electrode layer has a thickness of 40 nm to 120 nm; forming a gDPP-g2T channel layer 104, an Ag / AgCl gate 106, and a hydrogel / electrolyte layer 107; and finally depositing a Parylene or other monolithic encapsulation layer 108 to form a sensing window and external connection pad openings.
[0019] like Figure 3 As shown, the OECT front-end sensor may include at least two input OECT devices and at least one bias / tail OECT device. Figure 3 The diagram illustrates a specific implementation of the three-transistor OECT sensor 200, where the first OECT device / M1 input OECT 201 and the second OECT device / M2 input OECT 202 form a differential input pair, and the third OECT device / M5 tail current OECT 203 serves as a bias / tail-end OECT device. In another embodiment, the resistive load can be replaced with an equivalent OECT load to form a five-transistor OECT front-end structure.
[0020] like Figure 4 As shown, the signal processing circuit 400 includes an input coupling and filtering unit 401, an instrumentation amplification unit 402, an integral feedback unit 403, a second-order low-pass filter unit 404, a voltage follower and output buffer unit 405, and an OECT operating point voltage acquisition unit 406. The equivalent cutoff frequency of the integral feedback unit 403 can be set below the main ECG frequency band, for example, below 0.5Hz or a set value within the range of 0.05Hz to 0.5Hz, and its equivalent time constant can be from 0.5s to 60s. This analog loop operates continuously or quasi-continuously to pull the output baseline of the instrumentation amplification unit back to the ADC input range to prevent saturation of the subsequent stage, but it does not directly change the source-drain bias or gate bias of the OECT device.
[0021] like Figure 5As shown, the adjustable bias generation circuit includes a multi-channel digital-to-analog converter circuit 501 and a polarity mapping circuit 502. The multi-channel digital-to-analog converter circuit 501 outputs multiple analog voltages; the polarity mapping circuit 502 is composed of a voltage follower, an inverting amplifier, a level shifter circuit, or a combination thereof, and is used to map the multiple digital-to-analog converter voltages into positive and negative bias voltages such as VDD, VSS, Vbias, and Vref. The update cycle of the digital operating point adjustment loop can be from 5s to 300s, and its operating frequency is lower than the equivalent response frequency of the analog low-frequency drift suppression loop.
[0022] A dual-loop operating point stabilization method applied to the front end of electrocardiogram (ECG) signal acquisition includes: a control unit acquiring the OECT operating point voltage at a predetermined sampling period. The operating point voltage includes at least one of the OECT output common-mode voltage, source-drain operating voltage, common source node voltage, and tail bias node voltage. The control unit calculates the mean or median of N consecutive sampled values, where N is an integer greater than or equal to 2. When all N consecutive sampled values deviate from the target operating range, and the output change rate of the integral feedback unit 403 is lower than a preset threshold, and no QRS complex is detected in the current sampling window, the control unit allows the bias voltage to be updated. After each bias update, a stabilization waiting time is set, for example, 5s to 120s. During the stabilization waiting time, the next bias update is paused or the update step size is reduced.
[0023] Because the analog low-frequency drift suppression loop and the digital operating point adjustment loop differ in their operating nodes, time scales, and interlocking conditions, they are not simply superimposed. The analog loop processes the signal link baseline, bringing the ECG waveform into the sampleable range of subsequent stages; the digital loop processes the device operating point, bringing the OECT back to the target bias range. Without the analog loop, the digital loop cannot quickly prevent the instrumentation amplifier from saturating; without the digital loop, the analog loop cannot restore the transconductance and linear region of the OECT device itself; without interlocking constraints, the digital loop may misadjust the bias by following the transient output of the analog loop or valid ECG events.
Claims
1. An electrocardiogram (ECG) signal acquisition front-end, comprising an OECT front-end sensor, a signal processing circuit (400), an operating point acquisition circuit, an adjustable bias generation circuit, and a control unit, characterized in that, The OECT front-end sensor includes two input OECT devices for acquiring and amplifying ECG signals and a bias / tail OECT device for providing tail bias or bias current, and has a differential output terminal connected to the signal processing circuit (400); the signal processing circuit (400) includes an input filtering unit (401), an instrumentation amplification unit (402), an integral feedback unit (403), a low-pass filtering unit (404), and a voltage follower and level conditioning unit (405) connected in sequence; the output of the integral feedback unit (403) is connected to the reference terminal, compensation terminal, or equivalent bias terminal of the instrumentation amplification unit (402) to form an analog low-frequency drift suppression loop; The operating point acquisition circuit is used to acquire the operating point voltage of the OECT front-end sensor, and the adjustable bias generation circuit is used to provide at least one adjustable bias voltage to the OECT bias terminal of the OECT front-end sensor. The control unit forms a digital operating point adjustment loop through the operating point acquisition circuit and the adjustable bias generation circuit, and only allows the adjustment of the adjustable bias voltage when the output change rate of the integral feedback unit (403) is lower than a preset threshold, N consecutive sample values deviate from the target operating range, and no QRS group is detected in the current time window, where N is an integer greater than or equal to 2.
2. The ECG signal acquisition front-end according to claim 1, characterized in that, The time constant of the analog low-frequency drift suppression loop is 0.5s to 60s, the update cycle of the digital operating point adjustment loop is 5s to 300s, and the digital operating point adjustment loop sets a stable waiting time after each bias update, during which the next bias update is paused or the bias update step size is reduced.
3. The ECG signal acquisition front-end according to claim 1, characterized in that, The two input OECT devices employ resistive loads or equivalent OECT loads and form a differential input structure. The bias / tail-end OECT device is used to provide tail-end bias or bias current to the two input OECT devices.
4. The ECG signal acquisition front-end according to claim 3, characterized in that, The two input OECT devices and the bias / tail OECT device all adopt a stacked structure of OECT device (100); the OECT device (100) includes a flexible substrate (101), an Au source (102), an Au drain (103), a gDPP-g2T channel layer (104), an Au gate bottom or Au gate connection layer (105), an Ag / AgCl gate (106), a hydrogel / electrolyte layer (107) and an overall encapsulation layer (108). The hydrogel / electrolyte layer (107) covers or contacts the gDPP-g2T channel layer (104) and forms an ion conduction path with the Ag / AgCl gate (106); the overall encapsulation layer (108) is one or a combination of Parylene, PDMS, SU-8, epoxy encapsulant, and UV curable adhesive, and covers the non-sensing area and exposes the sensing window corresponding to the hydrogel / electrolyte layer (107).
5. The ECG signal acquisition front-end according to claim 4, characterized in that, The OECT front-end sensor is a three-tube OECT sensor array (200), including a first input OECT device (201), a second input OECT device (202), a bias / tail end OECT device (203), a common source node (204), an OUT+ output terminal (205), an OUT- output terminal (206), an ECG+ input terminal (207), an ECG- input terminal (208), a Vbias input terminal (209), and a VSS / tail end bias terminal (210).
6. The ECG signal acquisition front-end according to claim 5, characterized in that, The OUT+ output terminal (205) and OUT- output terminal (206) are respectively connected to the R3 resistor load interface (302) and R4 resistor load interface (303) on the external PCB / FPC adapter board (300); the OECT front-end sensor is connected to the external PCB / FPC adapter board (300) through Au external connection pad (211), conductive silver paste (212), UV fixing adhesive (213) and copper wire (214), wherein the conductive silver paste (212) is used for electrical connection and the UV fixing adhesive (213) is used for mechanical fixing and stress relief.
7. The ECG signal acquisition front-end according to claim 1, characterized in that, The input filtering unit (401) includes an input coupling capacitor and a bleed resistor, wherein the input coupling capacitor is 0.1μF to 10μF and the bleed resistor is 100kΩ to 20MΩ; the integral feedback unit (403) includes an integral amplifier, an integral resistor and an integral capacitor, wherein the integral resistor is 100kΩ to 20MΩ and the integral capacitor is 10nF to 100μF.
8. The ECG signal acquisition front-end according to claim 1, characterized in that, The adjustable bias generation circuit includes a multi-channel digital-to-analog converter circuit (501) and a polarity mapping circuit (502); the multi-channel digital-to-analog converter circuit (501) is used to output multiple digital-to-analog converter voltages, and the polarity mapping circuit (502) includes at least one of an inverting amplifier and a level shifting circuit, used to map the digital-to-analog converter voltages to at least one of VDD, VSS, Vbias, and Vref bias voltages; the operating point voltage includes at least one of the common-mode voltage of the differential output terminal of the OECT front-end sensor, the source-drain operating voltage of the input OECT device, the voltage of the common source node (204), and the bias node voltage of the bias / tail-end OECT device.
9. A method for stabilizing the dual-loop operating point of an electrocardiogram signal acquisition front-end as described in any one of claims 1 to 8, characterized in that, include: By applying the output of the integral feedback unit (403) to the reference terminal, compensation terminal or equivalent bias terminal of the instrument amplification unit (402), the low-frequency baseline drift in the signal processing circuit (400) is simulated and compensated; the operating point voltage of the OECT front-end sensor is acquired by the operating point acquisition circuit. When the output change rate of the integral feedback unit (403) is lower than a preset threshold, N consecutive sample values deviate from the target working range, and no QRS complex is detected in the current time window, the adjustable bias voltage of the OECT bias terminal is adjusted by the adjustable bias generation circuit; wherein, the analog feedback compensation is used to suppress the baseline drift of the signal processing circuit (400), and the adjustment of the adjustable bias voltage is used to make the OECT front-end sensor return to the target working range.
10. The dual-ring operating point stabilization method according to claim 9, characterized in that, The analog feedback compensation operates continuously with a time constant of 0.5s to 60s, the adjustable bias voltage is intermittently adjusted with an update cycle of 5s to 300s, and a stable waiting time is set after each bias update. Pause the next bias update or reduce the bias update step size during the stable waiting time.
