Cerebrospinal interface system, control method and chip

Abstract

The application provides a brain-spinal interface system, a control method and a chip. The brain-spinal interface system comprises: a collection module configured to receive an electroencephalogram signal through a multi-channel collection electrode, switch between a plurality of working states according to the received input signal, receive and condition the electroencephalogram signal in a collection state, and interrupt the electroencephalogram signal collection path in a stimulation protection state; an electrical stimulation module configured to output an electrical stimulation signal through a multi-channel stimulation electrode, and send an indication signal to the collection module when the electrical stimulation signal is output, so that the collection module switches to the stimulation protection state; and a calculation control module configured to send a control instruction to the collection module to switch the working state thereof, receive the electroencephalogram signal from the collection module, and send a control instruction to the electrical stimulation module according to the electroencephalogram signal to control the output of the electrical stimulation signal. The application can solve the technical problems of low integration and lack of stimulation artifact protection of the front end of the existing brain-spinal interface system.

Description

Technical Field

[0001] This application belongs to the field of neural interface integrated circuit technology, and relates to a brain-spinal interface system, control method and chip. Background Technology

[0002] Brain-spinal interface systems are used for the acquisition of electroencephalogram (EEG) signals and for nerve electrical stimulation, and have important applications in neuroscience research and clinical neuromodulation. Existing brain-spinal interface systems are typically implemented using discrete devices or board-level chip combinations, with the acquisition end and stimulation end designed independently.

[0003] In terms of acquisition circuits, traditional solutions lack active hardware protection mechanisms against stimulus artifacts. When the electrical stimulation module outputs a large current, the acquisition front end is easily damaged due to overvoltage, and the stimulation signal is easily coupled to adjacent channels through the acquisition electrodes, causing crosstalk.

[0004] In terms of electrical stimulation modules, existing products typically use a single stimulation chip as the current source, along with multiple switching chips to achieve multi-electrode switching. For example, to achieve arbitrary stimulation of 64 electrodes, if each switching chip only connects 4 electrodes, then 16 switching chips are needed to work with one stimulation chip, resulting in an excessively large PCB area and high system cost.

[0005] Furthermore, during high-speed multi-channel data transmission, timing offsets can easily occur when the main control device receives and collects data, affecting data integrity. Therefore, a highly integrated brain-spinal interface system with hardware protection mechanisms and reliable data transmission is needed. Summary of the Invention

[0006] This application provides a brain-spinal interface system, control method, and chip to solve the technical problems of low integration, lack of stimulation artifact protection at the acquisition front end, and easy deviation of data transmission timing in existing brain-spinal interface systems.

[0007] In a first aspect, this application provides a brain-spinous interface system, comprising: a data acquisition module configured to receive electroencephalogram (EEG) signals via multi-channel acquisition electrodes, the data acquisition module having multiple operating states, including at least an acquisition state and a stimulation protection state, the data acquisition module switching between the multiple operating states according to received input signals; in the acquisition state, the data acquisition module receiving and conditioning EEG signals; in the stimulation protection state, the data acquisition module interrupting the EEG signal acquisition pathway to avoid electrical stimulation signals; an electrical stimulation module configured to output electrical stimulation signals via multi-channel stimulation electrodes, and sending an indication signal to the data acquisition module when outputting electrical stimulation signals to cause the data acquisition module to switch to the stimulation protection state; and a calculation control module communicatively connected to the data acquisition module and the electrical stimulation module, configured to send control commands to the data acquisition module to switch its operating state, receive EEG signals from the data acquisition module, and send control commands to the electrical stimulation module according to the EEG signals to control the output of electrical stimulation signals.

[0008] In one implementation of the first aspect, the acquisition module includes an acquisition front-end, an analog-to-digital converter, and an acquisition control logic module; the acquisition control logic module includes a state machine and a digital logic control circuit, the state machine is configured with multiple working states, the state machine switches between the multiple working states according to the input signal, and the digital logic control circuit outputs a control signal according to the current state of the state machine to control the acquisition module to execute the corresponding working state.

[0009] In one implementation of the first aspect, the plurality of working states further include an impedance detection state and a reset state; in the impedance detection state, the acquisition module performs impedance detection on the acquisition electrodes; the state machine is configured to: enter the reset state for initialization after receiving a reset signal, enter the acquisition state to perform EEG signal acquisition after initialization, switch to the impedance detection state to perform electrode impedance detection when a test control signal is received, and switch to the stimulation protection state to interrupt the EEG signal acquisition pathway and avoid electrical stimulation signals when a stimulation control signal is received.

[0010] In one implementation of the first aspect, the acquisition front end includes an amplifier, a low-pass filter, a first switch group, and a second switch group for each acquisition channel; the first switch group is disposed between the input terminal of the amplifier and the acquisition electrode, the output terminal of the amplifier is connected to the second switch group via the low-pass filter, and the second switch group is disposed between the input terminals of the amplifiers of adjacent acquisition channels; in the acquisition state, the first switch group is closed and the second switch group is open, so that the EEG signal is output to the analog-to-digital converter after passing through the acquisition electrode, the first switch group, the amplifier, and the low-pass filter; in the stimulation protection state, the first switch group is open and the second switch group is closed to block the electrical stimulation signal from being transmitted to the amplifier via the acquisition electrode, and the input terminals of the amplifiers of adjacent acquisition channels are short-circuited by the second switch group to block crosstalk between the acquisition front end channels.

[0011] In one implementation of the first aspect, the electrostimulation module includes multiple current sources and a switch matrix integrated with an H-bridge driver and a switch array; wherein the output terminal of each current source is connected to a corresponding input terminal of the switch matrix, and the multiple output terminals of the switch matrix are connected to each stimulation electrode; the switch matrix is ​​configured to selectively connect the output terminal of any current source to any stimulation electrode according to a control signal, so that the multiple current sources are selectively connected to any electrode among the multi-channel stimulation electrodes, thereby realizing current stimulation output of any electrode.

[0012] In one implementation of the first aspect, the computing control module and the acquisition module are connected via an SPI interface; the SPI interface is configured to: receive data from the computing control module, encode the received data to obtain a write address and write data, and store the write data in a register array at the corresponding address; and, in response to a read instruction from the computing control module, read target data from the register array and output it to the computing control module via the MISO pin.

[0013] In one implementation of the first aspect, the SPI interface includes a master clock line, a master-output-slave-in data line, a master-in-slave-output data line, and a return clock line; the return clock line is configured to be sent by the acquisition module to the computing control module, the return clock being synchronized with the analog-to-digital converter output data transmitted on the master-in-slave-output data line, and the computing control module sampling the data on the master-in-slave-output data line according to the return clock to ensure the timing integrity of data reception.

[0014] In one implementation of the first aspect, an LVDS interface is further included, connected between the computational control module and the electrical stimulation module, and configured to transmit electrical stimulation control commands issued by the computational control module to the electrical stimulation module in the form of low-voltage differential signals, thereby realizing long-distance, high-speed data transmission between the computational control module and the electrical stimulation module.

[0015] Secondly, this application provides a control method for a brain-spinal interface system, comprising: receiving electroencephalogram (EEG) signals through multi-channel acquisition electrodes, and receiving and conditioning the EEG signals; acquiring and analyzing the EEG signals, and issuing an electrical stimulation output command when it is determined that electrical stimulation needs to be output based on the EEG signals; responding to the electrical stimulation output command, outputting an electrical stimulation signal through multi-channel stimulation electrodes, and simultaneously generating a switching indication signal; responding to the switching indication signal, switching from the acquisition state to a stimulation protection state, interrupting the signal acquisition path of the multi-channel acquisition electrodes in the stimulation protection state to avoid the electrical stimulation signal; and when the electrical stimulation signal stops outputting, switching back from the stimulation protection state to the acquisition state to resume receiving EEG signals through the multi-channel acquisition electrodes.

[0016] Thirdly, this application provides a chip, including: the aforementioned brain-spinal interface system.

[0017] As described above, the brain-spinal interface system, control method, and chip of this application have the following beneficial effects:

[0018] 1. In this application, the acquisition module can switch between acquisition and stimulation protection states. When the electrical stimulation module outputs an electrical stimulation signal, it actively sends an indication signal to the acquisition module, causing the acquisition module to switch to the stimulation protection state in a timely manner to interrupt the acquisition path. Without affecting the accuracy of normal EEG signal acquisition, this effectively avoids damage to the acquisition front end caused by electrical stimulation artifacts, achieving rapid collaborative protection between acquisition and stimulation. At the same time, the calculation control module sends control commands to the electrical stimulation module based on the received EEG signals to regulate the electrical stimulation output, forming a closed-loop control of acquisition-analysis-stimulation. The signal interaction and state coordination between the acquisition module, the electrical stimulation module, and the calculation control module achieve high integration, high security, and precise closed-loop control of the brain-spinous interface system as a whole. Therefore, this application can solve the technical problems of low integration, lack of stimulation artifact protection at the acquisition front end, and easy deviation of data transmission timing in existing brain-spinous interface systems.

[0019] 2. This application utilizes the impedance detection state of the acquisition module, which can trigger impedance detection of the acquisition electrodes at any time during acquisition or reset states, effectively improving the timeliness and response speed of system fault detection. The LVDS interface enables long-distance, low-noise, high-speed data transmission between the computational control link and the electrostimulation module, overcoming signal attenuation and noise interference problems during long-distance transmission. The state machine and digital logic control circuit in the acquisition control logic module achieve precise timing control and rapid switching of each working state of the acquisition module. By setting first and second switch groups at the acquisition front end, the signal path is connected during acquisition to ensure effective transmission of EEG signals, while the first switch group is disconnected during stimulation protection to block the transmission of high-current stimulation signals to the acquisition front end. Furthermore, the second switch group is closed to short-circuit the input terminals of adjacent channels to block crosstalk between channels. This dual protection further enhances the safety and signal quality of the acquisition front end.

[0020] 3. This application integrates the H-bridge driver and switch array into a switch matrix, enabling multiple current sources to be selectively connected to any stimulation electrode. This breaks the traditional limitation of one-to-one or fixed grouping between current sources and electrodes. Compared with existing PCB-level solutions using discrete stimulation chips and switch chips, it can save approximately 50% of the circuit area, significantly reducing manufacturing costs and chip area. The SPI interface, in conjunction with the register array, enables serial reading and writing of acquired data and control parameters, as well as configuration of the return clock, ensuring the timing integrity and reliability of data transmission between the computing control link and the acquisition module. Attached Figure Description

[0021] Figure 1 The diagram shown is a schematic diagram of the principle structure of the brain-spinal interface system described in the embodiments of this application.

[0022] Figure 2 The diagram shown is a schematic diagram of the principle structure of the acquisition module in the brain-spinous interface system described in this application embodiment.

[0023] Figure 3 The diagram shows the single-channel acquisition front-end switch closed state in the acquisition state of the brain-spinal interface system described in this application embodiment.

[0024] Figure 4 The diagram shows the single-channel acquisition front-end switch closed state in the brain-spinal interface system described in this application embodiment under stimulation.

[0025] Figure 5 The diagram shows the working process of the state machine in the brain-spinal interface system described in this application embodiment.

[0026] Figure 6 The diagram shows the connection relationship of the acquisition module in the brain-spinous interface system described in this application embodiment.

[0027] Figure 7 The diagram shown is a schematic representation of the electrical stimulation module in the brain-spinal interface system described in this application embodiment.

[0028] Figure 8 The diagram shown is an example of the brain-spinal interface system described in an embodiment of this application.

[0029] Figure 9 This diagram shows the signal flow of the acquisition module in the initialization state of the brain-spinous interface system described in this application embodiment.

[0030] Figure 10 The diagram shows the signal flow of the acquisition module in the acquisition state of the brain-spinal interface system described in this application embodiment.

[0031] Figure 11 The diagram shows the signal flow of the acquisition module in the stimulation state of the brain-spinal interface system described in this application embodiment.

[0032] Figure 12 The diagram shows the signal flow of the acquisition module in the detection state of the brain-spinal interface system described in this application embodiment.

[0033] Figure 13 The diagram shown is a flowchart illustrating the principle of the control method for the brain-spinal interface system described in this application embodiment.

[0034] Component designation explanation

[0035] 1 Brain-Spinal Interface System 11 Data Acquisition Module 111 Data collection front end 1111 Amplifier 1112 low-pass filter 1113 First switch group 1114 Second switch group 112 Analog-to-digital converter 113 Acquisition and control logic module 1131 state machine 1132 Digital logic control circuit 12 Electrical stimulation module 13 Calculation control module S10~S50 step Detailed Implementation

[0036] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0037] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0038] The technical solutions in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0039] Example 1

[0040] This embodiment addresses the technical problems of poor coordination between acquisition and stimulation in existing brain-spinal interface systems and the susceptibility of the acquisition front end to damage by stimulation artifacts, and provides a brain-spinal interface system. Figure 1 The diagram shown is a schematic representation of the brain-spinal interface system described in an embodiment of this application. Figure 1 As shown, the brain-spinal interface system 1 provided in this embodiment specifically includes: a data acquisition module 11, an electrical stimulation module 12, and a calculation and control module 13.

[0041] The acquisition module 11 is configured to receive EEG signals through multi-channel acquisition electrodes. The acquisition module 11 has multiple operating states, including at least an acquisition state and a stimulation protection state. The acquisition module 11 switches between these operating states based on the received input signal. In the acquisition state, the acquisition module 11 receives and modulates the EEG signals. In the stimulation protection state, the acquisition module 11 interrupts the EEG signal acquisition path to avoid electrical stimulation signals. The electrical stimulation module 12 is configured to output electrical stimulation signals through multi-channel stimulation electrodes and send an indication signal to the acquisition module 11 when outputting the electrical stimulation signal, causing the acquisition module 11 to switch to the stimulation protection state. The calculation and control module 13 is communicatively connected to both the acquisition module 11 and the electrical stimulation module 12. It is configured to send control commands to the acquisition module 11 to switch its operating state, receive EEG signals from the acquisition module 11, and send control commands to the electrical stimulation module 12 based on the EEG signals to control the output of the electrical stimulation signal.

[0042] The brain-spinal interface system 1 of this embodiment sets the acquisition state and stimulation protection state through the acquisition module 11, and actively sends an indication signal to the acquisition module 11 when the electrical stimulation module 12 outputs an electrical stimulation signal, so that the acquisition module 11 can switch to the stimulation protection state in real time to interrupt the acquisition path without the need for additional intervention from the calculation control module 13. This achieves rapid coordinated protection between acquisition and stimulation, effectively avoids damage to the acquisition front end 111 by the electrical stimulation pulse, and significantly improves the safety and reliability of the system. At the same time, the signal interaction and state coordination between the acquisition module 11, the electrical stimulation module 12 and the calculation control module 13 form a closed-loop control of acquisition-analysis-stimulation. The calculation control module 13 accurately adjusts the electrical stimulation output parameters according to the real-time acquired EEG signals, avoiding the blindness of open-loop stimulation. Overall, the brain-spinal interface system 1 achieves high safety, high signal integrity and precise closed-loop control, meeting the stringent requirements of system coordination and reliability for implantable or high-density brain-spinal interface application scenarios.

[0043] The following combination Figures 2 to 12 The acquisition module 11, electrical stimulation module 12, and calculation control module 13 of the brain-spinal interface system 1 of this embodiment will be described in detail.

[0044] Figure 2 The diagram shown is a schematic representation of the principle structure of the acquisition module 11 in the brain-spinal interface system 1 described in this application embodiment. Figure 2 As shown, in one implementation of this embodiment, the acquisition module 11 includes an acquisition front-end 111, an analog-to-digital converter 112, and an acquisition control logic module 113. The acquisition control logic module 113 includes a state machine 1131 and a digital logic control circuit 1132. The state machine 1131 is configured with multiple working states. The state machine 1131 switches between the multiple working states according to the input signal. The digital logic control circuit 1132 outputs a control signal according to the current state of the state machine 1131 to control the acquisition module 11 to execute the corresponding working state.

[0045] In this embodiment, the electrode signals are collected and fed into the multi-channel acquisition front-end 111, which receives and conditions the signals from each channel and converts the analog signals into digital signals via the analog-to-digital converter 112. The converted data and control signals interact bidirectionally or unidirectionally with the computing control circuit through the communication interface to realize the transmission of the collected data. The acquisition control logic module 113, as the core controller of the acquisition module 11, is responsible for coordinating the timing control, channel switching and logic management of the entire acquisition link.

[0046] Taking a single-channel acquisition front-end 111 as an example, in one implementation of this embodiment, the acquisition front-end 111 includes an amplifier 1111, a low-pass filter 1112, a first switch group 1113, and a second switch group 1114 for each acquisition channel; the first switch group 1113 is disposed between the input terminal of the amplifier 1111 and the acquisition electrode, the output terminal of the amplifier 1111 is connected to the second switch group 1114 via the low-pass filter 1112, and the second switch group 1114 is disposed between the input terminals of the amplifier 1111 of adjacent acquisition channels.

[0047] In the acquisition state, the first switch group 1113 is closed and the second switch group 1114 is open, allowing the EEG signal to pass through the acquisition electrodes, the first switch group 1113, the amplifier 1111, and the low-pass filter 1112 before being output to the analog-to-digital converter 112. In the stimulation protection state, the first switch group 1113 is open and the second switch group 1114 is closed to block the electrical stimulation signal from being transmitted to the amplifier 1111 via the acquisition electrodes. Furthermore, the second switch group 1114 short-circuits the input terminals of the amplifiers 1111 in adjacent acquisition channels to block crosstalk between the acquisition front-end channels 111.

[0048] Figure 3 The diagram shows the switch-closed state of the single-channel acquisition front-end 111 in the acquisition state of the brain-spinous interface system 1 described in this application embodiment; Figure 4 The diagram shows the switch-closed state of the acquisition front-end 111 in the brain-spinal interface system 1 described in this application embodiment under stimulation. Figure 3 and Figure 4 As shown, exemplarily, the first switch group 1113 includes switches S1, S2, S3, and S4, and the second switch group 1114 includes switches S5 and S6. Switches S1 and S2 are located between the acquisition electrode and the input terminal of amplifier 1111, switches S3 and S4 are located between the output terminal of low-pass filter 1112 and the input terminal of analog-to-digital converter 112, and switches S5 and S6 are located between the input terminals of amplifiers 1111 in adjacent acquisition channels.

[0049] like Figure 3 As shown, when the acquisition module 11 is in acquisition mode, switches S1-S4 in the first switch group 1113 are closed, and switches S5-S6 in the second switch group 1114 are open. In this state, the weak EEG signal picked up by the acquisition electrodes enters the differential input terminal of amplifier 1111 via S1 and S2. After being amplified by amplifier 1111, it enters the low-pass filter 1112 for filtering via S3 and S4, and is finally sent to the analog-to-digital converter 112 for sampling via the output terminal. In this signal path, S1-S4 act as selection switches for the signal transmission channel, ensuring that the EEG signal can be transmitted to the subsequent processing circuit completely and with low loss; S5-S6 are in the open state, avoiding signal coupling or shunting between adjacent channels due to short circuits at the input terminals, thereby ensuring the independence and accuracy of signal acquisition for each channel.

[0050] like Figure 4As shown, when the acquisition module 11 operates in the stimulation protection state, switches S1-S4 in the first switch group 1113 are open, and switches S5-S6 in the second switch group 1114 are closed. In this state, S1 and S2 are open, cutting off the physical path of the stimulation current from the acquisition electrode to the input terminal of the amplifier 1111; S3 and S4 are open, cutting off the signal path from the output terminal of the amplifier 1111 to the low-pass filter 1112 and the analog-to-digital converter 112, preventing the front-end circuit from being damaged by the large voltage swing that occurs during stimulation. At the same time, S5 and S6 are closed, shorting the differential input terminals of the amplifiers 1111 of adjacent acquisition channels to the common-mode potential, thereby making the input terminals of the amplifiers 1111 of each channel in an equipotential state, effectively blocking the path of inter-channel crosstalk signals caused by the potential difference between electrodes during stimulation to enter the amplifier 1111, further improving the ability of the acquisition front-end 111 to suppress residual interference signals in the stimulation state.

[0051] In this embodiment, by setting first and second switch groups 1114 in the acquisition front end 111, the signal path is connected in the acquisition state to ensure effective transmission of EEG signals. In the stimulation protection state, the first switch group 1113 is disconnected to block the transmission of high current stimulation signals to the acquisition front end 111. The second switch group 1114 is closed to short-circuit the input terminals of adjacent channels to block crosstalk between channels. The dual protection further improves the safety and signal quality of the acquisition front end 111.

[0052] In one implementation of this embodiment, the plurality of working states further includes an impedance detection state and a reset state; in the impedance detection state, the acquisition module 11 performs impedance detection on the acquisition electrode. This embodiment, through the impedance detection state of the acquisition module 11, allows impedance detection of the acquisition electrode to be triggered at any time in either the acquisition or reset state, effectively improving the timeliness and response speed of system fault detection.

[0053] In this embodiment, the state machine 1131 is configured with four working states: reset, acquisition, stimulation, and verification. The state machine 1131 switches between multiple states according to the received stimulation control signal or verification control signal to control the acquisition module 11 to perform EEG signal acquisition, electrode impedance detection, or stimulation protection avoidance accordingly, thereby realizing the coordinated operation and timing management between acquisition, detection, and stimulation.

[0054] Figure 5 This diagram illustrates the operation of state machine 1131 in the brain-spinal interface system 1 described in this embodiment. Figure 5As shown, state machine 1131 is configured with multiple operating states, including a reset state, an acquisition state, a stimulation state, and an impedance detection state. The clock signal serves as the timing control reference for switching between state machines 1131, and the reset signal is used to reset state machine 1131 to its initial state. The input signals of state machine 1131 include stimulation control signals and verification control signals. These signals are control signals obtained by encoding data received through the communication interface and are crucial for determining the switching of the entire acquisition module 11's operating states. State machine 1131 switches between multiple operating states based on the received input signals.

[0055] Specifically, the state machine 1131 is configured to: enter the reset state for initialization after receiving a reset signal; enter the acquisition state to perform EEG signal acquisition after initialization is completed; switch to the impedance detection state to perform electrode impedance detection when receiving a test control signal; and switch to the stimulation protection state to interrupt the EEG signal acquisition pathway and avoid electrical stimulation signals when receiving a stimulation control signal.

[0056] In this embodiment, the state machine 1131 operates as follows:

[0057] When the circuit is started and a reset signal is received, the state machine 1131 enters the reset state and performs preparatory work such as register initialization; after the reset is completed, the state machine 1131 switches to the acquisition state and begins to record EEG signals.

[0058] When the state machine 1131 is in the acquisition state and receives a test signal, the state machine 1131 jumps from the acquisition state to the impedance detection state to perform electrode impedance detection. When the detection completion signal is valid, it means that the detection work is over, and the state machine 1131 returns to the acquisition state to continue working.

[0059] When the state machine 1131 is in the acquisition state and receives a stimulation signal, the state machine 1131 jumps from the acquisition state to the stimulation state. At this time, the acquisition work is suspended and the switch on the acquisition signal link is disconnected to avoid damage to the acquisition circuit due to high current stimulation. When the stimulation signal is removed, it means that the stimulation circuit has finished working, and the state machine 1131 returns to the acquisition state to continue recording EEG signals.

[0060] In both the reset state and the acquisition state, the impedance detection state can be entered through the test signal to realize the instantaneous test function of electrode impedance and improve the response speed of fault detection.

[0061] Figure 6 This diagram illustrates the connection relationship of the acquisition module 11 in the brain-spinal interface system 1 described in this embodiment. Figure 6As shown, the input terminal of the digital logic control circuit 1132 is connected to the current state output terminal of the state machine 1131 to acquire the current state indicator signal. Based on this current state indicator signal, the digital logic control circuit 1132 generates corresponding control output signals through internal logic operations, including an acquisition enable signal, a verification enable signal, and a stimulation enable signal, which are used to control the acquisition module 11 to perform corresponding functions such as EEG signal acquisition, electrode impedance detection, and stimulation protection avoidance, respectively. In this embodiment, through the state machine 1131 and the digital logic control circuit 1132 in the acquisition control logic module 113, precise timing control and rapid switching of the various working states of the acquisition module 11 are achieved.

[0062] Figure 7 The diagram shown is a schematic representation of the electrical stimulation module 12 in the brain-spinal interface system 1 described in this application embodiment. Figure 7 As shown, in one implementation of this embodiment, the electrical stimulation module 12 includes multiple current sources and a switch matrix integrated with an H-bridge driver and a switch array. The output terminal of each current source is connected to a corresponding input terminal of the switch matrix, and the multiple output terminals of the switch matrix are connected to each stimulation electrode. The switch matrix is ​​configured to selectively connect the output terminal of any current source to any stimulation electrode according to a control signal, so that the multiple current sources are selectively connected to any electrode in the multi-channel stimulation electrode array, achieving current stimulation output from any electrode.

[0063] In existing products, a separate stimulation chip is typically required as the current source output, along with multiple switching chips to achieve the function of selecting any stimulation electrode. However, this discrete chip combination architecture requires a large layout area on the PCB board, increasing the difficulty of system integration and manufacturing costs. Taking the 64-channel electrostimulation module 12 as an example, if a single switching chip can only connect four electrodes, at least 16 switching chips are needed to achieve arbitrary stimulation selection of 64 electrodes.

[0064] In contrast, the electrical stimulation module 12 described in this application integrates the H-bridge driver and the switch array into a single switch matrix. Taking the 64-channel electrical stimulation module 12 as an example, the module has 16 current sources, enabling free switching of the 64 stimulation electrodes without the need for multiple independent switch chips. This integrated solution eliminates the significant area required by discrete switch chips and corresponding PCB layouts in existing solutions, saving approximately 50% of the circuit area, significantly reducing system manufacturing costs, improving integration, and making it more suitable for the compact design requirements of the high-channel-density brain-spinal interface system 1.

[0065] Therefore, this embodiment integrates the H-bridge driver and the switch array into a switch matrix. Utilizing the flexibility of the switch matrix, multiple current sources can be selectively connected to any stimulation electrode, breaking the traditional limitation of one-to-one or fixed grouping of current sources and electrodes. Furthermore, by combining the H-bridge driver and the switch array into one unit, this embodiment can also achieve biphasic current stimulation.

[0066] In one implementation of this embodiment, the computing control module 13 can be implemented using any one or more combinations of a microcontroller, a digital signal processor, or a field-programmable gate array (FPGA). The microcontroller is used to implement system-level control, communication scheduling, and configuration management; the digital signal processor is used to perform high-speed, complex mathematical operations and is suitable for real-time signal processing; the FPGA, utilizing its parallel processing architecture and low latency characteristics, is suitable for preprocessing and real-time control of multi-channel EEG signals.

[0067] In one implementation of this embodiment, the computational control module 13 is configured to: receive digitized EEG signal data from the acquisition module 11 via an SPI interface; perform signal processing operations such as preprocessing, feature extraction, and pattern recognition on the received EEG signals to decode the EEG signals into instructions with clear control significance; generate corresponding electrical stimulation control instructions based on the decoding results, and send them to the electrical stimulation module 12 via a communication link to control the magnitude, timing, and output channel of the stimulation current.

[0068] In one implementation of this embodiment, the computing control module 13 and the acquisition module 11 are connected via an SPI interface. The SPI interface is configured to: receive data from the computing control module 13, encode the received data to obtain a write address and write data, and store the write data in a register array at the corresponding address; and, in response to a read instruction from the computing control module 13, read target data from the register array and output it to the computing control module 13 via the MISO pin.

[0069] In this embodiment, the communication interface is an SPI interface, which receives data from the computing control module 13. When the SPI interface receives a write command, the received data is encoded to obtain a write address and write data, and the write data is stored in the register array at the location corresponding to the write address. When the SPI interface receives a read command, the received data is encoded to obtain a read address, and the target data in the register array corresponding to the read address is output to the computing control module 13 through the SPI interface. The acquisition module 11 also includes a register array, which is used to store the digital EEG signal data of each channel after analog-to-digital conversion, and waits for the computing control module 13 to read it through the SPI interface.

[0070] The digital EEG signal data is the multi-channel conversion result output by the analog-to-digital converter 112, and the data of each channel in the register array is stored at the corresponding address location. The input signals of the state machine 1131, including stimulation control signals and test control signals, are control signals obtained by encoding the data received through the SPI interface, and are used for switching the working state of the acquisition module 11.

[0071] This embodiment uses the SPI interface in conjunction with a register array to achieve serial reading and writing of acquired data and control parameters, as well as configuration of the return clock, ensuring the timing integrity and reliability of data transmission between the computing control link and the acquisition module 11.

[0072] In one implementation of this embodiment, such as Figure 6 As shown, the SPI interface includes a master clock line (SCLK), a master-slave input / output data line (MOSI), a master-slave output data line (MISO), and a return clock line (SCLK_RET). The return clock line is configured to be sent from the acquisition module 11 to the computing control module 13. This return clock is synchronized with the output data of the analog-to-digital converter 112 transmitted on the master-slave output data line. The computing control module 13 samples the data on the master-slave output data line according to the return clock to ensure the timing integrity of the data reception.

[0073] Considering the long transmission path for the computational control module 13 to send commands to the electrostimulation module 12, a high-speed data transmission interface (such as an LVDS interface) is set up to realize long-distance transmission between the electrostimulation module 12 and the computational control module 13 through this interface, so as to meet the requirements of high bandwidth, low noise, and high-speed data transmission.

[0074] Specifically, in one implementation of this embodiment, an LVDS interface is further included, connected between the computing control module 13 and the electrical stimulation module 12. It is configured to transmit the electrical stimulation control commands issued by the computing control module 13 to the electrical stimulation module 12 in the form of low-voltage differential signals. The LVDS interface enables long-distance, low-noise, high-speed data transmission between the computing control link and the electrical stimulation module 12, overcoming the problems of signal attenuation and noise interference in long-distance transmission.

[0075] Figure 8 The diagram shown is an example of the brain-spinal interface system 1 described in an embodiment of this application. Figure 8 As shown, the brain-spinal interface system 1 described in this embodiment includes a data acquisition front-end 111, an analog-to-digital converter (ADC) 112, an SPI interface, a data acquisition control logic module 113, a register array, a computational control module 13, and an LVDS interface. Its working principle is as follows: EEG signals picked up by multi-channel acquisition electrodes first enter the data acquisition front-end 111 for reception and conditioning, then are converted into digital signals by the ADC 112 and transmitted to the computational control module 13 via the SPI interface. Simultaneously, the computational control module 13 sends control commands to the data acquisition control logic via the SPI interface to configure the working state and parameters of the data acquisition front-end 111, and temporarily stores and reads / writes the acquired data and control parameters via the register array. The computational control module 13 analyzes and processes the received EEG signals, generates corresponding electrical stimulation control commands, and transmits them long-distance to the electrical stimulation module 12 via the LVDS interface to achieve precise control of the stimulation current magnitude, timing, and output channel. The above modules work together to form a closed-loop brain-spinal interface system 1 integrating EEG signal acquisition, data processing, and electrical stimulation output.

[0076] Figures 9 to 12 The process of the acquisition module 11 switching to different states according to the acquisition control circuit is described, where the dashed arrows represent signals that are not needed in that state.

[0077] Figure 9 This diagram illustrates the signal flow of the acquisition module 11 in the initialization state of the brain-spinal interface system 1 described in this embodiment. Figure 9 As shown, when the acquisition module 11 is powered on, initialization configuration is required. Specifically, the calculation control module 13 sends configuration parameters to the internal SPI interface of the acquisition module 11 via the SPI interface. After receiving the configuration parameters via the SPI interface, the operating parameters are written into the register array at the address locations corresponding to each acquisition channel, according to the corresponding address information. Subsequently, the output terminals of these register arrays output the configuration parameters to the corresponding acquisition front-end 111 to complete the operating parameter configuration of each channel acquisition front-end 111, thereby preparing for the normal acquisition of subsequent EEG signals.

[0078] Figure 10 This diagram illustrates the signal flow of the acquisition module 11 in the brain-spinal interface system 1 described in this embodiment, during the acquisition process. Figure 10 As shown, after the acquisition module 11 completes its initialization configuration, it enters the acquisition state. At this time, the acquisition enable signal output by the digital logic control circuit 1132 is valid, and the analog-to-digital converter 112 starts working, converting the analog EEG signals input from the acquisition front-end 111 of each channel into digital signals. The multi-channel digital EEG signal data output by the analog-to-digital converter 112 is first registered in the register array at the address corresponding to each channel, and then sequentially output to the SPI interface through the serial output terminal of the register array, and then sent to the computing control module 13 through the master-in, slave-out data line of the SPI interface. To avoid timing offset caused by long-distance transmission or clock delay matching differences when the computing control module 13 receives the output data of the analog-to-digital converter 112, a return clock line is also provided in the SPI interface. This return clock is generated by the acquisition module 11 and sent to the computing control module 13, and is synchronized with the data transmitted on the master-in, slave-out data line. The computing control module 13 samples the received data according to the return clock to ensure the timing integrity of the data reception.

[0079] Figure 11 This diagram illustrates the signal flow of the acquisition module 11 in the brain-spinal interface system 1 described in this embodiment, operating in a stimulated state. Figure 11 As shown, when the electrical stimulation module 12 starts working, the control data sent by the calculation control module 13 through the SPI interface is encoded to generate a stimulation control signal. This stimulation control signal is input to the state machine 1131 of the acquisition module 11, causing the acquisition module 11 to switch to the stimulation protection state. At this time, the digital logic control circuit 1132 outputs a stimulation enable signal according to the current state of the state machine 1131. This stimulation enable signal controls the switch group in the acquisition front-end 111 to perform corresponding on / off switching to cut off the signal path from the acquisition electrode to the amplifier 1111, thereby protecting the acquisition front-end 111 and the analog-to-digital converter 112 circuit from the large current stimulation signal output by the electrical stimulation module 12 and avoiding damage to the acquisition front-end 111.

[0080] Figure 12 This diagram illustrates the signal flow of the acquisition module 11 in the detection state of the brain-spinal interface system 1 described in this embodiment. Figure 12As shown, when the acquisition module 11 is in the detection state, the detection control signal is sent by the calculation control module 13 to the SPI interface inside the acquisition module 11 via the SPI interface. This control signal is encoded to generate a verification control signal and input to the state machine 1131, causing the acquisition module 11 to switch to the impedance detection state. At this time, the digital logic control circuit 1132 outputs a verification enable signal according to the current state of the state machine 1131, causing the acquisition module 11 to start detecting the impedance on each acquisition electrode. The measured impedance values ​​of each channel electrode are saved to the address corresponding to each channel in the register array. Subsequently, the calculation control module 13 sends a read command via the SPI interface to read the electrode impedance values ​​stored in the register array, thereby realizing real-time monitoring and evaluation of the contact state of the acquisition electrodes.

[0081] The brain-spinal interface system 1 of this embodiment can be applied to the field of motor function reconstruction and neurorehabilitation after spinal cord injury (SCI). The brain-spinal interface system 1 acquires EEG signals of motor intention emitted by the brain in real time by implanting acquisition electrodes in the motor cortex of the patient's brain. An external computing control module 13 (which can be implemented using a microcontroller (MCU), digital signal processor (DSP), or field-programmable gate array (FPGA)) decodes and analyzes the signals, generating corresponding electrical stimulation control commands. These commands are then transmitted via a communication link to an electrical stimulation module 12 implanted in the epidural space below the level of the spinal cord injury. The electrical stimulation module 12 outputs precisely controlled electrical stimulation signals in terms of timing and intensity to activate the spinal cord neural circuits below the injury level, thereby assisting the patient in performing actions such as walking.

[0082] The brain-spinous interface system 1 can be further extended to personalized neuromodulation of chronic pain, adjunctive treatment of scoliosis, and neuromodulation treatment of neurological diseases such as post-stroke motor dysfunction and gait disorder in Parkinson's disease. Its hardware can be configured as an implantable acquisition module 11 and an electrical stimulation module 12 combined with an external portable computing control module 13. The implant and the external device interact with each other through a wireless communication link to meet the personalized treatment needs of different patients and different stages of disease, and has broad clinical application prospects.

[0083] Example 2

[0084] Please see Figure 13 The diagram shows a flowchart illustrating the principle of the control method for the brain-spinal interface system described in this application. Figure 13 As shown, this embodiment provides a control method for a brain-spinal interface system, applied to the brain-spinal interface system 1 described in this application, specifically including the following steps S10 to S50.

[0085] Step S10: Receive EEG signals through multi-channel acquisition electrodes, and receive and condition the EEG signals.

[0086] In step S10, the brain-spinous interface system 1 is controlled to operate in acquisition mode, receiving EEG signals through multi-channel acquisition electrodes and receiving and conditioning the EEG signals. Specifically, the acquisition module 11 operates in acquisition mode, with the first switch group 1113 in the acquisition front end 111 closed and the second switch group 1114 open. The EEG signal passes sequentially through the acquisition electrodes, the first switch group 1113, the amplifier 1111, and the low-pass filter 1112, and is then output to the analog-to-digital converter 112 for sampling, thereby realizing the conditioning and digital conversion of the EEG signal.

[0087] Step S20: Acquire and analyze the EEG signal. When it is determined from the EEG signal that electrical stimulation needs to be output, issue an electrical stimulation output command.

[0088] In step S20, the electroencephalogram (EEG) signals are acquired and analyzed. When it is determined that electrical stimulation is needed based on the EEG signals, an electrical stimulation output command is issued. Specifically, the calculation and control module 13 receives digitized EEG signal data from the acquisition module 11 through a communication interface, performs preprocessing, feature extraction, and pattern recognition on the EEG signals, and decodes the patient's motor intentions into commands with control significance. When it is determined that electrical stimulation is needed based on the decoding results, an electrical stimulation output command is generated and sent to the electrical stimulation module 12.

[0089] In step S30, in response to the electrical stimulation output command, an electrical stimulation signal is output through the multi-channel stimulation electrode, and a switching indication signal is generated at the same time.

[0090] In step S30, in response to the electrical stimulation output command, an electrical stimulation signal is output through the multi-channel stimulation electrode, and a switching indication signal is generated simultaneously. Specifically, after receiving the electrical stimulation output command from the calculation and control module 13, the electrical stimulation module 12 routes the corresponding current source to the target stimulation electrode through its internal switching matrix according to the stimulation parameters (including current magnitude, timing, and output channel) contained in the command, and outputs the electrical stimulation signal; at the same time, the electrical stimulation module 12 actively generates a switching indication signal when it starts outputting the electrical stimulation signal, and sends the indication signal to the acquisition module 11.

[0091] Step S40: In response to the switching indication signal, switch from the acquisition state to the stimulation protection state. In the stimulation protection state, interrupt the signal acquisition path of the multi-channel acquisition electrode to avoid the electrical stimulation signal.

[0092] In step S40, in response to the switching indication signal, the acquisition state is switched to the stimulation protection state. In the stimulation protection state, the signal acquisition path of the multi-channel acquisition electrode is interrupted to avoid the electrical stimulation signal. Specifically, after the acquisition module 11 receives the switching indication signal from the electrical stimulation module 12, the state machine 1131 switches from the acquisition state to the stimulation protection state. The digital logic control circuit 1132 outputs a stimulation enable signal according to the current state of the state machine 1131, controlling the first switch group 1113 in the acquisition front-end 111 to open and the second switch group 1114 to close, so as to cut off the signal path from the acquisition electrode to the amplifier 1111, avoid the large current stimulation signal from entering the acquisition front-end 111 and causing damage to the circuit, and block the crosstalk between channels by shorting the input terminals of adjacent channels.

[0093] Step S50: When the electrical stimulation signal stops being output, the system switches from the stimulation protection state back to the acquisition state, and resumes receiving EEG signals through the multi-channel acquisition electrodes.

[0094] In step S50, when the electrical stimulation signal stops outputting, the system switches from the stimulation protection state back to the acquisition state, resuming the reception of EEG signals through the multi-channel acquisition electrodes. Specifically, after the electrical stimulation module 12 completes the electrical stimulation output, the electrical stimulation signal is released, and the electrical stimulation module 12 stops sending switching indication signals; the state machine 1131 of the acquisition module 11 switches from the stimulation protection state back to the acquisition state, the digital logic control circuit 1132 outputs an acquisition enable signal, controlling the first switch group 1113 in the acquisition front-end 111 to close and the second switch group 1114 to open, resuming the reception and conditioning of EEG signals, and continuing the real-time acquisition of EEG signals.

[0095] It should be noted that the specific implementation of each step in this method embodiment can refer to the description of the corresponding function in the aforementioned embodiment of the brain-spinous interface system 1, and will not be repeated here. However, it should be noted that the brain-spinous interface system 1 described in the above embodiment can implement the control method of the brain-spinous interface system 1 described in this application, but the implementation system of the control method of the brain-spinous interface system 1 described in this application includes, but is not limited to, the structure of the brain-spinous interface system 1 listed in this embodiment. All structural modifications and substitutions of the prior art made according to the principles of this application are included within the protection scope of this application.

[0096] The protection scope of the control method of the brain-spinous interface system 1 described in this application is not limited to the execution order of the steps listed in this embodiment. Any solution implemented by adding, subtracting, or replacing steps in the prior art based on the principles of this application is included within the protection scope of this application.

[0097] Example 3

[0098] This embodiment provides a chip, including the aforementioned brain-spinal interface system 1.

[0099] In one implementation of this embodiment, the chip is a monolithic integrated chip, with the acquisition module 11, the electrical stimulation module 12, and the computing control module 13 integrated on the same semiconductor substrate. The chip is configured as an implantable chip for implantation into a patient to acquire electroencephalogram (EEG) signals and output electrical stimulation signals. By integrating the acquisition module 11, electrical stimulation module 12, and computing control module 13 into a single chip, the inter-chip interconnections and additional PCB layout area required by discrete chip solutions are avoided, significantly improving system integration, reducing the overall chip area, and lowering system power consumption, thus meeting the stringent requirements of miniaturization and low power consumption for implantable applications.

[0100] In another implementation of this embodiment, at least some of the acquisition module 11, the electrical stimulation module 12, and the computing control module 13 are integrated into the chip using a System-on-Chip (SoC) architecture. The chip includes: an acquisition front-end array 111 containing 128 acquisition channels, each channel connected to a corresponding acquisition electrode for receiving EEG signals; an analog-to-digital converter 112 connected to the output of the acquisition front-end array 111 for converting analog EEG signals into digital signals; an acquisition control logic module 113 containing a state machine 1131 and a digital logic control circuit 1132 for controlling the acquisition module 11 to switch between an acquisition state, a stimulation protection state, and an impedance detection state; an electrical stimulation module 12 containing 16 current sources and a switch matrix integrated with an H-bridge driver and a switch array, the switch matrix being connected to 64 stimulation electrodes for outputting electrical stimulation signals according to control commands; and a computing control module 13, communicatively connected to the acquisition control logic module 113 via an on-chip SPI interface and to the electrical stimulation module 12 via an on-chip LVDS interface.

[0101] In another implementation of this embodiment, the chip further includes a register array, which is integrated with the acquisition control logic module 113 in the same chip area. The register array is used to store multi-channel digital EEG signal data output by the analog-to-digital converter 112, as well as the operating configuration parameters and electrode impedance detection results of the acquisition module 11. The computing control module 13 performs read and write operations on the register array through the SPI interface to read the acquired data, configure the operating parameters, and acquire the impedance detection results. By integrating the register array inside the chip, the additional area and power consumption required by off-chip memory devices are avoided, further improving the chip's integration and data access speed.

[0102] In another implementation of this embodiment, the chip further includes an on-chip clock management circuit for generating clock signals required for the operation of the acquisition module 11 and the electrical stimulation module 12. The clock management circuit is configured to provide a clock signal to the state machine 1131 as a timing control reference for state switching, and to provide a return clock to the SPI interface. The return clock is synchronized with the data output by the analog-to-digital converter 112 to ensure the timing integrity of the computing control module 13 when receiving data.

[0103] In another implementation of this embodiment, the chip further includes an on-chip power management circuit for providing operating power to the acquisition module 11, the electrical stimulation module 12, and the computing control module 13. The power management circuit is configured to generate multiple sets of supply voltages, including at least digital circuit operating voltages and analog circuit operating voltages, and to provide a high-voltage power supply (HVDD) to the current source in the electrical stimulation module 12 to meet the high-voltage swing requirements of the electrical stimulation output.

[0104] In another implementation of this embodiment, the chip further includes a wireless communication interface connected to the computing control module 13 and configured to enable wireless data interaction between the chip and an external device. The chip transmits the acquired EEG signals to the external device via the wireless communication interface and receives control commands and parameter configurations from the external device via the same interface. The wireless communication interface is selected from any one of Bluetooth, near-field communication, radio frequency identification (RFID), or Medical Implantable Communication Service (MICS) frequency band wireless communication.

[0105] In the above chip embodiment, the chip executes the following process during operation: It receives EEG signals through acquisition electrodes, which are then conditioned and converted from analog to digital by the acquisition front-end 111 and stored in a register array; the calculation and control module 13 reads and analyzes the EEG signals, generating electrical stimulation control commands based on the analysis results; the electrical stimulation module 12 routes the current source to the target stimulation electrode via a switch matrix according to the control commands, outputting an electrical stimulation signal, and simultaneously sends an indication signal to the acquisition module 11; the acquisition module 11 switches to a stimulation protection state in response to the indication signal, interrupting the acquisition path to avoid the electrical stimulation signal; after the electrical stimulation ends, the acquisition state is restored, and EEG signals are received again. The specific implementation of each of the above steps can be referred to the description of the corresponding functions in the aforementioned system and method embodiments, and will not be repeated here.

[0106] In the embodiments provided in this application, it should be understood that the disclosed systems or methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For instance, the division of circuit modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between systems or modules may be electrical, mechanical, or other forms.

[0107] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the objectives of the embodiments of this application, depending on actual needs. For example, the functional modules in the various embodiments of this application may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.

[0108] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0109] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0110] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A brain-spinal interface system, characterized in that, include: The acquisition module is configured to receive EEG signals through a multi-channel acquisition electrode. The acquisition module has multiple working states, including at least an acquisition state and a stimulation protection state. The acquisition module switches between the multiple working states according to the received input signal. In the acquisition state, the acquisition module receives and modulates the EEG signals. In the stimulation protection state, the acquisition module interrupts the EEG signal acquisition path to avoid the electrical stimulation signal. The electrical stimulation module is configured to output an electrical stimulation signal through a multi-channel stimulation electrode and send an indication signal to the acquisition module when outputting the electrical stimulation signal, so that the acquisition module switches to the stimulation protection state. as well as The calculation control module is communicatively connected to both the acquisition module and the electrical stimulation module. It is configured to send control commands to the acquisition module to switch its working state, receive EEG signals from the acquisition module, and send control commands to the electrical stimulation module based on the EEG signals to control the output of electrical stimulation signals.

2. The brain-spinal interface system according to claim 1, characterized in that, The acquisition module includes an acquisition front-end, an analog-to-digital converter, and an acquisition control logic module. The acquisition control logic module includes a state machine and a digital logic control circuit. The state machine is configured with multiple working states and switches between the multiple working states according to the input signal. The digital logic control circuit outputs a control signal according to the current state of the state machine to control the acquisition module to execute the corresponding working state.

3. The brain-spinal interface system according to claim 2, characterized in that, The multiple operating states also include an impedance detection state and a reset state; in the impedance detection state, the acquisition module performs impedance detection on the acquisition electrode. The state machine is configured to: enter the reset state for initialization after receiving a reset signal; enter the acquisition state to perform EEG signal acquisition after initialization is completed; switch to the impedance detection state to perform electrode impedance detection when receiving a test control signal; and switch to the stimulation protection state to interrupt the EEG signal acquisition pathway and avoid electrical stimulation signals when receiving a stimulation control signal.

4. The brain-spinal interface system according to claim 2, characterized in that, The acquisition front end includes an amplifier, a low-pass filter, a first switch group, and a second switch group for each acquisition channel; the first switch group is disposed between the input terminal of the amplifier and the acquisition electrode, the output terminal of the amplifier is connected to the second switch group via the low-pass filter, and the second switch group is disposed between the input terminals of the amplifiers of adjacent acquisition channels; In the acquisition state, the first switch group is closed and the second switch group is open, so that the EEG signal is output to the analog-to-digital converter after passing through the acquisition electrodes, the first switch group, the amplifier and the low-pass filter; In the stimulation protection state, the first switch group is open and the second switch group is closed to block the electrical stimulation signal from being transmitted to the amplifier through the acquisition electrode, and the input terminals of the amplifiers of adjacent acquisition channels are short-circuited by the second switch group to block crosstalk between acquisition front-end channels.

5. The brain-spinal interface system according to claim 1, characterized in that, The electrical stimulation module includes multiple current sources and a switch matrix integrated with an H-bridge driver and a switch array; wherein, the output terminal of each current source is connected to the corresponding input terminal of the switch matrix, and the multiple output terminals of the switch matrix are connected to each stimulation electrode. The switch matrix is ​​configured to selectively connect the output terminal of any current source to any stimulation electrode according to a control signal, so that the plurality of current sources are selectively connected to any electrode among the multi-channel stimulation electrodes, thereby realizing current stimulation output of any electrode.

6. The brain-spinal interface system according to claim 1, characterized in that, The computing control module and the acquisition module are connected via an SPI interface for communication. The SPI interface is configured to: receive data from the computing control module, encode the received data to obtain a write address and write data, and store the write data in the register array at the corresponding address; In response to a read command from the computing control module, target data is read from the register array and output to the computing control module via the MISO pin.

7. The brain-spinal interface system according to claim 6, characterized in that, The SPI interface includes a master clock line, master-output-slave-in data lines, master-in-slave-output data lines, and a return clock line; The return clock line is configured to send a return clock from the acquisition module to the computing control module. The return clock is synchronized with the analog-to-digital converter output data transmitted on the master-input-slave-output data line. The computing control module samples the data on the master-input-slave-output data line according to the return clock to ensure the timing integrity of the data reception.

8. The brain-spinal interface system according to claim 1, characterized in that, It also includes an LVDS interface, connected between the computing control module and the electrical stimulation module, configured to transmit electrical stimulation control commands issued by the computing control module to the electrical stimulation module in the form of low-voltage differential signals, thereby realizing long-distance, high-speed data transmission between the computing control module and the electrical stimulation module.

9. A control method for a brain-spinal interface system, characterized in that, include: The system receives and modulates electroencephalogram (EEG) signals using multi-channel acquisition electrodes. Acquire and analyze the EEG signals, and when it is determined from the EEG signals that electrical stimulation needs to be output, issue an electrical stimulation output command; In response to the electrical stimulation output command, an electrical stimulation signal is output through the multi-channel stimulation electrode, and a switching indication signal is generated simultaneously. In response to the switching indication signal, the acquisition state is switched to the stimulation protection state. In the stimulation protection state, the signal acquisition path of the multi-channel acquisition electrode is interrupted to avoid the electrical stimulation signal. When the electrical stimulation signal stops being output, the system switches back from the stimulation protection state to the acquisition state, and resumes receiving EEG signals through the multi-channel acquisition electrodes.

10. A chip, characterized in that, include: The brain-spinal interface system according to any one of claims 1 to 8.

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