Deposition mask, method of manufacturing the same, and electronic device manufactured by using the same

Abstract

The present invention relates to a deposition mask, a method of manufacturing the same, and an electronic device manufactured by using the same. The deposition mask includes a mask substrate, and a thin film including a first mask cell region having a first size and a second mask cell region having a second size, and located on the mask substrate. The thin film has a first pixel opening passing through the first mask cell region and a second pixel opening passing through the second mask cell region. The mask substrate has a first cell opening exposing the first mask cell region and a second cell opening exposing the second mask cell region.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0057092, filed with the Korean Intellectual Property Office on April 30, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a deposition mask, a method for manufacturing the deposition mask, and an electronic device manufactured using the deposition mask. Background Technology

[0003] Wearable devices, in the form of glasses or helmets, have been developed in which the focal point is formed at a distance close to the user's eyes. Wearable devices can provide users with augmented reality (AR) or virtual reality (VR) visuals. For example, wearable devices can be head-mounted display (HMD) devices or AR glasses.

[0004] In wearable devices such as HMD devices or AR glasses, a display specification of approximately 3000 pixels per inch (PPI) or higher is required to allow users to use the wearable device for extended periods without experiencing dizziness. Therefore, silicon-based organic light-emitting diode (OLEDoS) technology has emerged for use in high-resolution, small-scale organic light-emitting display devices. OLEDoS is a technology in which organic light-emitting diodes (OLEDs) are arranged on a semiconductor substrate on which complementary metal-oxide-semiconductor (CMOS) elements are arranged.

[0005] To manufacture high-resolution display panels with approximately 3000 PPI or higher, high-resolution deposition masks are required. For example, a deposition mask can be used as a shadow mask in a deposition process for forming a light-emitting layer on a backplane substrate. In the deposition process, the backplane substrate can be located on the deposition mask, and the deposition source for providing the vapor-phase deposition material can be located below the deposition mask. For example, the deposition mask may include a mask substrate and a thin film located on the mask substrate. The thin film may include mask cell regions having multiple pixel openings, and the mask substrate may include cell openings that expose the mask cell regions. Summary of the Invention

[0006] The present disclosure provides a deposition mask that can improve the efficiency of mask substrate use, a method for manufacturing the deposition mask, and an electronic device manufactured using the deposition mask.

[0007] However, the embodiments of this disclosure are not limited to those set forth herein. The above and other embodiments of this disclosure will become more apparent to those skilled in the art upon which this disclosure pertains from the following detailed description.

[0008] In one or more embodiments of this disclosure, a deposition mask may include: a mask substrate and a thin film located on the mask substrate. The thin film may include a first mask cell region having a first size and a second mask cell region having a second size. The thin film may have a first pixel opening penetrating the first mask cell region and a second pixel opening penetrating the second mask cell region. The mask substrate may have a first cell opening exposing the first mask cell region and a second cell opening exposing the second mask cell region.

[0009] In one or more embodiments of this disclosure, the second mask unit region may be located on the edge portion of the mask substrate, and the second size may be smaller than the first size.

[0010] In one or more embodiments of this disclosure, the gap between the second mask unit regions may be equal to or less than the gap between the first mask unit regions.

[0011] In one or more embodiments of this disclosure, the second mask unit region may be arranged symmetrically with respect to the center of the mask substrate.

[0012] In one or more embodiments of this disclosure, the second dimension may be about 0.3 to about 0.9 times the first dimension.

[0013] In one or more embodiments of this disclosure, the deposition mask may further include a post-inorganic film located on the rear surface of the mask substrate. The thin film may be located on the front surface of the mask substrate, and the post-inorganic film may comprise the same material as the thin film and have a greater thickness than the thin film.

[0014] In one or more embodiments of this disclosure, the post-inorganic membrane may have the same thickness as the thin film and have a greater residual stress than the thin film.

[0015] In one or more embodiments of this disclosure, the film may further include a first peripheral region around a first mask unit region and a second peripheral region around a second mask unit region, and have a first groove defining the first peripheral region and a second groove defining the second peripheral region.

[0016] In one or more embodiments of this disclosure, the post-inorganic membrane may comprise the same material as the thin film and have the same thickness as the thin film, and the area of ​​the post-inorganic membrane may be equal to the area of ​​the remaining area of ​​the thin film excluding the first mask unit region, the first peripheral region, the second mask unit region, and the second peripheral region.

[0017] In one or more embodiments, a method of manufacturing a deposition mask may include: forming a thin film on a mask substrate, the thin film including a first mask unit region having a first size and a second mask unit region having a second size; forming a first pixel opening penetrating the first mask unit region and a second pixel opening penetrating the second mask unit region; and forming a first unit opening exposing the first mask unit region and a second unit opening exposing the second mask unit region.

[0018] In one or more embodiments of this disclosure, a second mask unit region may be formed on an edge portion of a mask substrate, and the second dimension may be smaller than the first dimension.

[0019] In one or more embodiments of this disclosure, the gap between the second mask unit regions may be equal to or less than the gap between the first mask unit regions.

[0020] In one or more embodiments of this disclosure, the second mask unit region may be formed to be arranged symmetrically with respect to the center of the mask substrate.

[0021] In one or more embodiments of this disclosure, the second dimension may be about 0.3 to about 0.9 times the first dimension.

[0022] In one or more embodiments of this disclosure, the method may further include forming a post-inorganic film on the rear surface of a mask substrate. A thin film may be formed on the front surface of the mask substrate, and the post-inorganic film may comprise the same material as the thin film and have a greater thickness than the thin film.

[0023] In one or more embodiments of this disclosure, the post-inorganic membrane may have the same thickness as the thin film and have a greater residual stress than the thin film.

[0024] In one or more embodiments of this disclosure, the method may further include: forming a first groove defining a first peripheral region surrounding a first mask unit region and a second groove defining a second peripheral region surrounding a second mask unit region.

[0025] In one or more embodiments of this disclosure, the post-inorganic membrane may comprise the same material as the thin film and have the same thickness as the thin film, and the area of ​​the post-inorganic membrane may be equal to the area of ​​the remaining area of ​​the thin film excluding the first mask unit region, the first peripheral region, the second mask unit region, and the second peripheral region.

[0026] In one or more embodiments of this disclosure, an electronic device may include a display panel. The display panel may include a backplane substrate and a plurality of light-emitting layers formed on the backplane substrate using a deposition mask. The deposition mask may include a mask substrate and a thin film. The thin film includes a first mask unit region having a first size and a second mask unit region having a second size and is located on the mask substrate. The thin film may have a first pixel opening penetrating the first mask unit region and a second pixel opening penetrating the second mask unit region. The mask substrate may have a first unit opening exposing the first mask unit region and a second unit opening exposing the second mask unit region. The plurality of light-emitting layers may be formed from light-emitting materials provided through a first pixel opening in one of the first mask unit regions or a second pixel opening in one of the second mask unit regions.

[0027] In one or more embodiments of this disclosure, the electronic device may further include at least one of a processor, a memory, and a power module.

[0028] In one or more embodiments as described above, a second mask unit region having a smaller size than the first mask unit region may be located on an edge portion of the mask substrate. Accordingly, the number of mask unit regions located on the mask substrate can be increased, and as a result, the utilization efficiency of the mask substrate can be improved.

[0029] Other features and embodiments will become apparent from the following detailed description and accompanying drawings. Attached Figure Description

[0030] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0031] Figure 1 This is a block diagram of an electronic device according to one or more embodiments of the present disclosure;

[0032] Figure 2 These are schematic diagrams of electronic devices according to various embodiments of the present disclosure;

[0033] Figure 3 This is an exploded perspective view illustrating a display device according to one or more embodiments of the present disclosure;

[0034] Figure 4 It is a diagram. Figure 3 Block diagram of the display device shown;

[0035] Figure 5 It is a diagram. Figure 4 The equivalent circuit diagram of the example of the first sub-pixel shown;

[0036] Figure 6 It is a diagram. Figure 3 A schematic floor plan of an example of a display panel shown;

[0037] Figure 7 It is a diagram. Figure 6 A schematic enlarged plan view of an example of the display area shown;

[0038] Figure 8 It is a diagram. Figure 6 A schematic enlarged plan view of another example of the display area shown;

[0039] Figure 9 It is shown in the diagram along Figure 7 A schematic cross-sectional view of an example display panel taken by line I1-I1' shown;

[0040] Figure 10 It is shown in the diagram along Figure 7 A schematic cross-sectional view of another example of a display panel, shown by line I1-I1'.

[0041] Figure 11 It is shown in the diagram along Figure 7 A schematic cross-sectional view of another example of a display panel, shown by line I1-I1'.

[0042] Figure 12 This is a schematic perspective view illustrating an example of a head-mounted display;

[0043] Figure 13 It is a diagram. Figure 12 A schematic exploded perspective view of the head-mounted display shown;

[0044] Figure 14 This is a schematic perspective view illustrating another example of a head-mounted display;

[0045] Figure 15 This is a schematic diagram illustrating a deposition mask according to one or more embodiments and a deposition apparatus including the deposition mask;

[0046] Figure 16 It is a diagram. Figure 15 A schematic bottom view of the backplate substrate shown;

[0047] Figure 17 It is a diagram. Figure 15 A schematic plan view of the deposition mask shown;

[0048] Figure 18 It is a diagram. Figure 17 A schematic plan view of the first and second mask unit areas shown in the figure;

[0049] Figure 19 It is along Figure 18 The schematic cross-sectional view taken by line I2-I2' shown in the figure;

[0050] Figure 20 It is a diagram. Figure 18 A schematic plan view of another example of the deposition mask shown;

[0051] Figure 21 It is along Figure 20 The schematic cross-sectional view shown is taken by line I3-I3'; and

[0052] Figures 22 to 27 This is a schematic cross-sectional view illustrating a method for manufacturing a deposition mask according to one or more embodiments. Detailed Implementation

[0053] This disclosure will now be described more fully below with reference to the accompanying drawings, in which various embodiments of the disclosure are illustrated. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0054] It will also be understood that when an element or layer is referred to as being "on" another element or layer, the element or layer may be directly on that other element or layer, or there may be an intervening layer. Throughout the specification, the same reference numerals indicate the same parts.

[0055] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure. Similarly, the second element may also be referred to as the first element.

[0056] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “the,” and “at least one” do not refer to a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limited to “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprising” or “including” indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0057] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship of one element relative to another, as illustrated in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, relative terms are intended to cover different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “down” of another element will be oriented to be “up” of that other element. Thus, depending on the specific orientation of the drawing, the term “down” can cover both “down” and “up” orientations. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” another element will be oriented to be “above” that other element. Thus, the terms “below” and “under” can cover both “up” and “down” orientations.

[0058] Features of the various embodiments in the various embodiments of this disclosure may be combined with each other in part or in whole, and may operate in concert with each other in a variety of technical ways. The various embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0059] Considering the measurements discussed and the errors associated with the measurement of specific quantities (i.e., limitations of the measurement system), the terms "about" or "approximately" as used herein include the stated values ​​and mean within an acceptable deviation of the specific values ​​as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated values.

[0060] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having meanings consistent with their meanings in the relevant art and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0061] Furthermore, the phrase "in a plan view" means when viewing a portion of the object from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section taken by vertically cutting the portion of the object from the side. The terms "overlapping" or "overlapping" mean that the first object may be above, below, or to the side of the second object, and vice versa. Additionally, the term "overlapping" can include layering, stacking, facing or confronting, extending across, covering or partially covering, or any other suitable term as would be understood and appreciated by one of ordinary skill in the art. The expression "non-overlapping" can include meanings such as "separated from," "placed next to," or "offset from," and any other suitable equivalent as would be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "confronting" can mean that the first object may be directly or indirectly opposite the second object. In the case where a third object is located between the first and second objects, the first and second objects can be understood as being indirectly opposite each other, although still facing each other.

[0062] In the specification and claims, for the purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in connected or separate senses and can be understood to be equivalent to "and / or". In the specification and claims, for the purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group consisting of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0063] In this document, references are made to schematic cross-sectional views of idealized embodiments to describe the embodiments. Thus, variations in the shape of the figures can be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shape of the areas illustrated herein, but should include deviations in shape due to, for example, manufacturing processes. For example, areas illustrated or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners in the figures may be rounded. Therefore, the areas illustrated in the figures are purely schematic, and the shapes of the areas illustrated in the figures are not intended to illustrate precise shapes of the areas and are not intended to limit the scope of this disclosure, the present claims, and their equivalents.

[0064] Those skilled in the art will understand, in consideration of the whole content of this disclosure, that various suitable features of the various embodiments of this disclosure may be combined in part or in whole, or combined with each other, and may be technically interlocked in various suitable ways, and that the embodiments may be implemented independently of each other, or in combination with each other in any suitable way, unless otherwise stated or implied.

[0065] In the following description, embodiments will be described in detail with reference to the accompanying drawings.

[0066] The display device according to one or more embodiments of the present disclosure can be applied to various electronic devices. The electronic device according to one or more embodiments of the present disclosure includes the display device described below, and may further include modules or devices with additional functions in addition to the display device.

[0067] Figure 1 This is a block diagram of an electronic device according to one or more embodiments of the present disclosure.

[0068] refer to Figure 1 An electronic device 10 according to one or more embodiments of the present disclosure may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0069] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0070] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application program stored in the memory 13, image data signals and / or input control signals are transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0071] The power module 14 may include a power module such as, for example, a power adapter and / or a battery, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10.

[0072] At least one component of an electronic device 10 according to one or more embodiments of the present disclosure may be included in a display device 20 according to one or more embodiments of the present disclosure (e.g., see [link to display device 20]). Figure 3 Furthermore, some modules that are functionally included in a single module may be included in the display device 20, and other modules may be provided independently of the display device 20. For example, the display device 20 may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided in the electronic device 10 as other devices besides the display device 20.

[0073] Figure 2 This is a schematic diagram of an electronic device according to various embodiments of the present disclosure.

[0074] refer to Figure 2 The various electronic devices to which the display device 20 according to one or more embodiments of the present disclosure is applied may include not only image display electronic devices (such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e), but also wearable electronic devices (such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c) that include display modules, and in-vehicle electronic devices 10_3 that include display modules (such as rearview mirror displays and central information displays (CIDs) arranged on the dashboard and central instrument panel of a vehicle).

[0075] Figure 3 This is an exploded perspective view illustrating a display device according to one or more embodiments of the present disclosure. Figure 4 It is a diagram. Figure 3 Block diagram of the display device shown.

[0076] refer to Figure 3 and Figure 4The display device 20 according to one or more embodiments can be a device for displaying moving images and / or still images. The display device 20 according to one or more embodiments can be used as an electronic device 10 or a display module 11 of an electronic device 10. For example, the display device 20 according to one or more embodiments can be applied to portable electronic devices 10 such as mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and / or ultra-mobile PCs (UMPCs). The display device 20 according to one or more embodiments can be applied as a display module 11 of electronic devices 10 such as televisions, laptops, monitors, and / or billboards or Internet of Things (IoT) terminals. The display device 20 according to one or more embodiments can be applied to electronic devices 10 such as smartwatches, smartwatch phones, and / or head-mounted displays (HMDs) for implementing virtual reality and / or augmented reality.

[0077] The display device 20 according to one or more embodiments may include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit (e.g., a timing controller) 400, and a power supply circuit (e.g., a power supply unit) 500.

[0078] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 intersects the long side in the second direction DR2 may be a right angle, or may be rounded with an appropriate curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to other polygonal shapes, circular shapes, or elliptical shapes. The planar shape of the display device 20 may be consistent with the planar shape of the display panel 100, but this disclosure is not limited thereto.

[0079] The display panel 100 may include multiple pixels PX, multiple scan lines SL, multiple emission control lines EL, multiple data lines DL, a scan driver 610, an emission driver 620, and a data driver 700. For example... Figure 4 As shown, the display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0080] Multiple pixels (PX) can be set in the display area (DAA). These pixels (PX) can be arranged in a matrix along a first direction (DR1) and a second direction (DR2). For example, multiple pixels (PX) can be arranged along the rows and columns of a matrix along the first direction (DR1) and the second direction (DR2). Multiple scan lines (SL) and multiple emission control lines (EL) can extend along the first direction (DR1) and be arranged along the second direction (DR2). Multiple data lines (DL) can extend along the second direction (DR2) and be arranged along the first direction (DR1).

[0081] Multiple scan lines SL can include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. Multiple emit control lines EL can include multiple first emit control lines ECL1 and multiple second emit control lines ECL2.

[0082] Multiple pixels PX can include multiple sub-pixels SP1, SP2, and SP3. For example... Figure 5 As shown, the multiple sub-pixels SP1, SP2, and SP3 can each include multiple pixel transistors, and these pixel transistors can be formed using semiconductor processes and are disposed on a semiconductor substrate SSUB (see [reference]). Figure 9 For example, multiple pixel transistors can be formed using complementary metal-oxide-semiconductor (CMOS), but this disclosure is not limited thereto.

[0083] Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to a write scan line GWL, a control scan line GCL, a bias scan line GBL, a first emitt control line ECL1, a second emitt control line ECL2, and a data line DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage from the data line DL in response to a write scan signal from the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0084] The scan driver 610, transmit driver 620, and data driver 700 can be located in the non-display area NDA.

[0085] The scan driver 610 includes multiple scan transistors, and the emitter driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed on a semiconductor substrate SSUB using semiconductor processes (see [link to SSUB]). Figure 9 In, for example, multiple scanning transistors and multiple light-emitting transistors can be formed by CMOS, but this disclosure is not limited thereto.

[0086] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS from the timing control circuit 400, and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal in response to the scan timing control signal SCS, and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line GBL.

[0087] The transmit driver 620 includes a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 can receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 can generate a first transmit control signal based on the transmit timing control signal ECS and sequentially outputs the first transmit control signal to the first transmit control line ECL1. The second transmit control driver 622 can generate a second transmit control signal based on the transmit timing control signal ECS and sequentially outputs the second transmit control signal to the second transmit control line ECL2.

[0088] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed on a semiconductor substrate SSUB using semiconductor processes (see [reference]). Figure 9 For example, multiple data transistors can be formed using CMOS, but this disclosure is not limited thereto.

[0089] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0090] The heat dissipation layer 200 may overlap the display panel 100 on a third direction DR3 in the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a material with high thermal conductivity, such as graphite or metals such as silver (Ag), copper (Cu) and / or aluminum (Al).

[0091] Circuit board 300 can be electrically connected to the first pad portion of display panel 100 PDA1 using conductive adhesive components such as anisotropic conductive film (see...). Figure 6 Multiple first pads PD1 (see) Figure 6 Circuit board 300 can be a flexible printed circuit board (FPCB) with flexible material or a flexible film. Although circuit board 300 is in Figure 3 The circuit board 300 is shown unfolded, but it can be bent. In this case, one end of the circuit board 300 can be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The other end of the circuit board 300 can be attached to the first pad portion PDA1 of the display panel 100 using conductive adhesive components (see [reference]). Figure 6 Multiple first pads PD1 (see) Figure 6 One end of circuit board 300 can be the opposite end of the other end of circuit board 300.

[0092] The timing control circuit 400 can receive digital video data DATA and timing signals input from an external source. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0093] The power supply circuit 500 can generate multiple panel driving voltages based on external power voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply these voltages to the display panel 100. This will be discussed later. Figure 5 Describe the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0094] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In this case, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0095] Alternatively, each of the timing control circuit 400 and the power supply circuit 500 can be disposed in the non-display area NDA of the display panel 100, similar to the scan driver 610, transmit driver 620, and data driver 700. In this case, the timing control circuit 400 may include multiple timing transistors, and each power supply circuit 500 may include multiple power transistors. The multiple timing transistors and the multiple power transistors can be formed on a semiconductor substrate SSUB using semiconductor processes (see [link to semiconductor substrate]). Figure 9 In, for example, multiple sequential transistors and multiple power transistors can be formed by CMOS, but this disclosure is not limited thereto. Each of the timing control circuit 400 and the power supply circuit 500 can be disposed in the data driver 700 and the first pad portion of PDA1 (see...). Figure 6 )between.

[0096] Figure 5 It is a diagram. Figure 4 The equivalent circuit diagram of the example of the first sub-pixel shown.

[0097] refer to Figure 5 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line ECL1, the second emit control line ECL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to the first drive voltage line VSL, to which a first drive voltage VSS corresponding to a low potential voltage is applied; the second drive voltage VDL, to which a second drive voltage VDD corresponding to a high potential voltage is applied; and the third drive voltage VIL, to which a third drive voltage VINT corresponding to the initialization voltage is applied.

[0098] The first sub-pixel SP1 may include a light-emitting element LE, a first capacitor CP1, a second capacitor CP2, and multiple transistors T1 to T6.

[0099] The light-emitting element LE emits light in response to a drive current flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE can be proportional to the drive current. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode (OLED) including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but this disclosure is not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode; in this case, the light-emitting element LE can be a miniature light-emitting diode.

[0100] The first transistor T1 can be a driving transistor that controls the source-drain current (hereinafter referred to as "driving current") flowing between the source and drain electrodes of the first transistor T1 according to the voltage applied to the gate electrode of the first transistor T1.

[0101] A second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by the write scan signal of the write scan line GWL to connect that electrode of the first capacitor CP1 to the data line DL. Accordingly, the data voltage of the data line DL can be applied to that electrode of the first capacitor CP1.

[0102] A third transistor T3 can be disposed between a first node N1 (e.g., the first node N1 connected to the gate electrode of the first transistor) and a second node N2 (e.g., the second node N2 connected to the drain electrode of the first transistor T1). The third transistor T3 is turned on by a control scan signal controlling the scan line GCL to connect the first node N1 to the second node N2. For this reason, when the gate electrode and drain electrode of the first transistor T1 are connected, the first transistor T1 can operate like a diode (e.g., the first transistor T1 can be connected like a diode).

[0103] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emitter control signal of the first emitter control line ECL1 to connect the second node N2 to the third node N3. Correspondingly, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. A fifth transistor T5 can be disposed between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third drive voltage line VIL. Correspondingly, the third drive voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE.

[0104] A sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emitter control signal of the second emitter control line ECL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Accordingly, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1.

[0105] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL.

[0106] Each of the first to sixth transistors T1 to T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first to sixth transistors T1 to T6 can be a P-type MOSFET, but this disclosure is not limited thereto. Each of the first to sixth transistors T1 to T6 can be an N-type MOSFET. Alternatively, some of the first to sixth transistors T1 to T6 can be P-type MOSFETs, and each of the remaining transistors can be an N-type MOSFET.

[0107] Despite Figure 5 The first sub-pixel SP1 shown in the diagram includes six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 5 The circuit diagram shown. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 5 The quantities shown.

[0108] Furthermore, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 can be combined with... Figure 5 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the descriptions of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 are not repeated in this disclosure.

[0109] Figure 6 It is a diagram. Figure 3 A schematic floor plan of an example of a display panel shown.

[0110] refer to Figure 6The display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0111] The scan driver 610 can be disposed on a first side of the display area DAA, and the transmit driver 620 can be disposed on a second side of the display area DAA. For example, the scan driver 610 can be disposed on one side of the display area DAA in the first direction DR1, and the transmit driver 620 can be disposed on the other side of the display area DAA in the first direction DR1. However, this disclosure is not limited thereto, and the scan driver 610 and the transmit driver 620 can be disposed on both the first and second sides of the display area DAA.

[0112] The first pad portion PDA1 may include a plurality of first pads PD1 connected to pads or bumps on the circuit board 300 by conductive adhesive members. The first pad portion PDA1 may be located on the third side of the display area DAA. For example, the first pad portion PDA1 may be located on one side of the display area DAA in the second direction DR2. The first pad portion PDA1 may be located outside the data driver 700 in the second direction DR2.

[0113] The second pad portion PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating correctly. The multiple second pads PD2 may be connected to a fixture or probe pins during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a rigid printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0114] The second pad portion PDA2 can be located on the fourth side of the display area DAA. For example, the second pad portion PDA2 can be located on the other side of the display area DAA in the second direction DR2. The second pad portion PDA2 can also be located outside the second distribution circuit 720 in the second direction DR2.

[0115] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to multiple data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer greater than or equal to 2) data lines DL, and as a result, the number of multiple first pads PD1 can be reduced. The first distribution circuit 710 can be disposed on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed on one side of the display area DAA in the second direction DR2.

[0116] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each pixel PX in the display area DAA. The second distribution circuit 720 can be located on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be located on the other side of the display area DAA in the second direction DR2.

[0117] The cathode connection portion CCA can be the display element layer EML (see [link]). Figure 9 The second electrode CAT (see) Figure 9 The area connected to the first drive voltage line VSL of the non-display area NDA. The cathode connection portion CCA can be located outside at least one side of the display area DAA. For example, the cathode connection portion CCA can be located outside at least one of the left, right, top, and bottom sides of the display area DAA. Alternatively, as Figure 6 As shown, in order to reduce or minimize the deviation of the first drive voltage VSS caused by the voltage drop (IR drop) or voltage rise (IR rise) of the second electrode CAT in the display area DAA, the cathode connection portion CCA can be set around the display area DAA (e.g., around the display area DAA).

[0118] Figure 7 It is a diagram. Figure 6 A schematic enlarged plan view of an example of the display area shown. Figure 8 It is a diagram. Figure 6 A schematic enlarged plan view of another example of the display area shown.

[0119] refer to Figure 7 and Figure 8 Each pixel PX in the pixel PX includes a first emission region EA1, which is the emission region of the first sub-pixel SP1; a second emission region EA2, which is the emission region of the second sub-pixel SP2; and a third emission region EA3, which is the emission region of the third sub-pixel SP3.

[0120] like Figure 7 and Figure 8 As shown, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a quadrilateral or hexagonal shape in the plan view, but this disclosure is not limited thereto. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape, a circular shape, an elliptical shape, or an atypical shape other than quadrilateral and hexagonal in the plan view.

[0121] like Figure 7 As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 can be adjacent to each other in the first direction DR1. Furthermore, the first emission region EA1 and the third emission region EA3 can be adjacent to each other in the first direction DR1. Additionally, the second emission region EA2 and the third emission region EA3 can be adjacent to each other in the second direction DR2. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be different.

[0122] Alternatively, such as Figure 8 As shown, the emission regions EA1, EA2, EA3, and EA4 can have a hexagonal shape in the plan view. In this case, the first emission region EA1 and the third emission region EA3 can be adjacent in the first direction DR1, and the second emission region EA2 and the fourth emission region EA4 can be adjacent in the second direction DR2. Furthermore, the first emission region EA1 and the second emission region EA2 can be adjacent in the first oblique direction DD1, and the second emission region EA2 and the third emission region EA3 can be adjacent in the second oblique direction DD2. Additionally, the first emission region EA1 and the fourth emission region EA4 can be adjacent in the second oblique direction DD2, and the third emission region EA3 and the fourth emission region EA4 can be adjacent in the first oblique direction DD1. The first oblique direction DD1 can be the direction between the first direction DR1 and the second direction DR2, and can refer to a direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2, and the second oblique direction DD2 can be a direction perpendicular to the first oblique direction DD1.

[0123] The first sub-pixel SP1 can emit a first light, the second sub-pixel SP2 can emit a second light, and the third sub-pixel SP3 can emit a third light. Here, the first light can be light in the blue wavelength band, the second light can be light in the green wavelength band, and the third light can be light in the red wavelength band. For example, the blue wavelength band can be the wavelength band of light with a main peak wavelength in the range of approximately 370nm to 460nm, the green wavelength band can be the wavelength band of light with a main peak wavelength in the range of approximately 480nm to 560nm, and the red wavelength band can be the wavelength band of light with a main peak wavelength in the range of approximately 600nm to 750nm.

[0124] like Figure 7 As shown, each pixel PX in the plurality of pixels PX may include three emission regions EA1, EA2, and EA3, or as shown in the figure. Figure 8 As shown, each of the plurality of pixels PX may include four emission regions EA1, EA2, EA3, and EA4. In this case, the fourth emission region EA4 may emit the same second light as the second emission region EA2, but this disclosure is not limited thereto.

[0125] The emission regions of multiple pixels PX can be arranged in a strip structure along the first direction DR1, such as... Figure 8 The Pentium shown depicts emission regions EA1, EA2, EA3, and EA4 arranged in a diamond shape. ® The structure is arranged in a hexagonal shape, or in which the emission areas are arranged in a hexagonal shape. This PENTILE ® The arrangement structure can be referred to as an RGBG matrix structure (e.g., Pentium). ® Matrix structure or RGBG structure (e.g., Pentium) ® Structure). PENTILE ® It is a registered trademark of Samsung Display Co., Ltd. of the Republic of Korea.

[0126] Figure 9 It is shown in the diagram along Figure 7 The diagram shows a schematic cross-sectional view of an example display panel taken by line I1-I1'.

[0127] refer to Figure 9 The display panel 100 includes a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), an optical layer (OPL), a cover layer (CVL), and a polarizing plate (POL).

[0128] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) can be a reference. Figure 5 The first to sixth transistors, T1 to T6, are described.

[0129] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be disposed on the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the first type of impurity. For example, when the first type of impurity is a P-type impurity, the second type of impurity can be an N-type impurity. Alternatively, when the first type of impurity is an N-type impurity, the second type of impurity can be a P-type impurity.

[0130] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0131] The lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating film (SINS) can be disposed on the side surface of the gate electrode GE. The side insulating film (SINS) can also be disposed on the lower insulating film (BINS).

[0132] Each of the source region SA and the drain region DA can be a region doped with a type 1 impurity. The gate electrode GE of the pixel transistor PTR can overlap with the well region WA on a third-direction DR3 in the thickness direction of the semiconductor substrate SSUB. The channel region CH can overlap with the gate electrode GE on a third-direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the other side of the gate electrode GE.

[0133] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. Due to the lower insulating film BINS, the first low-concentration impurity region LDD1 can be a region having an impurity concentration lower than that of the source region SA. Due to the lower insulating film BINS, the second low-concentration impurity region LDD2 can be a region having an impurity concentration lower than that of the drain region DA. Due to the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA can be increased, thereby increasing the length of the channel region CH of each pixel transistor PTR in the pixel transistor PTR.

[0134] A first semiconductor insulating film SINS1 can be disposed on a semiconductor substrate SSUB. A second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1.

[0135] Multiple contact terminals (CTEs) can be disposed on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of each pixel transistor (PTR) through a hole penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The multiple contact terminals (CTEs) can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or alloys including one or more of these.

[0136] The third semiconductor insulating film SINS3 can be disposed on the side surface of each of the plurality of contact terminals CTEs and on the second semiconductor insulating film SINS2. The top surface of each of the plurality of contact terminals CTEs can be exposed by the third semiconductor insulating film SINS3 without being covered by the third semiconductor insulating film SINS3.

[0137] Each of the first semiconductor insulating film SINS1, the second semiconductor insulating film SINS2, and the third semiconductor insulating film SINS3 may be made of silicon carbonitride (SiCN) and / or silicon oxide (SiO2). x It can be formed by inorganic membranes, but this disclosure is not limited thereto.

[0138] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate such as a polyimide substrate. In this case, the pixel transistor PTR can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, while the polymer resin substrate can be a flexible substrate that can be bent and / or rolled up.

[0139] The backplane EBP of the light-emitting element includes multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple interlayer insulating films INS1 to INS9.

[0140] The insulating films INS1 to INS9 between the first to ninth layers are used to insulate the first to eighth conductive layers ML1 to ML8. The first to eighth conductive layers ML1 to ML8 are used to connect multiple contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving... Figure 5 The circuit of the first sub-pixel SP1 shown.

[0141] For example, the first to sixth transistors T1 to T6 are formed only in the semiconductor backplane SBP, and the connection between the first to sixth transistors T1 to T6 and the first capacitor CP1 and the second capacitor CP2 is accomplished through the first to eighth conductive layers ML1 to ML8. Furthermore, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE is also accomplished through the first to eighth conductive layers ML1 to ML8.

[0142] The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 can be formed from substantially the same material. The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 can be formed from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or alloys including one or more of these. The first to eighth interlayer insulating films INS1 to INS8 can be made from substantially the same material. The first to eighth interlayer insulating films INS1 to INS8 can be made from silicon oxide (SiO2). x It can be formed by inorganic membranes, but this disclosure is not limited thereto.

[0143] The ninth interlayer insulating film INS9 can be disposed on the eighth interlayer insulating film INS8 and the eighth conductive layer ML8. The ninth interlayer insulating film INS9 can be made of silicon oxide (SiO2). x It can be formed by inorganic membranes, but this disclosure is not limited thereto.

[0144] Each of the ninth vias VA9 can penetrate the ninth interlayer insulating film INS9 and connect to the exposed eighth conductive layer ML8. The ninth vias VA9 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and / or alloys including one or more of them.

[0145] The display element layer (EML) can be disposed on the backplane (EBP) of the light-emitting element. The display element layer (EML) may include a tenth interlayer insulating film (INS10) and an eleventh interlayer insulating film (INS11), a reflective electrode (RL), a first electrode (AND), a light-emitting stack (IL), a second electrode (CAT), a pixel defining film (PDL), and multiple trenches (TRC).

[0146] The reflective electrode RL can be disposed on the ninth interlayer insulating film INS9. Each of the reflective electrodes RL may include at least one of reflective electrodes RL1, RL2, RL3, and RL4. For example, as Figure 9As shown, each of the reflective electrodes RL may include the first to fourth reflective electrodes RL1, RL2, RL3 and RL4.

[0147] The first reflective electrode RL1 can be disposed on the ninth interlayer insulating film INS9 and can be connected to the ninth via VA9. Each of the second reflective electrodes RL2 can be disposed on the corresponding first reflective electrode RL1. Each of the third reflective electrodes RL3 can be disposed on the corresponding second reflective electrode RL2. Each of the fourth reflective electrodes RL4 can be disposed on the corresponding third reflective electrode RL3.

[0148] Since the fourth reflective electrode RL4 is the electrode that substantially reflects light from the light-emitting element LE, the thickness of the fourth reflective electrode RL4 can be greater than the thickness of each of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3; however, this disclosure is not limited thereto. For example, in one or more embodiments, since the second reflective electrode RL2 is the electrode that substantially reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4.

[0149] The reflective electrode RL can be formed from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or alloys comprising one or more of these. For example, the first reflective electrode RL1 can contain titanium nitride (TiN), the second reflective electrode RL2 can contain aluminum (Al), the third reflective electrode RL3 can contain titanium nitride (TiN), and the fourth reflective electrode RL4 can contain titanium (Ti).

[0150] The tenth interlayer insulating film INS10 can be disposed on the ninth interlayer insulating film INS9. The tenth interlayer insulating film INS10 can be disposed between adjacent reflective electrodes RL. The tenth interlayer insulating film INS10 can be a film used to flatten the stepped portion caused by the reflective electrode RL. The eleventh interlayer insulating film INS11 can be disposed on the tenth interlayer insulating film INS10 and the reflective electrode RL.

[0151] The tenth interlayer insulating film INS10 and the eleventh interlayer insulating film INS11 can be made of silicon oxide (SiO2). x It can be formed by inorganic membranes, but this disclosure is not limited thereto.

[0152] The eleventh interlayer insulating film INS11 can be an optical auxiliary film used to adjust the resonant distance of light emitted from the light-emitting stack IL in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The thickness of the eleventh interlayer insulating film INS11 can be different for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. That is, in order to adjust the distance from the reflective electrode RL to the second electrode CAT according to the dominant wavelength of the light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the thickness of the eleventh interlayer insulating film INS11 can be set for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0153] For example, such as Figure 9 As shown, the thickness of the eleventh interlayer insulating film INS11 in the first sub-pixel SP1 can be greater than the thickness of the eleventh interlayer insulating film INS11 in the second sub-pixel SP2, and the thickness of the eleventh interlayer insulating film INS11 in the second sub-pixel SP2 can be greater than the thickness of the eleventh interlayer insulating film INS11 in the third sub-pixel SP3. In this case, the distance between the first electrode AND and the reflective electrode RL in the first sub-pixel SP1 is greater than the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2. Furthermore, the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2 is greater than the distance between the first electrode AND and the reflective electrode RL in the third sub-pixel SP3.

[0154] Each of the tenth vias VA10 can penetrate the eleventh interlayer insulating film INS11 and can be connected to the exposed fourth reflective electrode RL4. The tenth vias VA10 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or alloys including one or more of these. The thickness of the tenth via VA10 in the first sub-pixel SP1 can be greater than the thickness of the tenth via VA10 in the second sub-pixel SP2, and the thickness of the tenth via VA10 in the second sub-pixel SP2 can be greater than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0155] The first electrode AND of each light-emitting element LE can be disposed on the eleventh interlayer insulating film INS11 and can be connected to the tenth via VA10. The first electrode AND of each light-emitting element LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, the reflective electrode RL, the first to ninth vias VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each light-emitting element LE can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or an alloy thereof, or a transparent conductive oxide. For example, the first electrode AND of each light-emitting element LE can be titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), and / or indium zinc oxide (IZO), but this disclosure is not limited thereto.

[0156] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each light-emitting element (LE). The PDL can cover the edge of the first electrode AND of each light-emitting element (LE). The PDL can separate a first emission region EA1, a second emission region EA2, and a third emission region EA3. Each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be a region in which a light-emitting element LE comprising the first electrode AND, a light-emitting stack IL, and a second electrode CAT is disposed.

[0157] The first emission region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT in the first sub-pixel SP1 are sequentially stacked to emit light. The second emission region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT in the second sub-pixel SP2 are sequentially stacked to emit light. The third emission region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT in the third sub-pixel SP3 are sequentially stacked to emit light.

[0158] The pixel-defining film (PDL) may include a first pixel-defining film (PDL1), a second pixel-defining film (PDL2), and a third pixel-defining film (PDL3). The first pixel-defining film (PDL1) may be disposed on the edge of the first electrode AND of each light-emitting element (LE). The second pixel-defining film (PDL2) may be disposed on the first pixel-defining film (PDL1), and the third pixel-defining film (PDL3) may be disposed on the second pixel-defining film (PDL2). The first pixel-defining film (PDL1), the second pixel-defining film (PDL2), and the third pixel-defining film (PDL3) may be made of silicon oxide (SiO2). x The first pixel defining film PDL1 and the third pixel defining film PDL3 can be formed from silicon nitride (SiN). x The second pixel defining film (PDL2) can be formed from an inorganic film of the form factor (SiO2). x It is formed from an inorganic film. The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 can each have a thickness of approximately 500 Å.

[0159] To reduce or prevent the possibility of the first encapsulated inorganic film TFE1 being cut due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may have a cross-sectional structure with stepped portions. Step coverage refers to the ratio of the thickness of the film formed on the inclined portion to the thickness of the film formed on the flat portion. The lower the step coverage, the greater the possibility of the film being cut at the inclined portion.

[0160] Each of the multiple trench TRCs can extend through the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. The eleventh interlayer insulating film INS11 can be partially recessed at each of the multiple trench TRCs.

[0161] At least one trench TRC can be set between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 9 The diagram shows two trench TRCs positioned between adjacent sub-pixels SP1, SP2, and SP3, but this disclosure is not limited thereto.

[0162] The light-emitting stacked IL can include multiple stacked layers IL1, IL2 and IL3. Figure 9 The illustrated light-emitting stack IL has a three-tiered structure including a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3, but this disclosure is not limited thereto. For example, as Figure 10 As shown, the light-emitting stacked IL can have a dual-tandem structure including two stacked layers IL1 and IL2.

[0163] In a three-tiered cascade structure, the light-emitting stack IL can have a cascaded structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different lights. For example, the light-emitting stack IL may include a first stacked layer IL1 that emits a first light, a second stacked layer IL2 that emits a second light, and a third stacked layer IL3 that emits a third light. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 can be stacked sequentially.

[0164] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first light-emitting layer emitting first light, and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second light-emitting layer emitting second light, and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third light-emitting layer emitting third light, and a third electron transport layer are sequentially stacked.

[0165] A first charge generation layer for supplying holes to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first stacked layer IL1 and a P-type charge generation layer for supplying holes to the second stacked layer IL2. The N-type charge generation layer may include a dopant of a metallic material.

[0166] A second charge generation layer for supplying holes to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be disposed between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stacked layer IL2 and a P-type charge generation layer for supplying holes to the third stacked layer IL3.

[0167] A first stacked layer IL1 can be disposed on the first electrode AND and the pixel defining film PDL, and the residual film RIL disposed on the bottom surface of each trench TRC can be made of the same material as the first stacked layer IL1. Due to the trench TRC, the first stacked layer IL1 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A second stacked layer IL2 can be disposed on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 can be cut between adjacent sub-pixels SP1, SP2, and SP3. A cavity ESS or blank space can be disposed between the residual film RIL in the trench TRC and the second stacked layer IL2. A third stacked layer IL3 can be disposed on the second stacked layer IL2. The third stacked layer IL3 is not cut by the trench TRC and can be configured to cover the second stacked layer IL2 in each trench TRC.

[0168] In a three-series structure, each of the plurality of trench TRCs can be a structure for cutting off the first charge generation layer, the second charge generation layer, and the first to third hole transport layers of the first to third stacked layers IL1, IL2, and IL3 between adjacent sub-pixels SP1, SP2, and SP3. Furthermore, in a two-series structure, each of the plurality of trench TRCs can be a structure for cutting off the charge generation layer and the lower stacked layer disposed between the lower stacked layer and the upper stacked layer.

[0169] To stably cut the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the multiple trench TRCs can be greater than the height of the pixel-defining film PDL. The height of each of the multiple trench TRCs refers to the length of each of the multiple trench TRCs on the third-direction DR3. The height of the pixel-defining film PDL refers to the length of the pixel-defining film PDL on the third-direction DR3. To cut the charge generation layer and hole transport layer of the light-emitting stacked IL of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, different structures can exist to replace the trench TRCs. For example, instead of trench TRCs, inverted conical partition walls can be disposed on the pixel-defining film PDL.

[0170] also, Figure 9 The illustrated light-emitting stack IL is disposed in a first emission region EA1, a second emission region EA2, and a third emission region EA3, but this disclosure is not limited thereto. For example, instead of the light-emitting stack IL, the first light-emitting layer may be disposed in the first emission region EA1, and the second emission region EA2 and the third emission region EA3 may be omitted. Furthermore, the second light-emitting layer may be disposed in the second emission region EA2, and the first emission region EA1 and the third emission region EA3 may be omitted. Furthermore, the third light-emitting layer may be disposed in the third emission region EA3, and the first emission region EA1 and the second emission region EA2 may be omitted. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0171] The second electrode CAT can be disposed on the light-emitting stack IL. That is, the second electrode CAT can be disposed on the third stack layer IL3. The second electrode CAT can be formed of a transparent conductive oxide (TCO) that can transmit light (such as ITO and / or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, the luminous efficiency in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be improved due to the microcavity effect.

[0172] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic film TFE1 or TFE3 to prevent oxygen and / or moisture from penetrating into the display element layer EML. The first encapsulation inorganic film TFE1 can be disposed on the second electrode CAT, and the second encapsulation inorganic film TFE3 can be disposed above the first encapsulation inorganic film TFE1. The first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3 can each be made of silicon nitride (SiN). x ), silicon oxynitride (SiO) x N y ), silicon dioxide (SiO) x Titanium oxide (TiO) x ) and / or aluminum oxide (AlO) x It is formed by alternating stacking of two or more inorganic membranes in an inorganic membrane.

[0173] Furthermore, the encapsulation layer TFE may include at least one organic film TFE2 to protect the display element layer EML from foreign matter such as dust. The encapsulation organic film TFE2 may be disposed between the first encapsulation inorganic film TFE1 and the second encapsulation inorganic film TFE3. The encapsulation organic film TFE2 may be a monomer. Alternatively, the encapsulation organic film TFE2 may be an organic film comprising, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin.

[0174] The adhesive layer ADL can be a layer used to bond the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL can be a double-sided adhesive component. Alternatively, the adhesive layer ADL can be a transparent adhesive component such as a transparent adhesive or a transparent adhesive resin.

[0175] The optical layer OPL includes multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the adhesive layer ADL.

[0176] The first color filter CF1 may overlap with the first emission region EA1 of the first sub-pixel SP1. The first color filter CF1 may transmit light of a first color (or first light), that is, light in the blue wavelength band. The blue wavelength band may be from about 370 nm to about 460 nm. Therefore, the first color filter CF1 may transmit light of the first color emitted from the first emission region EA1.

[0177] The second color filter CF2 can overlap with the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color (or second light), that is, light in the green wavelength band. The green wavelength band can be from approximately 480 nm to approximately 560 nm. Therefore, the second color filter CF2 can transmit light of the second color emitted from the second emission region EA2.

[0178] The third color filter CF3 can overlap with the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of the third color (or third light), that is, light in the red wavelength band. The red wavelength band can be from about 600nm to about 750nm. Therefore, the third color filter CF3 can transmit light of the third color emitted from the third emission region EA3.

[0179] Multiple lenses LNS can be respectively disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the multiple lenses LNS can be a structure for increasing the proportion of light directed to the front of the display device 20. Each of the multiple lenses LNS can have a cross-sectional shape that convexes in the upward direction.

[0180] A filler layer (FIL) can be disposed on multiple lens lenses (LNS). The filler layer FIL can have a suitable refractive index (e.g., a predetermined refractive index) such that light travels in the third-direction DR3 at the interface between the filler layer FIL and the multiple lens lenses (LNS). Furthermore, the filler layer FIL can be a planarization layer. The filler layer FIL can be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin.

[0181] A cover layer CVL can be disposed on a filler layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. When the cover layer CVL is a polymer resin, it can be directly applied to the filler layer FIL.

[0182] The polarizer POL can be disposed on one surface of the CVL cover layer. The polarizer POL can be a structure used to reduce or prevent visibility degradation caused by reflection of external light. The polarizer POL can include a linear polarizer and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (e.g., a quarter-wave plate), but this disclosure is not limited thereto. However, the polarizer POL can be omitted when the visibility degradation caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0183] Figure 10 It is shown in the diagram along Figure 7 The schematic cross-sectional view of another example of a display panel is shown, with line I1-I1' as the cut.

[0184] Besides the structural differences in the light-emitting stacked ILs described above, Figure 10 Implementation examples and Figure 9 The difference in the embodiment is that the first electrode AND of each light-emitting element LE is in contact with and electrically connected to the side surface of the connection electrode ANC connected to the eighth conductive layer ML8. Figure 10 Implementation examples and Figure 9 The embodiment also differs in that the trench TRC is omitted, and instead, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 have an eaves-shaped or mushroom-shaped cross-sectional structure. Figure 10 In the embodiments, the omission of Figure 9 Redundant descriptions of parts already described in the embodiments.

[0185] refer to Figure 10 Multiple connecting electrodes ANC can be respectively disposed on the first portion AA1 of the ninth interlayer insulating film INS9. Each of the multiple connecting electrodes ANC can be disposed on the first portion AA1 of the ninth interlayer insulating film INS9 corresponding to that connecting electrode ANC. The multiple connecting electrodes ANC can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), alloys comprising one or more of these, and / or transparent conductive oxides. For example, the multiple connecting electrodes ANC may include titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), and / or indium zinc oxide (IZO), but this disclosure is not limited thereto.

[0186] Multiple reflective electrodes RL can be disposed on multiple connecting electrodes ANC. Each of the multiple reflective electrodes RL can be disposed on a connecting electrode ANC corresponding to that reflective electrode RL. The multiple reflective electrodes RL can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or alloys including one or more of these. For example, each of the multiple reflective electrodes RL may include aluminum (Al) with high reflectivity.

[0187] Multiple optical auxiliary films (OALs) can be respectively disposed on multiple reflective electrodes (RLs). Each of the multiple optical auxiliary films (OALs) can be disposed on the reflective electrode (RL) corresponding to that optical auxiliary film (OAL). The multiple optical auxiliary films (OALs) can be made of silicon oxide (SiO2). x It can be formed by inorganic membranes, but this disclosure is not limited thereto.

[0188] In each of the first emission region EA1 and the third emission region EA3, a stepped layer STPL can be disposed on the reflective electrode RL, and an optical auxiliary film OAL can be disposed on the stepped layer STPL. In the second emission region EA2, only the optical auxiliary film OAL can be disposed on the reflective electrode RL. The thickness of the optical auxiliary film OAL in the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be substantially the same.

[0189] Due to the stepped layer STPL, the distance between the reflective electrode RL and the first electrode AND in the first emission region EA1 and the third emission region EA3 can be greater than the distance between the reflective electrode RL and the first electrode AND in the second emission region EA2. The thickness of the stepped layer STPL and the thickness of the optical auxiliary film OAL can be set by taking into account the wavelength and resonant distance of the light emitted from the first stacked layer IL1 of the light-emitting stack IL and the wavelength and resonant distance of the light emitted from the second stacked layer IL2 of the light-emitting stack IL.

[0190] Each of the light-emitting elements LE may include a first electrode AND, a light-emitting stack IL, and a second electrode CAT.

[0191] The first electrode AND of each light-emitting element LE can be disposed on the optical auxiliary film OAL corresponding to that light-emitting element LE. Since the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL are stacked sequentially, the first electrode AND of each light-emitting element LE can be disposed on the top and side surfaces of the optical auxiliary film OAL, the side surface of the reflective electrode RL, and the side surface of the connecting electrode ANC. Accordingly, the first electrode AND of each light-emitting element LE can contact and be electrically connected to the side surfaces of the reflective electrode RL and the connecting electrode ANC. Therefore, compared to when the first electrode AND of each light-emitting element LE is connected to the reflective electrode RL exposed through a through-hole in the optical auxiliary film OAL, the number of mask processes can be reduced, thereby reducing manufacturing costs and improving manufacturing efficiency.

[0192] The first electrode AND of each light-emitting element LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the connecting electrode ANC, the first to ninth vias VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE.

[0193] The ninth interlayer insulating film INS9 may include a first portion AA1 that overlaps with the connecting electrode ANC on the third-direction DR3, and a second portion AA2 that does not overlap with the connecting electrode ANC on the third-direction DR3. The thickness of the first portion AA1 and the thickness of the second portion AA2 of the ninth interlayer insulating film INS9 may be substantially the same.

[0194] Alternatively, the thickness of the first portion AA1 of the ninth interlayer insulating film INS9 can be greater than the thickness of the second portion AA2 of the ninth interlayer insulating film INS9. In this case, the side surface of the first portion AA1 of the ninth interlayer insulating film INS9 can be exposed, and the first electrode AND of each light-emitting element LE in the light-emitting element LE can be disposed on the exposed side surface of the first portion AA1 of the ninth interlayer insulating film INS9.

[0195] The first electrode AND of each light-emitting element LE can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or an alloy thereof or a transparent conductive oxide. For example, the first electrode AND of each light-emitting element LE may include titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), and / or indium zinc oxide (IZO), but this disclosure is not limited thereto.

[0196] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each light-emitting element (LE). The PDL can cover the edge of the first electrode AND of each light-emitting element (LE). The PDL can separate a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3.

[0197] The pixel-limited film (PDL) may include a first pixel-limited film (PDL1), a second pixel-limited film (PDL2), a third pixel-limited film (PDL3), and a fourth pixel-limited film (PDL4).

[0198] The first pixel defining film PDL1 can be disposed on the first electrode AND of each light-emitting element LE. Specifically, the first pixel defining film PDL1 can cover a portion of the top surface of the first electrode AND disposed on the optical auxiliary film OAL. Furthermore, the first pixel defining film PDL1 can cover the first electrode AND disposed on the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The first pixel defining film PDL1 can be disposed on the top surface of the second portion AA2 of the ninth interlayer insulating film INS9.

[0199] The planarization film PNS is a film used to planarize the stepped portions caused by the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL.

[0200] The planarization film PNS can be disposed on the first pixel defining film PDL1, which covers the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. Alternatively, the planarization film PNS can be disposed on the first pixel defining film PDL1, which is disposed on the second portion AA2 of the ninth interlayer insulating film INS9.

[0201] The planarization film PNS can be disposed between adjacent connecting electrodes ANC on the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent reflecting electrodes RL on the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent optical auxiliary films OAL on the first direction DR1 or the second direction DR2.

[0202] There is no step layer STPL in the second emission region EA2, while there is a step layer STPL in each of the first emission region EA1 and the third emission region EA3. Accordingly, the height of the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL in the second emission region EA2 can be smaller than the height of the connecting electrode ANC, the reflective electrode RL, the step layer STPL, and the optical auxiliary film OAL in the first emission region EA1 and the third emission region EA3. Therefore, the planarization film PNS can cover the top surface of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND disposed in the second emission region EA2.

[0203] Conversely, the top surface of the planarization film PNS can be flatly connected to the top surface of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND disposed in the first emission region EA1 and the third emission region EA3. That is, the planarization film PNS may not cover the top surface of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND disposed in each of the first emission region EA1 and the third emission region EA3.

[0204] The second pixel limiting film PDL2 can be disposed on the first pixel limiting film PDL1 and the planarization film PNS, the third pixel limiting film PDL3 can be disposed on the second pixel limiting film PDL2, and the fourth pixel limiting film PDL4 can be disposed on the third pixel limiting film PDL3. The first pixel limiting film PDL1 and the third pixel limiting film PDL3 can be made of silicon nitride (SiN). x The second pixel defining film (PDL2), the fourth pixel defining film (PDL4), and the planarization film (PNS) can be formed from inorganic films of the same type, while the second pixel defining film (PDL2), the fourth pixel defining film (PDL4), and the planarization film (PNS) can be formed from silicon oxide (SiO2). x It is formed from an inorganic film. The first pixel defining film PDL1 is formed from a material different from that of the planarization film PNS, and therefore can be used as a barrier layer in the chemical mechanical polishing process for the planarization film PNS.

[0205] When both the planarization film PNS and the second pixel defining film PDL2 are formed as silicon oxide (SiO) x When using inorganic films, the planarization film PNS and the second pixel-defining film PDL2 can be formed as a single layer film.

[0206] Since the length of the third pixel defining film PDL3 in one direction is less than the length of the fourth pixel defining film PDL4 in that same direction, the bottom surface of the fourth pixel defining film PDL4 can be exposed by the third pixel defining film PDL3 without being covered by it. In other words, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 can have a roof-shaped or mushroom-shaped cross-sectional structure.

[0207] The light-emitting stack IL can be disposed on the first electrode AND and the pixel-defining film PDL. The light-emitting stack IL can include a first stacked layer IL1 and a second stacked layer IL2 that emit different lights. When the light-emitting stack IL has a dual-tandem structure, one of the first stacked layer IL1 and the second stacked layer IL2 can emit light with a wavelength range including one of a first light, a second light, and a third light, and the other can emit light with a wavelength range including the other two light wavelengths. For example, the first stacked layer IL1 can emit light with a wavelength range including the first light and the wavelength range including the third light, and the second stacked layer IL2 can emit light with a wavelength range including the second light. Here, the first light can be light in the blue wavelength band, the second light can be light in the green wavelength band, and the third light can be light in the red wavelength band.

[0208] A charge generation layer for supplying holes to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The charge generation layer may include an N-type charge generation layer for supplying electrons to the first stacked layer IL1 and a P-type charge generation layer for supplying holes to the second stacked layer IL2. The N-type charge generation layer may include a dopant of a metallic material.

[0209] The first stacked layer IL1 is not formed on the bottom surface of the fourth pixel-defining film PDL4, which is exposed but not covered by the third pixel-defining film PDL3, and therefore can be cut through the eaves-shaped or mushroom-shaped cross-sectional structure of the third pixel-defining film PDL3 and the fourth pixel-defining film PDL4. In this case, the first hole transport layer of the first stacked layer IL1 and the charge generation layer disposed between the first stacked layer IL1 and the second stacked layer IL2 can also be cut. Furthermore, although Figure 10 The diagram shows that the second stacked layer IL2 is connected without being disconnected, but the second hole transport layer of the second stacked layer IL2 can be disconnected, and the second electron transport layer of the second stacked layer IL2 can be connected without being disconnected. Therefore, leakage current can be prevented from flowing through the first hole transport layer of the first stacked layer IL1, the second hole transport layer of the second stacked layer IL2, and the charge generation layer between the adjacent emitting regions EA1, EA2, and EA3. Accordingly, the light-emitting stacked ILs in the adjacent emitting regions EA1, EA2, and EA3 can be prevented from emitting light other than the originally intended light due to the influence of the above current.

[0210] although Figure 10 The diagram illustrates a dual-tandem structure of two stacked layers, IL1 and IL2, but this disclosure is not limited thereto. For example, the light-emitting stacked IL can have, for instance, a dual-tandem structure of two stacked layers, IL1 and IL2. Figure 9The diagram shows a triple-cascaded structure comprising three stacked layers IL1, IL2, and IL3. In this case, by adjusting the height of the third pixel-defining film PDL3, it is possible to design a structure such that the charge-generating layers between the first stacked layer IL1 and the second stacked layer IL2, and between the second stacked layer IL2 and the third stacked layer IL3, are severed. Alternatively, as... Figure 9 As shown, a trench TRC can be added that extends through the first pixel-defining film PDL1, the planarization film PNS, the second pixel-defining film PDL2, and the third pixel-defining film PDL3. In this case, the trench TRC can extend through at least a portion of the ninth interlayer insulating film INS9, but this disclosure is not limited thereto.

[0211] Figure 11 It is shown in the diagram along Figure 7 The schematic cross-sectional view of another example of a display panel, shown by line I1-I1'.

[0212] Figure 11 Implementation examples and Figure 10 The difference in this embodiment is that the light-emitting element LE has a single-layer structure. Figure 11 In the embodiments, the omission of Figure 10 Redundant descriptions of parts already described in the embodiments.

[0213] refer to Figure 11 The pixel-defining film (PDL) can be disposed on the ninth interlayer insulating film (INS9) and the first electrode (AND), and the planarization film (PNS) can be disposed on the pixel-defining film (PDL). The planarization film (PNS) and the pixel-defining film (PDL) can have openings exposing the first electrode (AND), and the light-emitting stack (IL) can be disposed on the first electrode (AND). For example, the pixel-defining film (PDL) can have openings exposing the first electrode (AND) in the first emission region (EA1), the second emission region (EA2), and the third emission region (EA3), and the planarization film (PNS) can have openings exposing the first electrode (AND) in the second emission region (EA2). For example, the light-emitting stack (IL) can include a first stack layer (IL1_1), a second stack layer (IL1_2), and a third stack layer (IL1_3).

[0214] The first stacked layer IL1_1 may be disposed on the first electrode AND exposed by the pixel-defining film PDL in the first emission region EA1. The first stacked layer IL1_1 may also be disposed on a portion of the pixel-defining film PDL. For example, the first stacked layer IL1_1 may include a hole injection layer, a hole transport layer, a first light-emitting layer, an electron transport layer, and an electron injection layer.

[0215] The second stacked layer IL1_2 can be disposed on the first electrode AND exposed in the second emission region EA2 by the planarization film PNS and the pixel defining film PDL. The second stacked layer IL1_2 can also be disposed on a portion of the planarization film PNS. For example, the second stacked layer IL1_2 may include a hole injection layer, a hole transport layer, a second light-emitting layer, an electron transport layer, and an electron injection layer.

[0216] The third stacked layer IL1_3 can be disposed on the first electrode AND exposed through the pixel-defining film PDL in the third emission region EA3. The third stacked layer IL1_3 can also be disposed on a portion of the pixel-defining film PDL. For example, the third stacked layer IL1_3 may include a hole injection layer, a hole transport layer, a third light-emitting layer, an electron transport layer, and an electron injection layer.

[0217] The first stacked layer IL1_1, the second stacked layer IL1_2, and the third stacked layer IL1_3 can be spaced apart from each other (e.g., spaced apart), and therefore, in Figure 10 In the embodiments, the second pixel defining film PDL2, the third pixel defining film PDL3, and the fourth pixel defining film PDL4 used to separate the light-emitting stack IL can be omitted.

[0218] The first stacked layer IL1_1 of the first emission region EA1 can emit a first light, the second stacked layer IL1_2 of the second emission region EA2 can emit a second light, and the third stacked layer IL1_3 of the third emission region EA3 can emit a third light. Accordingly, in Figure 9 In the embodiments, the multiple lenses LNS of the optical layer OPL, the fill layer FIL, and the first color filter CF1, the second color filter CF2, and the third color filter CF3 used can be omitted.

[0219] Figure 12 This is a schematic perspective view illustrating an example of a head-mounted display. Figure 13 It is a diagram. Figure 12 The schematic exploded perspective view of the head-mounted display shown.

[0220] refer to Figure 12 and Figure 13 A head-mounted display 1000 according to one or more embodiments includes a first display device 20_1, a second display device 20_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted strap 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0221] The first display device 20_1 provides an image to the user's left eye, and the second display device 20_2 provides an image to the user's right eye. Since each of the first display device 20_1 and the second display device 20_2 is substantially combined with... Figures 3 to 11 The descriptions of the first display device 20 and the second display device 20_2 are the same, so the descriptions of the first display device 20_1 and the second display device 20_2 will be omitted.

[0222] The first optical component 1510 may be disposed between the first display device 20_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 20_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0223] The intermediate frame 1400 can be disposed between the first display device 20_1 and the control circuit board 1600, and between the second display device 20_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 20_1, the second display device 20_2, and the control circuit board 1600.

[0224] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 20_1 and the second display device 20_2 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data DATA, and transmit the digital video data DATA to the first display device 20_1 and the second display device 20_2 via connectors.

[0225] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 20_1, and can transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 20_2. Alternatively, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 20_1 and the second display device 20_2.

[0226] The display device housing 1100 is used to house the first display device 20_1, the second display device 20_2, the intermediate frame 1400, the first optical component 1510, the second optical component 1520, and the control circuit board 1600. The housing cover 1200 is configured to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 12 and Figure 13The first eyepiece 1210 and the second eyepiece 1220 are shown to be independently configured, but this disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0227] The first eyepiece 1210 can be aligned with the first display device 20_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 20_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 20_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 20_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0228] The headband 1300 is used to fasten the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 remain positioned over the user's left and right eyes, respectively. When the display device housing 1100 is made lightweight and compact, the head-mounted display 1000 can be as follows: Figure 14 The one shown is provided with eyeglass frames instead of a headband 1300.

[0229] Figure 14 This is a schematic perspective view illustrating another example of a head-mounted display.

[0230] refer to Figure 14 The head-mounted display 1000_1 according to one or more embodiments may be an eyeglass-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to one or more embodiments may include a display device 20_3, a left eyeglass lens 1010, a right eyeglass lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, an optical path changing component 1070, and a display device housing 1200_1.

[0231] The display device housing 1200_1 can accommodate the display device 20_3, the optical component 1060, and the light path changing component 1070. The image displayed on the display device 20_3 can be magnified by the optical component 1060 and, after the light path is changed by the light path changing component 1070, can be provided to the user's right eye through the right spectacle lens 1020. As a result, the user can view an augmented reality image composed of the virtual image displayed on the display device 20_3 and the real image seen through the right spectacle lens 1020 through their right eye.

[0232] Figure 14The illustrated display device housing 1200_1 is located at the right end of the support frame 1030, but this disclosure is not limited thereto. For example, the display device housing 1200_1 may be located at the left end of the support frame 1030, and in this case, the image of the display device 20_3 can be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be located at both the left and right ends of the support frame 1030, and in this case, the user can view the image displayed on the display device 20_3 through both the left and right eyes.

[0233] Figure 15 This is a schematic diagram illustrating a deposition mask according to one or more embodiments and a deposition apparatus including the deposition mask.

[0234] refer to Figure 15 The deposition apparatus 2000 according to one or more embodiments can be used to form a deposition material layer on a substrate. For example, the deposition apparatus 2000 according to one or more embodiments can be used in a display panel 100 (see...) Figure 3 In the manufacturing process of [the material], it is used to form a light-emitting layer on the backplane substrate 3000 (or display substrate). For example, such as Figure 11 The semiconductor backplane (SBP) and light-emitting element backplane (EBP) shown can be located on the backplane substrate 3000, and the electrode pattern (e.g., the first electrode AND as the anode electrode) can be located on the light-emitting element backplane EBP. Furthermore, a pixel-defining film (PDL) having an opening exposing the first electrode AND can be located on the light-emitting element backplane EBP. As an example, the deposition apparatus 2000 can form a first light-emitting layer on the first electrode AND of a first emission region EA1. As another example, the deposition apparatus 2000 can form a second light-emitting layer on the first electrode AND of a second emission region EA2. As yet another example, the deposition apparatus 2000 can form a third light-emitting layer on the first electrode AND of a third emission region EA3.

[0235] The deposition apparatus 2000 may include a deposition source 2200 for providing vapor-phase deposited material on a backplane substrate 3000, a substrate chuck 2300 for supporting the backplane substrate 3000 so that the backplane substrate 3000 faces the deposition source 2200, and a mask chuck 2400 located between the deposition source 2200 and the substrate chuck 2300 to support a deposition mask 4000 so that the deposition mask 4000 faces the backplane substrate 3000. The deposition source 2200, the substrate chuck 2300, and the mask chuck 2400 may be located in a process chamber (or evaporation chamber) 2100.

[0236] The process chamber 2100 may have an internal space, and the deposition process for forming a deposition material layer on the backplane substrate 3000 can be performed within the internal space of the process chamber 2100. The process chamber 2100 may be connected to a vacuum pump, and a vacuum atmosphere can be created within the internal space of the process chamber 2100 by means of the vacuum pump. An opening for loading / unloading the backplane substrate 3000 and the deposition mask 4000 may be provided on one wall of the process chamber 2100, and this opening may be opened and closed by a gate valve.

[0237] The deposition source 2200 can be located in the process chamber 2100, and the deposition material can be stored in the deposition source 2200. The deposition source 2200 allows deposition materials such as organic, inorganic, and / or conductive materials to evaporate toward the backplane substrate 3000, and the evaporated deposition material can be deposited on the backplane substrate 3000 through a deposition mask 4000. For example, the deposition source 2200 can be used to evaporate organic light-emitting materials for forming a light-emitting layer on the backplane substrate 3000, and can be provided with a heater for evaporating the organic light-emitting material. The evaporated organic light-emitting material can be deposited on an electrode pattern on the backplane substrate 3000 through the deposition mask 4000, thereby forming a light-emitting layer on the electrode pattern of the backplane substrate 3000. Figure 15 As shown, the deposition source 2200 may be located on the central portion of the bottom surface of the process chamber 2100, but the deposition source 2200 may be configured to move horizontally by a separate actuator.

[0238] The substrate chuck 2300 can be located above the deposition source 2200 and can support the backplane substrate 3000 such that the backplane substrate 3000 faces the deposition source 2200. For example, the substrate chuck 2300 can be an electrostatic chuck that uses electrostatic force to fix the rear surface of the backplane substrate 3000. Specifically, the electrode pattern (e.g., the first electrode AND) can be located on the front surface of the backplane substrate 3000, and the substrate chuck 2300 can fix the rear surface of the backplane substrate 3000 such that the front surface of the backplane substrate 3000 faces downward (i.e., towards the deposition source 2200).

[0239] Multiple lifting fingers 2350 for loading the backplane substrate 3000 onto the substrate chuck 2300 can be arranged in the process chamber 2100. The lifting fingers 2350 can be arranged around the substrate chuck 2300 and the mask chuck 2400, and can be moved vertically by finger drivers 2360 respectively. For example, three or four lifting fingers 2350 can be arranged around the substrate chuck 2300 and the mask chuck 2400, and can be moved in a third direction DR3 by the finger drivers 2360.

[0240] The backplane substrate 3000 can be loaded into the process chamber 2100 by a transport robot and then transported from the robot to the lifting finger 2350 below the substrate chuck 2300. In this case, the rear surface of the backplane substrate 3000 can face the bottom surface of the substrate chuck 2300, and the lifting finger 2350 can support the front edge portion of the backplane substrate 3000. The finger actuator 2360 can raise the lifting finger 2350, making the backplane substrate 3000 adjacent to the bottom surface of the substrate chuck 2300, and the rear surface of the backplane substrate 3000 can be fixed to the bottom surface of the substrate chuck 2300 by electrostatic force.

[0241] The finger actuator 2360 can be disposed on the upper cover of the process chamber 2100 and can be connected to the lifting fingers 2350 via a drive shaft 2362 extending vertically through the upper cover of the process chamber 2100. The finger actuator 2360 can move the lifting fingers 2350 vertically to load or unload the backplane substrate 3000. Furthermore, the finger actuator 2360 can rotate the lifting fingers 2350 relative to the corresponding drive shaft 2362. For example, the finger actuator 2360 can rotate the lifting fingers 2350 such that the ends of the lifting fingers 2350 do not overlap with the substrate chuck 2300 and the mask chuck 2400, thereby enabling the lifting fingers 2350 to move vertically. Additionally, the finger actuator 2360 can rotate the lifting fingers 2350 such that the ends of the lifting fingers 2350 overlap with the edge portion of the backplane substrate 3000 to support the edge portion of the backplane substrate 3000.

[0242] The deposition mask 4000 can be loaded into the process chamber 2100 by a transport robot and transported to a lifting finger 2350 above the mask chuck 2400. An edge portion of the deposition mask 4000 can be positioned on the end of the lifting finger 2350, and a finger actuator 2360 can lower the lifting finger 2350 to load the deposition mask 4000 onto the mask chuck 2400. In this configuration, a groove can be provided at the edge portion of the mask chuck 2400 into which the end of the lifting finger 2350 can be inserted, and after the deposition mask 4000 is loaded onto the mask chuck 2400, the finger actuator 2360 can rotate the lifting finger 2350 so that it does not overlap with the mask chuck 2400.

[0243] The mask chuck 2400 can support the edge portion of the deposition mask 4000. For example, the mask chuck 2400 can be an electrostatic chuck configured to hold the edge portion of the deposition mask 4000 using electrostatic force. Specifically, the mask chuck 2400 can have a circular opening to expose the deposition mask 4000 toward the deposition source 2200. For example, the mask chuck 2400 can have a disk shape or a quadrilateral plate shape with a circular opening.

[0244] The deposition apparatus 2000 may include chuck drivers for adjusting the position and orientation of the backplane substrate 3000 and the deposition mask 4000. For example, the deposition apparatus 2000 may include a substrate chuck driver 2500 for moving the substrate chuck 2300 and a mask chuck driver 2600 for moving the mask chuck 2400.

[0245] The substrate chuck driver 2500 can move the substrate chuck 2300 along a first direction DR1, a second direction DR2, and a third direction DR3 to adjust the position of the backplane substrate 3000. In this case, the first direction DR1 can be a first horizontal direction, the second direction DR2 can be a second horizontal direction perpendicular to the first direction DR1, and the third direction DR3 can be a vertical direction. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be the X-axis direction, the Y-axis direction, and the Z-axis direction, respectively.

[0246] The base plate chuck driver 2500 can rotate the base plate chuck 2300 about the Z-axis to adjust the azimuth angle of the back plate base plate 3000 (i.e., the angle at which the back plate base plate 3000 is fixed on the bottom surface of the base plate chuck 2300). Further, the base plate chuck driver 2500 can rotate the base plate chuck 2300 about the X-axis and also about the Y-axis to adjust the tilt of the back plate base plate 3000. For example, the base plate chuck driver 2500 may include a hexapod actuator 2510 that provides movement in six degrees of freedom (X, Y, Z, θx, θy, and θz).

[0247] The substrate chuck driver 2500 may include a substrate stage 2520 on which a hexapod actuator 2510 is mounted, and a second actuator 2530 connected to the substrate stage 2520. The substrate stage 2520 may be located horizontally within the process chamber 2100, and the second actuator 2530 may be located above the process chamber 2100. The second actuator 2530 may be connected to the substrate stage 2520 via a plurality of drive shafts 2532 extending through the top cover of the process chamber 2100 in a third direction DR3 (i.e., the vertical direction (Z-axis direction)), and may move the substrate stage 2520 in the direction of the central axis of the hexapod actuator 2510 (i.e., the vertical direction). For example, the second actuator 2530 may be configured using a brushless DC motor, a linear motor, and / or a direct drive (DD) motor, and the height of the substrate chuck 2300 may be adjusted for loading or unloading the backplane substrate 3000.

[0248] The hexa-legged actuator 2510 may include a first platform connected to the base plate chuck 2300, a second platform mounted on the base plate stage 2520, and six sub-actuators located between the first and second platforms. For example, the six sub-actuators may each be configured using a brushless DC motor, a voice coil linear motor, a stepper motor, a direct drive (DD) motor, and / or a servo motor, and may enable the first platform to move and rotate to adjust the horizontal position, vertical position, azimuth angle, and tilt of the backplate base plate 3000.

[0249] The mask chuck driver 2600 can move and rotate the mask chuck 2400 to adjust the horizontal position of the deposition mask 4000 and the azimuth angle of the deposition mask 4000 (i.e., the angle at which the deposition mask 4000 is positioned on the mask chuck 2400). The mask chuck driver 2600 can move the mask chuck 2400 in a direction parallel to the deposition mask 4000 and rotate the mask chuck 2400 relative to its central axis. For example, the mask chuck driver 2600 can move the mask chuck 2400 in a first direction DR1 (X-axis) and a second direction DR2 (Y-axis), and can rotate the mask chuck 2400 relative to a third direction DR3 (Z-axis).

[0250] The mask chuck driver 2600 may include, for example, a piezoelectric actuator 2610 that provides motion in three degrees of freedom (X, Y, and θz). The piezoelectric actuator 2610 may have an opening communicating with a circular opening of the mask chuck 2400. The mask chuck 2400 may be spaced upwardly from the piezoelectric actuator 2610 by a selected distance. For example, a plurality of support members 2612 may be arranged on the piezoelectric actuator 2610, and the mask chuck 2400 may be located on the plurality of support members 2612.

[0251] The mask chuck driver 2600 may include a mask stage 2620 located horizontally within the process chamber 2100 and supporting the piezoelectric actuator 2610. For example, the mask stage 2620 may have an opening communicating with the opening of the piezoelectric actuator 2610 and may be supported by multiple struts 2622 connected to the top cover of the process chamber 2100.

[0252] After the backplane substrate 3000 and the deposition mask 4000 are loaded onto the substrate chuck 2300 and the mask chuck 2400, respectively, the second actuator 2530 can lower the substrate chuck 2300 to bring the backplane substrate 3000 into proximity with the deposition mask 4000. The hexapod actuator 2510 can adjust the gap between the backplane substrate 3000 and the deposition mask 4000, and can adjust the tilt of the substrate chuck 2300 to adjust the parallelism between the substrate chuck 2300 and the mask chuck 2400. For example, in one or more embodiments, a plurality of gap sensors for measuring the gap between the substrate chuck 2300 and the mask chuck 2400 can be mounted on the substrate chuck 2300, and the hexapod actuator 2510 can adjust the parallelism between the substrate chuck 2300 and the mask chuck 2400 based on the measurements from the gap sensors.

[0253] The deposition apparatus 2000 may include a camera 2700 for acquiring positional information of the backplane substrate 3000 and the deposition mask 4000 for alignment between the backplane substrate 3000 and the deposition mask 4000. For example, a substrate alignment key 3300 (see...) Figure 16 The mask alignment key 4600 can be arranged on the edge portion of the backplane substrate 3000, and the mask alignment key 4600 (see...) Figure 17 The substrate chuck driver 2500 or the mask chuck driver 2600 can be arranged on the edge portion of the deposition mask 4000. The deposition apparatus 2000 may include a camera 2700 for detecting the substrate alignment key 3300 and the mask alignment key 4600, and the substrate chuck driver 2500 or the mask chuck driver 2600 may align the backplane substrate 3000 and the deposition mask 4000 with each other based on the position information of the substrate alignment key 3300 and the mask alignment key 4600 obtained by the camera 2700.

[0254] As described above, after the parallelism adjustment between the substrate chuck 2300 and the mask chuck 2400 and the positional alignment between the backplane substrate 3000 and the deposition mask 4000 are performed, the backplane substrate 3000 can be placed on the deposition mask 4000. For example, the hexapod actuator 2510 can adjust the height of the substrate chuck 2300 such that the gap between the backplane substrate 3000 and the deposition mask 4000 becomes a selected gap, such as a gap of a few micrometers. In another example, the hexapod actuator 2510 can adjust the height of the substrate chuck 2300 such that the backplane substrate 3000 contacts the deposition mask 4000.

[0255] After the backplane substrate 3000 is placed on the deposition mask 4000, the deposition source 2200 can provide a vapor-phase deposition material onto the backplane substrate 3000 through the deposition mask 4000, thereby forming a deposition material layer on the backplane substrate 3000. For example, the deposition source 2200 can provide a vapor-phase light-emitting material for forming a light-emitting layer on the backplane substrate 3000, and this vapor-phase light-emitting material can pass through the first pixel opening 4312 of the deposition mask 4000 (see...). Figure 18 ) and the second pixel opening 4322 (see Figure 18 The electrode pattern is deposited on the backplane substrate 3000.

[0256] Figure 16 It is a diagram. Figure 15 A schematic bottom view of the backplate substrate shown.

[0257] refer to Figure 16 The backplane substrate 3000 may include a first display unit region 3110 and a second display unit region 3120. For example, the backplane substrate 3000 may include a semiconductor substrate (such as a single-crystal silicon wafer), and the first display unit region 3110 and the second display unit region 3120 may be located on the semiconductor substrate. Furthermore, according to one or more embodiments, the backplane substrate 3000 may include a first scribe line region 3210 located between the first display unit regions 3110, a second scribe line region 3220 located between the second display unit regions 3120, and a third scribe line region 3230 located between adjacent first display unit regions 3110 and second display unit regions 3120.

[0258] According to one or more embodiments, such as Figure 16 As illustrated, the first display unit region 3110 can be arranged in a matrix along a first direction DR1 and a second direction DR2. According to one or more embodiments, the second display unit region 3120 can have a smaller size than the first display unit region 3110 and can be located outside the first display unit region 3110. For example, the second display unit region 3120 can be located on an edge portion of the semiconductor substrate. For example, the second display unit region 3120 can be located on an edge portion of the semiconductor substrate where the first display unit region 3110 is not located.

[0259] After the display panel manufacturing process is completed, the first display unit area 3110 and the second display unit area 3120 can be individualized by a cutting process, and the individualized first display unit area 3110 and the second display unit area 3120 can each be used as the display panel 100 of the electronic device 10 or the display device 20 (see...). Figure 3For example, the first direction DR1 can be a first horizontal direction, and the second direction DR2 can be a second horizontal direction perpendicular to the first direction DR1. According to one or more embodiments, such as... Figure 16 As illustrated in the figure, the first display unit area 3110 and the second display unit area 3120 may each have a quadrilateral shape. For example, the first display unit area 3110 and the second display unit area 3120 may each have a rectangular shape. However, the first display unit area 3110 and the second display unit area 3120 can be changed into various shapes as needed, therefore the scope of this disclosure is not limited by the shapes of the first display unit area 3110 and the second display unit area 3120.

[0260] According to one or more embodiments, the first display unit area 3110 and the second display unit area 3120 may each include as follows: Figure 11 The diagram illustrates a semiconductor backplane (SBP) and a light-emitting element backplane (EBP) located on the semiconductor backplane (SBP). Furthermore, multiple electrode patterns (e.g., multiple first electrodes AND) may be located on the light-emitting element backplane (EBP), and a pixel-defining film (PDL) having openings exposing the first electrodes AND may be located on the light-emitting element backplane (EBP) and the first electrodes AND. In this case, the electrode patterns of the first display unit region 3110 and the second display unit region 3120 may be located on the front surface of the backplane substrate 3000, and the substrate chuck 2300 may fix the rear surface of the backplane substrate 3000 such that the electrode patterns of the first display unit region 3110 and the second display unit region 3120 face downwards (i.e., towards the deposition source 2200).

[0261] According to one or more embodiments, the backplane substrate 3000 may include substrate alignment keys 3300. For example, the substrate alignment keys 3300 may be located on an edge portion of the backplane substrate 3000 and may be used for positional alignment between the backplane substrate 3000 and the deposition mask 4000. Figure 16 As shown, two substrate alignment keys 3300 are used, but the number of substrate alignment keys 3300 can be changed differently, so the scope of this disclosure is not limited by the number of substrate alignment keys 3300.

[0262] Figure 17 It is a diagram. Figure 15 A schematic plan view of the deposition mask shown. Figure 18 It is a diagram. Figure 17 The diagram shows a schematic plan view of the first and second mask unit areas. Figure 19 It is along Figure 18 The diagram shows a schematic cross-section taken by line I2-I2'.

[0263] refer to Figures 17 to 19According to one or more embodiments, the deposition mask 4000 may include a first mask unit region 4310 and a second mask unit region 4320 corresponding to a first display unit region 3110 and a second display unit region 3120 of the backplane substrate 3000, respectively. Furthermore, according to one or more embodiments, the deposition mask 4000 may include a first grid region 4330, a second grid region 4340, and a third grid region 4350 corresponding to a first scribe line region 3210, a second scribe line region 3220, and a third scribe line region 3230 of the backplane substrate 3000, respectively.

[0264] According to one or more embodiments, the first mask unit region 4310 and the second mask unit region 4320 may each have a first pixel opening 4312 and a second pixel opening 4322 that expose the electrode patterns of the first display unit region 3110 and the second display unit region 3120 during the deposition process. For example, when the backplane substrate 3000 is located on the deposition mask 4000 during the deposition process, the electrode pattern of the backplane substrate 3000 (e.g., the first electrode AND) may be located on the first pixel opening 4312 and the second pixel opening 4322 of the deposition mask 4000, and the vapor deposition material provided from the deposition source 2200 may be deposited on the first electrode AND through the first pixel opening 4312 and the second pixel opening 4322.

[0265] According to one or more embodiments, the deposition mask 4000 may include a mask substrate 4100, a buffer inorganic film 4200 located on the mask substrate 4100, and a thin film 4300 located on the buffer inorganic film 4200.

[0266] According to one or more embodiments, the mask substrate 4100 may have a first unit opening 4110 and a second unit opening 4120 corresponding to a first display unit region 3110 and a second display unit region 3120 of the backplane substrate 3000, respectively. According to one or more embodiments, the mask substrate 4100 may comprise monocrystalline silicon. For example, a monocrystalline silicon wafer having a thickness of about 700 μm to about 800 μm (e.g., about 725 μm or about 775 μm) may be used as the mask substrate 4100.

[0267] According to one or more embodiments, the first unit opening 4110 and the second unit opening 4120 may be formed to penetrate the mask substrate 4100, and the mask substrate 4100 may include rib regions 4130 defining the first unit opening 4110 and the second unit opening 4120. For example, the mask substrate 4100 may include a first rib region located between the first unit openings 4110, a second rib region located between the second unit openings 4120, and a third rib region located between adjacent first unit openings 4110 and second unit openings 4120.

[0268] According to one or more embodiments, the thin film 4300 may include a first mask unit region 4310 and a second mask unit region 4320 corresponding to the first display unit region 3110 and the second display unit region 3120 of the backplane substrate 3000, respectively. Furthermore, according to one or more embodiments, the thin film 4300 may include a first grid region 4330, a second grid region 4340, and a third grid region 4350 corresponding to the first scribe line region 3210, the second scribe line region 3220, and the third scribe line region 3230 of the backplane substrate 3000, respectively. For example, the first grid region 4330 may be located between the first mask unit regions 4310, the second grid region 4340 may be located between the second mask unit regions 4320, and the third grid region 4350 may be located between adjacent first mask unit regions 4310 and second mask unit regions 4320. Furthermore, the first grid region 4330, the second grid region 4340, and the third grid region 4350 may overlap with the first rib region, the second rib region, and the third rib region of the mask substrate 4100 in the thickness direction (e.g., in the third direction DR3), respectively.

[0269] According to one or more embodiments, such as Figure 17 and Figure 18 As illustrated, the first mask unit area 4310 and the second mask unit area 4320 may each have a quadrilateral shape. For example, the first mask unit area 4310 and the second mask unit area 4320 may each have a rectangular shape. However, the shapes of the first mask unit area 4310 and the second mask unit area 4320 may be changed differently depending on the shapes of the first display unit area 3110 and the second display unit area 3120, therefore the scope of this disclosure is not limited by the shapes of the first mask unit area 4310 and the second mask unit area 4320.

[0270] According to one or more embodiments, such as Figure 17 As shown, the first mask unit region 4310 can be arranged in a matrix along a first direction DR1 and a second direction DR2. For example, the first direction DR1 can be a first horizontal direction, and the second direction DR2 can be a second horizontal direction perpendicular to the first direction DR1. According to one or more embodiments, the second mask unit region 4320 can have a smaller size than the first mask unit region 4310 and can be located outside the first mask unit region 4310. For example, the second mask unit region 4320 can be located on an edge portion of the mask substrate 4100. For example, the second mask unit region 4320 can be located on an edge portion of the mask substrate 4100 where the first mask unit region 4310 is not located.

[0271] According to one or more embodiments, the first mask unit region 4310 may have a first size, and the second mask unit region 4320 may have a second size smaller than the first size. For example, the second size may be about 0.3 to about 0.9 times the first size. According to one or more embodiments, the second mask unit region 4320 may be located on the edge portion of the mask substrate 4100 where the first mask unit region 4310 cannot be disposed, thus increasing the total number of mask unit regions on the mask substrate 4100 by increasing the number of second mask unit regions 4320.

[0272] According to one or more embodiments, the gap w2 between the second mask unit regions 4320 (i.e., the width w2 of the second grid region 4340) can be equal to or less than the gap w1 between the first mask unit regions 4310 (i.e., the width w1 of the first grid region 4330). For example, the width w2 of the second grid region 4340 can be about 0.3 to about 1 times the width w1 of the first grid region 4330. Furthermore, according to one or more embodiments, the gap w3 between adjacent first mask unit regions 4310 and second mask unit regions 4320 (i.e., the width w3 of the third grid region 4350) can be equal to or less than the gap w1 between the first mask unit regions 4310 (i.e., the width w1 of the first grid region 4330). For example, the width w3 of the third grid region 4350 can be about 0.3 to about 1 times the width w1 of the first grid region 4330.

[0273] According to one or more embodiments, each of the first mask unit regions 4310 may have a plurality of first pixel openings 4312, and each of the second mask unit regions 4320 may have a plurality of second pixel openings 4322. According to one or more embodiments, the first pixel openings 4312 may be formed to penetrate the first mask unit region 4310, and the second pixel openings 4322 may be formed to penetrate the second mask unit region 4320. For example, the first pixel openings 4312 and the second pixel openings 4322 may be arranged to correspond to the first electrodes AND of the first display unit region 3110 and the second display unit region 3120, respectively. For example, the first pixel openings 4312 and the second pixel openings 4322 may be arranged to correspond to, for example, the first electrode AND of the first display unit region 3110 and the second display unit region 3120. Figure 9 and Figure 10 The first electrode AND of the first emission region EA1, the first electrode AND of the second emission region EA2, and the first electrode AND of the third emission region EA3 are shown in the diagram. For example, the first pixel opening 4312 and the second pixel opening 4322 can be arranged to correspond to... Figure 11 The first electrode AND of one of the first emission regions EA1, EA2, and EA3 in the diagram corresponds to the first emission region AND.

[0274] According to one or more embodiments, a buffer inorganic film 4200 may be located on a mask substrate 4100 and may have a first buffer opening 4210 exposing a first mask unit region 4310 and a second buffer opening 4220 exposing a second mask unit region 4320. According to one or more embodiments, the first mask unit region 4310 may be a region exposed through the first buffer opening 4210 and the first unit opening 4110, and the second mask unit region 4320 may be a region exposed through the second buffer opening 4220 and the second unit opening 4120. That is, the first buffer opening 4210 may be located on the first unit opening 4110, and the first mask unit region 4310 may be located on the first buffer opening 4210. Furthermore, the second buffer opening 4220 may be located on the second unit opening 4120, and the second mask unit region 4320 may be located on the second buffer opening 4220.

[0275] According to one or more embodiments, when the backplane substrate 3000 is placed on the deposition mask 4000 during the deposition process, the first mask unit region 4310 and the second mask unit region 4320 can face the first display unit region 3110 and the second display unit region 3120, respectively, and the first grid region 4330, the second grid region 4340, and the third grid region 4350 can face the first scribe line region 3210, the second scribe line region 3220, and the third scribe line region 3230, respectively. In this case, the first pixel opening 4312 can be exposed to the deposition source 2200 through the first buffer opening 4210 and the first unit opening 4110, and the second pixel opening 4322 can be exposed to the deposition source 2200 through the second buffer opening 4220 and the second unit opening 4120. In other words, during the deposition process, the vapor deposition material provided from the deposition source 2200 can be deposited on the first electrode AND of the backplane substrate 3000 through the first unit opening 4110, the second unit opening 4120, the first buffer opening 4210, the second buffer opening 4220, the first pixel opening 4312, and the second pixel opening 4322.

[0276] According to one or more embodiments, the buffer inorganic film 4200 and the thin film 4300 may be located on the front surface 4102 of the mask substrate 4100 (see [link]). Figure 22 The intermediate inorganic film 4400 and the rear inorganic film 4500 can be located on the rear surface 4104 of the mask substrate 4100 (see [reference]). Figure 22 For example, the intermediate inorganic film 4400 may be located on the rear surface 4104 of the mask substrate 4100, and the rear inorganic film 4500 may be located on the intermediate inorganic film 4400.

[0277] According to one or more embodiments, the intermediate inorganic membrane 4400 may have a first intermediate opening 4410 connected to the first unit opening 4110 and a second intermediate opening 4420 connected to the second unit opening 4120, and the rear inorganic membrane 4500 may have a first rear opening 4510 connected to the first intermediate opening 4410 and a second rear opening 4520 connected to the second intermediate opening 4420.

[0278] According to one or more embodiments, the first pixel opening 4312 can be exposed toward the deposition source 2200 through the first buffer opening 4210, the first unit opening 4110, the first intermediate opening 4410, and the first rear opening 4510, and the second pixel opening 4322 can be exposed toward the deposition source 2200 through the second buffer opening 4220, the second unit opening 4120, the second intermediate opening 4420, and the second rear opening 4520. Furthermore, during the deposition process, vapor-deposited material provided from the deposition source 2200 can be deposited on the first electrode AND of the backplane substrate 3000 through the first rear opening 4510, the second rear opening 4520, the first intermediate opening 4410, the second intermediate opening 4420, the first unit opening 4110, the second unit opening 4120, the first buffer opening 4210, the second buffer opening 4220, the first pixel opening 4312, and the second pixel opening 4322.

[0279] According to one or more embodiments, the intermediate inorganic film 4400 and the post-inorganic film 4500 can be used as etching masks in an etching process for forming the first unit opening 4110 and the second unit opening 4120. For example, the first unit opening 4110 and the second unit opening 4120 can be formed by an anisotropic etching process using the intermediate inorganic film 4400 and the post-inorganic film 4500 as etching masks. For example, a single-crystal silicon wafer can be used as the mask substrate 4100, and the first unit opening 4110 and the second unit opening 4120 can be formed by a first wet etching process using a first etchant (such as tetramethylammonium hydroxide (TMAH) solution and / or potassium hydroxide (KOH) solution, etc.). In this case, the single-crystal silicon wafer used as the mask substrate 4100... <100> The crystal orientation can be a third orientation DR3, and correspondingly, the first unit opening 4110 and the second unit opening 4120 can have a width that gradually decreases from the rear surface 4104 of the mask substrate 4100 toward the front surface 4102 of the mask substrate 4100 by a first wet etching process. For example, the inner surfaces of the first unit opening 4110 and the second unit opening 4120 can have a tilt angle of about 54.7° relative to the rear surface of the mask substrate 4100.

[0280] According to one or more embodiments, the buffer inorganic film 4200 may comprise a material having etch selectivity relative to the mask substrate 4100. According to one or more embodiments, the buffer inorganic film 4200 may comprise silicon oxide (SiO2). x The intermediate inorganic film 4400 can be formed on the front surface 4102 of the mask substrate 4100 to have a thickness of about 0.2 μm to about 2 μm by a thermal oxidation process. According to one or more embodiments, the intermediate inorganic film 4400 can be made of the same material as the buffer inorganic film 4200. According to one or more embodiments, the intermediate inorganic film 4400 may include silicon oxide (SiO₂). x The intermediate inorganic film 4400 can be formed on the rear surface 4104 of the mask substrate 4100 with a thickness of about 0.2 μm to about 2 μm by a thermal oxidation process. For example, the intermediate inorganic film 4400 can be formed simultaneously (e.g., concurrently) with the buffer inorganic film 4200 by a thermal oxidation process.

[0281] According to one or more embodiments, after the first unit opening 4110 and the second unit opening 4120 are formed, the first buffer opening 4210 and the second buffer opening 4220 of the buffer inorganic film 4200 can be formed by a wet etching process. For example, when the buffer inorganic film 4200 comprises silicon oxide (SiO2). x When the first buffer opening 4210 and the second buffer opening 4220 are formed, they can be formed by a second wet etching process using a second etchant (such as buffer oxide etchant (BOE) and / or diluted HF).

[0282] According to one or more embodiments, the thin film 4300 may comprise a material having etch selectivity relative to the buffer inorganic film 4200. According to one or more embodiments, the thin film 4300 may comprise silicon nitride (SiN). x And it can be formed on the buffer inorganic film 4200 with a thickness of about 0.3 μm to about 3 μm by a low-pressure chemical vapor deposition (LPCVD) process.

[0283] According to one or more embodiments, the thin film 4300 may comprise silicon-rich silicon nitride having a silicon content higher than that of stoichiometric silicon nitride (Si3N4). For example, when the silicon content of the thin film 4300 is equal to or lower than the silicon content of stoichiometric silicon nitride (Si3N4), the residual stress (e.g., residual tensile stress) of the thin film 4300 may increase, and therefore, overall warping of the entire deposition mask 4000 may occur. According to one or more embodiments, in order to reduce the overall warping of the deposition mask 4000, the residual tensile stress of the thin film 4300 is preferably below 500 MPa, and for this purpose, the thin film 4300 preferably comprises silicon-rich silicon nitride.

[0284] For example, when silicon nitride is expressed as Si x N y In this case, the ratio of silicon content to nitrogen content in silicon nitride represents the 'x / y' value, and the ratio of silicon content to nitrogen content in stoichiometric silicon nitride (Si3N4) (i.e., the 'x / y' value) is 0.75. According to one or more embodiments, the ratio of silicon content to nitrogen content in the thin film 4300 can be controlled within the range of about 0.8 to about 1.2.

[0285] According to one or more embodiments, to avoid irregular deformation of the deposition mask 4000 due to the second mask unit region 4320 and the second unit opening 4120, the second mask unit region 4320 and the second unit opening 4120 can be arranged symmetrically with respect to the center of the mask substrate 4100, such as... Figure 17 As shown in the diagram. That is to say, the second mask unit area 4320 and the second unit opening 4120 can be arranged in a point-symmetric manner with respect to the center point of the mask substrate 4100.

[0286] According to one or more embodiments, the post-inorganic film 4500 may comprise the same material as the thin film 4300. For example, the post-inorganic film 4500 may comprise silicon-rich silicon nitride and may be formed simultaneously (e.g., concurrently) with the thin film 4300 via an LPCVD process. In this case, the silicon-to-nitrogen content ratio of the post-inorganic film 4500 may be the same as that of the thin film 4300, and it may have the same thickness as the thin film 4300.

[0287] According to one or more embodiments, the area of ​​the post-inorganic film 4500 can be smaller than the area of ​​the thin film 4300 due to the first unit opening 4110 and the second unit opening 4120. Therefore, when the post-inorganic film 4500 and the thin film 4300 are made of the same material and the thickness of the post-inorganic film 4500 is the same as the thickness of the thin film 4300, the force applied to the mask substrate 4100 due to the residual tensile stress of the thin film 4300 may be greater than the force applied to the mask substrate 4100 due to the residual tensile stress of the post-inorganic film 4500, which may cause overall warping of the deposition mask 4000. According to one or more embodiments, to reduce the overall warping of the deposition mask 4000, the post-inorganic film 4500 can have a thickness greater than the thickness of the thin film 4300. For example, the thickness of the post-inorganic film 4500 can be adjusted such that the force applied to the mask substrate 4100 due to the residual tensile stress of the post-inorganic film 4500 becomes substantially equal to the force applied to the mask substrate 4100 due to the residual tensile stress of the thin film 4300. For example, the thickness of the post-inorganic film 4500 can be adjusted to a range of about 1 μm to about 10 μm.

[0288] According to one or more embodiments, the post-inorganic film 4500 may have the same thickness as the thin film 4300, and may be formed to have a residual stress greater than that of the thin film 4300. For example, the post-inorganic film 4500 may be made of silicon nitride (SiN). x The inorganic film 4500 is formed by adjusting the ratio of silicon content to nitrogen content so that the residual tensile stress of the inorganic film 4500 is greater than that of the thin film 4300. Specifically, the ratio of silicon content to nitrogen content in the inorganic film 4500 can be adjusted so that the force applied to the mask substrate 4100 due to the residual tensile stress of the thin film 4300 and the force applied to the mask substrate 4100 due to the residual tensile stress of the inorganic film 4500 are approximately equal. For example, the ratio of silicon content to nitrogen content in the inorganic film 4500 can be less than that in the thin film 4300. For example, the ratio of silicon content to nitrogen content in the inorganic film 4500 can be adjusted to a range of about 0.6 to about 0.8.

[0289] Figure 20 It is a diagram. Figure 18 A schematic plan view of another example of the deposition mask shown. Figure 21 It is along Figure 20 The schematic cross-sectional view shown is taken by line I3-I3'.

[0290] Figure 20 and Figure 21 Implementation examples and Figure 18 and Figure 19 The difference in the embodiments is that the film 4300 includes a first peripheral region 4314 surrounding (e.g., around) the first mask unit region 4310 and a second peripheral region 4324 surrounding (e.g., around) the second mask unit region 4320. Figure 20 and Figure 21 In the embodiments, the omission of Figure 18 and Figure 19 Redundant descriptions of parts already described in the embodiments.

[0291] refer to Figure 20 and Figure 21 The thin film 4300 may include a first peripheral region 4314 surrounding the first mask unit region 4310 and a second peripheral region 4324 surrounding the second mask unit region 4320. According to one or more embodiments, the thin film 4300 may have a first groove 4316 defining the first peripheral region 4314 and a second groove 4326 defining the second peripheral region 4324.

[0292] For example, the first mask unit region 4310 may be the region exposed through the first unit opening 4110, and the first peripheral region 4314 may have an annular shape surrounding the first mask unit region 4310 and may be located on the mask substrate 4100. That is, the first mask unit region 4310 may be supported on the first unit opening 4110 by the first peripheral region 4314. Furthermore, the second mask unit region 4320 may be the region exposed through the second unit opening 4120, and the second peripheral region 4324 may have an annular shape surrounding the second mask unit region 4320 and may be located on the mask substrate 4100. That is, the second mask unit region 4320 may be supported on the second unit opening 4120 by the second peripheral region 4324.

[0293] According to one or more embodiments, a first groove 4316 may define a first peripheral region 4314. For example, the first groove 4316 may have an annular shape around (e.g., surrounding) the first peripheral region 4314 and may be formed to penetrate the film 4300. Accordingly, the first mask unit region 4310 and the first peripheral region 4314 may be separated from the remaining region 4360 of the film 4300. According to one or more embodiments, a second groove 4326 may define a second peripheral region 4324. For example, the second groove 4326 may have an annular shape around (e.g., surrounding) the second peripheral region 4324 and may be formed to penetrate the film 4300. Therefore, the second mask unit region 4320 and the second peripheral region 4324 may be separated from the remaining region 4360 of the film 4300.

[0294] According to one or more embodiments, the thin film 4300 may include silicon nitride (SiN). x For example, thin film 4300 may be made of silicon-rich silicon nitride, and the ratio of silicon content to nitrogen content in thin film 4300 may be from about 0.8 to about 1.2. According to one or more embodiments, post-inorganic film 4500 may comprise the same material as thin film 4300. For example, post-inorganic film 4500 may be made of silicon-rich silicon nitride, and the ratio of silicon content to nitrogen content in post-inorganic film 4500 may be from about 0.8 to about 1.2.

[0295] According to one or more embodiments, the thin film 4300 and the rear inorganic film 4500 may have the same thickness, and the area of ​​the remaining area 4360 of the thin film 4300, excluding the first mask unit region 4310, the first peripheral region 4314, the second mask unit region 4320, and the second peripheral region 4324, may be approximately equal to the area of ​​the rear inorganic film 4500. For example, the first groove 4316 may overlap with the inner surface of the first rear opening 4510 in the thickness direction of the mask substrate 4100 (e.g., in the third direction DR3), and the second groove 4326 may overlap with the inner surface of the second rear opening 4520 in the third direction DR3.

[0296] According to one or more embodiments, the residual tensile stress of the remaining region 4360 of the thin film 4300 can be approximately equal to the residual tensile stress of the subsequent inorganic film 4500. Therefore, the force applied to the mask substrate 4100 due to the residual tensile stress of the remaining region 4360 of the thin film 4300 can be approximately equal to the force applied to the mask substrate 4100 due to the residual tensile stress of the subsequent inorganic film 4500. Furthermore, when the first mask unit region 4310, the first peripheral region 4314, the second mask unit region 4320, and the second peripheral region 4324 are separated from the remaining region 4360 of the thin film 4300 by the first groove 4316 and the second groove 4326, the force applied to the mask substrate 4100 due to the residual tensile stress of the first mask unit region 4310, the first peripheral region 4314, the second mask unit region 4320, and the second peripheral region 4324 can be significantly reduced, thereby reducing the overall warpage of the deposition mask 4000.

[0297] According to one or more embodiments, when the first mask unit region 4310, the first peripheral region 4314, the second mask unit region 4320, and the second peripheral region 4324 are separated from the remaining region 4360 of the thin film 4300, the residual tensile stress of the first mask unit region 4310 and the second mask unit region 4320 can be relatively reduced, thereby reducing the unit warpage of the first mask unit region 4310 and the second mask unit region 4320.

[0298] According to one or more embodiments, the buffer inorganic film 4200 may have a third groove 4212 connected to the first groove 4316 and a fourth groove 4222 connected to the second groove 4326. For example, the third groove 4212 may overlap with the first groove 4316 in the thickness direction of the mask substrate 4100 (e.g., on the third direction DR3), and the fourth groove 4222 may overlap with the second groove 4326 in the thickness direction of the mask substrate 4100. Furthermore, according to one or more embodiments, the third groove 4212 and the fourth groove 4222 may extend through the buffer inorganic film 4200, so that the front surface 4102 of the mask substrate 4100 (see...) Figure 22It can be exposed through the third groove 4212 and the fourth groove 4222.

[0299] According to one or more embodiments, the buffer inorganic film 4200 may include a first buffer pattern 4214 defined by a third groove 4212 and a second buffer pattern 4224 defined by a fourth groove 4222. For example, the first buffer pattern 4214 may have an annular shape defining a first buffer opening 4210 and may be located on the front surface 4102 of the mask substrate 4100 around the first unit opening 4110. According to one or more embodiments, a first peripheral region 4314 of the thin film 4300 may be located on the first buffer pattern 4214. In this case, the first mask unit region 4310 and the first peripheral region 4314 of the thin film 4300 may be supported on the front surface 4102 of the mask substrate 4100 by the first buffer pattern 4214. Further, for example, the second buffer pattern 4224 may have an annular shape defining a second buffer opening 4220 and may be located on the front surface 4102 of the mask substrate 4100 around the second unit opening 4120. According to one or more embodiments, the second peripheral region 4324 of the thin film 4300 may be located on the second buffer pattern 4224. In this case, the second mask unit region 4320 and the second peripheral region 4324 of the thin film 4300 may be supported on the front surface 4102 of the mask substrate 4100 by the second buffer pattern 4224.

[0300] Figures 22 to 27 This is a schematic cross-sectional view illustrating a method for manufacturing a deposition mask according to one or more embodiments.

[0301] refer to Figure 22 A buffer inorganic film 4200 may be formed on the front surface 4102 of the mask substrate 4100. According to one or more embodiments, the mask substrate 4100 may comprise monocrystalline silicon. For example, a monocrystalline silicon wafer having a thickness in the range of about 700 μm to about 800 μm (e.g., about 725 μm or about 775 μm) may be used as the mask substrate 4100.

[0302] According to one or more embodiments, the buffer inorganic membrane 4200 may include silicon oxide (SiO2). x For example, the buffer inorganic film 4200 can be formed on the front surface 4102 of the mask substrate 4100 by a thermal oxidation process or a CVD process to have a thickness of about 0.2 μm to about 2 μm.

[0303] An intermediate inorganic film 4400 may be formed on the rear surface 4104 of the mask substrate 4100. According to one or more embodiments, the intermediate inorganic film 4400 may comprise silicon oxide (SiO2). xFor example, the intermediate inorganic film 4400 can be formed on the back surface 4104 of the mask substrate 4100 by a thermal oxidation process or a CVD process to have a thickness of about 0.2 μm to about 2 μm. As another example, the intermediate inorganic film 4400 can be formed simultaneously (e.g., concurrently) with the buffer inorganic film 4200 by a thermal oxidation process or a CVD process.

[0304] refer to Figure 23 Thin film 4300 can be formed on buffer inorganic film 4200. According to one or more embodiments, thin film 4300 may include silicon nitride (SiN). x Furthermore, the thin film 4300 can be conformally formed to have a thickness of approximately 0.3 μm to approximately 3 μm using an LPCVD process. For example, a silicon source gas such as silane (SiH4) or dichlorosilane (DCS) and a nitrogen source gas such as nitrogen (N2) or ammonia (NH3) can be supplied onto the buffer inorganic film 4200, and the thin film 4300 can be formed by the reaction of the silicon source gas and the nitrogen source gas.

[0305] According to one or more embodiments, the thin film 4300 may comprise silicon-rich silicon nitride having a silicon content higher than that of stoichiometric silicon nitride (Si3N4). According to one or more embodiments, the ratio of silicon content to nitrogen content of the thin film 4300 may be controlled within the range of about 0.8 to about 1.2. For example, an LPCVD process may be performed at low pressure and high temperature to form the silicon-rich silicon nitride film. For example, the LPCVD process may be performed at a pressure atmosphere of about 210 mTorr to about 250 mTorr and a temperature atmosphere of about 800°C to about 850°C.

[0306] According to one or more embodiments, the post-inorganic film 4500 may be formed on the intermediate inorganic film 4400. According to one or more embodiments, the post-inorganic film 4500 may include silicon nitride (SiN). x The inorganic film 4400 can be conformally formed to have a uniform thickness on the intermediate inorganic film 4400 using an LPCVD process. For example, the post-inorganic film 4500 can be made of the same material as the thin film 4300 and can be formed simultaneously with the thin film 4300 using an LPCVD process. In this case, the post-inorganic film 4500 can have the same thickness as the thin film 4300, and the silicon content to nitrogen content ratio of the post-inorganic film 4500 can be the same as that of the thin film 4300.

[0307] According to one or more embodiments, the post-inorganic film 4500 may be formed on the intermediate inorganic film 4400 after the thin film 4300 is formed. According to one or more embodiments, the post-inorganic film 4500 may be made of the same material as the thin film 4300 and may be formed by an LPCVD process to have a thickness greater than that of the thin film 4300. For example, the post-inorganic film 4500 may comprise silicon-rich silicon nitride, and the silicon-to-nitrogen content ratio of the post-inorganic film 4500 may be the same as that of the thin film 4300. Furthermore, for example, the post-inorganic film 4500 may have a thickness of about 1 μm to about 10 μm.

[0308] According to one or more embodiments, the post-inorganic film 4500 can be formed to have the same thickness as the thin film 4300, and can be made of a material having a residual stress greater than that of the thin film 4300. For example, the post-inorganic film 4500 can be formed to have the same thickness as the thin film 4300 by an LPCVD process, and can be made of silicon nitride (SiN) having a residual tensile stress greater than that of the thin film 4300. x It is made by means of silicon. For example, the ratio of silicon content to nitrogen content in the post-inorganic membrane 4500 can be controlled in the range of about 0.6 to about 0.8.

[0309] refer to Figure 24 The thin film 4300 can be patterned to form a first pixel opening 4312 and a second pixel opening 4322. For example, after a photoresist pattern exposing the portions to be formed of the first pixel opening 4312 and the second pixel opening 4322 is formed on the thin film 4300, an anisotropic etching process (e.g., a plasma etching process or a reactive ion etching (RIE) process) using the photoresist pattern as an etching mask can be performed to form the first pixel opening 4312 and the second pixel opening 4322 throughout the thin film 4300. For example, when the thin film 4300 includes silicon nitride (SiN... x When anisotropic etching is performed, a first reactive gas containing fluorine (such as CF4, C2F4, C2F6, C3F6, C3F8, C4F6, C4F8, CH3F, CH2F2, C2HF5, CHF3, NF3, or SF6), a second reactive gas containing oxygen (such as O2, NO, or NO2), and a sputtering gas (such as He, Ne, Ar, or Xe) can be used until the buffer inorganic film 4200 is exposed. After the first pixel opening 4312 and the second pixel opening 4322 are formed, the photoresist pattern can be removed by an ashing process and / or a stripping process.

[0310] According to one or more embodiments, the thin film 4300 may include openings 4110, respectively, through which a first unit opening 4110 to be subsequently formed (see...). Figure 26 and Figure 27 ) and the second unit opening 4120 (see Figure 26 and Figure 27 The first mask unit region 4310 and the second mask unit region 4320 are exposed. According to one or more embodiments, the first mask unit region 4310 may have a first size, and the second mask unit region 4320 may have a second size smaller than the first size. For example, the second size may be about 0.3 to about 0.9 times the first size. According to one or more embodiments, such as... Figure 17 As illustrated in the figure, the second mask unit region 4320 may be located on the edge portion of the mask substrate 4100 and may be symmetrically placed relative to the center of the mask substrate 4100. According to one or more embodiments, such as Figure 18 As illustrated in the diagram, the gap w2 between the second mask unit regions 4320 can be equal to or less than the gap w1 between the first mask unit regions 4310. Furthermore, the gap w3 between adjacent first mask unit regions 4310 and second mask unit regions 4320 can be equal to or less than the gap w1 between the first mask unit regions 4310. (As referenced...) Figures 17 to 19 The first mask unit region 4310 and the second mask unit region 4320 are described, therefore detailed descriptions of them will be omitted.

[0311] refer to Figure 25 The rear inorganic film 4500 and the intermediate inorganic film 4400 can be patterned to form a first rear opening 4510, a second rear opening 4520, a first intermediate opening 4410, and a second intermediate opening 4420 that expose the rear surface 4104 of the mask substrate 4100 where the first unit opening 4110 and the second unit opening 4120 are to be formed. For example, after a photoresist pattern exposing the portions where the first rear opening 4510 and the second rear opening 4520 are to be formed is formed on the rear inorganic film 4500, an anisotropic etching process (e.g., a plasma etching process or a RIE process) using the photoresist pattern as an etching mask can be performed to form the first rear opening 4510, the second rear opening 4520, the first intermediate opening 4410, and the second intermediate opening 4420.

[0312] For example, an anisotropic etching process can be performed using a first reactive gas containing fluorine (such as CF4, C2F4, C2F6, C3F6, C3F8, C4F6, C4F8, CH3F, CH2F2, C2HF5, CHF3, NF3, and / or SF6, etc.), a second reactive gas containing oxygen (such as O2, NO, and / or NO2, etc.), and a sputtering gas (such as He, Ne, Ar, and / or Xe, etc.) until the rear surface 4104 of the mask substrate 4100 is exposed. For example, the first reactive gas, the second reactive gas, and the sputtering gas can be used during the formation of the first rear opening 4510 and the second rear opening 4520, and the first reactive gas and the sputtering gas can be used during the formation of the first intermediate opening 4410 and the second intermediate opening 4420. That is, after the first rear opening 4510 and the second rear opening 4520 are formed, the supply of the second reactive gas can be stopped. After the first rear opening 4510, the second rear opening 4520, the first intermediate opening 4410 and the second intermediate opening 4420 are formed, the photoresist pattern can be removed by an ashing process and / or a stripping process.

[0313] refer to Figure 26 The mask substrate 4100 can be patterned to form a first unit opening 4110 and a second unit opening 4120 exposing the buffer inorganic film 4200. According to one or more embodiments, the first unit opening 4110 and the second unit opening 4120 can be formed by an anisotropic etching process using a post-inorganic film 4500 and an intermediate inorganic film 4400 as an etching mask. For example, the first unit opening 4110 and the second unit opening 4120 can be formed by a first wet etching process using a first etchant (such as a TMAH solution and / or a KOH solution, etc.), and the first wet etching process can be performed until the buffer inorganic film 4200 is exposed.

[0314] According to one or more embodiments, a single-crystal silicon wafer is used as a mask substrate 4100. <100> The crystal orientation can be a third orientation DR3, and accordingly, the first unit opening 4110 and the second unit opening 4120 can be formed by a first wet etching process to have a width that gradually decreases from the rear surface 4104 of the mask substrate 4100 toward the front surface 4102 of the mask substrate 4100. For example, the inner surfaces of the first unit opening 4110 and the second unit opening 4120 can have a tilt angle of approximately 54.7° relative to the rear surface 4104 of the mask substrate 4100.

[0315] According to one or more embodiments, the buffer inorganic film 4200 can be used as an etching stop film during the first wet etching process. For example, when the buffer inorganic film 4200 is omitted, the first etchant may be provided onto the front portion of the mask substrate 4100 through the first pixel opening 4312 and the second pixel opening 4322. In this case, hydrogen (H2) bubbles may be generated in the first pixel opening 4312 and the second pixel opening 4322 due to the reaction between the first etchant and the front portion of the mask substrate 4100, and the film 4300 may be damaged by the hydrogen (H2) bubbles. According to one or more embodiments, the buffer inorganic film 4200 can prevent the first etchant from being provided onto the front portion of the mask substrate 4100 through the first pixel opening 4312 and the second pixel opening 4322, thereby preventing damage to the film 4300 during the first wet etching process.

[0316] refer to Figure 27 The portion of the buffer inorganic film 4200 exposed through the first unit opening 4110 and the second unit opening 4120 can be removed, thereby forming a first buffer opening 4210 and a second buffer opening 4220 exposing the first mask unit region 4310 and the second mask unit region 4320. For example, when the buffer inorganic film 4200 is made of silicon oxide (SiO2), x When the first buffer opening 4210 and the second buffer opening 4220 are manufactured, they can be formed by a second wet etching process using a second etchant (such as BOE or diluted hydrofluoric acid, etc.), and the first pixel opening 4312 and the second pixel opening 4322 can be connected to the first unit opening 4110 and the second unit opening 4120 respectively through the first buffer opening 4210 and the second buffer opening 4220.

[0317] According to one or more embodiments, the post-inorganic film 4500 can be formed simultaneously (e.g., concurrently) with the thin film 4300 via an LPCVD process. In this case, the post-inorganic film 4500 can have the same thickness as the thin film 4300 and can be made of the same material as the thin film 4300. Furthermore, during the formation of the first pixel opening 4312 and the second pixel opening 4322, the first groove 4316 (see...) Figure 20 and Figure 21 ) and the second groove 4326 (see Figure 20 and Figure 21The first pixel opening 4312, the second pixel opening 4322, the first groove 4316, and the second groove 4326 can be formed simultaneously (e.g., concurrently). For example, a photoresist pattern exposing the portions to be formed of the first pixel opening 4312, the second pixel opening 4322, the first groove 4316, and the second groove 4326 can be formed simultaneously (e.g., concurrently) by an anisotropic etching process using the photoresist pattern as an etching mask. In this case, the first groove 4316 can define a first peripheral region 4314 surrounding (e.g., around) the first mask unit region 4310 (see [reference]). Figure 20 and Figure 21 The second recess 4326 may define a second peripheral region 4324 surrounding (e.g., around) the second mask unit region 4320 (see [reference]). Figure 20 and Figure 21 ).

[0318] According to one or more embodiments, the first rear opening 4510 can be formed such that the inner surface of the first rear opening 4510 overlaps with the first groove 4316 in the thickness direction of the mask substrate 4100, and the second rear opening 4520 can be formed such that the inner surface of the second rear opening 4520 overlaps with the second groove 4326 in the thickness direction of the mask substrate 4100. Accordingly, the remaining area 4360 of the thin film 4300, excluding the first mask unit region 4310, the first peripheral region 4314, the second mask unit region 4320, and the second peripheral region 4324 (see...) Figure 20 The area of ​​the inorganic membrane 4500 can be approximately equal to the area of ​​the inorganic membrane 4500.

[0319] According to one or more embodiments, the third groove 4212 (see Figure 21 ) and fourth groove 4222 (see Figure 21 The first buffer opening 4210 and the second buffer opening 4220 can be formed simultaneously (e.g., concurrently). For example, the first buffer opening 4210, the second buffer opening 4220, the third groove 4212 and the fourth groove 4222 can be formed simultaneously (e.g., concurrently) by a second wet etching process using a second etchant (such as BOE and / or diluted hydrofluoric acid, etc.), such that the first buffer pattern 4214 having the first buffer opening 4210 and the second buffer pattern 4224 having the second buffer opening 4220 can be separated from the buffer inorganic film 4200 by the third groove 4212 and the fourth groove 4222.

[0320] This disclosure should not be construed as limiting itself to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of this disclosure to those skilled in the art.

[0321] While this disclosure has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to this disclosure without departing from the spirit and scope of this disclosure as defined by the claims and their equivalents.

Claims

1. A deposition mask, comprising: mask substrate; as well as The thin film includes a first mask unit region having a first size and a second mask unit region having a second size, and is located on the mask substrate. The thin film has a first pixel opening penetrating the first mask unit region and a second pixel opening penetrating the second mask unit region, and The mask substrate has a first unit opening that exposes the first mask unit area and a second unit opening that exposes the second mask unit area.

2. The deposition mask according to claim 1, wherein, The second mask unit area is located on the edge portion of the mask substrate, and The second dimension is smaller than the first dimension.

3. The deposition mask according to claim 2, wherein, The gap between the second mask unit areas is equal to or less than the gap between the first mask unit areas.

4. The deposition mask according to claim 1, wherein, The second mask unit area is arranged symmetrically with respect to the center of the mask substrate.

5. The deposition mask according to claim 1, wherein, The second dimension is 0.3 to 0.9 times the first dimension.

6. The deposition mask according to claim 1, further comprising: The inorganic film is located on the rear surface of the mask substrate. The thin film is located on the front surface of the mask substrate, and The inorganic membrane comprises the same material as the thin film, but has a greater thickness than the thin film.

7. The deposition mask according to claim 1, further comprising: The inorganic film is located on the rear surface of the mask substrate. The thin film is located on the front surface of the mask substrate, and The inorganic membrane has the same thickness as the thin film, but has a greater residual stress than the thin film.

8. The deposition mask according to claim 1, wherein, The film further includes a first peripheral region surrounding the first mask unit region and a second peripheral region surrounding the second mask unit region, and has a first groove defining the first peripheral region and a second groove defining the second peripheral region.

9. The deposition mask according to claim 8, further comprising: The inorganic film is located on the rear surface of the mask substrate. The thin film is located on the front surface of the mask substrate. The inorganic membrane comprises the same material as the thin film and has the same thickness. Wherein, the area of ​​the inorganic film is equal to the area of ​​the remaining area of ​​the film excluding the first mask unit area, the first peripheral area, the second mask unit area, and the second peripheral area.

10. A method for manufacturing a deposition mask, comprising: A thin film is formed on a mask substrate, the thin film comprising a first mask unit region having a first size and a second mask unit region having a second size; A first pixel opening penetrating the first mask unit area and a second pixel opening penetrating the second mask unit area are formed; and A first cell opening is formed to expose the first mask cell area and a second cell opening is formed to expose the second mask cell area.

11. The method according to claim 10, wherein, The second mask unit area is formed on the edge portion of the mask substrate, and The second dimension is smaller than the first dimension.

12. The method according to claim 11, wherein, The gap between the second mask unit areas is equal to or less than the gap between the first mask unit areas.

13. The method according to claim 10, wherein, The second mask unit area is arranged symmetrically with respect to the center of the mask substrate.

14. The method of claim 10, wherein, The second dimension is 0.3 to 0.9 times the first dimension.

15. The method of claim 10, further comprising: An inorganic film is formed on the rear surface of the mask substrate. The thin film is formed on the front surface of the mask substrate, and The inorganic membrane comprises the same material as the thin film, but has a greater thickness than the thin film.

16. The method of claim 10, further comprising: An inorganic film is formed on the rear surface of the mask substrate. The thin film is formed on the front surface of the mask substrate, and The inorganic membrane has the same thickness as the thin film, but has a greater residual stress than the thin film.

17. The method of claim 10, further comprising: A first groove is formed that defines a first peripheral area around the first mask unit area and a second groove that defines a second peripheral area around the second mask unit area.

18. The method of claim 17, further comprising: An inorganic film is formed on the rear surface of the mask substrate. The thin film is formed on the front surface of the mask substrate. The inorganic membrane comprises the same material as the thin film and has the same thickness. Wherein, the area of ​​the inorganic film is equal to the area of ​​the remaining area of ​​the film excluding the first mask unit area, the first peripheral area, the second mask unit area, and the second peripheral area.

19. An electronic device comprising a display panel, in, The display panel includes a backplane substrate and a plurality of light-emitting layers formed on the backplane substrate using a deposition mask according to any one of claims 1 to 9 or the method according to any one of claims 10 to 18. The plurality of light-emitting layers are formed by light-emitting materials provided through the first pixel opening in one of the first mask unit regions or the second pixel opening in one of the second mask unit regions.

20. The electronic device of claim 19, further comprising: At least one of a processor, memory, and power module.

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