Deposition mask, method of manufacturing a deposition mask, and electronic device

Abstract

The present disclosure relates to a deposition mask, a method of manufacturing a deposition mask, and an electronic device. The deposition mask includes a mask substrate defining a cell opening, a buffer inorganic film on the mask substrate and including an eave region exposed through the cell opening, and a membrane on the eave region and defining a plurality of pixel openings in communication with the cell opening.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2025-0057098, filed on April 30, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to deposition masks, methods for manufacturing deposition masks, and electronic devices manufactured using deposition masks. Background Technology

[0004] Wearable devices capable of focusing at close range to the user's eyes have been developed in the form of glasses or helmets. Such wearable devices can provide users with augmented reality (AR) or virtual reality (VR) visuals. For example, wearable devices can be head-mounted display (HMD) devices or AR glasses.

[0005] Such HMD devices or AR glasses can include display specifications of approximately 3000 PPI (pixels per inch) or higher, allowing users to use them for extended periods without adverse symptoms such as dizziness. For this purpose, organic light-emitting diode-on-silicon (OLEDoS) technology has emerged for use in high-resolution, small-scale organic light-emitting display devices. OLEDoS is a technology in which organic light-emitting diodes (OLEDs) are arranged on a semiconductor substrate on which complementary metal-oxide-semiconductor (CMOS) elements can be arranged.

[0006] To manufacture display panels with a high resolution of approximately 3000 PPI or higher, high-resolution deposition masks can be used. For example, a deposition mask can be used as a shadow mask in a deposition process for forming a light-emitting layer on a substrate. In the deposition process, the substrate can be placed on the deposition mask, and the deposition source for providing the vapor deposition material can be placed under the deposition mask.

[0007] For example, a deposition mask can be fabricated by forming a membrane with multiple pixel openings on a mask substrate and partially removing the mask substrate to form cell openings that expose the pixel openings. However, due to residual stress in the membrane, deformation of the deposition mask may occur. For example, global warpage may occur, where the entire deposition mask is deformed, and cell warpage may occur, where the mask cell regions of the membrane are deformed. As a result, the pixel position accuracy (PPA), dimensional uniformity, etc., of the light-emitting layer may be degraded.

[0008] The information disclosed in this background section is intended to enhance the understanding of the background of this disclosure and may contain information that does not constitute prior art. Summary of the Invention

[0009] One or more embodiments of this disclosure relate to a deposition mask having an improved structure capable of reducing deformation, a method of manufacturing a deposition mask, and an electronic device manufactured using a deposition mask.

[0010] However, the embodiments of this disclosure are not limited to those set forth herein. Other aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0011] In one or more embodiments of this disclosure, a deposition mask includes: a mask substrate defining a cell opening; a buffer inorganic film located on the mask substrate and including an eaves region exposed through the cell opening; and a diaphragm located on the eaves region and defining a plurality of pixel openings communicating with the cell opening.

[0012] In one or more embodiments of this disclosure, the buffer inorganic membrane may have residual compressive stress, and the diaphragm may have residual tensile stress.

[0013] In one or more embodiments of this disclosure, the width of the eaves area can be in the range of about 1 μm to about 100 μm.

[0014] In one or more embodiments of this disclosure, the edge region of the diaphragm may be located on the eaves region, and the width of the overlapping area between the edge region and the eaves region of the diaphragm may be in the range of about 0.5 μm to about 50 μm.

[0015] In one or more embodiments of this disclosure, the mask substrate may include a rib region defining the cell opening, the buffer inorganic film may include a grid region located on the rib region, and the eaves region may extend from the grid region and may be positioned above the grid region.

[0016] In one or more embodiments of this disclosure, the deposition mask may further include a spacer pattern located on the grid area.

[0017] In one or more embodiments of this disclosure, the spacer pattern may include: a first spacer pattern located on the grid area; and a second spacer pattern located on the first spacer pattern. The second spacer pattern may include the same material as the diaphragm.

[0018] In one or more embodiments of this disclosure, the deposition mask may further include mask alignment keys located on the edge region of the buffer inorganic film. The first spacer pattern may include the same material as the mask alignment keys.

[0019] In one or more embodiments of this disclosure, the deposition mask may further include a protective film pattern located on the mask alignment key. The protective film pattern may include the same material as the diaphragm.

[0020] In one or more embodiments of this disclosure, a method of manufacturing a deposition mask includes: forming a buffer inorganic film on a mask substrate; forming a diaphragm having a plurality of pixel openings on the buffer inorganic film; forming preliminary cell openings that partially expose the buffer inorganic film by partially removing the mask substrate; forming buffer openings that partially expose the diaphragm by removing portions of the buffer inorganic film exposed through the preliminary cell openings; and forming cell openings that partially expose the buffer inorganic film by enlarging the preliminary cell openings. The diaphragm is located on an eaves region of the buffer inorganic film exposed through the cell openings.

[0021] In one or more embodiments of this disclosure, forming the diaphragm may include: forming a pre-inorganic film on the buffer inorganic film; and partially removing the pre-inorganic film to form the diaphragm having the plurality of pixel openings. The buffer inorganic film may have residual compressive stress, and the pre-inorganic film may have residual tensile stress.

[0022] In one or more embodiments of this disclosure, the method may further include: forming a mask alignment key on the edge region of the buffer inorganic film; and forming a protective film pattern on the mask alignment key. The protective film pattern can be formed synchronously (e.g., simultaneously) with the diaphragm having the plurality of pixel openings by partially removing the front inorganic film.

[0023] In one or more embodiments of this disclosure, the method may further include: forming a first spacer pattern on the buffer inorganic film; and forming a second spacer pattern on the first spacer pattern. The first spacer pattern may be formed synchronously (e.g., simultaneously) with the mask alignment key, and the second spacer pattern may be formed synchronously (e.g., simultaneously) with the protective film pattern.

[0024] In one or more embodiments of this disclosure, the buffer inorganic film may be formed on the front surface of the mask substrate, and forming the preliminary unit opening may include: forming an intermediate inorganic film on the rear surface of the mask substrate; forming a rear inorganic film on the intermediate inorganic film; forming a rear opening that partially exposes the intermediate inorganic film by partially removing the rear inorganic film; forming a preliminary intermediate opening that partially exposes the rear surface of the mask substrate by partially removing a portion of the intermediate inorganic film exposed through the rear opening; and forming the preliminary unit opening by performing an etching process that uses (e.g., utilizes) the rear inorganic film and the intermediate inorganic film as an etching mask.

[0025] In one or more embodiments of this disclosure, the initial intermediate opening may have a width smaller than that of the rear opening, and forming the unit opening may include: forming the intermediate opening by removing the remainder of the portion of the intermediate inorganic membrane exposed through the rear opening; and enlarging the initial unit opening by removing an inner surface portion defining the initial unit opening (the inner surface portion of the initial unit opening).

[0026] In one or more embodiments of this disclosure, the formation of the intermediate opening and the formation of the buffer opening are performed synchronously (e.g., simultaneously).

[0027] In one or more embodiments of this disclosure, the method may further include: forming an etch stop film on the buffer inorganic film and the diaphragm; and removing the etch stop film after forming the buffer opening.

[0028] In one or more embodiments of this disclosure, the edge region of the diaphragm may be located on the eaves region, and the area where the edge region and the eaves region of the diaphragm overlap each other may have a width smaller than the width of the eaves region.

[0029] In one or more embodiments of this disclosure, an electronic device includes a display panel. The display panel includes a substrate and a plurality of light-emitting layers formed on the substrate using (e.g., utilizing) a deposition mask. The deposition mask includes: a mask substrate having (e.g., defining) cell openings; a buffer inorganic film located on the mask substrate and including an eaves region exposed through the cell openings; and a septum located on the eaves region and having (e.g., defining) a plurality of pixel openings communicating with the cell openings. The plurality of light-emitting layers are formed by a deposition process that provides vapor-phase luminescent material onto the substrate through the cell openings and the pixel openings.

[0030] In one or more embodiments of this disclosure, the electronic device may further include at least one of a processor, a memory, and a power module.

[0031] In one or more embodiments of this disclosure, the diaphragm may be located on the eaves region of the buffer inorganic membrane exposed through the unit opening. The buffer inorganic membrane may have residual compressive stress, and the diaphragm may have residual tensile stress. Therefore, the deformation of the diaphragm can be reduced by the residual compressive stress of the buffer inorganic membrane and the residual tensile stress of the diaphragm.

[0032] For example, one or more embodiments provide a deposition mask and an associated manufacturing method that improves pixel positioning accuracy and reduces global warpage and cell warpage by controlling residual stress in multiple layers. The deposition mask may include optional features such as spacer patterns, mask alignment keys, and protective film patterns to facilitate alignment and handling during deposition. The method may further include the sequential or simultaneous formation of buffer openings, intermediate openings, and cell openings to expose a septum with pixel openings, thereby enabling precise deposition of luminescent material onto a substrate through the deposition mask. As described herein, these structural and process features collectively support high-resolution display panels and electronic devices incorporating such panels.

[0033] Other features and embodiments may be apparent from the following detailed description and accompanying drawings. Attached Figure Description

[0034] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure. In the drawings:

[0035] Figure 1 This is a block diagram of an electronic device according to one or more embodiments of the present disclosure;

[0036] Figure 2 A schematic diagram of an electronic device according to an embodiment of the present disclosure is shown;

[0037] Figure 3 This is an exploded perspective view of a display device according to one or more embodiments of the present disclosure;

[0038] Figure 4 It is based on one or more embodiments of this disclosure Figure 3 A block diagram of a display device;

[0039] Figure 5 It is based on one or more embodiments of this disclosure Figure 4 The equivalent circuit diagram of the first sub-pixel;

[0040] Figure 6It is based on one or more embodiments of this disclosure Figure 3 A schematic floor plan of the display panel;

[0041] Figure 7 It is based on one or more embodiments of this disclosure Figure 6 A schematic enlarged plan view of a portion of the display area;

[0042] Figure 8 It is based on one or more embodiments of this disclosure Figure 6 A schematic enlarged plan view of a portion of the display area;

[0043] Figure 9 It is according to one or more embodiments of this disclosure along Figure 7 A schematic cross-sectional view of the display panel taken by line I1-I1';

[0044] Figure 10 It is according to one or more embodiments of this disclosure along Figure 7 A schematic cross-sectional view of the display panel taken by line I1-I1';

[0045] Figure 11 It is according to one or more embodiments of this disclosure along Figure 7 A schematic cross-sectional view of the display panel taken by line I1-I1';

[0046] Figure 12 This is a schematic perspective view of a head-mounted display according to one or more embodiments of the present disclosure;

[0047] Figure 13 It is based on one or more embodiments of this disclosure Figure 12 A schematic exploded perspective view of a head-mounted display;

[0048] Figure 14 This is a schematic perspective view of a head-mounted display according to one or more embodiments of the present disclosure;

[0049] Figure 15 This is a schematic diagram illustrating a deposition mask and deposition apparatus according to one or more embodiments of the present disclosure;

[0050] Figure 16 It is based on one or more embodiments of this disclosure Figure 15 A schematic bottom view of the base plate shown in the figure;

[0051] Figure 17 It is based on one or more embodiments of this disclosure Figure 15 A schematic plan view of the deposition mask shown in the figure;

[0052] Figure 18This illustrates one or more embodiments according to the present disclosure. Figure 17 A schematic plan view of the diaphragm;

[0053] Figure 19 It is according to one or more embodiments of this disclosure along Figure 18 A schematic cross-sectional view of the line I2-I2';

[0054] Figure 20 It is based on one or more embodiments of this disclosure Figure 17 A schematic cross-sectional view of the mask alignment key shown in the figure;

[0055] Figure 21 It is based on one or more embodiments of this disclosure Figure 17 A schematic cross-sectional view of the spacer pattern; and

[0056] Figures 22 to 34 This is a schematic cross-sectional view illustrating a method of manufacturing a deposition mask according to one or more embodiments of the present disclosure. Detailed Implementation

[0057] This disclosure can be modified in many alternative forms, and therefore specific embodiments will be illustrated and described in more detail in the accompanying drawings. However, it should be understood that this is not intended to limit this disclosure to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of this disclosure.

[0058] In the following description, exemplary embodiments will be presented in more detail with reference to the accompanying drawings. However, this disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments illustrated herein. Rather, these embodiments are provided as examples so that this disclosure will be comprehensive and complete, and will fully convey to those skilled in the art the aspects and features of this disclosure. Accordingly, processes, elements, and techniques not essential for a person of ordinary skill in the art to fully understand the aspects and features of this disclosure may not be described. It will be understood that when an element (such as a region, layer, film, area, or portion) is referred to as being “on” or “connected” to another element, it may be directly on or directly connected to the other element, or one or more intermediary elements may be present. Conversely, when an element or layer is referred to as being “directly on”, “directly connected to,” or “immediately adjacent to” another element or layer, no intermediary element or layer is present. Additionally, it will be understood that when an element is referred to as being “between” two elements, it may be the only element between the two elements, or one or more intermediary elements may be present.

[0059] Unless otherwise stated, the same reference numerals denote the same elements throughout the accompanying drawings and written description, and therefore, their repeated descriptions are not required.

[0060] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or segments, these elements, components, areas, layers, and / or segments should not be limited by these terms. These terms are used to distinguish one element, component, area, layer, or segment from another element, component, area, layer, or segment. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, area, layer, or segment described below may be referred to as the second element, component, area, layer, or segment.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, “a,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. For example, “an element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limiting “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any one and all combinations of one or more of the associated listed items.

[0062] Unless otherwise apparent from the public information, expressions such as “at least one of…”, “multiple,” “one of…”, and other prepositional phrases, when preceding / following a list of elements, should be understood to include a disjunctive list if written as a conjunctive list, and vice versa. For example, expressions such as “at least one of a, b, and c,” “one selected from the group consisting of a, b, and c,” “at least one selected from a, b, and c,” “at least one of a, b, and c,” “one of a, b, and c,” and “at least one of a to c” indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0063] As used herein, the terms “use” and “being used” can be considered synonymous with the terms “exploitation” and “being exploited”, respectively.

[0064] Furthermore, when describing embodiments of this disclosure, the use of "may" refers to "one or more embodiments of this disclosure".

[0065] It will be further understood that the terms “comprising,” “including,” and “having,” as used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Additionally, the terms “comprising,” “including,” “having,” or similar terms include or support the terms “consisting of,” and “substantially constitutes,” indicating the presence of the stated features, integers, steps, operations, elements, and / or components, and the absence or substantial absence of other features, integers, steps, operations, elements, components, and / or groups thereof.

[0066] For ease of interpretation, spatial relative terms such as “above,” “below,” “bottom,” “lower,” “below,” “above,” “upper,” “top,” etc., are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). It will be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figures is flipped, an element described as “below,” “under,” or “below” other elements or features would then be oriented as “above” other elements or features. Thus, the illustrative terms “below” and “below” can cover both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0067] In view of the whole of this disclosure, those skilled in the art will understand that each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with one another, and may be technically interlocked and operated in a variety of suitable ways, and each embodiment may be implemented independently of one another or in any suitable combination of the other, unless otherwise stated or implied. As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms and not as terms of degree, and are intended to describe the inherent deviations of measured or calculated values ​​that those skilled in the art will recognize. As used herein, “substantially” includes the stated value and means within an acceptable range of deviation for a particular value as determined by those skilled in the art considering the measurements discussed and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “substantially” may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0068] Furthermore, any numerical range disclosed and / or described herein is intended to include all subranges with the same numerical precision contained within the described range. For example, the range “1.0 to 10.0” is intended to include all subranges between the described minimum value of 1.0 and the described maximum value of 10.0 (and including both the described minimum value of 1.0 and the described maximum value of 10.0), i.e., having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described herein is intended to include all higher numerical limits contained therein. Accordingly, the applicant reserves the right to amend this specification, including the claims, to explicitly describe any subranges contained within the range explicitly described herein.

[0069] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0070] The embodiments described herein are illustrated with reference to cross-sectional examples, which are illustrative examples of idealized embodiments. Thus, variations in the illustrated shape will be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to a specific shape of the region as illustrated herein, but should include, for example, deviations in shape due to manufacturing processes. For example, a region illustrated or described as flat may have rough and / or non-linear characteristics. Furthermore, illustrated sharp corners may be rounded. Therefore, the regions illustrated in the drawings are schematic in nature, and their shapes are not intended to illustrate precise shapes of the regions, nor are they intended to limit the scope of the claims. Additionally, in the drawings, for clarity, the relative dimensions of elements, layers, and regions (e.g., including length, width, and thickness) may be exaggerated.

[0071] In the following description, embodiments will be described in more detail with reference to the accompanying drawings.

[0072] The display device according to one or more embodiments of the present disclosure can be applied to one or more suitable electronic devices. The electronic device according to one or more embodiments of the present disclosure includes the display device described above, and in addition to the display device, the electronic device according to one or more embodiments of the present disclosure may further include modules or devices with additional functions.

[0073] Figure 1This is a block diagram of an electronic device according to one or more embodiments of the present disclosure.

[0074] refer to Figure 1 An electronic device 10 according to one or more embodiments of the present disclosure may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0075] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0076] The memory 13 can store data information necessary for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals are transmitted to the display module 11, and the display module 11 is able to process the received signals and output image information through the display screen.

[0077] The power module 14 may include a power module such as a power adapter or battery, and a power conversion module configured to convert the power supplied by the power module to generate the power necessary for the operation of the electronic device 10.

[0078] At least one component of an electronic device 10 according to one or more embodiments of the present disclosure may be included in a display device 20 according to one or more embodiments of the present disclosure (see...). Figure 3 In addition, some modules that are functionally included in a module may be included in the display device 20, while other modules may be provided separately from the display device 20. For example, the display device 20 may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided in the form of other devices within the electronic device 10 that are different from the display device 20.

[0079] Figure 2 A schematic diagram of an electronic device according to one or more suitable embodiments of the present disclosure is shown.

[0080] refer to Figure 2The display device 20 according to one or more embodiments of the present disclosure is applied to one or more suitable electronic devices, including not only image display electronic devices (such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions 10_1d, and desktop monitors 10_1e), but also wearable electronic devices (such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c) and vehicle electronic devices 10_3 (such as central information displays (CIDs) arranged in the dashboard of automobiles, interior mirror displays, central instrument panels, and / or dashboards).

[0081] Figure 3 This is an exploded perspective view illustrating a display device according to one or more embodiments of the present disclosure. Figure 4 This illustrates one or more embodiments according to the present disclosure. Figure 3 A block diagram of the display device.

[0082] refer to Figure 3 and Figure 4 The display device 20 according to one or more embodiments can be a device for displaying moving or still images. The display device 20 according to one or more embodiments can be used as an electronic device 10 or a display module 11 of the electronic device 10 (see...). Figure 1 For example, the display device 20 according to one or more embodiments can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, ultra-mobile PCs (UMPCs), etc. The display device 20 according to one or more embodiments can be applied as a display module for electronic devices such as televisions, laptops, monitors, billboards, or Internet of Things (IoT) terminals. The display device 20 according to one or more embodiments can be applied to electronic devices such as smartwatches, watch phones, head-mounted displays (HMDs) for realizing virtual and augmented reality.

[0083] The display device 20 according to one or more embodiments may include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit (or timing controller) 400, and a power supply circuit (or power supply unit) 500.

[0084] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having a short side extending in a first direction DR1 and a long side extending in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side extending in the first direction DR1 and the long side extending in the second direction DR2 intersect may be a right angle or rounded with a set or predetermined curvature. The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to other polygonal shapes, circular shapes, or elliptical shapes. The planar shape of the display device 20 may be consistent with the planar shape of the display panel 100, but this disclosure is not limited thereto.

[0085] The display panel 100 may include multiple pixels PX, multiple scan lines SL, multiple emission control lines EL, multiple data lines DL, a scan driver 610, an emission driver 620, and a data driver 700. For example... Figure 4 As shown, the display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0086] Multiple pixels (PX) can be arranged in the display area (DAA). Multiple pixels (PX) can be arranged in a matrix along a first direction (DR1) and a second direction (DR2). Multiple scan lines (SL) and multiple emission control lines (EL) can extend along the first direction (DR1) and are arranged along the second direction (DR2). Multiple data lines (DL) can extend along the second direction (DR2) and are arranged along the first direction (DR1).

[0087] Multiple scan lines SL can include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. Multiple emit control lines EL include multiple first emit control lines ECL1 and multiple second emit control lines ECL2.

[0088] Multiple pixels PX can include multiple sub-pixels SP1, SP2, and SP3. For example... Figure 5 As shown, the multiple sub-pixels SP1, SP2, and SP3 may include multiple pixel transistors, and the multiple pixel transistors may be formed and arranged on a semiconductor substrate SSUB using semiconductor processes (e.g., see...). Figure 9 For example, the multiple pixel transistors of multiple sub-pixels SP1, SP2 and SP3 can be formed by complementary metal-oxide semiconductor (CMOS), but this disclosure is not limited thereto.

[0089] Each of the multiple sub-pixels SP1, SP2, and SP3 can be connected to a write scan line GWL, a control scan line GCL, a bias scan line GBL, a first emission control line ECL1, a second emission control line ECL2, and a data line DL. Each of the multiple sub-pixels SP1, SP2, and SP3 can receive the data voltage of the data line DL in response to the write scan signal of the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0090] The scan driver 610, the transmit driver 620, and the data driver 700 can be arranged in the non-display area NDA.

[0091] The scan driver 610 includes a plurality of scan transistors, and the emitter driver 620 includes a plurality of light-emitting transistors. The plurality of scan transistors and the plurality of light-emitting transistors can be formed on a semiconductor substrate SSUB (e.g., see [reference needed]) using semiconductor processes. Figure 9 For example, multiple scanning transistors and multiple light-emitting transistors can be formed by CMOS, but this disclosure is not limited thereto.

[0092] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS from the timing control circuit 400 and output them sequentially to the write scan line GWL. The control scan signal output unit 612 may generate control scan signals according to the scan timing control signal SCS and output them sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate bias scan signals according to the scan timing control signal SCS and output them sequentially to the bias scan line GBL.

[0093] The transmit driver 620 includes a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 can receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 can generate a first transmit control signal based on the transmit timing control signal ECS and outputs them sequentially to a first transmit control line ECL1. The second transmit control driver 622 can generate a second transmit control signal based on the transmit timing control signal ECS and outputs them sequentially to a second transmit control line ECL2.

[0094] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed on a semiconductor substrate SSUB (e.g., see [reference]). Figure 9 For example, multiple data transistors can be formed using CMOS, but this disclosure is not limited thereto.

[0095] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In such an embodiment, sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0096] The heat dissipation layer 200 may overlap with the display panel 100 on a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100, for example, on its rear surface. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a material with high thermal conductivity, such as graphite or metals such as silver (Ag), copper (Cu), aluminum (Al), etc.

[0097] Circuit board 300 can be electrically connected to the first pad portion of display panel 100 PDA1 using conductive adhesive components (such as anisotropic conductive film) (e.g., see...). Figure 6 Multiple first pads PD1 (e.g., see...) Figure 6 Circuit board 300 can be a flexible film or a flexible printed circuit board with flexible materials. Although circuit board 300 is in Figure 3 The circuit board 300 is illustrated as unfolded, but it can be bent. In such an embodiment, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The other end of the circuit board 300 may be connected to the first pad portion of the display panel 100, PDA1, using conductive adhesive members (e.g., see...). Figure 6 Multiple first pads PD1 (e.g., see...) Figure 6 One end of circuit board 300 can be the opposite end of the other end of circuit board 300.

[0098] The timing control circuit 400 can receive digital video data and timing signals input from an external source. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can output digital video data DATA and the data timing control signal DCS to the data driver 700.

[0099] The power supply circuit 500 can generate multiple panel driving voltages based on external power voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. This will be discussed later. Figure 5 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are described in more detail.

[0100] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In such an embodiment, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0101] In one or more embodiments, similar to scan driver 610, transmit driver 620, and data driver 700, each of timing control circuitry 400 and power supply circuitry 500 may be arranged in the non-display area NDA of display panel 100. In such embodiments, timing control circuitry 400 may include a plurality of timing transistors, and power supply circuitry 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed on semiconductor substrate SSUB (e.g., see [reference needed]) using semiconductor processes. Figure 9 On the data driver 700. For example, multiple sequential transistors and multiple power transistors can be formed by CMOS, but this disclosure is not limited thereto. Each of the timing control circuitry 400 and the power supply circuitry 500 can be arranged on the data driver 700 and the first pad portion of PDA1 (e.g., see...). Figure 6 )between.

[0102] Figure 5 This illustrates one or more embodiments according to the present disclosure. Figure 4The equivalent circuit diagram of the example of the first sub-pixel is shown in the figure.

[0103] refer to Figure 5 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line ECL1, the second emit control line ECL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to the first drive voltage VSS corresponding to the low potential voltage (see...). Figure 4 The first driving voltage line VSL and the second driving voltage VDD corresponding to the high potential voltage are applied (see...). Figure 4 The second drive voltage line VDL and the third drive voltage VINT corresponding to the initialization voltage are applied (see...). Figure 4 The third driving voltage line VIL is applied.

[0104] The first sub-pixel SP1 may include multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0105] The light-emitting element LE emits light in response to a drive current flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE can be proportional to the drive current. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but this disclosure is not limited thereto. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode; in this case, the light-emitting element LE can be a miniature light-emitting diode.

[0106] The first transistor T1 may be a driving transistor that controls the source-drain current (hereinafter referred to as the "driving current") flowing between its source and drain electrodes according to the voltage applied to its gate electrode.

[0107] A second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by the write scan signal of the write scan line GWL to connect that electrode of the first capacitor CP1 to the data line DL. Accordingly, the data voltage of the data line DL can be applied to that electrode of the first capacitor CP1.

[0108] The third transistor T3 can be arranged between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal controlling the scan line GCL to connect the first node N1 to the second node N2. For this reason, if the gate electrode and drain electrode of the first transistor T1 are connected, the first transistor T1 can operate like a diode (e.g., when the gate electrode and drain electrode of the first transistor T1 are connected, the first transistor T1 can operate like a diode).

[0109] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emitter control signal of the first emitter control line ECL1 to connect the second node N2 to the third node N3. Correspondingly, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. A fifth transistor T5 can be arranged between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third drive voltage line VIL. Correspondingly, the third drive voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE.

[0110] A sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emitter control signal of the second emitter control line ECL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Accordingly, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1.

[0111] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL.

[0112] Each of the first transistors T1 to the sixth transistor T6 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 to the sixth transistor T6 may be a P-type MOSFET, but this disclosure is not limited thereto. Each of the first transistors T1 to the sixth transistor T6 may be an N-type MOSFET. In one or more embodiments, some of the first transistors T1 to the sixth transistor T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0113] Despite Figure 5The example shown illustrates that the first sub-pixel SP1 includes six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to this. Figure 5 The equivalent circuit diagram is shown below. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 5 The quantities shown in the figure.

[0114] Furthermore, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 can be combined with... Figure 5 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the descriptions of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 need not be repeated in this disclosure.

[0115] Figure 6 This illustrates one or more embodiments according to the present disclosure. Figure 3 A schematic floor plan of an example display panel shown in the figure.

[0116] refer to Figure 6 The display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0117] The scan driver 610 can be arranged on a first side of the display area DAA, and the transmit driver 620 can be arranged on a second side of the display area DAA. For example, the scan driver 610 can be arranged on one side of the display area DAA in a first direction DR1, and the transmit driver 620 can be arranged on the other side of the display area DAA in the first direction DR1. However, this disclosure is not limited thereto, and each of the scan driver 610 and the transmit driver 620 can be arranged on either the first side or the second side of the display area DAA.

[0118] The first pad portion PDA1 may include a plurality of first pads PD1, which are connected to pads or bumps of the circuit board 300 via conductive adhesive members. The first pad portion PDA1 may be arranged on the third side of the display area DAA. For example, the first pad portion PDA1 may be arranged on one side of the display area DAA in the second direction DR2. The first pad portion PDA1 may be arranged on the second direction DR2 relative to the display area DAA outside the data driver 700.

[0119] The second pad portion PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating correctly. The multiple second pads PD2 may be connected to a fixture or probe during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a rigid printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0120] The second pad portion PDA2 can be arranged on the fourth side of the display area DAA. For example, the second pad portion PDA2 can be arranged on the other side of the display area DAA in the second direction DR2, relative to the third side of the display area DAA. The second pad portion PDA2 can also be arranged outside the second distribution circuit 720 in the second direction DR2 relative to the display area DAA.

[0121] The first distribution circuit 710 distributes the data voltage applied through the first pad portion of PDA1 to multiple data lines DL (e.g., see...). Figure 4 For example, the first distribution circuit 710 can distribute the data voltage applied through one of the first pads PD1 in the first pad portion PDA1 to P data lines DL (P being a positive integer greater than or equal to 2), and as a result, the number of multiple first pads PD1 can be reduced. In other words, each of the first pads PD1 can supply data voltage to multiple data lines DL, thereby reducing the number of first pads PD1. The first distribution circuit 710 can be arranged on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be arranged on one side of the display area DAA in the second direction DR2.

[0122] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each pixel PX in the display area DAA. The second distribution circuit 720 can be arranged on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be arranged on the other side of the display area DAA in the second direction DR2.

[0123] The cathode connection (CCA) can be a display element layer (EML) within which (for example, see...) Figure 9 The second electrode CAT (e.g., see...) Figure 9 The first drive voltage line VSL connected to the non-display area NDA (see...) Figure 5The cathode connection portion (CCA) can be arranged on the outer side of at least one side of the display area (DAA). For example, the cathode connection portion (CCA) can be arranged on the outer side of at least one of the left, right, upper, and lower sides of the display area (DAA). In one or more embodiments, such as Figure 6 As shown, the cathode connection CCA can be arranged to surround (e.g., encircle) the display area DAA in order to minimize or reduce the first drive voltage VSS caused by the voltage drop (IR drop) or voltage rise (IR rise) of the second electrode CAT in the display area DAA (see Figure 1). Figure 4 () deviation.

[0124] Figure 7 It is based on one or more embodiments of this disclosure Figure 6 A schematic enlarged plan view of a portion of the display area. Figure 8 It is based on one or more embodiments of this disclosure Figure 6 A schematic enlarged plan view of a portion of the display area.

[0125] refer to Figure 7 and Figure 8 Each pixel PX includes a first emission region EA1, which is the emission region of the first sub-pixel SP1; a second emission region EA2, which is the emission region of the second sub-pixel SP2; and a third emission region EA3, which is the emission region of the third sub-pixel SP3.

[0126] The first launch area EA1, the second launch area EA2, and the third launch area EA3 can be arranged as follows in the plan view: Figure 7 and Figure 8 The quadrilateral or hexagonal shapes shown are not limited thereto. The first emission region EA1, the second emission region EA2, and the third emission region EA3 may have polygonal shapes, circular shapes, elliptical shapes, or atypical shapes other than quadrilaterals or hexagons in the plan view.

[0127] like Figure 7 As shown, in each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the first direction DR1. Further, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. In one or more embodiments, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the second direction DR2. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different.

[0128] Alternatively, according to one or more embodiments, such as Figure 8As shown, emission regions EA1, EA2, EA3, and EA4 can each have a hexagonal shape in the planar view. In such an embodiment, the first emission region EA1 and the third emission region EA3 can be adjacent in the first direction DR1, and the second emission region EA2 and the fourth emission region EA4, which is the emission region of the fourth sub-pixel SP4, can be adjacent in the second direction DR2. Additionally, the first emission region EA1 and the second emission region EA2 can be adjacent in the first diagonal direction DD1, and the second emission region EA2 and the third emission region EA3 can be adjacent in the second diagonal direction DD2. Furthermore, the first emission region EA1 and the fourth emission region EA4 can be adjacent in the second diagonal direction DD2, and the third emission region EA3 and the fourth emission region EA4 can be adjacent in the first diagonal direction DD1. The first diagonal direction DD1 can be the direction between the first direction DR1 and the second direction DR2, and can refer to a direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 can be a direction orthogonal (e.g., perpendicular) to the first diagonal direction DD1.

[0129] The first sub-pixel SP1 can be used to emit a first light, the second sub-pixel SP2 can be used to emit a second light, and the third sub-pixel SP3 can be used to emit a third light. When a fourth sub-pixel SP4 is present, the fourth sub-pixel SP4 can be used to emit a second light and can have a structure substantially the same as that of the second sub-pixel SP2. Here, the first light can be light in the blue wavelength band, the second light can be light in the green wavelength band, and the third light can be light in the red wavelength band. For example, the blue wavelength band can be the wavelength band of light whose main peak wavelength is in the range of approximately 370 nm to 460 nm, the green wavelength band can be the wavelength band of light whose main peak wavelength is in the range of approximately 480 nm to 560 nm, and the red wavelength band can be the wavelength band of light whose main peak wavelength is in the range of approximately 600 nm to 750 nm.

[0130] Each of the multiple pixels PX can be as follows Figure 7 As shown, it includes three launch zones EA1, EA2, and EA3, or it can be as follows: Figure 8 As shown, it includes four emission regions EA1, EA2, EA3, and EA4. In such an embodiment, the fourth emission region EA4 can be used to emit the same second light as the second emission region EA2, but this disclosure is not limited thereto.

[0131] The emission regions of multiple pixels PX can be arranged in a stripe structure along a first direction DR1, wherein the emission regions EA1, EA2, EA3, and EA4 are arranged as follows: Figure 8 The diamond-shaped arrangement of the PENTILE shown in the image ®The structure, or the emission area within it, is arranged in a hexagonal shape. (PENTILE) ® It is an officially registered trademark of Samsung Display Co., Ltd.

[0132] Figure 9 It is according to one or more embodiments of this disclosure along Figure 7 A schematic cross-sectional view of the display panel taken by line I1-I1'.

[0133] refer to Figure 9 The display panel 100 includes a semiconductor substrate SBP, a light-emitting element substrate EBP, a display element layer EML, a packaging layer TFE, an optical layer OPL, a cover layer CVL, and a polarizer POL.

[0134] The semiconductor substrate (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) can be a reference. Figure 5 The first transistor T1 to the sixth transistor T6 are described.

[0135] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type (type) of impurity. Multiple well regions WA can be arranged on the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type (type) of impurity. The second type (type) of impurity can be different from the first type (type) of impurity. For example, if the first type (type) of impurity is a P-type impurity, then the second type (type) of impurity can be an N-type impurity (e.g., when the first type (type) of impurity is a P-type impurity, the second type (type) of impurity can be an N-type impurity). In one or more embodiments, if the first type (type) of impurity is an N-type impurity, then the second type (type) of impurity can be a P-type impurity (e.g., when the first type (type) of impurity is an N-type impurity, the second type (type) of impurity can be a P-type impurity).

[0136] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0137] The lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. The side insulating film (SINS) can be disposed on the side surface of the gate electrode GE. The side insulating film (SINS) can also be disposed on the lower insulating film (BINS).

[0138] Each of the source region SA and the drain region DA can be a region doped with a first type (species) of impurities. The gate electrode GE of the pixel transistor PTR can overlap with the well region WA on a third direction DR3, which is the thickness direction of the semiconductor substrate SSUB. The channel region CH can overlap with the gate electrode GE on a third direction DR3. The source region SA can be disposed on one side of the gate electrode GE, and the drain region DA can be disposed on the other side of the gate electrode GE.

[0139] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 may be a region having a lower impurity concentration than the drain region DA due to the lower insulating film BINS. The distance between the source region SA and the drain region DA may be increased due to the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, thereby increasing the length of the channel region CH of each pixel transistor PTR.

[0140] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB. The second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1.

[0141] Multiple contact terminals (CTEs) can be arranged on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to a corresponding one of the gate electrode (GE), source region (SA), and drain region (DA) of the corresponding pixel transistor (PTR) through a hole penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The multiple contact terminals (CTEs) can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) and / or alloys including one or more of them.

[0142] The third semiconductor insulating film SINS3 can be disposed on the side surface of each of the plurality of contact terminals CTEs. The top surface of each of the plurality of contact terminals CTEs can be exposed and not covered by the third semiconductor insulating film SINS3.

[0143] Each of the first semiconductor insulating film SINS1, the second semiconductor insulating film SINS2, and the third semiconductor insulating film SINS3 can be made of silicon carbonitride (SiCN) or silicon oxide (SiO2). x Inorganic membranes can be formed, but this disclosure is not limited thereto.

[0144] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate such as a polyimide substrate. In such embodiments, thin-film transistors can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, while the polymer resin substrate can be a flexible substrate that can be bent or flexed.

[0145] The light-emitting element base plate EBP includes multiple conductive layers ML1 to ML8, multiple through holes VA1 to VA9, and multiple interlayer insulating films INS1 to INS9.

[0146] Interlayer insulating films INS1 to INS9 are used to insulate first conductive layers ML1 to eighth conductive layers ML8. First conductive layers ML1 to eighth conductive layers ML8 are used to connect multiple contact terminals CTE exposed from the semiconductor substrate SBP, thereby achieving... Figure 5 The circuitry for the first sub-pixel SP1 is shown in the diagram.

[0147] For example, transistors T1 through T6 (see Figure 5 ) can be formed in the semiconductor substrate SBP, and the first transistor T1 to the sixth transistor T6 are connected to the first capacitor CP1 and the second capacitor CP2 (see Figure 5 The connection is achieved through the first conductive layer ML1 to the eighth conductive layer ML8. In one or more embodiments, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE is also achieved through the first conductive layer ML1 to the eighth conductive layer ML8.

[0148] The first conductive layers ML1 to ML8 and the first through-holes VA1 to VA8 can be formed of substantially the same material. The first conductive layers ML1 to ML8 and the first through-holes VA1 to VA8 can be formed of any one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). The first through-holes VA1 to VA8 can be made of substantially the same material. The first interlayer insulating film INS1 to INS8 can be made of silicon oxide (SiO2). x Inorganic membranes can be formed, but this disclosure is not limited thereto.

[0149] The ninth interlayer insulating film INS9 can be disposed on the eighth interlayer insulating film INS8 and the eighth conductive layer ML8. The ninth interlayer insulating film INS9 can be made of silicon oxide (SiO2). x Inorganic membranes can be formed, but this disclosure is not limited thereto.

[0150] Each of the ninth vias VA9 can penetrate the ninth interlayer insulating film INS9 and connect to the exposed eighth conductive layer ML8. The ninth via VA9 can be formed of any one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd).

[0151] The display element layer (EML) can be disposed on the light-emitting element substrate (EBP). The display element layer (EML) may include a tenth interlayer insulating film (INS10) and an eleventh interlayer insulating film (INS11), a reflective electrode (RL), a first electrode (AND), a light-emitting stack (IL), a second electrode (CAT), a pixel defining film (PDL), and multiple trenches (TRC).

[0152] The reflective electrode RL can be disposed on the ninth interlayer insulating film INS9. Each reflective electrode RL may include at least one reflective electrode layer RL1, RL2, RL3 and / or RL4. For example, as Figure 9 As shown, each reflective electrode RL may include a first reflective electrode layer to a fourth reflective electrode layer RL1, RL2, RL3 and RL4.

[0153] The first reflective electrode layer RL1 can be disposed on the ninth interlayer insulating film INS9 and can be connected to the ninth through-hole VA9. Each second reflective electrode layer RL2 can be disposed on its corresponding first reflective electrode layer RL1. Each third reflective electrode layer RL3 can be disposed on its corresponding second reflective electrode layer RL2. Each fourth reflective electrode layer RL4 can be disposed on its corresponding third reflective electrode layer RL3.

[0154] Because the second reflective electrode layer RL2 is an electrode layer that essentially reflects light from the light-emitting element LE, the thickness of the second reflective electrode layer RL2 can be greater than the thickness of each of the first reflective electrode layer RL1, the third reflective electrode layer RL3, and the fourth reflective electrode layer RL4.

[0155] The first reflective electrode layer RL1 may be formed of any one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the first reflective electrode layer RL1 may contain titanium nitride (TiN), the second reflective electrode layer RL2 may contain aluminum (Al), the third reflective electrode layer RL3 may contain titanium nitride (TiN), and the fourth reflective electrode layer RL4 may contain titanium (Ti).

[0156] The tenth interlayer insulating film INS10 can be disposed on the ninth interlayer insulating film INS9. The tenth interlayer insulating film INS10 can be disposed between adjacent reflective electrodes RL. The tenth interlayer insulating film INS10 can be a film used to planarize the stepped portion caused by the reflective electrode RL. The eleventh interlayer insulating film INS11 can be disposed on the tenth interlayer insulating film INS10 and the reflective electrode RL.

[0157] The tenth interlayer insulating film INS10 and the eleventh interlayer insulating film INS11 can be made of silicon oxide (SiO2). x Inorganic membranes can be formed, but this disclosure is not limited thereto.

[0158] The eleventh interlayer insulating film INS11 can be an optical auxiliary film used to adjust the resonant distance of light emitted from the light-emitting stack IL in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The thickness of the eleventh interlayer insulating film INS11 can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, in order to adjust the distance from the reflective electrode RL to the second electrode CAT according to the main peak wavelength of the light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the thickness of the eleventh interlayer insulating film INS11 can be set for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0159] For example, such as Figure 9 As shown, the thickness of the eleventh interlayer insulating film INS11 in the first sub-pixel SP1 can be greater than the thickness of the eleventh interlayer insulating film INS11 in the second sub-pixel SP2, and the thickness of the eleventh interlayer insulating film INS11 in the second sub-pixel SP2 can be greater than the thickness of the eleventh interlayer insulating film INS11 in the third sub-pixel SP3. In such an embodiment, the distance between the first electrode AND and the reflective electrode RL in the first sub-pixel SP1 can be greater than the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2. Furthermore, the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP2 can be greater than the distance between the first electrode AND and the reflective electrode RL in the third sub-pixel SP3.

[0160] Each tenth via VA10 can penetrate the eleventh interlayer insulating film INS11 and connect to the exposed fourth reflective electrode layer RL4. The tenth via VA10 can be formed of any one or an alloy of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). The thickness of the tenth via VA10 in the first sub-pixel SP1 can be greater than the thickness of the tenth via VA10 in the second sub-pixel SP2, and the thickness of the tenth via VA10 in the second sub-pixel SP2 can be greater than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0161] The first electrode AND of each light-emitting element LE can be disposed on the eleventh interlayer insulating film INS11 and connected to the tenth via VA10. The first electrode AND of each light-emitting element LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth via VA10, the reflective electrode RL, the first vias VA1 to the ninth vias VA9, the first conductive layers ML1 to the eighth conductive layers ML8, and the contact terminal CTE. The first electrode AND of each light-emitting element LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including one or more of them. For example, the first electrode AND of each light-emitting element LE can be titanium nitride (TiN).

[0162] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each light-emitting element (LE). The PDL can cover the edge of the first electrode AND of each light-emitting element (LE). The PDL can separate a first emission region EA1, a second emission region EA2, and a third emission region EA3. Each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be a region in which the light-emitting element (LE) is disposed, including the first electrode AND, the light-emitting stack IL, and the second electrode CAT.

[0163] The first emission region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0164] The pixel-defining film (PDL) may include first pixel-defining films to third pixel-defining films PDL1, PDL2, and PDL3. The first pixel-defining film PDL1 may be disposed on the edge of the first electrode AND of each light-emitting element (LE), the second pixel-defining film PDL2 may be disposed on the first pixel-defining film PDL1, and the third pixel-defining film PDL3 may be disposed on the second pixel-defining film PDL2. The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 may be made of silicon oxide (SiO2). x Inorganic films of the type ) are formed. Alternatively, in one or more embodiments, the first pixel defining film PDL1 and the third pixel defining film PDL3 may be formed of silicon nitride (SiN). x Inorganic films of this type are formed, while the second pixel defining film PDL2 can be made of silicon oxide (SiO2). x ( ) Formation of inorganic films. The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 can each have a thickness of approximately 500 Å.

[0165] To prevent or reduce the likelihood of the first encapsulated inorganic film TFE1 breaking due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may have a cross-sectional structure with stepped portions. Step coverage refers to the ratio of the thickness (or amount) of the film formed on the inclined portion to the thickness (or amount) of the film formed on the flat portion. The lower the step coverage, the greater the likelihood that the film will break at the inclined portion.

[0166] Each of the multiple trench TRCs can penetrate the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3. The eleventh interlayer insulating film INS11 can be at least partially recessed at each of the multiple trench TRCs.

[0167] At least one trench TRC can be arranged between adjacent sub-pixels SP1, SP2, and SP3. Although Figure 9 Two trench TRCs are arranged between adjacent sub-pixels SP1, SP2 and SP3, but this disclosure is not limited thereto.

[0168] The light-emitting stack IL can include multiple stacked layers IL1, IL2 and IL3. Figure 9 An example of a light-emitting stack IL has a three-layer tandem structure including a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3, but this disclosure is not limited thereto. For example, the light-emitting stack IL may have, for example, a three-layer tandem structure including a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3. Figure 10 The diagram shows a dual-tandem structure comprising two stacked layers.

[0169] In a three-tiered structure, the light-emitting stack IL can have a series structure comprising multiple intermediate layers IL1, IL2, and IL3 that emit different lights. For example, the light-emitting stack IL may include a first stacked layer IL1 that emits a first light, a second stacked layer IL2 that emits a second light, and a third stacked layer IL3 that emits a third light. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 can be stacked sequentially.

[0170] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first light-emitting layer emitting first light, and a first electron transport layer are stacked sequentially. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second light-emitting layer emitting second light, and a second electron transport layer are stacked sequentially. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third light-emitting layer emitting third light, and a third electron transport layer are stacked sequentially.

[0171] A first charge-generating layer for supplying holes to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The first charge-generating layer may include an N-type charge-generating layer that supplies electrons to the first stacked layer IL1 and a P-type charge-generating layer that supplies holes to the second stacked layer IL2. The N-type charge-generating layer may include a dopant of a metallic material.

[0172] A second charge generation layer for supplying holes to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be disposed between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer that supplies electrons to the second stacked layer IL2 and a P-type charge generation layer that supplies holes to the third stacked layer IL3.

[0173] A first stacked layer IL1 may be disposed on the first electrode AND and the pixel defining film PDL, and a residual film RIL disposed on the bottom surface of each trench TRC may comprise the same material as the first stacked layer IL1. Due to the trench TRC, the first stacked layer IL1 may be disconnected between adjacent sub-pixels SP1, SP2, and SP3. A second stacked layer IL2 may be disposed on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 may be disconnected between adjacent sub-pixels SP1, SP2, and SP3. A cavity ESS or empty space may be disposed in the trench TRC between the residual film RIL and the second stacked layer IL2. A third stacked layer IL3 may be disposed on the second stacked layer IL2. The third stacked layer IL3 may not be disconnected by the trench TRC and may be disposed to cover the second stacked layer IL2 at each location (inside) the trench TRC.

[0174] In a three-series structure, each of the plurality of trench TRCs may be a structure for disconnecting the first hole transport layer to the third hole transport layer, the first charge generation layer, and the second charge generation layer of the first to third stacked layers IL1, IL2, and IL3 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3. In one or more embodiments, in a dual-series structure, each of the plurality of trench TRCs may be a structure for disconnecting the lower stacked layer and the charge generation layer disposed between the lower stacked layer and the upper stacked layer.

[0175] To ensure a stable disconnect between the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent sub-pixels SP1, SP2, and SP3, the height of each of the plurality of trench TRCs can be greater than the height of the pixel-defining film PDL. The height of each of the plurality of trench TRCs refers to the length of each of the plurality of trench TRCs in the third direction DR3. The height of the pixel-defining film PDL refers to the length of the pixel-defining film PDL in the third direction DR3. To ensure that the charge generation layer and hole transport layer of the light-emitting stack IL of the display element layer EML are disconnected between adjacent sub-pixels SP1, SP2, and SP3, different structures can exist to replace the trench TRCs. For example, instead of trench TRCs, inverted conical partition walls can be arranged on the pixel-defining film PDL.

[0176] In one or more embodiments, Figure 9 An illuminating stack IL is exemplified by emitting light in a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3, but this disclosure is not limited thereto. For example, instead of the illuminating stack IL, a first illuminating layer may be disposed in the first emitting region EA1 and may not be provided in the second emitting regions EA2 and the third emitting region EA3. Furthermore, a second illuminating layer may be disposed in the second emitting region EA2 and may not be provided in the first emitting region EA1 and the third emitting region EA3. Additionally, a third illuminating layer may be disposed in the third emitting region EA3 and may not be provided in the first emitting region EA1 and the second emitting region EA2. In such an embodiment, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL may not be provided.

[0177] The second electrode CAT can be disposed on the light-emitting stack IL. For example, the second electrode CAT can be disposed on the third stack layer IL3. The second electrode CAT can be formed of a transparent conductive oxide (TCO) capable of transmitting light (such as indium tin oxide (ITO) or indium zinc oxide (IZO)) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, the luminous efficiency can be improved in each of the first to third sub-pixels SP1, SP2, and SP3 due to the microcavity effect.

[0178] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic film TFE1 and TFE3 to prevent or reduce the possibility of oxygen or moisture penetrating into the display element layer EML. The first encapsulation inorganic film TFE1 can be disposed on the second electrode CAT, and the second encapsulation inorganic film TFE3 can be disposed above the first encapsulation inorganic film TFE1. The first encapsulation inorganic film TFE1 and / or the second encapsulation inorganic film TFE3 can be made of silicon nitride (SiN). x ) layer, silicon oxynitride (SiON) layer, silicon oxide (SiO) layer x ) layer, titanium dioxide (TiO) x ) layer and / or alumina (AlO) x Multilayer formation is formed by alternating stacking of two or more inorganic layers in a layer.

[0179] In one or more embodiments, the encapsulation layer TFE may include at least one organic film TFE2 to protect the display element layer EML from foreign matter such as dust. The encapsulation organic film TFE2 may be disposed between a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE3. The encapsulation organic film TFE2 may be a monomer. In one or more embodiments, the encapsulation organic film TFE2 may be an organic film comprising, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0180] The adhesive layer ADL can be a layer used to bond the encapsulation layer TFE to the optical layer OPL. The adhesive layer ADL can be a double-sided adhesive member. In one or more embodiments, the adhesive layer ADL can be a transparent adhesive member, such as a transparent adhesive or a transparent adhesive resin.

[0181] The optical layer OPL includes multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 may be arranged on the adhesive layer ADL.

[0182] The first color filter CF1 can overlap with the first emission region EA1 of the first sub-pixel SP1. The first color filter CF1 can be used to transmit light of a first color, namely, light in the blue wavelength band. The blue wavelength band can be the wavelength band of light whose main peak wavelength is in the range of about 370 nm to about 460 nm. Therefore, the first color filter CF1 can be used to transmit light of the first color emitted from the first emission region EA1.

[0183] The second color filter CF2 can overlap with the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can be used to transmit light of a second color, namely, light in the green wavelength band. The green wavelength band can be the wavelength band of light whose main peak wavelength is in the range of about 480 nm to about 560 nm. Therefore, the second color filter CF2 can be used to transmit light of the second color emitted from the second emission region EA2.

[0184] The third color filter CF3 can overlap with the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can be used to transmit light of the third color, that is, light in the red wavelength band. The red wavelength band can be the wavelength band of light whose main peak wavelength is in the range of about 600 nm to about 750 nm. Therefore, the third color filter CF3 can be used to transmit light of the third color emitted from the third emission region EA3.

[0185] Multiple lenses LNS can be arranged on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the multiple lenses LNS can be a structure for increasing the proportion of light directed in front of the display device 10. Each of the multiple lenses LNS can have a cross-sectional shape that convexes in the upward direction.

[0186] A filler layer (FIL) can be disposed on multiple lenses (LNS). The filler layer (FIL) can have a set or predetermined refractive index such that light travels in the third direction (DR3) at the interface between the filler layer (FIL) and the multiple lenses (LNS). Furthermore, the filler layer (FIL) can be a planarization layer. The filler layer (FIL) can be an organic film comprising, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0187] A cover layer CVL can be disposed on a filler layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it can be attached to the filler layer FIL. In such embodiments, the filler layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. When the cover layer CVL is a polymer resin, it can be directly applied to the filler layer FIL.

[0188] A polarizer (POL) can be disposed on one surface of the CVL (container layer). The polarizer POL can be a structure used to reduce or prevent visibility degradation caused by reflection of external light. The polarizer POL can include a linear polarizer and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but this disclosure is not limited thereto. However, if the visibility degradation caused by reflection of external light is sufficiently overcome by the first to third color filters CF1, CF2, and CF3, a polarizer may not be provided (e.g., when the visibility degradation caused by reflection of external light is sufficiently overcome by the first to third color filters CF1, CF2, and CF3, a polarizer may not be provided).

[0189] Figure 10 It is according to one or more embodiments of this disclosure along Figure 7 A schematic cross-sectional view of the display panel taken by line I1-I1'.

[0190] Figure 10 Implementation examples and Figure 9 The difference in the embodiment is that the first electrode AND of each light-emitting element LE is in contact with and electrically connected to the side surface of the connection electrode ANC connected to the eighth conductive layer ML8. Figure 10 Implementation examples and Figure 9 The embodiment also differs in that the trench TRC is omitted, and instead, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 have an eaves-shaped or mushroom-shaped cross-sectional structure. Figure 10 In some embodiments, it may not be necessary to provide references to the already referenced Figure 9 Redundant descriptions in the descriptive section.

[0191] refer to Figure 10 Multiple connecting electrodes ANC can be respectively arranged on the first portion AA1 of the ninth interlayer insulating film INS9. Each of the multiple connecting electrodes ANC can be arranged on its corresponding first portion AA1 of the ninth interlayer insulating film INS9. The multiple connecting electrodes ANC can be formed of any one or more alloys or transparent conductive oxides of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the multiple connecting electrodes ANC may include titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but this disclosure is not limited thereto.

[0192] Multiple reflective electrodes RL can be arranged on multiple connecting electrodes ANC. Each of the multiple reflective electrodes RL can be arranged on its corresponding connecting electrode ANC. The multiple reflective electrodes RL can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising one or more of these. For example, each of the multiple reflective electrodes RL may include aluminum (Al) with high reflectivity.

[0193] Multiple optical auxiliary films (OALs) can be disposed on multiple reflective electrodes (RLs). Each of the multiple optical auxiliary films (OALs) can be disposed on its corresponding reflective electrode (RL). The multiple optical auxiliary films (OALs) can be made of silicon oxide (SiO2). x Inorganic membranes can be formed, but this disclosure is not limited thereto.

[0194] In each of the first emission region EA1 and the third emission region EA3, a stepped layer STPL can be disposed on the reflective electrode RL, and an optical auxiliary film OAL can be disposed on the stepped layer STPL. In the second emission region EA2, only the optical auxiliary film OAL can be disposed on the reflective electrode RL. In the first emission region EA1, the second emission region EA2, and the third emission region EA3, the thickness of the optical auxiliary film OAL can be substantially the same.

[0195] Due to the stepped layer STPL, the distance between the reflective electrode RL and the first electrode AND in the third emission region EA1 and the third emission region EA3 along the third direction DR3 can be greater than the distance between the reflective electrode RL and the first electrode AND in the second emission region EA2 along the third direction DR3. The thickness of the stepped layer STPL and the thickness of the optical auxiliary film OAL can be determined by considering the wavelength and resonant distance of the light emitted from the first stacked layer IL1 of the light-emitting stack IL and the wavelength and resonant distance of the light emitted from the second stacked layer IL2 of the light-emitting stack IL.

[0196] Each light-emitting element LE may include a first electrode AND, a light-emitting stack IL, and a second electrode CAT.

[0197] The first electrode AND of each light-emitting element LE can be disposed on its corresponding optical auxiliary film OAL. Because the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL are stacked sequentially, the first electrode AND of each light-emitting element LE can be disposed on the top and side surfaces of the optical auxiliary film OAL, the side surface of the reflective electrode RL, and the side surface of the connecting electrode ANC. Accordingly, the first electrode AND of each light-emitting element LE can contact and be electrically connected to the side surfaces of the reflective electrode RL and the connecting electrode ANC. Therefore, compared to connecting the first electrode AND of each light-emitting element LE to the reflective electrode RL exposed through a through-hole penetrating the optical auxiliary film OAL, the number of masking processes can be reduced, thereby reducing manufacturing costs and increasing manufacturing efficiency.

[0198] The first electrode AND of each light-emitting element LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the connecting electrode ANC, the first through hole VA1 to the ninth through hole VA9, the first conductive layer ML1 to the eighth conductive layer ML8 and the contact terminal CTE.

[0199] The ninth interlayer insulating film INS9 may include a first portion AA1 that overlaps with the connecting electrode ANC on the third-direction DR3, and a second portion AA2 that does not overlap with the connecting electrode ANC on the third-direction DR3. The thickness of the first portion AA1 and the thickness of the second portion AA2 of the ninth interlayer insulating film INS9 may be substantially the same.

[0200] Alternatively, in one or more embodiments, the thickness of the first portion AA1 of the ninth interlayer insulating film INS9 may be greater than the thickness of the second portion AA2 of the ninth interlayer insulating film INS9. In such an embodiment, the side surface of the first portion AA1 of the ninth interlayer insulating film INS9 may be exposed, and the first electrode AND of each light-emitting element LE may be disposed on the exposed side surface of the first portion AA1 of the ninth interlayer insulating film INS9.

[0201] The first electrode AND of each light-emitting element LE can be formed of any one or more alloys or transparent conductive oxides of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd). For example, the first electrode AND of each light-emitting element LE may include titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but this disclosure is not limited thereto.

[0202] A pixel-defining film (PDL) can be disposed on a portion of the first electrode AND of each light-emitting element (LE). The PDL can cover the edge of the first electrode AND of each light-emitting element (LE). The PDL can separate a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3.

[0203] The pixel-limiting film (PDL) may include the first pixel-limiting film to the fourth pixel-limiting film, PDL1, PDL2, PDL3 and PDL4.

[0204] The first pixel defining film PDL1 can be disposed on the first electrode AND of each light-emitting element LE. For example, the first pixel defining film PDL1 can cover a portion of the top surface of the portion of the first electrode AND disposed on the optical auxiliary film OAL. Further, the first pixel defining film PDL1 can cover the portion of the first electrode AND disposed on the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The first pixel defining film PDL1 can be disposed on the top surface of the second portion AA2 of the ninth interlayer insulating film INS9.

[0205] The planarization film PNS is a film used to planarize the stepped portions caused by the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL.

[0206] The planarization film PNS can be disposed on a portion of the first pixel defining film PDL1 covering the first electrode AND disposed on the side surface of the connecting electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The planarization film PNS can also be disposed on a portion of the first pixel defining film PDL1 disposed on the second portion AA2 of the ninth interlayer insulating film INS9.

[0207] The planarization film PNS can be disposed between adjacent connecting electrodes ANC on the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent reflecting electrodes RL on the first direction DR1 or the second direction DR2. The planarization film PNS can be disposed between adjacent optical auxiliary films OAL on the first direction DR1 or the second direction DR2.

[0208] The step layer STPL may not be present in the second emission region EA2, while the step layer STPL may be present in each of the first emission region EA1 and the third emission region EA3. Accordingly, the height of the connecting electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL in the second emission region EA2 may be less than the height of the connecting electrode ANC, the reflective electrode RL, the step layer STPL, and the optical auxiliary film OAL in the first emission region EA1 and the third emission region EA3. Therefore, the planarization film PNS may cover the top surface of the portion of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND disposed in the second emission region EA2.

[0209] In contrast, the top surface of the planarization film PNS can be flatly connected to the top surface of the portion of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND disposed in the first emission region EA1 and the third emission region EA3. For example, the planarization film PNS may not cover the top surface of the portion of the first pixel defining film PDL1 disposed on the top surface of the first electrode AND disposed in each of the first emission region EA1 and the third emission region EA3.

[0210] The second pixel-defining film PDL2 can be disposed on the first pixel-defining film PDL1 and the planarization film PNS, the third pixel-defining film PDL3 can be disposed on the second pixel-defining film PDL2, and the fourth pixel-defining film PDL4 can be disposed on the third pixel-defining film PDL3. The first pixel-defining film PDL1 and the third pixel-defining film PDL3 can be made of silicon nitride (SiN). x Inorganic films of this type are formed, while the second pixel defining film PDL2, the fourth pixel defining film PDL4, and the planarization film PNS can be formed from silicon oxide (SiO2). x ( ) Formation of an inorganic film. The first pixel defining film PDL1 is formed of a material different from that of the planarization film PNS, and therefore can be used as a stop in the chemical mechanical polishing process used for the planarization film PNS.

[0211] When the planarization film PNS and the second pixel-defining film PDL2 are both made of silicon oxide (SiO) x When an inorganic film is formed, the planarization film PNS and the second pixel-defining film PDL2 can be formed as a single film.

[0212] Because the length of the third pixel defining film PDL3 in one direction is less than the length of the fourth pixel defining film PDL4 in one direction, a portion of the bottom surface of the fourth pixel defining film PDL4 can be exposed and not covered by the third pixel defining film PDL3. For example, the third pixel defining film PDL3 and the fourth pixel defining film PDL4 can have an eaves-like or mushroom-shaped cross-sectional structure.

[0213] The light-emitting stack IL can be disposed on the first electrode AND and the pixel defining film PDL. The light-emitting stack IL can include a first stacked layer IL1 and a second stacked layer IL2 that emit different lights. When the light-emitting stack IL has a dual-tandem structure, one of the first stacked layer IL1 and the second stacked layer IL2 can be used to emit light within the wavelength range of any one of the first light, the second light, and the third light, and the other can be used to emit light within the wavelength range of the other two light sources. For example, the first stacked layer IL1 can be used to emit light within the wavelength range of the first light and the wavelength range of the third light, and the second stacked layer IL2 can be used to emit light within the wavelength range of the second light. Here, the first light can be light in the blue wavelength band, the second light can be light in the green wavelength band, and the third light can be light in the red wavelength band.

[0214] A charge-generating layer for supplying holes to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The charge-generating layer may include an N-type charge-generating layer that supplies electrons to the first stacked layer IL1 and a P-type charge-generating layer that supplies holes to the second stacked layer IL2. The N-type charge-generating layer may include a dopant of a metallic material.

[0215] The first stacked layer IL1 is not formed on the bottom surface of the exposed portion of the fourth pixel defining film PDL4 that is not covered by the third pixel defining film PDL3, and therefore can be disconnected through the eaves-like or mushroom-shaped cross-sectional structure of the third pixel defining film PDL3 and the fourth pixel defining film PDL4. In such an embodiment, the first hole transport layer of the first stacked layer IL1 and the charge generation layer disposed between the first stacked layer IL1 and the second stacked layer IL2 can also be disconnected. Furthermore, although Figure 10 For example, the second stacked layer IL2 is connected and not disconnected, but the second hole transport layer of the second stacked layer IL2 can be disconnected, and the second electron transport layer of the second stacked layer IL2 can be connected and not disconnected. Therefore, it is possible to prevent or reduce leakage current flowing between adjacent emitting regions EA1, EA2, and EA3 through the first hole transport layer of the first stacked layer IL1, the second hole transport layer of the second stacked layer IL2, and the charge generation layer. Accordingly, it is possible to prevent or reduce the possibility that the light-emitting stacks IL in adjacent emitting regions EA1, EA2, and EA3 will emit light other than the originally intended light due to the influence of the above current.

[0216] although Figure 10 The example illustrates a dual-tandem structure where the light-emitting stack IL comprises two stacked layers IL1 and IL2, but this disclosure is not limited thereto. For example, the light-emitting stack IL may have, for instance, a dual-tandem structure where the light-emitting stack IL comprises two stacked layers IL1 and IL2. Figure 9The diagram shows a three-tiered structure comprising three stacked layers. In such an embodiment, it can be designed such that the charge-generating layers between the first stacked layer IL1 and the second stacked layer IL2, and between the second stacked layer IL2 and the third stacked layer IL3, are disconnected by adjusting the height of the third pixel-defining film PDL3. Alternatively, in one or more embodiments, as shown... Figure 9 As shown, a trench TRC that penetrates the first pixel defining film PDL1, the planarization film PNS, the second pixel defining film PDL2, and the third pixel defining film PDL3 can be added. In such an embodiment, the trench TRC can penetrate at least a portion of the ninth interlayer insulating film INS9, but this disclosure is not limited thereto.

[0217] Figure 11 It is according to one or more embodiments of this disclosure along Figure 7 A schematic cross-sectional view of the display panel taken by line I1-I1'.

[0218] Figure 11 Implementation examples and Figure 10 The difference in the embodiments is that the light-emitting element LE has a single stacked structure. Figure 11 In some embodiments, it may not be necessary to provide references to the already referenced Figure 10 Redundant descriptions in the descriptive section.

[0219] refer to Figure 11 The pixel-defining film (PDL) can be disposed on the ninth interlayer insulating film (INS9) and the first electrode AND, and the planarization film (PNS) can be disposed on the pixel-defining film (PDL). The planarization film PNS and the pixel-defining film (PDL) can have openings exposing the first electrode AND, and the light-emitting stack (IL) can be disposed on the first electrode AND. For example, the pixel-defining film (PDL) can have openings exposing the first electrode AND in the first emission region EA1, the second emission region EA2, and the third emission region EA3, and the planarization film PNS can have an opening exposing the first electrode AND in the second emission region EA2. The first electrode AND can be exposed by the planarization film PNS in the first emission region EA1 and the third emission region EA3 because the height of the planarization film PNS on the third-direction DR3 may not be high enough to cover the top surface of the first electrode AND in the first emission region EA1 and the third emission region EA3.

[0220] For example, the light-emitting stack IL may include a first stack layer IL1_1, a second stack layer IL1_2, and a third stack layer IL1_3.

[0221] The first stacked layer IL1_1 may be disposed in the first emission region EA1 on the first electrode AND exposed through the pixel-defining film PDL. The first stacked layer IL1_1 may also be disposed on a portion of the pixel-defining film PDL. For example, the first stacked layer IL1_1 may include a hole injection layer, a hole transport layer, a first light-emitting layer, an electron transport layer, and an electron injection layer.

[0222] The second stacked layer IL1_2 can be disposed in the second emission region EA2 on the first electrode AND exposed through the planarization film PNS and the pixel defining film PDL. The second stacked layer IL1_2 can also be disposed on a portion of the planarization film PNS. For example, the second stacked layer IL1_2 may include a hole injection layer, a hole transport layer, a second light-emitting layer, an electron transport layer, and an electron injection layer.

[0223] The third stacked layer IL1_3 can be disposed in the third emission region EA3 on the first electrode AND exposed through the pixel-defining film PDL. The third stacked layer IL1_3 can also be disposed on a portion of the pixel-defining film PDL. For example, the third stacked layer IL1_3 may include a hole injection layer, a hole transport layer, a third light-emitting layer, an electron transport layer, and an electron injection layer.

[0224] The first stacked layer IL1_1, the second stacked layer IL1_2, and the third stacked layer IL1_3 can be spaced apart and / or separated from each other (e.g., spaced apart or separated), and therefore may not require the provision of a method for... Figure 10 In the embodiments, the second to fourth pixel defining films PDL2, PDL3 and PDL4 of the light-emitting stack IL are separated.

[0225] The first stacked layer IL1_1 in the first emission region EA1 can be used to emit a first light, the second stacked layer IL1_2 in the second emission region EA2 can be used to emit a second light, and the third stacked layer IL1_3 in the third emission region EA3 can be used to emit a third light. Accordingly, it is not necessary to provide... Figure 9 The embodiments use optical layers OPL with first to third color filters CF1, CF2 and CF3, multiple lenses LNS and filler layer FIL.

[0226] Figure 12 This is a schematic perspective view of a head-mounted display according to one or more embodiments of the present disclosure. Figure 13 It is based on one or more embodiments of this disclosure Figure 12 A schematic exploded perspective view of a head-mounted display.

[0227] refer to Figure 12 and Figure 13A head-mounted display 1000 according to one or more embodiments includes a first display device 20_1, a second display device 20_2, a display device housing 1100, a housing cover 1200, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0228] The first display device 20_1 provides an image to the user's left eye, and the second display device 20_2 provides an image to the user's right eye. This is because each of the first display device 20_1 and the second display device 20_2 is combined with... Figures 3 to 11 The display devices 20 described are substantially the same, so a description of the first display device 20_1 and the second display device 20_2 is not required.

[0229] The first optical component 1510 may be disposed between the first display device 20_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 20_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0230] The intermediate frame 1400 can be arranged between the first display device 20_1 and the control circuit board 1600, and between the second display device 20_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 20_1, the second display device 20_2, and the control circuit board 1600.

[0231] The control circuit board 1600 can be arranged between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 20_1 and the second display device 20_2 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data DATA, and transmit the digital video data DATA to the first display device 20_1 and the second display device 20_2 via connectors.

[0232] The control circuit board 1600 can be used to transmit digital video data DATA corresponding to a left-eye image improved or optimized for the user's left eye to a first display device 20_1, and can be used to transmit digital video data DATA corresponding to a right-eye image improved or optimized for the user's right eye to a second display device 20_2. Alternatively, in one or more embodiments, the control circuit board 1600 can be used to transmit the same digital video data DATA to both the first display device 20_1 and the second display device 20_2.

[0233] The display device housing 1100 is used to house the first display device 20_1, the second display device 20_2, the intermediate frame 1400, the first optical component 1510, the second optical component 1520, and the control circuit board 1600. A housing cover 1200 is arranged to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 12 and Figure 13 The first eyepiece 1210 and the second eyepiece 1220 are arranged separately, but this disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0234] The first eyepiece 1210 can be aligned with the first display device 20_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 20_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 20_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 20_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0235] A headband 1300 is used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are positioned over the user's left and right eyes, respectively. When the display device housing 1100 is implemented to be lightweight and compact, such as... Figure 14 As shown, instead of the headband 1300, the head-mounted display 1000 can be provided with an eyeglass frame.

[0236] Figure 14 This is a schematic perspective view of a head-mounted display according to one or more embodiments of the present disclosure.

[0237] refer to Figure 14 The head-mounted display 1000_1 according to one or more embodiments may be an eyeglass-type (or similar) display device, wherein the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to one or more embodiments may include a display device 20_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, a light path alteration component 1070, and a display device housing 1200_1.

[0238] The display device housing 1200_1 can accommodate the display device 20_3, the optical component 1060, and the light path changing component 1070. The image displayed on the display device 20_3 can be magnified by the optical component 1060 and, after its light path is changed by the light path changing component 1070, provided to the user's right eye through the right eye lens 1020. As a result, the user can view the augmented reality image through their right eye, where the virtual image displayed on the display device 20_3 is combined with the real image seen through the right eye lens 1020.

[0239] Figure 14 The display device housing 1200_1 is exemplified as being located at the right end of the support frame 1030, but this disclosure is not limited thereto. For example, the display device housing 1200_1 may be located at the left end of the support frame 1030, and in such an embodiment, the image displayed on the display device 20_3 can be provided to the user's left eye. Alternatively, in one or more embodiments, the display device housing 1200_1 may be located at both the left and right ends of the support frame 1030, and in such an embodiment, the user can view the image displayed on the display device 20_3 through both the left and right eyes.

[0240] Figure 15 This is a schematic diagram illustrating a deposition mask and a deposition apparatus including a deposition mask according to one or more embodiments of the present disclosure.

[0241] refer to Figure 15 The deposition apparatus 2000 according to one or more embodiments can be used to form a deposition material layer on a substrate. For example, the deposition apparatus 2000 according to one or more embodiments can be used to deposit a layer of material on a display panel 100 (e.g., see...). Figure 3 In the manufacturing process of [the material], a light-emitting layer is formed on the substrate (or display substrate) 3000. For example, such as... Figure 11 The semiconductor substrate SBP and the light-emitting element substrate EBP shown can be located on the substrate 3000, and the electrode pattern (e.g., the first electrode used as the anode electrode AND (e.g., see...) Figure 11 The pixel-defining film (PDL) can be located on the light-emitting element substrate EBP. In one or more embodiments, the pixel-defining film (PDL) has an opening that exposes the first electrode AND (e.g., see...). Figure 11 The light-emitting layer can be located on the substrate EBP of the light-emitting element. As an example, the deposition apparatus 2000 can form a first light-emitting layer on the first electrode AND in the first emission region EA1. The deposition apparatus 2000 can form a second light-emitting layer on the first electrode AND in the second emission region EA2. The deposition apparatus 2000 can form a third light-emitting layer on the first electrode AND in the third emission region EA3.

[0242] The deposition apparatus 2000 may include a deposition source 2200 for providing vapor deposition material on a substrate 3000, a substrate chuck 2300 for supporting the substrate 3000 facing the deposition source 2200, and a mask chuck 2400 located between the deposition source 2200 and the substrate chuck 2300 to support a deposition mask 4000 facing the substrate 3000. The deposition source 2200, the substrate chuck 2300, and the mask chuck 2400 may be located in a process chamber (or evaporation chamber) 2100.

[0243] The process chamber 2100 may have an internal space, and the deposition process for forming a deposition material layer on the substrate 3000 can be performed within the internal space of the process chamber 2100. The process chamber 2100 may be connected to a vacuum pump, and a vacuum atmosphere may be generated within the internal space of the process chamber 2100 by the vacuum pump. An opening for loading / unloading the substrate 3000 and the deposition mask 4000 may be provided on a wall of the process chamber 2100, and this opening may be opened and closed by a gate valve.

[0244] The deposition source 2200 can be located in the process chamber 2100, and the deposition material can be stored in the deposition source 2200. The deposition source 2200 can evaporate deposition materials such as organic materials, inorganic materials, and conductive materials toward the substrate 3000, and the evaporated deposition material can be deposited onto the substrate 3000 through a deposition mask 4000. For example, the deposition source 2200 can evaporate organic light-emitting materials for forming a light-emitting layer on the substrate 3000, and can be provided with a heater for evaporating the organic light-emitting material. The evaporated organic light-emitting material can be deposited onto an electrode pattern on the substrate 3000 through the deposition mask 4000, thereby forming a light-emitting layer on the electrode pattern of the substrate 3000. Figure 15 As shown, the deposition source 2200 may be located on the central portion of the bottom surface of the process chamber 2100, but the deposition source 2200 may be configured to move horizontally by a separate drive.

[0245] The substrate chuck 2300 can be located above the deposition source 2200 and can support the substrate 3000 such that the substrate 3000 faces the deposition source 2200. For example, the substrate chuck 2300 can be an electrostatic chuck that uses electrostatic force to hold the rear surface of the substrate 3000. For example, the electrode pattern (e.g., the first electrode AND) can be located on the front surface of the substrate 3000, and the substrate chuck 2300 can hold the rear surface of the substrate 3000 such that the front surface of the substrate 3000 faces downward, i.e., towards the deposition source 2200.

[0246] Multiple lifting fingers 2350 for loading the base plate substrate 3000 onto the substrate chuck 2300 can be arranged in the process chamber 2100. The lifting fingers 2350 can be arranged around the substrate chuck 2300 and the mask chuck 2400, and can be moved vertically by finger drivers 2360 respectively. For example, three or four lifting fingers 2350 can be arranged around the substrate chuck 2300 and the mask chuck 2400, and can be moved in a third direction DR3 by the finger drivers 2360.

[0247] The base plate substrate 3000 can be loaded into the process chamber 2100 by a transfer robot and then transferred from the transfer robot to the lifting finger 2350 below the substrate chuck 2300. In this embodiment, the rear surface of the base plate substrate 3000 can face the bottom surface of the substrate chuck 2300, and the lifting finger 2350 can support the front edge portion of the base plate substrate 3000. The finger driver 2360 can raise the lifting finger 2350 so that the base plate substrate 3000 is adjacent to the bottom surface of the substrate chuck 2300, and the rear surface of the base plate substrate 3000 can be held on the bottom surface of the substrate chuck 2300 by electrostatic force.

[0248] A finger actuator 2360 may be disposed on the upper cover of the process chamber 2100 and may be connected to a lifting finger 2350 via a drive shaft 2362 extending vertically through the upper cover of the process chamber 2100. The finger actuator 2360 may vertically move the lifting finger 2350 to load or unload the base plate substrate 3000. In one or more embodiments, the finger actuator 2360 may rotate the lifting finger 2350 relative to each of the drive shafts 2362. For example, the finger actuator 2360 may rotate the lifting finger 2350 such that the end of the lifting finger 2350 does not overlap with the base plate chuck 2300 and the mask chuck 2400, thereby enabling vertical movement of the lifting finger 2350. In one or more embodiments, the finger actuator 2360 may rotate the lifting finger 2350 such that the end of the lifting finger 2350 overlaps with an edge portion of the base plate substrate 3000 to support the edge portion of the base plate substrate 3000.

[0249] The deposition mask 4000 can be loaded into the process chamber 2100 via a transfer robot and can be transferred to a lifting finger 2350 above the mask chuck 2400. An edge portion of the deposition mask 4000 can be positioned on the end of the lifting finger 2350, and a finger actuator 2360 can lower the lifting finger 2350 to load the deposition mask 4000 onto the mask chuck 2400. In such an embodiment, a recess into which the end of the lifting finger 2350 is inserted can be provided at the edge portion of the mask chuck 2400, and the finger actuator 2360 can rotate the lifting finger 2350 after the deposition mask 4000 is loaded onto the mask chuck 2400, so that the lifting finger 2350 does not overlap with the mask chuck 2400.

[0250] The mask chuck 2400 can support the edge portion of the deposition mask 4000. For example, the mask chuck 2400 can be an electrostatic chuck configured to hold the edge portion of the deposition mask 4000 using electrostatic force. In particular, the mask chuck 2400 can have a circular opening to expose the deposition mask 4000 toward the deposition source 2200. For example, the mask chuck 2400 can have a disk shape or a quadrilateral plate shape with a circular opening.

[0251] The deposition apparatus 2000 may include chuck drivers for adjusting the position and angle of the substrate 3000 and the deposition mask 4000. For example, the deposition apparatus 2000 may include a substrate chuck driver 2500 for moving the substrate chuck 2300 and a mask chuck driver 2600 for moving the mask chuck 2400.

[0252] The substrate chuck driver 2500 can move the substrate chuck 2300 in a first direction DR1, a second direction DR2, and a third direction DR3 to adjust the position of the base plate substrate 3000. In such an embodiment, the first direction DR1 can be a first horizontal direction, the second direction DR2 can be a second horizontal direction orthogonal to (e.g., perpendicular to) the first direction DR1, and the third direction DR3 can be a vertical direction. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be the X-axis direction, the Y-axis direction, and the Z-axis direction, respectively.

[0253] The base plate chuck driver 2500 can rotate the base plate chuck 2300 about the Z-axis to adjust the azimuth angle of the base plate 3000, that is, the angle at which the base plate 3000 is held on the bottom surface of the base plate chuck 2300. Furthermore, the base plate chuck driver 2500 can rotate the base plate chuck 2300 about the X-axis and also about the Y-axis to adjust the tilt of the base plate 3000. For example, the base plate chuck driver 2500 may include a hexapod actuator 2510 that provides six degrees of freedom (X, Y, Z, θx, θy, and θz).

[0254] The substrate chuck driver 2500 may include a substrate stage 2520 and a second actuator 2530 connected to the substrate stage 2520, with a hexapod actuator 2510 mounted on the substrate stage 2520. The substrate stage 2520 may be horizontally located in the process chamber 2100, and the second actuator 2530 may be located above the process chamber 2100. The second actuator 2530 may be connected to the substrate stage 2520 via a plurality of drive shafts 2532 extending through the upper cover of the process chamber 2100 in a third direction DR3 (i.e., the vertical direction (Z-axis direction)), and may move the substrate stage 2520 in the direction of the central axis of the hexapod actuator 2510 (i.e., the vertical direction). For example, the second actuator 2530 may be configured using a brushless DC motor, a linear motor, a direct drive (DD) motor, etc., and the height of the substrate chuck 2300 may be adjusted to load or unload the baseboard substrate 3000.

[0255] The hexa-legged actuator 2510 may include: a first platform connected to the base plate chuck 2300; a second platform mounted on the base plate stage 2520; and six sub-actuators located between the first and second platforms. For example, the six sub-actuators may each be configured using a brushless DC motor, a voice coil linear motor, a stepper motor, a direct drive (DD) motor, a servo motor, etc., and may enable the first platform to move and rotate to adjust the horizontal position, vertical position, azimuth angle, and tilt of the base plate 3000.

[0256] The mask chuck driver 2600 can move and rotate the mask chuck 2400 to adjust the horizontal position and azimuth angle of the deposition mask 4000, i.e., the angle at which the deposition mask 4000 is positioned on the mask chuck 2400. The mask chuck driver 2600 can move the mask chuck 2400 in a direction parallel to the deposition mask 4000 and rotate the mask chuck 2400 relative to its central axis. For example, the mask chuck driver 2600 can move the mask chuck 2400 in a first direction DR1 (X-axis) and a second direction DR2 (Y-axis), and can rotate the mask chuck 2400 relative to a third direction DR3 (Z-axis).

[0257] The mask chuck driver 2600 may include, for example, a piezoelectric actuator 2610 that provides motion in three degrees of freedom (X, Y, and θz). The piezoelectric actuator 2610 may have an opening communicating with a circular opening of the mask chuck 2400. The mask chuck 2400 may be spaced upwards from the piezoelectric actuator 2610 by a selected distance. For example, a plurality of support members 2612 may be arranged on the piezoelectric actuator 2610, and the mask chuck 2400 may be located on the plurality of support members 2612.

[0258] The mask chuck driver 2600 may include a mask stage 2620, which is horizontally located in the process chamber 2100 and supports the piezoelectric actuator 2610. For example, the mask stage 2620 may have an opening communicating with the opening of the piezoelectric actuator 2610 and may be supported by a plurality of posts 2622 connected to the upper cover of the process chamber 2100.

[0259] After the substrate 3000 and deposition mask 4000 are mounted onto the substrate chuck 2300 and mask chuck 2400, respectively, the second actuator 2530 can lower the substrate chuck 2300, thereby bringing the substrate 3000 adjacent to the deposition mask 4000. The hexapod actuator 2510 can adjust the gap between the substrate 3000 and the deposition mask 4000, and can adjust the tilt of the substrate chuck 2300 to adjust the parallelism between the substrate chuck 2300 and the mask chuck 2400. For example, multiple gap sensors for measuring the gap between the substrate chuck 2300 and the mask chuck 2400 can be mounted on the substrate chuck 2300, and the hexapod actuator 2510 can adjust the parallelism between the substrate chuck 2300 and the mask chuck 2400 based on the measurements from the gap sensors.

[0260] The deposition apparatus 2000 may include a camera 2700 for acquiring positional information of the substrate 3000 and the deposition mask 4000, for alignment between the substrate 3000 and the deposition mask 4000. For example, a substrate alignment key 3300 (see, for example, see...) Figure 16The mask can be arranged on the edge portion of the base plate 3000, and the mask alignment key 4600 (e.g., see...) Figure 17 The substrate 3000 and the deposition mask 4000 can be arranged on the edge portion of the deposition mask 4000. The deposition apparatus 2000 may include a camera 2700 for detecting the substrate alignment key 3300 and the mask alignment key 4600, and the substrate chuck driver 2500 or the mask chuck driver 2600 may align the substrate 3000 and the deposition mask 4000 with each other based on the position information of the substrate alignment key 3300 and the mask alignment key 4600 obtained by the camera 2700.

[0261] As described above, after adjusting the parallelism between the substrate chuck 2300 and the mask chuck 2400 and aligning the base substrate 3000 and the deposition mask 4000, the base substrate 3000 can be positioned on the deposition mask 4000. For example, the hexapod actuator 2510 can adjust the height of the substrate chuck 2300 such that the gap between the base substrate 3000 and the deposition mask 4000 becomes a selected gap, for example, a gap of several μm. In another example, the hexapod actuator 2510 can adjust the height of the substrate chuck 2300 so that the base substrate 3000 contacts the deposition mask 4000.

[0262] After positioning the substrate 3000 on the deposition mask 4000, the deposition source 2200 can provide vapor-phase deposition material onto the substrate 3000 through the deposition mask 4000, thereby forming a deposition material layer on the substrate 3000. For example, the deposition source 2200 can provide vapor-phase light-emitting material for forming a light-emitting layer on the substrate 3000, and the vapor-phase light-emitting material can pass through the pixel opening 4310 of the deposition mask 4000 (e.g., see...). Figure 18 The electrode pattern is deposited on the substrate 3000.

[0263] Figure 16 This illustrates one or more embodiments according to the present disclosure. Figure 15 A schematic bottom view of the base plate substrate.

[0264] refer to Figure 16 The base plate substrate 3000 may include multiple display unit areas 3100 and cutting channel areas 3200 located between the display unit areas 3100. For example... Figure 16 As shown, the display unit area 3100 can be arranged in a matrix along the first direction DR1 and the second direction DR2, and can be individualized into the display panel 100 by a dicing process after the display manufacturing process is completed (e.g., see...). Figure 3(For example, after the display manufacturing process is completed, the display unit area 3100 can be divided into individual display panels 100 by a dicing process.) For example, the first direction DR1 can be a first horizontal direction, and the second direction DR2 can be a second horizontal direction orthogonal (e.g., perpendicular) to the first direction DR1. In one or more embodiments, as shown in the figures, each display unit area 3100 can have, for example, a quadrilateral shape.

[0265] For example, each display unit area 3100 may include, for example, Figure 11 The semiconductor substrate SBP and the light-emitting element substrate EBP located on the semiconductor substrate SBP are shown. In one or more embodiments, multiple electrode patterns (e.g., multiple first electrodes AND (e.g., see...)) are used. Figure 11 The pixel defining film (PDL) can be located on the light-emitting element substrate EBP, and has an opening exposing the first electrode AND can be located on the light-emitting element substrate EBP and the first electrode AND. In such an embodiment, the electrode pattern of the display unit region 3100 can be arranged on the front surface of the substrate 3000, and the substrate chuck 2300 can hold the rear surface of the substrate 3000 such that the electrode pattern of the display unit region 3100 faces downward, i.e., facing the deposition source 2200.

[0266] According to one or more embodiments, the substrate 3000 may include substrate alignment keys 3300. For example, the substrate alignment keys 3300 may be located on one or more edge portions of the substrate 3000 and may be used for positional alignment between the substrate 3000 and the deposition mask 4000. Figure 16 As shown, two substrate alignment keys 3300 are used, but the number of substrate alignment keys 3300 can be varied, and the scope of this disclosure is not limited to a specific number of substrate alignment keys 3300.

[0267] Figure 17 This illustrates one or more embodiments according to the present disclosure. Figure 15 A schematic plan view of the deposition mask. Figure 18 This illustrates one or more embodiments according to the present disclosure. Figure 17 A schematic plan view of the diaphragm is shown in the figure. Figure 19 It is according to one or more embodiments of this disclosure along Figure 18 A schematic cross-sectional view of the line I2-I2'.

[0268] refer to Figures 17 to 19 The deposition mask 4000 may include display unit areas 3100 (see below) of the substrate 3000. Figure 16The corresponding diaphragm 4300 and the grid area 4210 corresponding to the dicing area 3200 of the substrate 3000. Each diaphragm 4300 may have multiple pixel openings 4310 that expose the electrode pattern of the substrate 3000 in the deposition process. For example, if the substrate 3000 is positioned on (e.g., above) the deposition mask 4000 in the deposition process, the electrode pattern of the substrate 3000 (e.g., the first electrode AND (e.g., see...) Figure 11 The electrode pattern (e.g., the first electrode AND) of the substrate 3000 can be positioned on (e.g., above) the pixel opening 4310 of the deposition mask 4000 (e.g., when the substrate 3000 is positioned on (e.g., above) the deposition mask 4000 in the deposition process, and accordingly, the first electrode AND can be exposed toward the deposition source 2200 through the pixel opening 4310.

[0269] According to one or more embodiments, the deposition mask 4000 may include a mask substrate 4100, a buffer inorganic film 4200 located on the mask substrate 4100, and a diaphragm 4300 located on the buffer inorganic film 4200.

[0270] According to one or more embodiments, the mask substrate 4100 may have cell openings 4110 corresponding to the display cell regions 3100 of the base substrate 3000. For example, the cell openings 4110 may be formed to penetrate the mask substrate 4100, and the mask substrate 4100 may include rib regions 4120 defining the cell openings 4110. According to one or more embodiments, the mask substrate 4100 may include monocrystalline silicon. For example, a monocrystalline silicon substrate having a thickness in the range of about 700 μm to about 800 μm (e.g., about 725 μm or about 775 μm) may be used as the mask substrate 4100.

[0271] According to one or more embodiments, the buffer inorganic film 4200 may include a grid region 4210 located on a rib region 4120 of a mask substrate 4100 and an eave region 4220 exposed through a cell opening 4110. For example, in a plan view, the eave region 4220 may extend from the grid region 4210 in a first direction DR1 and a second direction DR2, and may have a ring shape with a constant width. For example, the eave region 4220 may have a generally quadrilateral ring shape and may define a buffer opening 4230 communicating with the cell opening 4110.

[0272] According to one or more embodiments, diaphragms 4300 may be located on the eaves region 4220 of the buffer inorganic film 4200, and each diaphragm 4300 may have a plurality of pixel openings 4310. Pixel openings 4310 may be formed to penetrate the diaphragm 4300 and may communicate with unit openings 4110 through buffer openings 4230. For example, portions of the diaphragm 4300 with pixel openings 4310 may be exposed through buffer openings 4230, and edge portions of the diaphragm 4300 may be positioned on the eaves region 4220 of the buffer inorganic film 4200.

[0273] According to one or more embodiments, such as... Figure 17 and Figure 18 As shown, each diaphragm 4300 may have a quadrilateral plate shape. However, the shapes of the unit opening 4110 of the mask substrate 4100, the eaves area 4220, the buffer opening 4230 of the buffer inorganic film 4200, and the diaphragm 4300 may vary depending on the shape of the display unit area 3100 of the base plate substrate 3000, and therefore the scope of this disclosure is not limited to a specific shape.

[0274] According to one or more embodiments, if the substrate 3000 is located on the deposition mask 4000 during the deposition process, the diaphragm 4300 may face the display cell region 3100, and the grid region 4210 of the buffer inorganic film 4200 may face the dicing region 3200 (e.g., when the substrate 3000 is located on the deposition mask 4000 during the deposition process, the diaphragm 4300 may face the display cell region 3100, and the grid region 4210 of the buffer inorganic film 4200 may face the dicing region 3200). In such an embodiment, the pixel opening 4310 may be exposed toward the deposition source 2200 through the buffer opening 4230 and the cell opening 4110, and the vapor deposition material provided from the deposition source 2200 during the deposition process may be deposited on the first electrode AND of the substrate 3000 through the cell opening 4110, the buffer opening 4230, and the pixel opening 4310.

[0275] According to one or more embodiments, such as Figure 17 As shown, the diaphragm 4300 can be arranged in a matrix along a first direction DR1 and a second direction DR2. For example, the first direction DR1 can be a first horizontal direction, and the second direction DR2 can be a second horizontal direction orthogonal (e.g., perpendicular) to the first direction DR1. Pixel openings 4310 can be arranged to correspond to the first electrode AND of the display unit area 3100. As an example, pixel openings 4310 can be arranged to correspond to, for example,... Figure 9 and Figure 10The first emission region EA1, the second emission region EA2, and the third emission region EA3 shown correspond to the first electrodes AND. In some embodiments, the pixel opening 4310 can be arranged to correspond to, as shown in the figure, the first emission region EA1, the second emission region EA2, and the third emission region EA3. In some embodiments, the pixel opening 4310 can be arranged to correspond to, as shown in the figure, the first electrode AND of the first emission region EA1, the second emission region EA2 Figure 11 The first electrode AND in any one or more of the first emission region EA1, the second emission region EA2 and the third emission region EA3 shown corresponds to the first electrode AND.

[0276] According to one or more embodiments, the buffer inorganic membrane 4200 and the diaphragm 4300 may be located on the front surface 4102 of the mask substrate 4100 (e.g., see...). Figure 22 On the mask substrate 4100, the intermediate inorganic film 4400 and the rear inorganic film 4500 can be located on the rear surface 4104 of the mask substrate 4100 (e.g., see...). Figure 22 For example, the intermediate inorganic film 4400 may be located on the rear surface 4104 of the mask substrate 4100, and the rear inorganic film 4500 may be located on the intermediate inorganic film 4400.

[0277] According to one or more embodiments, the intermediate inorganic film 4400 and the rear inorganic film 4500 may each have an intermediate opening 4410 and a rear opening 4510 communicating with the cell opening 4110, respectively. According to one or more embodiments, the intermediate inorganic film 4400 and the rear inorganic film 4500 may be used as etching masks in an etching process for forming the cell opening 4110. In such an embodiment, the pixel opening 4310 may be exposed toward the deposition source 2200 via the buffer opening 4230, the cell opening 4110, the intermediate opening 4410, and the rear opening 4510. In one or more embodiments, vapor-deposited material provided from the deposition source 2200 during the deposition process may be deposited on the first electrode AND of the substrate 3000 via the rear opening 4510, the intermediate opening 4410, the cell opening 4110, the buffer opening 4230, and the pixel opening 4310.

[0278] According to one or more embodiments, the cell opening 4110 can be formed by an anisotropic etching process using an intermediate inorganic film 4400 and a post-inorganic film 4500 as an etching mask. For example, a monocrystalline silicon substrate can be used as the mask substrate 4100, and the cell opening 4110 can be formed by a wet etching process using an etchant such as tetramethylammonium hydroxide (TMAH) solution or potassium hydroxide (KOH) solution. In such an embodiment, the monocrystalline silicon substrate used as the mask substrate 4100... <100> The crystal orientation can correspond to the third orientation DR3, and accordingly, the cell opening 4110 formed by the wet etching process can have a width that gradually decreases from the rear surface 4104 of the mask substrate 4100 toward the front surface 4102 of the mask substrate 4100. For example, the inner surface of the cell opening 4110 can have an inclination angle of about 54.7° relative to the rear surface of the mask substrate 4100.

[0279] According to one or more embodiments, the buffer opening 4230 of the buffer inorganic film 4200 can be formed by a wet etching process. For example, if the buffer inorganic film 4200 comprises silicon oxide (SiO2). x The buffer opening 4230 can then be formed by a wet etching process using an etchant such as a buffer oxide etchant (BOE) or diluted hydrofluoric acid (HF) (e.g., when the buffer inorganic film 4200 comprises silicon oxide (SiO2)). x When the buffer opening 4230 is formed, it can be formed by a wet etching process using an etchant such as buffer oxide etchant (BOE) or diluted HF.

[0280] According to one or more embodiments, the buffer inorganic film 4200 and the intermediate inorganic film 4400 may comprise materials having etch selectivity relative to the mask substrate 4100. For example, the buffer inorganic film 4200 and the intermediate inorganic film 4400 may each comprise silicon oxide (SiO2) with residual compressive stress. x For example, the buffer inorganic film 4200 and the intermediate inorganic film 4400 can be formed on the front surface 4102 and the rear surface 4104 of the mask substrate 4100 by thermal oxidation or chemical vapor deposition (CVD) processes, respectively, and can each have a thickness in the range of about 0.2 μm to about 2 μm.

[0281] According to one or more embodiments, the diaphragm 4300 and the post-inorganic membrane 4500 may comprise materials having etch selectivity relative to the buffer inorganic membrane 4200, the intermediate inorganic membrane 4400, and the mask substrate 4100. For example, the diaphragm 4300 and the post-inorganic membrane 4500 may each comprise silicon nitride (SiN) with residual tensile stress. x For example, the diaphragm 4300 and the post-inorganic membrane 4500 can each be formed by low-pressure chemical vapor deposition (LPCVD) to have a thickness of about 0.3 μm to about 3 μm.

[0282] According to one or more embodiments, the eaves region 4220 of the buffer inorganic membrane 4200 may be a region exposed through the cell opening 4110. For example, the eaves region 4220 may be defined by an inner surface defining the cell opening 4110 and an inner surface defining the buffer opening 4230 (defined by the inner surfaces of the cell opening 4110 and the buffer opening 4230). According to one or more embodiments, the width w1 of the eaves region 4220 may be greater than the width w2 of the area where the edge region of the diaphragm 4300 overlaps with the eaves region 4220. According to one or more embodiments, the eaves regions 4220 may each have a width w1 of about 1 μm to about 100 μm, and the width w2 of the area where the edge region of the diaphragm 4300 and the eaves region 4220 overlap each other in the thickness direction (e.g., third direction DR3) of the mask substrate 4100 may each be in the range of about 0.5 μm to about 50 μm. For example, the width w1 of the eaves area 4220 can each be in the range of about 10 μm to about 30 μm, and the width w2 of the edge area of ​​the diaphragm 4300 and the area where the eaves area 4220 overlaps with each other can each be in the range of about 5 μm to about 15 μm.

[0283] According to one or more embodiments, if the diaphragm 4300 is located on the eaves region 4220 of the buffer inorganic membrane 4200 and the buffer inorganic membrane 4200 has residual compressive stress, the eaves region 4220 of the buffer inorganic membrane 4200 may protrude from the front surface 4102 of the mask substrate 4100 on the third-direction DR3 due to the residual compressive stress (e.g., see...). Figure 19 (The upward bending of the eaves region 4220) (For example, when the diaphragm 4300 is located on the eaves region 4220 of the buffer inorganic membrane 4200 and the buffer inorganic membrane 4200 has residual compressive stress, the eaves region 4220 of the buffer inorganic membrane 4200 may protrude from the front surface 4102 of the mask substrate 4100 on the third-direction DR3 due to the residual compressive stress (for example, see...) Figure 19 (The upward bend of the eaves area 4220). For example, the eaves area 4220 may extend from the grid area 4210 and be positioned higher than the grid area 4210. For example, as... Figure 19As shown, the eaves region 4220 of the buffer inorganic membrane 4200 can be raised upward on the third direction DR3. When the diaphragm 4300 has residual tensile stress, deformation of the diaphragm 4300 may occur due to the residual tensile stress. However, according to one or more embodiments of this disclosure, if the edge portion of the diaphragm 4300 is located on the eaves region 4220 of the buffer inorganic membrane 4200, the deformation of the diaphragm 4300 due to residual tensile stress can be reduced by the deformation of the eaves region 4220 due to residual compressive stress (e.g., when the edge portion of the diaphragm 4300 is located on the eaves region 4220 of the buffer inorganic membrane 4200, the deformation of the diaphragm 4300 due to residual tensile stress can be reduced by the deformation of the eaves region 4220 due to residual compressive stress). As a result, as Figure 19 As shown, due to the deformation of the eaves region 4220, the diaphragm 4300 can remain in a flat state. Therefore, the unit warpage of the deposition mask 4000 can be reduced by buffering the residual compressive stress of the inorganic membrane 4200 and the residual tensile stress of the diaphragm 4300.

[0284] Unlike the above, if the buffer inorganic membrane 4200 and the diaphragm 4300 have the same residual stress (e.g., if both the buffer inorganic membrane 4200 and the diaphragm 4300 have residual compressive stress), a moment may be generated in the third-direction DR3 at the overlapping portion of the eaves 4220 of the buffer inorganic membrane 4200 and the edge portions of the diaphragm 4300 (e.g., when the buffer inorganic membrane 4200 and the diaphragm 4300 have the same residual stress, a moment may be generated in the third-direction DR3 at the overlapping portion of the eaves 4220 of the buffer inorganic membrane 4200 and the edge portions of the diaphragm 4300). In such a case, deformation of the diaphragm 4300 protruding convexly from the mask substrate 4100 in the third-direction DR3 may occur. Therefore, it is not desirable for the buffer inorganic membrane 4200 and the diaphragm 4300 to have the same residual stress. For example, it is not desirable for both the buffer inorganic membrane 4200 and the diaphragm 4300 to have residual compressive stress.

[0285] According to one or more embodiments, the diaphragm 4300 may comprise silicon-rich (Si-rich) silicon nitride having a silicon content (e.g., silicon weight) higher than the stoichiometric silicon content (e.g., silicon weight) of silicon nitride (Si3N4). For example, if the silicon content (e.g., silicon weight) of the diaphragm 4300 is equal to or lower than the stoichiometric silicon content (e.g., silicon weight) of silicon nitride (Si3N4), the residual tensile stress of the diaphragm 4300 may increase, thereby causing global warpage of the deposition mask 4000. According to one or more embodiments, to reduce global warpage of the deposition mask 4000, the residual tensile stress of the diaphragm 4300 may be below about 500 MPa, and the diaphragm 4300 may comprise silicon-rich silicon nitride.

[0286] For example, if silicon nitride is represented as Si x N y Furthermore, the ratio of silicon content (e.g., silicon amount) to nitrogen content (e.g., nitrogen amount) in silicon nitride is called the "x / y" value. The ratio of silicon content (e.g., silicon amount) to nitrogen content (e.g., nitrogen amount) in stoichiometric silicon nitride (Si3N4) (i.e., the "x / y" value of Si3N4) is 0.75 (e.g., when silicon nitride is represented as Si...). x N y Furthermore, when the ratio of silicon content (e.g., silicon amount) to nitrogen content (e.g., nitrogen amount) of silicon nitride is referred to as the "x / y" value, the ratio of silicon content (e.g., silicon amount) to nitrogen content (e.g., nitrogen amount) of stoichiometric silicon nitride (Si3N4) (i.e., the "x / y" value of Si3N4) is 0.75. According to one or more embodiments, the ratio of silicon content (e.g., silicon amount) to nitrogen content (e.g., nitrogen amount) of the separator 4300 can be controlled or selected to be in the range of about 0.8 to about 1.2.

[0287] According to one or more embodiments, the post-inorganic film 4500 may comprise the same material as the separator 4300. For example, the post-inorganic film 4500 may be formed by an LPCVD process and may have the same thickness as the separator 4300. According to one or more embodiments, the area of ​​the post-inorganic film 4500 may be substantially equal to the sum of the areas of the separators 4300. Accordingly, the force applied to the mask substrate 4100 due to the residual tensile stress of the separator 4300 and the force applied to the mask substrate 4100 due to the residual tensile stress of the post-inorganic film 4500 may become substantially equal to or substantially similar to each other, and thus global warpage of the deposition mask 4000 may be reduced.

[0288] According to one or more embodiments, such as... Figure 17As shown, the deposition mask 4000 may include a mask alignment key 4600. For example, the mask alignment key 4600 may be located on an edge portion of the deposition mask 4000 and may be used for positional alignment between the substrate 3000 and the deposition mask 4000. Figure 17 In this process, two mask alignment keys 4600 are used, but the number of mask alignment keys 4600 can vary, and accordingly, the scope of this disclosure is not limited to a specific number of mask alignment keys 4600.

[0289] Figure 20 This illustrates one or more embodiments according to the present disclosure. Figure 17 A schematic cross-sectional view of the mask alignment key.

[0290] refer to Figure 20 The mask alignment key 4600 may be located on an edge portion of the mask substrate 4100. According to one or more embodiments, the mask alignment key 4600 may be positioned on an edge portion (e.g., an edge region) of the buffer inorganic film 4200. In one or more embodiments, the mask alignment key 4600 may comprise a metal, such as copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), cobalt (Co), etc., and may be formed by forming a metal film on the buffer inorganic film 4200 and then patterning the metal film.

[0291] According to one or more embodiments, the deposition mask 4000 may include a protective film pattern 4610 disposed on the mask alignment key 4600. According to one or more embodiments, the protective film pattern 4610 may include the same material as the diaphragm 4300 and may have the same thickness as the diaphragm 4300. For example, a pre-inorganic membrane 4010 (e.g., see...) Figure 25 and Figure 26 The buffer inorganic membrane 4200 and the mask alignment key 4600 can be formed, and the diaphragm 4300 and the protective membrane pattern 4610 can be formed by patterning the front inorganic membrane 4010.

[0292] Refer again Figures 17 to 19 The deposition mask 4000 may include a spacer pattern 4700. According to one or more embodiments, the spacer pattern 4700 may be arranged on the grid regions 4210 of the buffer inorganic film 4200. The spacer pattern 4700 can be used to prevent or reduce the possibility of damage to the diaphragm 4300 that may occur during the deposition process due to contact with the substrate 3000.

[0293] Figure 21 This illustrates one or more embodiments according to the present disclosure. Figure 17 A schematic cross-sectional view of the spacer pattern.

[0294] refer to Figure 21 Each spacer pattern 4700 may include: a first spacer pattern 4710 located on a grid region 4210 of the buffer inorganic film 4200; and a second spacer pattern 4720 located on the first spacer pattern 4710. According to one or more embodiments, the first spacer pattern 4710 may include the same material as the mask alignment key 4600. For example, the mask alignment key 4600 and the first spacer pattern 4710 may be formed simultaneously (e.g., concurrently) by forming a metal film on the buffer inorganic film 4200 and then patterning the metal film. In such an embodiment, the mask alignment key 4600 and the first spacer pattern 4710 may include substantially the same material and may have substantially the same thickness.

[0295] According to one or more embodiments, the second spacer pattern 4720 may comprise the same material as the diaphragm 4300. For example, the pre-inorganic membrane 4010 may be formed on the buffer inorganic membrane 4200, the mask alignment key 4600, and the first spacer pattern 4710, and by patterning the pre-inorganic membrane 4010, the diaphragm 4300, the protective membrane pattern 4610, and the second spacer pattern 4720 may be formed simultaneously (e.g., concurrently). In such embodiments, the diaphragm 4300, the protective membrane pattern 4610, and the second spacer pattern 4720 may all comprise substantially the same material and may all have substantially the same thickness.

[0296] According to one or more embodiments, the top surface of the second spacer pattern 4720 may have the same height as the top surface of the diaphragm 4300, or it may have a higher height than the top surface of the diaphragm 4300. Accordingly, during the deposition process, the diaphragm 4300 may not contact the substrate 3000, or even if the diaphragm 4300 does contact the substrate 3000, damage to the diaphragm 4300 due to contact with the substrate 3000 may be reduced. According to one or more embodiments, the first spacer pattern 4710 may have a thickness equal to or greater than the height by which the eaves region 4220 is raised due to the residual compressive stress of the buffer inorganic film 4200. For example, the first spacer pattern 4710 may have a thickness of about 0.5 μm to about 3 μm.

[0297] Figures 22 to 34 This is a schematic cross-sectional view illustrating a method of manufacturing a deposition mask according to one or more embodiments of the present disclosure.

[0298] refer to Figure 22A buffer inorganic film 4200 can be formed on the front surface 4102 of the mask substrate 4100. According to one or more embodiments, the mask substrate 4100 may include monocrystalline silicon. For example, a monocrystalline silicon substrate having a thickness in the range of about 700 μm to about 800 μm (e.g., about 725 μm or about 775 μm) can be used as the mask substrate 4100.

[0299] According to one or more embodiments, the buffer inorganic membrane 4200 may include silicon oxide (SiO2). x A buffer inorganic film 4200 with a thickness of about 0.2 μm to about 2 μm can be formed on the front surface 4102 of the mask substrate 4100 by thermal oxidation or CVD process.

[0300] An intermediate inorganic film 4400 may be formed on the rear surface 4104 of the mask substrate 4100. According to one or more embodiments, the intermediate inorganic film 4400 may comprise silicon oxide (SiO2). x For example, an intermediate inorganic film 4400 with a thickness of about 0.2 μm to about 2 μm can be formed on the rear surface 4104 of the mask substrate 4100 by a thermal oxidation process or a CVD process. For example, the intermediate inorganic film 4400 can be formed simultaneously (e.g., concurrently) with the buffer inorganic film 4200 by a thermal oxidation process or a CVD process.

[0301] refer to Figure 23 and Figure 24 Mask alignment keys 4600 and first spacer patterns 4710 can be formed on the buffer inorganic film 4200. According to one or more embodiments, mask alignment keys 4600 can be formed on edge portions of the buffer inorganic film 4200, and can be formed in the grid areas 4210 of the buffer inorganic film 4200 (e.g., see...). Figure 21 The first spacer pattern 4710 is formed on the buffer inorganic film 4200. For example, by forming a metal film on the buffer inorganic film 4200 and then patterning the metal film, the mask alignment key 4600 and the first spacer pattern 4710 can be formed simultaneously (e.g., at the same time).

[0302] In one or more embodiments, the metal film may include metals such as copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), cobalt (Co), etc., and may be formed by a sputtering process to have a thickness of about 0.5 μm to about 3 μm. Subsequently, a photoresist pattern may be formed on the metal film to expose portions of the metal film other than those where the mask alignment bond 4600 and the first spacer pattern 4710 are to be formed, and the photoresist pattern may be used as an etching mask to perform an anisotropic etching process (e.g., a plasma etching process), thereby forming the mask alignment bond 4600 and the first spacer pattern 4710 on the buffer inorganic film 4200. The photoresist pattern may be removed by an ashing process and / or a stripping process after the formation of the mask alignment bond 4600 and the first spacer pattern 4710.

[0303] refer to Figure 25 and Figure 26 The front inorganic film 4010 can be formed on the buffer inorganic film 4200, the mask alignment key 4600, and the first spacer pattern 4710. According to one or more embodiments, the front inorganic film 4010 may comprise silicon nitride (SiN). x And it can be conformally formed to have a thickness of about 0.3 μm to about 3 μm by LPCVD process. For example, a silicon source gas such as silane (SiH4) or dichlorosilane (DCS) and a nitrogen source gas such as nitrogen (N2) or ammonia (NH3) can be supplied to the buffer inorganic film 4200, the mask alignment bond 4600 and the first spacer pattern 4710 (above), and the front inorganic film 4010 can be formed by the reaction between the silicon source gas and the nitrogen source gas.

[0304] A post-inorganic film 4500 may be formed on the intermediate inorganic film 4400. According to one or more embodiments, the post-inorganic film 4500 may include silicon nitride (SiN). x The inorganic membrane 4010 and the inorganic membrane 4500 can be formed on the intermediate inorganic membrane 4400 by an LPCVD process to have a thickness of about 0.3 μm to about 3 μm. For example, the preceding inorganic membrane 4010 and the following inorganic membrane 4500 can be formed simultaneously (e.g., concurrently) by an LPCVD process. In such an embodiment, the following inorganic membrane 4500 can have a thickness substantially the same as that of the preceding inorganic membrane 4010.

[0305] According to one or more embodiments, the pre-inorganic film 4010 may comprise silicon-rich silicon nitride having a silicon content (e.g., silicon weight) higher than the stoichiometric silicon content (e.g., silicon weight) of silicon nitride (Si3N4). According to one or more embodiments, the ratio of silicon content (e.g., silicon weight) to nitrogen content (e.g., nitrogen weight) of the pre-inorganic film 4010 may be controlled or selected to be in the range of about 0.8 to about 1.2. For example, an LPCVD process may be performed at low pressure and high temperature to form the silicon-rich silicon nitride film. For example, the LPCVD process may be performed in a pressure atmosphere of about 210 mTorr to about 250 mTorr and a temperature atmosphere of about 800°C to about 850°C. According to one or more embodiments, if the post-inorganic membrane 4500 is formed synchronously (e.g., simultaneously) with the pre-inorganic membrane 4010, the ratio of silicon content (e.g., amount of silicon) to nitrogen content (e.g., amount of nitrogen) of the post-inorganic membrane 4500 can be substantially the same as the ratio of silicon content (e.g., amount of silicon) to nitrogen content (e.g., amount of nitrogen) of the pre-inorganic membrane 4010 (e.g., when the post-inorganic membrane 4500 is formed synchronously (e.g., simultaneously) with the pre-inorganic membrane 4010, the ratio of silicon content (e.g., amount of silicon) to nitrogen content (e.g., amount of nitrogen) of the post-inorganic membrane 4500 can be substantially the same as the ratio of silicon content (e.g., amount of silicon) to nitrogen content (e.g., amount of nitrogen) of the pre-inorganic membrane 4010).

[0306] refer to Figure 27 The front inorganic film 4010 can be patterned to form a septum 4300 having a pixel opening 4310 penetrating the septum 4300 on the buffer inorganic film 4200. Additionally, the front inorganic film 4010 can be patterned to form a protective film pattern 4610 on the mask alignment key 4600 and the first spacer pattern 4710, respectively (see, for example, see...). Figure 20 ) and second spacer pattern 4720 (e.g., see Figure 21 For example, a photoresist pattern can be formed on the front inorganic film 4010 to expose the portion where the pixel opening 4310 is to be formed, and to expose the portion of the front inorganic film 4010 other than the portion where the diaphragm 4300, the protective film pattern 4610, and the second spacer pattern 4720 are to be formed. The photoresist pattern can be used as an etching mask to perform an anisotropic etching process (e.g., a plasma etching process or a reactive ion etching (RIE) process), thereby forming the diaphragm 4300, the protective film pattern 4610, the second spacer pattern 4720, and the pixel opening 4310.

[0307] For example, if the preceding inorganic film 4010 includes silicon nitride (SiN) xAnisotropic etching processes can be performed using a first reactant gas containing fluorine (such as CF4, C2F4, C2F6, C3F6, C3F8, C4F6, C4F8, CH3F, CH2F2, C2HF5, CHF3, NF3, or SF6), a second reactant gas containing oxygen (such as O2, NO, or NO2), and sputtering gases (such as He, Ne, Ar, or Xe). (For example, current inorganic films 4010 include silicon nitride (SiN).) x When performing an anisotropic etching process, a first reactive gas containing fluorine (such as CF4, C2F4, C2F6, C3F6, C3F8, C4F6, C4F8, CH3F, CH2F2, C2HF5, CHF3, NF3, or SF6), a second reactive gas containing oxygen (such as O2, NO, or NO2), and a sputtering gas (such as He, Ne, Ar, or Xe) can be used until the buffer inorganic film 4200 is exposed. The photoresist pattern can be removed by an ashing process and / or a stripping process after the formation of the septum 4300, the protective film pattern 4610, the second spacer pattern 4720, and the pixel opening 4310.

[0308] refer to Figure 28 An etch stop film 4020 can be formed on the buffer inorganic film 4200, the diaphragm 4300, the protective film pattern 4610, and the second spacer pattern 4720. According to one or more embodiments, the etch stop film 4020 may comprise a photoresist or an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB), and can be formed by spin coating and baking processes.

[0309] refer to Figure 29 The inorganic film 4500 can be partially removed to form the rear opening 4510. According to one or more embodiments, the inorganic film 4500 can be patterned to form the rear opening 4510 that partially exposes the intermediate inorganic film 4400. In such an embodiment, the portion 4402 of the intermediate inorganic film 4400 exposed through the rear opening 4510 can overlap with the diaphragm 4300 in the thickness direction of the mask substrate 4100 (e.g., on the third-direction DR3). For example, after forming a photoresist pattern on the inorganic film 4500 that exposes the portion to be formed of the rear opening 4510, the photoresist pattern can be used as an etching mask to perform an anisotropic etching process (e.g., a plasma etching process or a RIE process), thereby forming the rear opening 4510 that penetrates the inorganic film 4500.

[0310] For example, if the post-inorganic film 4500 includes silicon nitride (SiN) xAnisotropic etching processes can be performed using a first reactive gas containing fluorine (such as CF4, C2F4, C2F6, C3F6, C3F8, C4F6, C4F8, CH3F, CH2F2, C2HF5, CHF3, NF3, or SF6), a second reactive gas containing oxygen (such as O2, NO, or NO2), and sputtering gases (such as He, Ne, Ar, or Xe). (For example, when the inorganic film 4500 includes silicon nitride (SiN)). x When performing an anisotropic etching process, a first reactive gas containing fluorine (such as CF4, C2F4, C2F6, C3F6, C3F8, C4F6, C4F8, CH3F, CH2F2, C2HF5, CHF3, NF3, or SF6), a second reactive gas containing oxygen (such as O2, NO, or NO2), and a sputtering gas (such as He, Ne, Ar, or Xe) can be used until the intermediate inorganic film 4400 is exposed, thereby forming the post-opening 4510. The photoresist pattern can be removed by an ashing process and / or a stripping process after the post-opening 4510 is formed.

[0311] refer to Figure 30 The intermediate inorganic film 4400 can be partially removed to form an initial intermediate opening 4404. According to one or more embodiments, the intermediate inorganic film 4400 can be patterned to form a rear surface 4104 that partially exposes the mask substrate 4100 (e.g., see...). Figure 22 The initial intermediate opening 4404. According to one or more embodiments, the initial intermediate opening 4404 may have a width smaller than the width of the rear opening 4510, and may be formed as a portion 4402 of the intermediate inorganic film 4400 exposed through the rear opening 4510. For example, after forming a photoresist pattern on the portion 4402 of the intermediate inorganic film 4400 exposed through the rear opening 4510 of the rear inorganic film 4500 to expose the portion to which the initial intermediate opening 4404 is to be formed, the photoresist pattern can be used as an etching mask to perform an anisotropic etching process (e.g., a plasma etching process or a RIE process) to form the initial intermediate opening 4404 penetrating the intermediate inorganic film 4400.

[0312] For example, if the intermediate inorganic film 4400 includes silicon oxide (SiO2) x Anisotropic etching processes can be performed using fluorine-containing reactive gases (such as CF4, C2F4, C2F6, C3F6, C3F8, C4F6, C4F8, CH3F, CH2F2, C2HF5, CHF3, NF3, or SF6) and sputtering gases (such as He, Ne, Ar, or Xe). (For example, when the intermediate inorganic film 4400 includes silicon oxide (SiO2)...) xWhen performing anisotropic etching, fluorine-containing reactive gases (such as CF4, C2F4, C2F6, C3F6, C3F8, C4F6, C4F8, CH3F, CH2F2, C2HF5, CHF3, NF3, or SF6) and sputtering gases (such as He, Ne, Ar, or Xe) can be used until the rear surface 4104 of the exposed mask substrate 4100 is exposed, thereby forming a preliminary intermediate opening 4404. The photoresist pattern can be removed by an ashing process and / or a stripping process after the preliminary intermediate opening 4404 is formed.

[0313] According to one or more embodiments, a portion 4406 of the intermediate inorganic film 4400 between the inner surface defining the initial intermediate opening 4404 and the inner surface defining the rear opening 4510 (i.e., the portion 4406 of the intermediate inorganic film 4400 exposed through the rear opening 4510 after the formation of the initial intermediate opening 4404) can have a constant width in the first direction DR1 and the second direction DR2 (e.g., the inner surfaces of the rear opening 4510 and the initial intermediate opening 4404 can be substantially parallel to the thickness direction of the mask substrate 4100 (i.e., the third direction DR3)). Additionally, the rear portion 4106 of the mask substrate 4100 exposed through the initial intermediate opening 4404 can overlap with the separator 4300 in the thickness direction (i.e., the third direction DR3) of the mask substrate 4100.

[0314] refer to Figure 31 The mask substrate 4100 can be partially removed (i.e., the mask substrate 4100 can be partially patterned) to form preliminary cell openings 4108 for exposing the buffer inorganic film 4200. In one or more embodiments, the preliminary cell openings 4108 can be formed by an etching process (e.g., an anisotropic etching process) using the post-inorganic film 4500 and the intermediate inorganic film 4400 as etching masks. For example, the preliminary cell openings 4108 can be formed by a first wet etching process using an etchant such as a TMAH solution, KOH solution, etc., and the first wet etching process can be performed until the buffer inorganic film 4200 is exposed.

[0315] According to one or more embodiments, a single-crystal silicon substrate is used as a mask substrate 4100. <100> The crystal orientation can correspond to the third orientation DR3, and accordingly, the preliminary cell opening 4108 formed by the first wet etching process can have a rear surface 4104 from the mask substrate 4100 (e.g., see...). Figure 22 ) toward the front surface 4102 of the mask substrate 4100 (e.g., see Figure 22The width gradually decreases. For example, the inner surface of the initial unit opening 4108 may have an inclination angle of approximately 54.7° relative to the rear surface 4104 of the mask substrate 4100.

[0316] According to one or more embodiments, the portion 4202 of the buffer inorganic film 4200 exposed through the initial unit opening 4108 can overlap with the diaphragm 4300 in the thickness direction (i.e., third direction DR3) of the mask substrate 4100. For example, the portion 4202 of the buffer inorganic film 4200 exposed through the initial unit opening 4108 can overlap with the diaphragm 4300 where the pixel opening 4310 is formed (e.g., see...) in the thickness direction of the mask substrate 4100. Figure 27 (Partial overlap)

[0317] refer to Figure 32 The portion 4202 of the buffer inorganic membrane 4200 exposed through the initial unit opening 4108 can be removed (see...). Figure 31 In one or more embodiments, the portion 4202 of the buffer inorganic film 4200 exposed through the initial unit opening 4108 may be removed to form a buffer opening 4230 that partially exposes the diaphragm 4300. In one or more embodiments, the buffer opening 4230 may expose the portion of the diaphragm 4300 where the pixel opening 4310 is formed, and edge portions of the diaphragm 4300 may remain on the buffer inorganic film 4200. For example, edge portions of the diaphragm 4300 may remain on the eaves region 4220 of the buffer inorganic film 4200 (see...). Figure 19 and Figure 21 For example, if the buffer inorganic membrane 4200 includes silicon dioxide (SiO2). x The buffer opening 4230 can be formed by using a second wet etching process with an etchant such as BOE, diluted hydrofluoric acid, etc. (e.g., when the buffer inorganic film 4200 includes silicon oxide (SiO2)). x (When this is done, a second wet etching process using etchants such as BOE, diluted hydrofluoric acid, etc. can be used to form a buffer opening 4230).

[0318] According to one or more embodiments, the portion 4406 of the intermediate inorganic film 4400 exposed through the rear opening 4510 can be removed by a second wet etching process (e.g., see...). Figure 31 This forms the intermediate opening 4410. For example, if the intermediate inorganic film 4400 includes silicon oxide (SiO2), then... x Then, the initial intermediate opening 4404 can be enlarged by a second wet etching process (for example, when the intermediate inorganic film 4400 includes silicon oxide (SiO2)). xDuring this process, the initial intermediate opening 4404 can be enlarged by a second wet etching process, thereby forming an intermediate opening 4410 with a size approximately the same as that of the subsequent opening 4510. In one embodiment, the formation of the intermediate opening 4410 can be performed simultaneously with the formation of the buffer opening 4230.

[0319] According to one or more embodiments, the etch stop film 4020 can prevent or reduce the mesh region 4210 of the buffer inorganic film 4200 (e.g., see...). Figure 19 and Figure 21 The possibility that the eaves area 4220 and the eaves area 4220 will be etched during the second wet etching process. For example, only the portion 4202 of the buffer inorganic film 4200 exposed through the initial unit opening 4108 and the portion 4406 of the intermediate inorganic film 4400 exposed through the rear opening 4510 can be selectively removed by the second wet etching process.

[0320] refer to Figure 33 The cell opening 4110 can be formed by enlarging the initial cell opening 4108 to expose the eaves region 4220 of the buffer inorganic film 4200. According to one or more embodiments, the cell opening 4110 can be formed by removing the inner surface portion defining the initial cell opening 4108 (the inner surface portion of the initial cell opening 4108), and in addition to these, rib regions 4120 defining the cell opening 4110 can also be formed. For example, the cell opening 4110 can be formed by a third wet etching process using an etchant such as a TMAH solution, KOH solution, etc., and the inner surface of the cell opening 4110 can be relative to the rear surface 4104 of the mask substrate 4100 (e.g., see...). Figure 22 It has a tilt angle of approximately 54.7°.

[0321] According to one or more embodiments, the eaves region 4220 of the buffer inorganic film 4200 may be a region extending from the rib region 4120 of the mask substrate 4100 toward the cell opening 4110, and the grid region 4210 of the buffer inorganic film 4200 may be a region located on the rib region 4120 of the mask substrate 4100. According to one or more embodiments, the width w1 of each eaves region 4220 (e.g., see...) Figure 19 The width w2 of each region in the region where the edge region and the eaves region 4220 of the diaphragm 4300 overlap with each other in the thickness direction of the mask substrate 4100 can be greater than the width w2 of the region. (For example, see...) Figure 19According to one or more embodiments, each of the eaves regions 4220 may have a width w1 of about 1 μm to about 100 μm, and the width w2 of the overlapping areas of the edge regions of the diaphragm 4300 and the eaves regions 4220 may each be in the range of about 0.5 μm to about 50 μm. For example, the width w1 of each eaves region 4220 may be about 10 μm to about 30 μm, and the width w2 of each overlapping area of ​​the edge regions of the diaphragm 4300 and the eaves regions 4220 may be about 5 μm to about 15 μm.

[0322] refer to Figure 34 The etch stop film 4020 can be removed, thereby connecting the pixel opening 4310 with the buffer opening 4230. According to one or more embodiments, if the etch stop film 4020 is removed, the eaves region 4220 of the buffer inorganic film 4200 can be lifted, for example, away from the front surface 4102 of the mask substrate 4100 on the third-party DR3 (e.g., see...). Figure 22 (For example, when the etch stop film 4020 is removed, the eaves region 4220 of the buffer inorganic film 4200 may be lifted away from the front surface 4102 of the mask substrate 4100, for example, on the third-direction DR3, due to the residual compressive stress of the buffer inorganic film 4200 and the residual tensile stress of the diaphragm 4300, and the diaphragm 4300 may remain in a flat state due to this deformation of the eaves region 4220.)

[0323] According to one or more embodiments, the etching stop film 4020 can be removed by a wet etching process, a plasma etching process, etc. For example, if the etching stop film 4020 comprises an organic insulating material, it can be removed by a fourth wet etching process using an etchant such as acetone, ethanol, toluene, propylene glycol, propylene glycol methyl ether acetate, triethylene glycol monobutyl ether, diethylene glycol monophenyl ether, amide solvent, dicarbonyl solvent, diethylene glycol dibenzoate, tricarbonyl solvent, triethyl citrate, phthalate solvent, butyl benzyl phthalate, di(2-ethylhexyl) phthalate, di(2-ethylhexyl) isophthalate, monoethylene glycol phthalate, or N-methyl-2-pyrrolidone (NMP). For example, when the etch stop film 4020 comprises an organic insulating material, it can be removed by a fourth wet etching process using etchants such as acetone, ethanol, toluene, propylene glycol, propylene glycol methyl ether acetate, triethylene glycol monobutyl ether, diethylene glycol monophenyl ether, amide solvents, dicarbonyl solvents, diethylene glycol dibenzoate, tricarbonyl solvents, triethyl citrate, phthalate solvents, butyl benzyl phthalate, di(2-ethylhexyl) phthalate, di(2-ethylhexyl) isophthalate, monoethylene glycol phthalate, or N-methyl-2-pyrrolidone (NMP). In one or more embodiments, if the etch stop film 4020 comprises a photoresist, it can be removed by an ashing process and / or a stripping process.

[0324] As described above, the etch stop film 4020 is removed after forming the unit opening 4110. However, unlike the above, the etch stop film 4020 can be removed after forming the buffer opening 4230 and the intermediate opening 4410. In this case, the unit opening 4110 can be formed after removing the etch stop film 4020. When the etch stop film 4020 is removed before forming the unit opening 4110 as described above, the diaphragm 4300 may deform to some extent due to residual tensile stress. However, if the unit opening 4110 is subsequently formed, the diaphragm 4300 can be planarized by the eaves region 4220 of the buffer inorganic film 4200 exposed by the unit opening 4110 (e.g., when the unit opening 4110 is subsequently formed, the diaphragm 4300 can be planarized by the eaves region 4220 of the buffer inorganic film 4200 exposed by the unit opening 4110).

[0325] According to one or more embodiments of the present disclosure as described above, deformation of the diaphragm 4300 can be reduced by buffering the eaves region 4220 of the inorganic film 4200 (e.g., residual compressive stress at the eaves region 4220), and deformation of the mask substrate 4100 can be reduced by controlling the area of ​​the diaphragm 4300 and the rear inorganic film 4500. As a result, cell warpage and global warpage of the deposition mask 4000 can be reduced, thereby contributing to improved accuracy in the deposition of light-emitting materials for display devices, leading to improved quality and resolution of the display devices.

[0326] Furthermore, for example, the combined structural configuration and manufacturing sequence described herein not only mitigate warpage but also ensure precise alignment of the pixel apertures with the underlying electrodes during vapor deposition. By integrating stress-balancing films, eaves regions, and optional spacers and alignment features, the deposition mask achieves dimensional stability, crucial for high-resolution OLED panels on silicon. These improvements collectively support the reliable fabrication of advanced display devices, including AR / VR head-mounted displays and other compact electronics requiring ultra-high pixel densities.

[0327] The deposition mask, display panel, electronic device, apparatus for manufacturing a display device, apparatus for manufacturing a deposition mask, and / or any other related apparatus or component described herein according to embodiments of this disclosure can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, various components of the apparatus can be formed on an integrated circuit (IC) chip or a discrete IC chip. Furthermore, various components of the apparatus can be implemented on a flexible printed circuit film, tape-on-a-carrier package (TCP), or printed circuit board (PCB), or formed on a substrate. Furthermore, various components of the apparatus can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which can be implemented in the computing device using standard memory devices (e.g., random access memory (RAM)). The computer program instructions can also be stored in other non-transitory computer-readable media (e.g., CD-ROM, flash memory drive, etc.). Furthermore, those skilled in the art will recognize that, without departing from the scope of the embodiments of this disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0328] It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered as applicable to other similar features or aspects in other embodiments. Therefore, as will be apparent to those skilled in the art, unless specifically instructed otherwise, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. It should be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined in the appended claims and their equivalents.

Claims

1. A deposition mask, comprising: Mask substrate, defining the cell opening; A buffer inorganic film is placed on the mask substrate and includes an eaves area exposed through the unit opening; as well as A diaphragm is located on the eaves area and defines a plurality of pixel openings that communicate with the cell opening.

2. The deposition mask according to claim 1, wherein the buffer inorganic film has residual compressive stress, and The diaphragm has residual tensile stress.

3. The deposition mask according to claim 1, wherein the width of the eaves area is in the range of 1 μm to 100 μm.

4. The deposition mask according to claim 1, wherein the edge region of the septum is on the eaves region, and The width of the overlapping area between the edge region and the eaves region of the diaphragm is in the range of 0.5 μm to 50 μm.

5. The deposition mask according to any one of claims 1 to 4, wherein the mask substrate includes a rib region defining the cell opening. The buffer inorganic membrane includes a grid region on the rib region, and The eaves area extends from the grid area and is positioned above the grid area.

6. The deposition mask according to claim 5, further comprising a spacer pattern on the grid area.

7. The deposition mask of claim 6, wherein the spacer pattern comprises: A first spacer pattern is present on the grid area; as well as The second spacer pattern is on top of the first spacer pattern, and The second spacer pattern comprises the same material as the diaphragm.

8. The deposition mask according to claim 7, further comprising a mask alignment key on the edge region of the buffer inorganic film. The first spacer pattern comprises the same material as the material of the mask alignment key.

9. The deposition mask according to claim 8, further comprising a protective film pattern on the mask alignment key, The protective film pattern therein comprises the same material as the diaphragm.

10. A method for manufacturing a deposition mask, comprising: A buffer inorganic film is formed on the mask substrate; A diaphragm with multiple pixel openings is formed on the buffer inorganic film; Preliminary unit openings that partially expose the buffer inorganic membrane are formed by partially removing the mask substrate; A buffer opening that partially exposes the diaphragm is formed by removing the portion of the buffer inorganic membrane that is exposed through the opening of the initial unit. as well as The initial unit opening is enlarged to form a unit opening that partially exposes the buffer inorganic membrane. The diaphragm is located on the eaves area of ​​the buffer inorganic membrane exposed through the unit opening.

11. The method of claim 10, wherein forming the diaphragm comprises: A pre-inorganic membrane is formed on the buffer inorganic membrane; as well as The preceding inorganic film is partially removed to form the septum having the plurality of pixel openings. The buffer inorganic membrane has residual compressive stress, and The former inorganic membrane has residual tensile stress.

12. The method of claim 11, further comprising: A mask alignment key is formed on the edge region of the buffer inorganic membrane; as well as A protective film pattern is formed on the mask alignment key. The protective film pattern is formed synchronously with the diaphragm having the plurality of pixel openings by partially removing the preceding inorganic film.

13. The method of claim 12, further comprising: A first spacer pattern is formed on the buffer inorganic membrane; as well as A second spacer pattern is formed on the first spacer pattern. The first spacer pattern is formed synchronously with the mask alignment key, and The second spacer pattern is formed synchronously with the protective film pattern.

14. The method of claim 10, wherein the buffer inorganic film is formed on the front surface of the mask substrate, and forming the initial unit opening comprises: An intermediate inorganic film is formed on the rear surface of the mask substrate; A post-inorganic membrane is formed on the intermediate inorganic membrane; A rear opening is formed by partially removing the rear inorganic membrane to partially expose the intermediate inorganic membrane; An initial intermediate opening is formed by partially exposing the rear surface of the mask substrate by partially removing the portion of the intermediate inorganic film exposed through the rear opening. as well as The initial cell opening is formed by performing an etching process that uses the post-inorganic film and the intermediate inorganic film as etching masks.

15. The method of claim 14, wherein the initial intermediate opening has a width smaller than the width of the subsequent opening, and forming the unit opening comprises: The intermediate opening is formed by removing the remainder of the portion of the intermediate inorganic membrane that is exposed through the rear opening; as well as The initial unit opening is enlarged by removing the inner surface portion that defines the initial unit opening.

16. The method of claim 15, wherein the formation of the intermediate opening is performed synchronously with the formation of the buffer opening.

17. The method according to any one of claims 10 to 16, further comprising: An etching stop film is formed on the buffer inorganic membrane and the diaphragm; as well as The etch stop film is removed after the buffer opening is formed.

18. The method according to any one of claims 10 to 16, wherein the edge region of the diaphragm is located on the eaves region, and The area where the edge region and the eaves region of the diaphragm overlap each other has a width smaller than the width of the eaves region.

19. An electronic device comprising: A display panel, wherein the display panel includes a substrate and a plurality of light-emitting layers formed on the substrate using a deposition mask. The deposition mask is the deposition mask according to any one of claims 1 to 9, and The plurality of light-emitting layers are formed by a deposition process, which provides vapor phase light-emitting material onto the substrate through the unit opening and the pixel opening.

20. The electronic device of claim 19, further comprising at least one of a processor, a memory, and a power module.

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